JP5539562B2 - Method for driving solid-state imaging device and solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device, an imaging system, and a solid-state imaging device driving method used for a scanner, a video camera, a digital still camera, and the like.

  In a conventional imaging device, a pixel having a configuration in which a photoelectric conversion unit that photoelectrically converts incident light also serves as an accumulation unit that accumulates charges is generally known.

  On the other hand, Patent Document 1 discloses a technique in which a charge storage unit is provided separately from the photoelectric conversion unit. In Patent Document 1, a global shutter can be realized by transferring the charges accumulated in the photoelectric conversion unit from all the pixels to the accumulation unit at the same time.

Patent Document 2 discloses a configuration in which a storage unit is provided separately from the photoelectric conversion unit, and most of the charge generated in the photoelectric conversion unit is transferred to the charge storage region without being stored in the photoelectric conversion unit. . FIG. 9 is a quotation of FIG. 6 of Patent Document 2. In the configuration disclosed in Patent Document 2, a MOS transistor having a buried channel structure is used in the transfer unit between the photoelectric conversion unit and the charge storage unit. According to Patent Document 2, the photoelectric conversion unit can be limited to a minimum size necessary for light reception. With this configuration, it is possible to realize an in-plane synchronous electronic shutter that aligns the start and end times of accumulation of all pixels in the plane.
JP 2004-111590 A JP 2006-246450 A

  FIG. 10 and FIG. 11 show diagrams quoting FIG. 2 and FIG. In Patent Document 1, first, a control switch (ABG) for discharging electric charges accumulated in a photodiode serving as a photoelectric conversion unit to a power supply (VDD) is turned off. Then, the time t2 in FIG. 11, which is the timing when the operation of transferring the charge accumulated in the photoelectric conversion unit to the accumulation unit is completed, is the start of the exposure accumulation period. Thereafter, the charge transferred to the storage unit after the exposure storage time has started is transferred to the floating diffusion FD.

  However, such an operation may not be able to accurately define the accumulation time in the pixel. In other words, it may be impossible to accurately grasp in which period the charge accumulated in the pixel is generated. For example, when considering a case where it is designed to have a minimum size necessary for light reception like the photoelectric conversion unit in Patent Document 2, in the state shown in FIG. The generated charge may exceed the amount of charge that can be accumulated in the photoelectric conversion unit. Charges that exceed the amount of charge that can be accumulated in the photoelectric conversion unit are discharged to the power source and the accumulation unit beyond the potential barrier formed in the ABG and FSG. That is, since a part of the electric charge generated after the accumulation time starts is discharged, there arises a problem that the accumulation time cannot be defined accurately. Therefore, the driving method disclosed in Patent Document 1 is designed to generate a charge larger than the amount of charge that can be accumulated in the photoelectric conversion unit, or to be the minimum size required for the photoelectric conversion unit to receive light. In such an imaging apparatus, the start of the accumulation time cannot be accurately defined.

  The operation according to Patent Document 2 shown in FIG. 9 may return to the state of FIG. 9A after the operation of reading out signals from the pixels in FIG. Conceivable. However, when the in-plane synchronized electronic shutter operation is performed, the start and end times of the period in which the pixels accumulate charges are the same for all rows, but the signals are read from the pixels for each row. Therefore, when the operation shown in FIG. 9 is repeated, the length of time from the state shown in FIG. 9G to the time when the state shown in FIG. If the length of this time is different, the dark current component stored in the storage unit during the period from the state of FIG. 9G to the state of FIG. The effect will change. Furthermore, not only the dark current but also the influence of the light incident on the pixel region during this period is different for each row, and the brightness of the resulting image may be different for each row. For this reason, it is considered that a false signal depending on the brightness of the subject is generated, and there is a concern about deterioration of image quality.

  An object of the present invention is to solve the above-described problem, and even when an amount of charge exceeding the amount of charge that can be accumulated in the photoelectric conversion unit is generated, the start of the accumulation time can be defined, and dark current and incident light can be defined. It is to provide a suitable method for reducing the difference in the influences of.

The solid-state imaging device driving method according to the first aspect of the present invention includes a photoelectric conversion unit that photoelectrically converts incident light, a storage unit that accumulates charges, and a first unit that connects the photoelectric conversion unit and the storage unit. A transfer unit, a second transfer unit connecting the storage unit and the floating diffusion unit, a third transfer unit connecting the photoelectric conversion unit and the power source, and connecting the floating diffusion unit and the power source. A reset unit, and at least in a period in which the pixel accumulates charges, a height of a potential barrier formed in the first transfer unit with respect to the charges accumulated in the accumulation unit is the third level. In the method of driving a solid-state imaging device having a pixel portion in which a plurality of pixels lower than the height of the potential barrier formed in the transfer portion is arranged in a matrix, a potential barrier is formed in the first transfer portion, and Potency in the third transfer section In the state where there is no potential barrier, the potential barrier is formed from the state where no potential barrier exists in the second transfer unit, and further, the potential storage is formed in the third transfer unit, so that the pixel accumulates electric charge. The potential barrier is formed in the second transfer unit without simultaneously removing the potential barrier in the second transfer unit and the reset unit. From this state, a potential barrier is formed in the second transfer unit, and a signal corresponding to the floating diffusion unit is read out .

According to another aspect of the present invention, there is provided a driving method for a solid-state imaging device, a photoelectric conversion unit that photoelectrically converts incident light, a storage unit that stores charges, and a charge generated by the photoelectric conversion unit is transferred to the storage unit. A first transfer transistor for transferring, a second transfer transistor for transferring the charge accumulated in the accumulation unit to the floating diffusion unit, and a third for transferring the charge generated in the photoelectric conversion unit to a power source. In the method of driving a solid-state imaging device having a pixel portion in which a plurality of pixels including a transfer transistor and a reset transistor that connects the floating diffusion portion and a power source are arranged in a matrix, the first transfer transistor is a buried channel. A low-level signal to the control electrode of the first transfer transistor, and a high-level signal to the control electrode of the third transfer transistor In a supply state, a signal supplied to the control electrode of the second transfer transistor is changed from a high level to a low level, and further, a signal supplied to the control electrode of the third transfer transistor is changed to a low level. The operation for accumulating charges in the pixels is started simultaneously on a plurality of lines of pixels arranged in a matrix, and signals supplied to the control electrode of the second transfer transistor and the control electrode of the reset transistor are simultaneously set to a high level. In this case, the signal supplied to the control electrode of the second transfer transistor is changed from a high level to a low level, and a signal corresponding to the floating diffusion portion is read out .

According to another aspect of the present invention, there is provided a driving method for a solid-state imaging device, wherein a photoelectric conversion unit that photoelectrically converts incident light, a storage unit that accumulates charges, and a first unit that connects the photoelectric conversion unit and the storage unit. A transfer unit, a second transfer unit connecting the storage unit and the floating diffusion unit, a third transfer unit connecting the photoelectric conversion unit and the power source, and connecting the floating diffusion unit and the power source. A reset portion, and a height of a potential barrier formed in the first transfer portion with respect to charges accumulated in the accumulation portion at least during a part of a period in which the pixels accumulate charges. In the driving method of the solid-state imaging device having the pixel unit in which a plurality of pixels lower than the height of the potential barrier formed in the third transfer unit is arranged in a matrix, a potential barrier is formed in the third transfer unit, And the first and first In the state where there is no potential barrier in the transfer portion of the second transfer portion, the operation of accumulating charges by forming the potential barrier from the state where the potential barrier does not exist in the second transfer portion is arranged in a matrix. Starting with a plurality of lines at the same time, and further forming a potential barrier in the first transfer unit, and eliminating the potential barrier at the same time in the second transfer unit and the reset unit, the potential in the second transfer unit A potential barrier is formed in the second transfer part from a state where no barrier is formed, and a signal corresponding to the floating diffusion part is read out .

According to still another aspect of the present invention, there is provided a driving method for a solid-state imaging device, a photoelectric conversion unit that photoelectrically converts incident light, a storage unit that stores charges, and a charge generated by the photoelectric conversion unit is transferred to the storage unit. A first transfer transistor for transferring the charge, a second transfer transistor for transferring the charge stored in the storage unit to the floating diffusion unit, and a second transfer transistor for transferring the charge generated in the photoelectric conversion unit to a power source. In the method of driving a solid-state imaging device having a pixel portion in which a plurality of pixels including three transfer transistors and a reset transistor for connecting the floating diffusion portion and a power source are arranged in a matrix, the first transfer transistor is embedded. A channel-type transistor that supplies a low-level signal to the control electrode of the third transfer transistor, and that controls the control electrodes of the first and second transfer transistors. In a state in which a low-level signal is supplied, a signal supplied to the control electrode of the second transfer transistor is changed from a high level to a low level, thereby causing the pixel to accumulate charges. A signal that is started simultaneously on a plurality of lines, and further, a signal supplied to the control electrode of the first transfer transistor is changed to a low level, and a signal supplied to the control electrode of the second transfer transistor and the control electrode of the reset transistor The signal supplied to the control electrode of the second transfer transistor is shifted from the high level to the low level without simultaneously setting the signal to the high level, and the signal corresponding to the floating diffusion portion is read out .

A solid-state imaging device according to still another aspect of the present invention includes a photoelectric conversion unit that photoelectrically converts incident light, a storage unit that accumulates charges, and a charge generated in the photoelectric conversion unit for transferring the charges to the accumulation unit. A first transfer transistor; a second transfer transistor for transferring the charge accumulated in the accumulation unit to the floating diffusion unit; and a third transfer for transferring the charge generated in the photoelectric conversion unit to a power source. A signal is supplied to a pixel portion in which a plurality of pixels including a transistor, a reset transistor that connects the floating diffusion portion and a power source are arranged in a matrix, and control electrodes of the first to third transfer transistors. A solid-state imaging device including a control unit, wherein the first transfer transistor is a buried channel transistor, and the control unit is connected to a control electrode of the first transfer transistor with a low voltage. The signal to be supplied to the control electrode of the second transfer transistor is changed from the high level to the low level while the bell signal is supplied and the high level signal is supplied to the control electrode of the third transfer transistor. In addition, by causing a signal supplied to the control electrode of the third transfer transistor to transition to a low level, the operation of the pixels accumulating charges is started simultaneously on a plurality of lines of pixels arranged in a matrix , The signal supplied to the control electrode of the second transfer transistor is changed from the high level to the low level without simultaneously setting the signal supplied to the control electrode of the second transfer transistor and the control electrode of the reset transistor to the high level. Transition is performed, and a signal corresponding to the floating diffusion portion is read out .

A solid-state imaging device according to still another aspect of the present invention includes a photoelectric conversion unit that photoelectrically converts incident light, a storage unit that accumulates charges, and a charge generated in the photoelectric conversion unit for transferring the charges to the accumulation unit. A first transfer transistor; a second transfer transistor for transferring the charge accumulated in the accumulation unit to the floating diffusion unit; and a third transfer for transferring the charge generated in the photoelectric conversion unit to a power source. A signal is supplied to a pixel portion in which a plurality of pixels including a transistor, a reset transistor that connects the floating diffusion portion and a power source are arranged in a matrix, and control electrodes of the first to third transfer transistors. A solid-state imaging device having a control unit, wherein the first transfer transistor is a buried channel type transistor, and the control unit is connected to a control electrode of the third transfer transistor. In a state in which a bell signal is supplied and a high level signal is supplied to the control electrodes of the first and second transfer transistors, the signal supplied to the control electrode of the second transfer transistor is changed from a high level to a low level. By making the transition to the level, the operation of accumulating the charge in the pixel is simultaneously started in a plurality of lines of the pixels arranged in a matrix, and the signal supplied to the control electrode of the first transfer transistor is set to the low level. The signal supplied to the control electrode of the second transfer transistor is changed from the high level without simultaneously changing the signal supplied to the control electrode of the second transfer transistor and the control electrode of the reset transistor to the high level. The signal is transferred to a low level and a signal corresponding to the floating diffusion portion is read out .

  According to the present invention, the start of the accumulation time can be suitably defined even when an amount of charge that exceeds the amount of charge that can be accumulated in the photoelectric conversion unit is generated.

The figure which shows schematic structure of the solid-state imaging device which concerns on embodiment of this invention. 1 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention. Sectional drawing of the pixel which concerns on FIG. Timing chart according to the first embodiment The figure which shows the potential state of the pixel which concerns on 1st Embodiment. Timing chart according to the second embodiment The figure which shows the potential state of the pixel which concerns on 2nd Embodiment. Diagram showing schematic configuration of imaging system The figure which quoted FIG. 6 of patent document 2 The figure which quoted FIG. 2 of patent document 1 The figure which quoted FIG. 5 of patent document 1

(First embodiment)
A first embodiment to which the present invention can be applied will be described. FIG. 1 is a schematic block diagram of a solid-state imaging device, which includes an imaging region 101 in which a plurality of pixels are arranged, a vertical scanning circuit 102 and a horizontal scanning circuit 103 which are control units. Here, it is assumed that the pixels arranged in the imaging region 101 are arranged in a matrix. The horizontal scanning circuit 103 causes the output circuit 104 to output signals from pixels for one row by sequentially scanning signal lines provided corresponding to the columns of pixels in the imaging region.

  FIG. 2 is an equivalent circuit diagram of pixels included in the imaging region 101. For simplification of description, the pixels included in the imaging region 101 are an example of a region of a total of 9 pixels of 3 rows × 3 columns, but the number of pixels is not limited to this. The anode of the photodiode (PD) 2 that is a photoelectric conversion unit is grounded to a fixed potential, and the cathode is connected to one terminal of the storage unit MEM via a first transfer switch 8 that is a first transfer unit. The cathode is further connected to a power supply line which is a second power supply functioning as an overflow drain (hereinafter, OFD) via a third transfer switch 13 which is a third transfer section. The other terminal of the storage unit MEM is grounded to a fixed potential. One terminal of the storage unit MEM is further connected to the gate terminal of the amplification transistor 12 via the second transfer switch 9 which is a second transfer unit. The gate terminal of the amplification transistor 12 is connected to the pixel power supply line via the reset transistor 10 which is a reset unit. Here, an example in which the first to third transfer units are configured by transistors is shown. In FIG. 2, the power supply line functioning as the OFD and the pixel power supply line are separated, but these may be connected to a common power supply or different power supplies.

  The selection transistor 11 has a drain terminal that is one main electrode connected to the pixel power supply line, and a source terminal that is the other main electrode connected to a drain that is one main electrode of the amplification transistor 12. When an active signal SEL is input to the control electrode, both main electrodes of the selection transistor are turned on. As a result, the amplification transistor 12 forms a source follower circuit with a constant current source (not shown) provided on the vertical signal line OUT, and a signal corresponding to the potential of the gate terminal which is the control electrode of the amplification transistor 12 is transmitted to the vertical signal line OUT. Appear in A signal is output from the solid-state imaging device based on the signal appearing on the vertical signal line OUT, and is displayed as an image through a signal processing circuit unit described later. Further, a node (hereinafter referred to as FD) 4 which is a floating diffusion portion in which the gate terminal of the amplification transistor 12 and the main electrode of the reset transistor 10 and the second transfer switch 9 are connected in common has a capacitance value. And can retain electric charge.

Next, FIG. 3 shows an example of a cross-sectional view when the pixel shown in FIG. 2 is formed over a semiconductor substrate.
The same reference numerals are given to the components corresponding to the respective components in FIG. Here, the case where the conductivity type of the semiconductor region uses electrons as signal charges will be described as an example. When holes are used, the conductivity type of each semiconductor region may be reversed.

  Reference numeral 201 denotes a P-type semiconductor region. It can be formed by implanting P-type impurity ions into an N-type semiconductor substrate, or a P-type semiconductor substrate may be used.

  Reference numeral 202 denotes an N-type semiconductor region (first conductivity type first semiconductor region) that constitutes a part of the photoelectric conversion unit. It has the same polarity as the signal charge electrons. A part of the P-type semiconductor region 201 (second conductivity type second semiconductor region) forms a PN junction.

  Reference numeral 203 denotes a P-type semiconductor region provided on the surface of the N-type semiconductor region 202. It is provided to make the photoelectric conversion part an embedded photodiode, and reduces the influence of the interface state and suppresses the generation of dark current generated on the surface of the photoelectric conversion part. The photoelectric conversion unit includes at least a first semiconductor region and a second semiconductor region that forms a PN junction with the first semiconductor region.

  Reference numeral 204 denotes a second transfer electrode constituting the second transfer switch. The potential state between the charge holding unit and the charge-voltage conversion unit (fourth semiconductor region described later) can be controlled by the voltage supplied to the second transfer electrode. The second transfer electrode is disposed on a second path between a third semiconductor region and a fourth semiconductor region described later via an insulating film.

  Reference numeral 205 denotes an N-type semiconductor region (first conductivity type third semiconductor region) that constitutes a part of the storage portion. The charge transferred from the photoelectric conversion unit can be accumulated for a certain period. Reference numeral 206 denotes a control electrode. It is arranged on the third semiconductor region via an insulating film, and the potential state of the third semiconductor region in the vicinity of the insulating film interface can be controlled. By supplying a voltage to the control electrode 206 during a period in which charges are held in the accumulation portion, it is possible to reduce the influence of dark current generated in the vicinity of the interface with the surface oxide film of the N-type semiconductor region 205. As will be described later, the voltage supplied at this time is preferably a negative voltage because it is necessary to collect holes at the interface between the third semiconductor region and the insulating film. For example, a voltage of about −3 V is supplied. This voltage is appropriately changed depending on the impurity concentration of the third semiconductor region.

  The storage unit MEM includes an N-type semiconductor region 205 and a control electrode 206.

  Reference numeral 207 denotes a first transfer electrode constituting the first transfer switch 8. The potential state of the first path between the photoelectric conversion unit and the electricity storage unit can be controlled. A semiconductor region 213 having a lower concentration than 202 is provided between 202 and 205 below the first transfer electrode. By adopting a configuration having such a buried channel, the potential relationship described with reference to FIG. 3 can be provided.

  Reference numeral 208 denotes a floating diffusion region (FD region). It functions as a charge / voltage converter. It is electrically connected to the gate of the amplification MOS transistor via a plug 209 and the like.

  Reference numeral 210 denotes a light shielding film. Arranged so that incident light does not enter the charge storage section. Although it is necessary to cover at least the storage portion MEM, as shown in the drawing, if the entire first transfer electrode and a part of the second transfer electrode are extended, the light is further blocked. Increased functionality is preferable.

  Reference numeral 211 denotes a charge discharge control electrode constituting the third transfer switch. The potential state of the third path between the photoelectric conversion unit and the OFD region can be controlled. The charge discharge control electrode is arranged on the third path via an insulating film. The potential state is controlled so that charges generated in the photoelectric conversion unit by incident light can be discharged to the OFD. The length of the accumulation period (exposure period) in the photoelectric conversion unit can be controlled by the voltage supplied to 211.

  212 is a part (fifth semiconductor region) constituting the OFD, and 215 is a plug for supplying a power supply voltage to 212, and is connected to a power supply (not shown). That is, the second power source includes 212 and 215.

  The first transfer switch 8 constitutes a first transfer transistor together with the photoelectric conversion unit and the storage unit. The second transfer switch 9 constitutes a second transfer transistor together with the storage unit and the floating diffusion unit 4. The third transfer switch 13 constitutes a third transfer transistor together with the photoelectric conversion unit and the second power supply.

  A plurality of, preferably two-dimensionally, unit pixels described with reference to FIGS. 2 and 3 are arranged to form an imaging region of the solid-state imaging device. A pixel can share a reset unit, an amplification unit, a selection unit, and the like among a plurality of photoelectric conversion units.

  Next, the operation according to the present embodiment will be described. FIG. 4 is a timing chart for explaining the operation according to the present embodiment. FIG. 5 shows the potential state of the pixel at each timing from the timing shown in FIG. 4 immediately before time t0 to the end of the accumulation time. FIG. Here, a case where a transistor including a photodiode, TX1, and an accumulation portion is a buried channel type transistor will be described as an example.

  FIG. 4 shows changes in the signals TX1 to TX3 given to the control electrodes of the first to third transfer units and the signal RES given to the control electrode of the reset unit. The subscripts n, n + 1, and n + 2 represent row numbers in the imaging region. For example, TX1 (n) means a signal given to the first transfer unit of the pixel in the nth row. That is, when the signal TX1 (n) becomes high level, the first transfer units of the pixels included in the row (line) are activated collectively.

  First, in the initial state before time t0, the signals TX1 (n) to TX1 (n + 2) and the signals TX2 (n) to TX2 (n + 2) are at the low level, the signals TX3 (n) to TX3 (n + 2) and the signal RES. (N) to RES (n + 2) are at a high level. FIG. 5A shows the potential state of the pixel at this time. In this period, there is a potential barrier formed in TX1 that corresponds to the first transfer unit with respect to the charge stored in the storage unit (MEM). On the other hand, since there is no potential barrier in TX3 corresponding to the third transfer unit, the charge (black circle in the figure) generated in the photodiode (PD) does not move to the storage unit (MEM), It is discharged to OFD through the transfer unit. Therefore, the pixel is in a state where it does not accumulate charges. As is apparent from the figure, it does not depend on the potential state in TX2. Here, the potential barrier formed in TX1 is lower than the potential barrier formed in TX2, as described above, an example in which the transistor including the photodiode, TX1, and storage unit is a buried channel type is considered. This is because.

  Since the signals TX2 (n) to TX2 (n + 2) are at a high level during the period from time t0 to time t1, the potential formed in TX2 that is the second transfer unit between the storage unit and the FD region (FD). There are no barriers. As a result, the charge held in the storage unit before time t0 is transferred to the FD region. The potential state of the pixel during this period is shown in FIG. During this period, the signals TX1 (n) to TX1 (n + 2) are at a low level and the signals TX3 (n) to TX3 (n + 2) are at a high level, so that the charge generated in the photodiode passes through the third transfer unit. And discharged to OFD. Therefore, the charge generated in the photodiode ideally does not exist in the accumulation portion at this time.

  When the signals TX1 (n) to TX1 (n + 2) become low level at time t1, the potential state of the pixel becomes as shown in FIG. This is the same as the state shown in FIG. Even during this period, there is a potential barrier formed at TX1 corresponding to the first transfer unit, while TX3 corresponding to the third transfer unit has no potential barrier. Therefore, the charge generated in the photodiode is discharged to the OFD through the third transfer unit without moving to the storage unit.

Next, when the signals TX3 (n) to TX3 (n + 2) transition to the low level at time t2, the potential state of the pixel becomes as shown in FIG. During this period, the potential barrier against the charge accumulated in the accumulation unit is higher in TX3 corresponding to the third transfer unit than in TX1 corresponding to the first transfer unit. Since the signals TX2 (n) to TX2 (n + 2) are at a low level, among the charges generated in the photodiode during this period, the charges exceeding the potential barrier at TX1 remain in the photodiode or the accumulation unit. Become.
Therefore, the accumulation time of each pixel starts from the timing at which the signals TX3 (n) to TX3 (n + 2) transition to the low level at time t2. That is, in the present embodiment, at time t0, in a state where the signal TX1 is at the low level and TX3 is at the high level, the signal TX2 transitions to the high level and the low level at time t1, and further, the signal TX3 is at the time t2. Transition to low level. This defines the start of the operation in which the pixel accumulates charges. According to such a driving method, even if more charges are generated in the photodiode than can be stored in the photodiode, they are discharged together with unnecessary charges as in the operation disclosed in Patent Document 1. Therefore, the start of the accumulation time can be suitably defined.

  Next, when the signals TX1 (n) to TX1 (n + 2) are at a high level during the period from the time t3 to the time t4, the potential barrier formed in the first transfer portion disappears, and the charge generated in the photodiode is accumulated. Is transferred to the unit MEM (FIG. 5E).

  At time t4, when the signals TX1 (n) to TX1 (n + 2) change to the low level and the signals TX3 (n) to TX3 (n + 2) change to the high level, the potential state of the pixel is as shown in FIG. It will be as shown in Since the charge generated in the photodiode after time t4 is discharged to the OFD through the third transfer unit, the accumulation time of all the pixels ends at time t4.

  In this way, by transferring all pixels in common from the photodiode to the storage unit, the storage start and end times of all the pixels can be matched, and an in-plane synchronized electronic shutter operation can be realized.

  Next, when the signal TX2 (n) becomes high level at time t6 during the period when the signal RES1 (n) from time t5 to time t7 is at low level, the signal is stored in the accumulation unit MEM of each pixel in the nth row. The held charges are transferred to the FD region via the second transfer unit TX2. At least at this timing, the selection unit is in the on state, and a level corresponding to the amount of charge transferred to the FD region appears on the vertical signal line by the source follower circuit formed by the amplification transistor and the constant current source. A signal corresponding to the level appearing on the vertical signal line is output from the output circuit.

  The same operation is performed for the pixels in the (n + 1) th row and the (n + 2) th row, and a signal corresponding to the pixel in each row is output from the output circuit. This completes the operation for one frame.

  In the operation shown in FIG. 4, the signal RES is at a high level except during a period in which signals are read from the pixels in each row. However, the signal RES is set to a high level in a pulse before the signal TX2 becomes a high level. May be.

  In the operation disclosed in Patent Document 1, if more charge is generated in the photodiode than can be stored in the photodiode, it is discharged as unnecessary charge, and the start of the pixel accumulation time cannot be properly defined. was there. That is, it is impossible to accurately grasp in which period the charge accumulated in the pixel is generated. On the other hand, if the above-described operation is performed, the start of the accumulation time can be suitably defined even if more charges are generated in the photodiode than the photodiode can accumulate.

  According to Patent Document 2, it can be considered that the operations from FIG. 10G to FIG. 10A are simultaneously performed on a plurality of lines of pixels arranged in a matrix. In that case, although the start of the accumulation time can be defined, stripe noise is generated due to the difference in the influence of dark current and incident light due to the difference in the period from FIG. 10 (g) to FIG. 10 (a). There is a risk. On the other hand, according to the present embodiment, the difference in the effects of dark current and incident light can be reduced.

(Second Embodiment)
An operation according to the second embodiment of the present invention will be described. FIG. 6 is a timing chart for explaining the operation according to the present embodiment. FIG. 7 shows the potential state of the pixel at each timing from the timing shown in FIG. 6 to immediately before the time t0 until the end of the accumulation time. FIG. Also in this embodiment, a case where a transistor including a photodiode, TX1, and an accumulation unit is a buried channel type transistor will be described as an example.

  FIG. 6 shows transitions of the signals TX1 to TX3 given to the first to third transfer units and the signal RES given to the reset unit. Subscripts n, n + 1, and n + 2 represent row numbers in the imaging region as in FIG. 4, and for example, TX1 (n) means a signal that is given to the first transfer unit of the pixels in the first row. .

  First, prior to time t0, signals TX1 (n) to TX1 (n + 2) supplied to the first transfer unit TX1 and signals TX2 (n) to TX2 (2 supplied to the second transfer unit TX2 ( Assume that n + 2) is at a low level. Furthermore, it is assumed that signals TX3 (n) to TX3 (n + 2) supplied to the third transfer unit TX3 and signals RES (n) to RES (n + 2) supplied to the reset unit RES are at a high level. The potential state at this time is as shown in FIG. Since there is a potential barrier between the photodiode (PD) and the storage portion (MEM), charges (black circles) generated in the photodiode are discharged to the OFD. Although not shown in FIG. 7A, since the signal RES is at a high level, charges are not accumulated in the FD region (FD) but are discharged to the pixel power supply line. Here, the potential barrier formed in TX1 is lower than the potential barrier formed in TX2, as described above, in which the transistor including the photodiode, TX1, and the storage unit is a buried channel type. This is because I am thinking.

  When the signals TX1 (n) to TX1 (n + 2) transition to the high level at time t0, the potential state of the pixel is as shown in FIG. 7B. During this period, the potential barrier is not formed in TX1, which is the first transfer unit between the photodiode and the storage unit, so that the charge generated in the photodiode moves to the OFD or the storage unit. Although not shown in FIG. 7, since the signal RES is at a high level, the charge that has moved to the FD is discharged to the pixel power supply line.

  At the subsequent time t1, the signals TX2 (n) to TX2 (n + 2) transition to the high level, the signals TX3 (n) to TX3 (n + 2) transition to the low level, and the potential state of the pixel is as shown in FIG. Become. Here, a potential barrier is formed in the third transfer unit TX3, and the potential barrier formed in the second transfer unit TX2 is eliminated. Therefore, the electric charge generated in the photodiode moves to the FD portion through the first transfer portion, the storage portion, and the second transfer portion.

  When the signals TX2 (n) to TX2 (n + 2) transition to the low level at time t2, a potential barrier is formed in TX2 that is the second transfer unit. The potential state of the pixel at this time is as shown in FIG. As is apparent from the figure, in this state, the charge generated in the photodiode remains in the region from the photodiode to the storage portion, so that the pixel storage time, that is, the operation of storing the charge in the pixel is started at time t2. Can be prescribed.

  When the signals TX1 (n) to TX1 (n + 2) transition to the low level at time t3 after the accumulation time starts, a potential barrier is formed in TX1 that is the first transfer unit. However, as shown in FIG. 7 (e), the potential barrier formed at TX1 is lower than the potential barrier formed at TX3, so that the potential barrier formed at TX1 out of the charges generated in the photodiode is reduced. Anything over it moves to the storage.

  When the signals TX1 (n) to TX1 (n + 2) become high level again at time t4, the potential state of the pixel becomes as shown in FIG. 7 (f) and is formed in TX1 during the period from time t3 to time t4. The charges that did not exceed the generated potential barrier move to the accumulation part.

  Then, at time t5, the signals TX1 (n) to TX1 (n + 2) transition to the low level, and the signals TX3 (n) to TX3 (n + 2) transition to the high level instead. The potential state of the pixel at this time is as shown in FIG. 7G. A potential barrier is formed in TX1 which is the first transfer unit, and a potential barrier formed in TX3 which is the third transfer unit. Disappears. Therefore, the charge generated in the photodiode is discharged to the OFD without moving to the storage portion, and therefore the end of the pixel storage time can be defined with this timing.

  Thereafter, when the signal TX2 (n) becomes high level at time t7 during the period when the signal RES (n) from time t6 to time t8 is at low level, the signal is held in the accumulation unit of each pixel in the nth row. The charge is transferred to the FD region via the second transfer unit TX2. At least at this timing, the selection unit is in an ON state, and therefore a level corresponding to the amount of charge transferred to the FD region appears on the vertical signal line by the source follower circuit formed by the amplification transistor and the constant current source. A signal corresponding to the level appearing on the vertical signal line is output from the output circuit.

  The same operation is performed for the pixels in the (n + 1) th row and the (n + 2) th row, the same operation is performed for the pixels in each row, and a signal corresponding to the pixel in each row is output from the output circuit. The operation for one frame for realizing the in-plane synchronous electronic shutter is thus completed.

  In the operation shown in FIG. 4, the signal RES is at a high level except during a period in which signals are read from the pixels in each row. However, the signal RES is set to a high level in a pulse before the signal TX2 becomes a high level. May be.

  In the driving method according to the present embodiment, in a state where the signal TX3 is at the low level and the signals TX1 and TX2 are at the high level, the operation in which the pixel accumulates charges by changing the signal TX2 to the low level is a matrix. It starts simultaneously with a plurality of lines of pixels arranged in a shape. Further, the signal TX1 is set to a low level. According to the driving method according to the present embodiment, even if more charges are generated in the photodiode than can be stored in the photodiode, the start of the storage time can be suitably defined. Further, according to the present embodiment, the difference in the influence of dark current and incident light can be reduced.

(Other)
FIG. 8 is a diagram showing a schematic configuration of the imaging system, which includes, for example, an optical unit 711, a solid-state imaging device 700, a signal processing circuit unit 708, a recording / communication unit 709, a timing generator 706, a CPU 707, and a reproduction / display unit. 710 and an operation unit 712 are included.

  An optical unit 711 that is an optical system such as a lens forms an image of a subject by causing light from the subject to form an image on the pixel unit 701 in which a plurality of pixels are two-dimensionally arranged in the solid-state imaging device 700. The pixel portion includes the above-described imaging region. The solid-state imaging device 700 outputs a signal corresponding to the light imaged on the pixel unit 701 at a timing based on a signal from the timing generator 706.

  The solid-state imaging device 700 includes a horizontal readout circuit 705 including a pixel unit 701 corresponding to the imaging region in FIG. 1 and a holding unit that temporarily holds a signal output from each pixel of the pixel unit 701 to a vertical signal line. . The horizontal readout circuit 705 may include an output unit corresponding to the output circuit 104 in FIG. The solid-state imaging device 700 further includes a vertical scanning circuit 702 that selects a row of pixels in the pixel portion, and a horizontal scanning circuit 703 that controls the horizontal readout circuit 705 to output a signal as a sensor signal output.

  A signal output from the solid-state imaging device 700 is input to a signal processing circuit unit 708 which is a signal processing unit, and the signal processing circuit unit 708 performs AD on the input electric signal according to a method determined by a program or the like. Perform processing such as conversion. A signal obtained by processing in the signal processing circuit unit 708 is sent to the recording / communication unit 709 as image data. The recording / communication unit 709 sends a signal for forming an image to the reproduction / display unit 710 and causes the reproduction / display unit 170 to reproduce and display a moving image or a still image. The recording communication unit 709 receives a signal from the signal processing circuit unit 708 and communicates with the CPU 707, and also performs an operation of recording a signal for forming an image on a recording medium (not shown).

  The CPU 707 comprehensively controls the operation of the imaging system, and outputs a control signal for controlling driving of the optical unit 711, the timing generator 706, the recording / communication unit 709, and the reproduction / display unit 710. . The CPU 707 includes a storage device (not shown) as a recording medium, for example, and a program necessary for controlling the operation of the imaging system is recorded therein. The CPU 707 outputs a drive mode instruction signal and a shooting instruction signal to the timing generator 706. The drive mode instruction signal and the shooting instruction signal are not different from each other, and may be a single signal.

  When the timing generator 706 receives a driving mode instruction signal and a photographing instruction signal from the CPU, the timing generator 706 sends a signal to the vertical scanning circuit 702 and the horizontal scanning circuit 703 so as to operate the solid-state imaging device 700 in a driving mode according to the signals. Supply.

  For example, the CPU 707 supplies a drive mode instruction signal and an imaging instruction signal to the timing generator 706 so as to perform imaging in the driving mode related to the in-plane synchronous electronic shutter. As a result, the timing generator 706 supplies a signal for performing an operation related to the in-plane synchronous electronic shutter to the solid-state imaging device 700. In response to this, the solid-state imaging device 700 is driven at the timing shown in FIG. 4, for example, and outputs a signal having the same accumulation time within the imaging surface to the signal processing circuit unit 708.

Further, for example, the CPU 707 supplies a drive mode instruction signal and a shooting instruction signal to the timing generator 706 so as to perform shooting in the driving mode related to the rolling electronic shutter.
As a result, the timing generator 706 supplies a signal for performing an operation related to the rolling electronic shutter to the solid-state imaging device 700. In response to this, the solid-state imaging device 700 is driven at the timing shown in FIG. 8, for example, and outputs to the signal processing circuit unit 708 a signal whose accumulation time in the imaging surface is different for each row of pixels.

  The operation unit 712 is an interface operated by the user, and outputs an operation signal corresponding to the operation by the user to the CPU 707. More specifically, a mode for shooting a moving image, a mode for shooting a still image, and the like can be switched, and a shutter timing can be determined.

  The reproduction / display unit 710 is for displaying the input image data as an image. For example, the image data held in a recording medium (not shown) can be displayed as an image via the recording / communication unit 708. Further, when used as an electronic viewfinder (EVF) described later, the image data supplied from the signal processing circuit unit 708 can be displayed as an image without using the recording / communication unit 708.

2 Photodiode (PD)
4 Floating diffusion region (FD)
DESCRIPTION OF SYMBOLS 8 1st transfer switch 9 2nd transfer switch 10 Reset transistor 11 Selection transistor 12 Amplification transistor 13 3rd transfer switch 21 Pixel 100 Solid-state imaging device 101 Imaging area 102 Vertical scanning circuit 103 Horizontal scanning circuit 104 Output circuit 700 Solid-state imaging device 701 Pixel Unit 702 Vertical scanning circuit 703 Horizontal scanning circuit 705 Horizontal readout circuit 706 Timing generator 707 CPU
708 Signal processing circuit unit 709 Recording / communication unit 710 Playback / display unit 711 Optical unit 712 Operation unit

Claims (8)

A photoelectric conversion unit that photoelectrically converts incident light;
An accumulator that accumulates charges;
A first transfer unit connecting the photoelectric conversion unit and the storage unit;
A second transfer unit connecting the storage unit and the floating diffusion unit;
A third transfer unit for connecting the photoelectric conversion unit and a power source;
A pixel including a reset unit that connects the floating diffusion unit and a power source, and is formed in the first transfer unit for charges accumulated in the accumulation unit at least in a period in which the pixels accumulate charges. In a driving method of a solid-state imaging device having a pixel portion in which a plurality of pixels in which the height of the potential barrier is lower than the height of the potential barrier formed in the third transfer portion is arranged in a matrix,
Forming a potential barrier from a state in which no potential barrier exists in the second transfer unit in a state in which a potential barrier is formed in the first transfer unit and no potential barrier exists in the third transfer unit;
Furthermore, by forming a potential barrier in the third transfer unit, the operation of accumulating charges in the pixels is started simultaneously on a plurality of lines of pixels arranged in a matrix ,
Without removing the potential barrier at the same time in the second transfer unit and the reset unit,
From a state in which no potential barrier is formed in the second transfer unit, a potential barrier is formed in the second transfer unit,
A method of driving a solid-state imaging device, wherein a signal corresponding to the floating diffusion unit is read . A photoelectric conversion unit that photoelectrically converts incident light;
An accumulator that accumulates charges;
A first transfer transistor for transferring the charge generated in the photoelectric conversion unit to the storage unit;
A second transfer transistor for transferring the charge accumulated in the accumulation unit to the floating diffusion unit;
A third transfer transistor for transferring charges generated in the photoelectric conversion unit to a power source;
In a method for driving a solid-state imaging device having a pixel unit in which a plurality of pixels including a reset transistor that connects the floating diffusion unit and a power source are arranged in a matrix,
The first transfer transistor is a buried channel type transistor;
A low level signal is supplied to the control electrode of the first transfer transistor and a high level signal is supplied to the control electrode of the third transfer transistor. Transition the supplied signal from high level to low level,
Furthermore, the operation of accumulating charges by the pixels is simultaneously started in a plurality of lines of pixels arranged in a matrix by changing the signal supplied to the control electrode of the third transfer transistor to a low level ,
Without simultaneously bringing the signals supplied to the control electrode of the second transfer transistor and the control electrode of the reset transistor to a high level,
The signal supplied to the control electrode of the second transfer transistor is changed from a high level to a low level,
A method of driving a solid-state imaging device, wherein a signal corresponding to the floating diffusion unit is read . A photoelectric conversion unit that photoelectrically converts incident light;
An accumulator that accumulates charges;
A first transfer unit connecting the photoelectric conversion unit and the storage unit;
A second transfer unit connecting the storage unit and the floating diffusion unit;
A third transfer unit for connecting the photoelectric conversion unit and a power source;
A first transfer unit for a charge stored in the storage unit at least in a part of a period in which the pixel stores a charge; and a reset unit that connects the floating diffusion unit and a power source. In a driving method of a solid-state imaging device having a pixel portion in which a plurality of pixels in which the height of the potential barrier formed in the third transfer portion is lower than the height of the potential barrier formed in the third transfer portion is arranged in a matrix,
In the state where a potential barrier is formed in the third transfer unit and the potential barrier is not present in the first and second transfer units, the potential barrier is changed from a state in which no potential barrier exists in the second transfer unit. The operation of accumulating charges by the pixels is simultaneously started in a plurality of lines of pixels arranged in a matrix,
Furthermore, a potential barrier is formed in the first transfer part ,
Without removing the potential barrier at the same time in the second transfer unit and the reset unit,
From a state in which no potential barrier is formed in the second transfer unit, a potential barrier is formed in the second transfer unit,
A method of driving a solid-state imaging device, wherein a signal corresponding to the floating diffusion unit is read . A photoelectric conversion unit that photoelectrically converts incident light;
An accumulator that accumulates charges;
A first transfer transistor for transferring the charge generated in the photoelectric conversion unit to the storage unit;
A second transfer transistor for transferring the charge accumulated in the accumulation unit to the floating diffusion unit;
A third transfer transistor for transferring charges generated in the photoelectric conversion unit to a power source;
In a method for driving a solid-state imaging device having a pixel unit in which a plurality of pixels including a reset transistor that connects the floating diffusion unit and a power source are arranged in a matrix,
The first transfer transistor is a buried channel type transistor;
In a state where a low level signal is supplied to the control electrode of the third transfer transistor and a high level signal is supplied to the control electrode of the first and second transfer transistors, the second transfer transistor By causing a signal supplied to the control electrode to transition from a high level to a low level, an operation in which the pixel accumulates electric charges is simultaneously started in a plurality of lines of pixels arranged in a matrix,
Further, the signal supplied to the control electrode of the first transfer transistor is changed to a low level ,
Without simultaneously bringing the signals supplied to the control electrode of the second transfer transistor and the control electrode of the reset transistor to a high level,
The signal supplied to the control electrode of the second transfer transistor is changed from a high level to a low level,
A method of driving a solid-state imaging device, wherein a signal corresponding to the floating diffusion unit is read .   5. The driving method of the solid-state imaging device according to claim 1, wherein the operation of accumulating charges in the pixels is simultaneously started in all the pixels of the pixel unit. A photoelectric conversion unit that photoelectrically converts incident light;
An accumulator that accumulates charges;
A first transfer transistor for transferring the charge generated in the photoelectric conversion unit to the storage unit;
A second transfer transistor for transferring the charge accumulated in the accumulation unit to the floating diffusion unit;
A third transfer transistor for transferring charges generated in the photoelectric conversion unit to a power source;
A reset transistor for connecting the floating diffusion unit and a power source, and a pixel unit including a plurality of pixels including a matrix,
A solid-state imaging device having a control section for supplying a signal to the control electrodes of the first to third transfer transistors,
The first transfer transistor is a buried channel type transistor;
The controller is
A low level signal is supplied to the control electrode of the first transfer transistor and a high level signal is supplied to the control electrode of the third transfer transistor. Transition the supplied signal from high level to low level,
Furthermore, by causing a signal to be supplied to the control electrode of the third transfer transistor to transition to a low level, the operation of accumulating charges in the pixel is simultaneously started in a plurality of lines of pixels arranged in a matrix ,
Without simultaneously bringing the signals supplied to the control electrode of the second transfer transistor and the control electrode of the reset transistor to a high level,
The signal supplied to the control electrode of the second transfer transistor is changed from a high level to a low level,
A solid-state imaging device, wherein a signal corresponding to the floating diffusion unit is read out . A photoelectric conversion unit that photoelectrically converts incident light;
An accumulator that accumulates charges;
A first transfer transistor for transferring the charge generated in the photoelectric conversion unit to the storage unit;
A second transfer transistor for transferring the charge accumulated in the accumulation unit to the floating diffusion unit;
A third transfer transistor for transferring charges generated in the photoelectric conversion unit to a power source;
A reset transistor for connecting the floating diffusion unit and a power source, and a pixel unit including a plurality of pixels including a matrix,
A solid-state imaging device having a control section for supplying a signal to the control electrodes of the first to third transfer transistors,
The first transfer transistor is a buried channel type transistor;
The controller is
In a state where a low level signal is supplied to the control electrode of the third transfer transistor and a high level signal is supplied to the control electrode of the first and second transfer transistors, the second transfer transistor By causing a signal supplied to the control electrode to transition from a high level to a low level, an operation in which the pixel accumulates electric charges is simultaneously started in a plurality of lines of pixels arranged in a matrix,
Further, the signal supplied to the control electrode of the first transfer transistor is changed to a low level ,
Without simultaneously bringing the signals supplied to the control electrode of the second transfer transistor and the control electrode of the reset transistor to a high level,
The signal supplied to the control electrode of the second transfer transistor is changed from a high level to a low level,
A solid-state imaging device, wherein a signal corresponding to the floating diffusion unit is read out .   8. The solid-state imaging device according to claim 6, wherein the control unit simultaneously starts an operation in which the pixels accumulate charges in all the pixels of the pixel unit. 9.

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