TW201435599A - An external device and a transmission system and the method of the heterogeneous device - Google Patents

Abstract

An external device and a transmission system and the method of the heterogeneous device can access the USB3.0 and PCI-E at the same time. The external device includes an USB3.0 socket, a first control module and a micro control unit. The USB3.0 socket couples to the computer. The USB3.0 socket includes a plurality of first pins and a plurality of second pins. The first control module couples to the second pins. The first control module receives an operation signal via from the computer. The micro control unit couples to the first pins and the first control module. The micro control unit receives a identify request via the first pins. The micro control unit generates a working signal and sends the working signal to the first control module.

Description

External device, heterogeneous device transmission system and method thereof

A transmission system and method for an external device and a heterogeneous device, and particularly relates to a transmission system and a method for connecting an external device and a heterogeneous device of a PCI-E through a USB 3.0.

With the rapid development of integrated circuits, the size of the computer can be thin and light and achieve faster computing power. For small computers, there is a limit to the space inside the host. Therefore, small computers do not provide an expansion of the interface card. Therefore, if a small computer wants to add another device, it will be expanded by external means.

In general, the Universal Serial Bus (USB) is an interface for an already mature external device. USB features support for hot-plug and plug-and-play (Plug-and-Play). And the USB3.0 interface can also be compatible with the old USB2.0 and USB1.1 devices.

With the large and fast transmission requirements, USB has also been developed to the third edition (hereinafter referred to as USB3.0). The transfer speed of USB3.0 is increased to 5G (Giga bps). So USB3.0 can provide faster transfer speeds. Therefore, some manufacturers have proposed to convert other transmission interfaces into USB3.0 interface. Other heterogeneous devices can be connected to the host through the USB 3.0 interface, enabling a single type of interface to connect to many different types of devices. Since the types of other transmission interfaces are different from the USB 3.0 interface, they are referred to as heterogeneous devices in this specification. In the case of the Republic of China Patent No. M375925, a "external system with USB 3.0 and PCI-E interface" (hereinafter referred to as M375925) is proposed. In the M375925, a device with a Peripheral Component Interconnect Express (PCI-E) is connected to a computer via a USB 3.0 cable.

The M375925 case adjusts the transmission pins in the USB3.0 connector so that the PCI-E electronics can be connected to the USB 3.0 interface via a USB 3.0 connector. Such a party Although the PCI-E device can be connected to USB3.0. However, the M375925 directly connects the differential voltage pins (D+, D-) of USB3.0 to the reference clock pins (REFCLK+, REFCLK-) of PCI-E. Since the signals transmitted by the clock pin and the differential voltage pin are not the same, the PCI-E device cannot obtain the corresponding clock. Therefore, in the absence of a correct clock, the PCI-E device performs the corresponding operation and an erroneous operation result will occur. Therefore, the M375925 case does not actually solve the operation of the two protocols at different clocks.

The present invention provides a transmission system for a heterogeneous device, characterized in that a corresponding type of transmission protocol is selected according to the connected device.

The transmission system of the heterogeneous device of the present invention includes a PCI-E device and a host end. The PCI-E device has a first interface, a microcontroller and a first control module, and the microcontroller is coupled to the first control module, the first interface has a plurality of first pins and a plurality of second pins; The terminal is connected to the PCI-E device, the host has a second interface and a second control module, and the second interface is correspondingly disposed on the first interface of the PCI-E device; wherein, when the PCI-E device is connected to the host, the second The control module is coupled to the microcontroller through the first pin, the second control module is coupled to the first control module through the second pin, and the second control module drives the microcontroller through the first pin. The microcontroller sends an identification signal to the first control module, and the second control module sends an operation signal to the first control module through the second pin.

The present invention further provides an external device, which is characterized in that a PCI-E device is connected through a USB 3.0 interface.

The external device of the present invention comprises a USB 3.0 interface, a first control module and a microcontroller. The USB3.0 interface is connected to the host end, and the USB3.0 interface has a plurality of first pin positions and a plurality of second pin positions; the first control module is connected to the second pin position of the USB3.0 interface, and the first control module Receiving an operation signal from the host end; the microcontroller is coupled to the first pin of the USB3.0 interface and the first control module, and the microcontroller receives the identification request through the first pin, and the microcontroller generates the identification according to the identification requirement The signal is sent to the first control module.

The invention further proposes a transmission method of a heterogeneous device, which is characterized in that a PCI-E device is connected through a USB 3.0 interface.

The transmission method of the heterogeneous device of the present invention comprises the following steps: the PCI-E device The USB3.0 interface connected to the host end; the second control module of the host end drives the PCI-E device's microcontroller through multiple first pins of the USB3.0 interface to generate the identification signal; the second control module transmits the USB3 The plurality of second pins of the .0 interface transmit the operation signal to the first control module of the PCI-E device; the identification signal is transmitted to the first control module; and the first control module performs the corresponding signal according to the identification signal and the operation signal. operating.

The external device of the present invention, the transmission system of the heterogeneous device and the method thereof can provide the correct clock required for the PCI-E device to operate, and thus the present invention can completely realize the purpose of hot plugging. The invention can be connected to the USB3.0 device by the USB3.0 interface, or can be connected to the PCI-E device, so that space saving can be achieved. The features and implementations of the present invention are described in detail below with reference to the drawings.

100‧‧‧Transmission system

110‧‧‧PCI-E equipment

111‧‧‧First interface

112‧‧‧Microcontroller

113‧‧‧First Control Module

114‧‧‧First pin

115‧‧‧second pin

120‧‧‧Host side

121‧‧‧second interface

122‧‧‧Second control module

Figure 1 is an architectural diagram of the present invention.

Figure 2 is a schematic diagram showing the configuration of the pin of the first interface of the present invention.

Figure 3 is a schematic diagram of the operational flow of the present invention.

Figure 4 is a schematic diagram of another operational flow of the present invention.

Please refer to FIG. 1 , which is an architectural diagram of the present invention. The transmission system 100 of the heterogeneous device of the present invention includes a PCI-E device 110 and a host terminal 120. The PCI-E device 110 has a first interface 111, a microcontroller 112 (Micro Control Unit, MCU for short), and a first control module 113 (PCI-E Host). The microcontroller 112 is coupled to the first interface 111 and the first control module 113. Information and drivers related to the PCI-E device 110 can be written into the microcontroller 112. The first interface 111 includes a plurality of first pins 114 and second pins 115. For the purpose of backward compatibility, the USB3.0 interface includes both the USB2.0 pin and the USB3.0 pin. Here, each pin of the USB 2.0 in the first interface 111 is defined as a first pin 114, and each pin of the USB 3.0 is defined as a second pin 115. The first pin 114 is coupled to the microcontroller 112 and the host end 120. The second pin 115 is coupled to the first control module 113 and the host end 120. The first interface 111 is a USB 3.0 transmission protocol. The first interface 111 can be a USB A type (USB A type) or a USB Type B (USB B type).

For the pin configuration used in the first interface 111 of the present invention, please refer to the following description. Please refer to FIG. 2, which is a schematic diagram of the pin configuration of the first interface of the present invention. The first pin is the first pin 114, which is connected to the USB 2.0 power pin (VBus) and the PCI-E power pin (Vcc). The second pin is the first pin 114, which is a differential voltage pin (D-) of USB2.0 and a differential voltage pin (D-) of USB2.0. The third leg is the first pin 114, which is connected to the differential voltage pin (D+) of USB2.0. The fourth pin is the first pin 114, which is connected to the grounding pin (GND) of the USB2.0 and the grounding pin (GND) of the PCI-E.

The fifth pin is the second pin 115, which is a receiving pin (RX-) of USB 3.0 and a PCI Express Receive Negative signal of PCI-E. The sixth pin is a second pin 115 that connects the receiving pin (RX+) of the USB 3.0 and the PERp pin (PCI Express Receive Positive signal) of the PCI-E. The seventh pin is the second pin 115, which is connected to the grounding pin of the USB3.0 and the grounding pin of the PCI-E. The eighth pin is the second pin 115, which is connected to the USB 3.0 transmission pin (TX-) and the PCI-E PET Express pin (PCI Express Transmit Negative signal). The ninth pin is the second pin 115, which is connected to the USB3.0 transmission pin (TX+) and the PCI-E PETp Transpon Positive signal (PCI Express Transmit Positive signal).

The host side 120 of the present invention may be, but not limited to, a personal computer, a notebook, or an all-in-one PC (AIO). The host end 120 includes a second interface 121 and a second control module 122. The type of the second control module 122 is determined according to the operation process of the host terminal 120. When the host terminal 120 is in the boot process, the second control module 122 is a Basic Input/Output System (BIOS), and the second control module 122 can drive the Platform Controller Hub to perform corresponding operations. Processing. If the host terminal 120 has entered the operation system (OS), the second control module 122 is executed by the operating system. The second interface 121 is also a USB 3.0 transmission protocol. In general, the type of the first interface 111 is relative to the type of the second interface 121. Alternatively, the present invention can also be connected to the first interface 111 and the second interface 121 via a USB 3.0 connection cable (Cable).

The host side 120 will be served by different objects in different operating environments. Two control modules 122. In the present invention, the operating environment is divided into a booting process and an operating environment. If the host 120 is in the process of booting, the control module is responsible for the BIOS. After the boot is completed, the host 120 runs the operating system. Therefore, in the environment of the operating system, the operating system is responsible for the related processing of the plug-in detection of the PCI-E device 110.

In order to clearly explain the operation sequence of the present invention in the booting process, please refer to FIG. 3, which is a schematic diagram of the operational flow of the present invention. The method for transmitting the heterogeneous device of the present invention includes the following steps: Step S310: connecting the expansion device to the second interface of the host device; Step S320: The BIOS determines that the type of the expansion device is a USB3.0 device or a PCI-E device; Step S330: The expansion device is a USB 3.0 device, and the BIOS operates the USB 3.0 device. Step S340: If the expansion device is a PCI-E device, the BIOS drives the PCI-E device's microcontroller through the first pin of the first interface. And generating an identification signal; step S350: the BIOS transmits the operation signal to the first control module of the PCI-E device through the plurality of second pins of the first interface; and step S360: transmitting the identification signal to the first control module; Step S370: The first control module performs corresponding operations according to the identification signal and the operation signal.

In order to distinguish between the device before identification and the device after identification, the device that is connected and not recognized is defined as an expansion device. The expansion device is connected to the host end 120 via a cable or a connector. Since the host terminal 120 is in the power-on state, the BIOS is responsible for the role of the second control module 122.

The BIOS can confirm the type of expansion device by timing and interrogating device information. When the BIOS issues an identification request, the BIOS waits for a response from the microcontroller 112. Since the information about the PCI-E device 110 or the USB 3.0 device has been carried in the microcontroller 112, the microcontroller 112 receives the identification request and generates a corresponding response signal. If the BIOS receives a response signal from the microcontroller 112 after a predetermined period of time, the BIOS will recognize the PCI-E device 110. If the response signal is not received after the preset time period, the BIOS will regard the device connected to the second interface 121 as a USB 3.0 device. If it is a USB3.0 device, the BIOS can connect through the original program.

If the connected expansion device is the PCI-E device 110, the BIOS transmits the first pin 114 of the first interface 111 and drives the microcontroller 112 of the PCI-E device 110 to generate an identification signal. The types of the identification signals include a reset signal, a wake-up signal (Wakeup), and a sleep signal (Sleep). The identification signal generated by the microcontroller 112 is coordinated with the control of the PCI-E device 110, so the PCI-E device 110 can cooperate with the correct timing when performing operations. The BIOS transmits the operation signal to the first control module 113 of the PCI-E device 110 through the plurality of second pins 115 of the first interface 111. The order of execution of steps S350 and S360 is not limited to this, and it is also possible for those skilled in the art to simultaneously perform or exchange the sequences.

The present invention can also be applied to the operation of the operating system in addition to the aforementioned booting process. When the operating system is running, the BIOS will not control the surrounding hardware. Therefore, when the operating system is running, the operating system functions as the second control module 122. Please refer to FIG. 4, which is a schematic diagram of another operational flow of the present invention. The embodiment includes the following steps: Step S410: connecting the expansion device to the second interface of the host end; Step S420: The operating system determines that the type of the expansion device is a USB3.0 device or a PCI-E device; Step S430: If the device is expanded For the USB3.0 device, the USB 3.0 device is operated by the operating system; Step S440: If the expansion device is a PCI-E device, the operating system drives the PCI-E device's microcontroller through the first pin of the first interface. And generating an identification signal; step S450: the operating system transmits the operation signal to the first control module of the PCI-E device through the plurality of second pins of the first interface; and step S460: transmitting the identification signal to the first control module; And step S470: the first control module performs a corresponding operation according to the identification signal and the operation signal.

Since the operating system has substantial control over the hardware of the host terminal 120, the operating system is used as the second control module 122 after the booting is completed. When the operating system detects that the second interface 121 has device access, the operating system will call the relevant interrupt program. There may be different implementations for the interrupt program described, depending on the type of work system.

When the expansion device is connected to the host end 120, the operating system passes through the first pin 114. The identification request is sent to the microcontroller 112 of the PCI-E device 110. If the expansion device receives the identification request, the microcontroller 112 will return a response message to the host 120. After receiving the response message, the operating system can identify the type of the expansion device according to the response message and call the relevant interrupt processing to connect the device. Taking Microsoft's Windows operating system (Windows OS) as an example, the Windows operating system can call a System Management Interrupt (SMI) or a Driver (Driver) as the identification and connection of the PCI-E device 110.

Next, the operating system transmits the microcontroller 112 of the PCI-E device 110 through the first pin 114 of the first interface 111 and generates an identification signal. The identification signal generated by the microcontroller 112 is coordinated with the control of the PCI-E device 110, so the PCI-E device 110 can cooperate with the correct timing when performing operations. The operating system transmits the operation signal to the first control module 113 of the PCI-E device 110 through the plurality of second pins 115 of the first interface 111. The order of execution of steps S450 and S460 is not limited to this, and it is also possible for those skilled in the art to simultaneously perform or exchange the sequences.

The external device, heterogeneous device transmission system 100 and method thereof of the present invention can provide the correct clock required for the PCI-E device 110 to operate, and thus the present invention can completely achieve the purpose of hot plugging. The present invention can be connected to a USB 3.0 device by a USB 3.0 interface, or can be connected to a PCI-E device 110. Therefore, the object of saving space can be achieved, and the present invention also takes into consideration the purpose of practicality.

While the present invention has been described above in terms of the preferred embodiments thereof, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The patent protection scope of the invention is subject to the definition of the scope of the patent application attached to the specification.

100‧‧‧Transmission system

110‧‧‧PCI-E equipment

111‧‧‧First interface

112‧‧‧Microcontroller

113‧‧‧First Control Module

114‧‧‧First pin

115‧‧‧second pin

120‧‧‧Host side

121‧‧‧second interface

122‧‧‧Second control module

Claims (10)

A transmission system for a heterogeneous device, characterized in that according to the connected device and selecting a corresponding type of transmission protocol, the transmission system of the heterogeneous device comprises: a PCI-E device having a first interface, a microcontroller and a first control module, the microcontroller is coupled to the first control module, the first interface has a plurality of first pins and a plurality of second pins; and a host end is connected to the first control module The PCI-E device has a second interface and a second control module, and the second interface is corresponding to the first interface of the PCI-E device; wherein the PCI-E device is connected to the host The second control module is coupled to the microcontroller through the first pin, and the second control module is coupled to the first control module through the second pin, the second control module The group drives the microcontroller through the first pins, so that the microcontroller sends an identification signal to the first control module, and the second control module transmits the second control module to the first control module. Send an operation signal. The transmission system of the heterogeneous device according to claim 1, wherein the pin position of the second interface is: the first pin is the first pin, and the USB pin is connected to the PCI pin and the PCI pin. -E power pin; the second pin is the first pin, which is connected to the differential voltage pin (D-) of USB2.0 and the differential voltage pin (D-) of USB2.0; The three pins are the first pin, which is connected to the differential voltage pin (D+) of the USB2.0; the fourth pin is the first pin, which is connected to the ground pin of the USB2.0. The grounding pin of the PCI-E; the fifth pin is the second pin, which is connected to the receiving pin (RX-) of the USB3.0 and the PERn pin of the PCI-E; the sixth pin The second pin is connected to the receiving pin (RX+) of the USB3.0 and the PERp pin of the PCI-E; the seventh pin is the second pin, which is connected to the USB3.0. The grounding pin and the grounding pin of the PCI-E; the eighth pin is the second pin, which is connected to the USB3.0 transmission pin (TX-) and the PCI-E PETn pin; The pin is the second pin, which is connected to the USB3.0 transmission pin (TX+) and the PCI-E PETp pin. The transmission system of the heterogeneous device according to claim 1, wherein the second control module is a BIOS or an operating system. The transmission system of the heterogeneous device according to claim 3, wherein the BIOS detects that the type of the device connected to the second interface is a USB 3.0 device or the PCI-E during the booting process. device. The transmission system of the heterogeneous device according to claim 3, wherein the host terminal runs on the operating system, and the operating system detects that the type of the device connected to the second interface is a USB 3.0 device or the PCI-E device. An external device, characterized in that a PCI-E device is connected through a USB3.0 interface, the external device includes: a USB3.0 interface, which is connected to a host end, the USB3.0 interface has a plurality of first pins and a plurality of second pins; a first control module connected to the second pins of the USB 3.0 interface, the first control module receiving an operation signal from the host end; and a micro The controller is coupled to the first pin of the USB 3.0 interface and the first control module, and the microcontroller receives an identification request through the first pin, the microcontroller is configured according to the The identification request generates an identification signal and sends the identification signal to the first control module. A transmission method of a heterogeneous device, characterized in that a PCI-E device is connected through a USB 3.0 interface, and the transmission method of the heterogeneous device includes the following steps: connecting a PCI-E device to a USB 3.0 interface of a host end; A second control module on the host side drives a microcontroller of the PCI-E device to generate an identification signal through a plurality of first pins of the USB 3.0 interface; the second control module transmits the USB 3.0 interface through the USB 3.0 interface The plurality of second pins transmit an operation signal to a first control module of the PCI-E device; the identification signal is transmitted to the first control module; and the first control module is configured according to the identification signal The operation signal performs corresponding operations. The method for transmitting a heterogeneous device according to claim 7, wherein the second control module is a BIOS or an operating system. The method for transmitting a heterogeneous device according to claim 8, wherein the step of connecting the PCI-E device to the USB 3.0 interface comprises: determining that the host terminal is in a booting process or in a running system; if the host terminal is During the boot process, the BIOS detects that the device connected to the USB 3.0 interface is a USB 3.0 device or the PCI-E device; If the host is running in the operating system, the operating system detects that the device connected to the USB 3.0 interface is the USB 3.0 device or the PCI-E device. The method for transmitting a heterogeneous device according to claim 9, wherein the step of detecting the device connected to the USB 3.0 interface further comprises: the second control module issuing a recognition to the device connected to the USB3.0 interface If the device connected to the USB 3.0 interface is the PCI-E device, the PCI-E device generates a response signal according to the identification request and returns the response signal to the second control module, if the USB 3.0 The device connected to the interface is the USB 3.0 device, and the USB 3.0 device generates another response signal according to the identification request and returns the response signal to the second control module.