CN103207850B - The transmission system of heterogeneous device - Google Patents
The transmission system of heterogeneous device Download PDFInfo
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- CN103207850B CN103207850B CN201310080842.8A CN201310080842A CN103207850B CN 103207850 B CN103207850 B CN 103207850B CN 201310080842 A CN201310080842 A CN 201310080842A CN 103207850 B CN103207850 B CN 103207850B
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Abstract
The transmission system of external equipment, heterogeneous device and its method, is characterized in that connecting PCI-E equipment through USB3.0 interface.External equipment comprises USB3.0 interface, first and controls module and microcontroller.USB3.0 interface is connected to host side, and USB3.0 interface has multiple first pin position and multiple crus secunda position; First controls the crus secunda position that module is connected to USB3.0 interface, and first controls module receives the operation signal coming from host side; The first pin position and first that microcontroller is coupled to USB3.0 interface controls module, microcontroller receives identification requirement through the first pin position, microcontroller requires to produce recognition signal according to identification, and recognition signal is sent to the first control module, external equipment can be operated normally under correct clock pulse.
Description
[technical field]
A transmission system for heterogeneous device, is particularly to a kind of transmission system connecting the heterogeneous device of PCI-E through USB3.0.
[background technology]
Along with the fast development of integrated circuit, make the volume of computing machine can be compact and reach arithmetic capability faster.For small-size computer, the space of main frame inside will be limited.Therefore small-size computer can not provide the expansion of adapter.So small-size computer is to other equipment newly-increased, will expand through external mode.Generally speaking, universal serial bus (UniversalSerialBus, be called for short USB) is the interface of the very ripe external equipment of item.The feature of USB supports hot plug (Hot-Plug) and plug and play (Plug-and-Play).And USB3.0 interface also can be compatible with old-fashioned USB2.0 and USB1.1 device.
Along with in a large number and transmit demand fast, USB is made also to develop into the third edition (hereinafter referred to as USB3.0).The transmission speed of USB3.0 is increased to 5G (Gigabps).So USB3.0 can provide transmission speed more fast.Therefore manufacturer is had to propose other transmission interfaces to be converted to USB3.0 interface.Other heterogeneous device can be connected to host side through the interface of USB3.0, make the interface of single kind reach the connection of number of different types equipment.Kind due to other transmission interfaces is different from USB3.0 interface, is therefore be referred to as heterogeneous device in this manual.Propose one in Republic of China patent No. M375925 case and " there is the outer welding system of USB3.0 and PCI-E interface " (hereinafter referred to as M375925 case).M375925 case allows the device with peripheral equipment linkage interface (PeripheralComponentInterconnectExpress, hereinafter referred to as PCI-E) be connected with computer through the connecting line of USB3.0.
M375925 case adjusts the transmission connecting-leg in USB3.0 joint, makes the electronic installation of PCI-E can be connected to USB3.0 interface by the joint of USB3.0.Although such mode can realize the connection of PCI-E device and USB3.0.But the differential voltage pin (D+, D-) of USB3.0 directly connects with the reference clock pulse pin (REFCLK+, REFCLK-) of PCI-E by M375925 case.Because clock pulse pin is not identical with the signal that differential voltage pin transmits, so PCI-E device also cannot obtain corresponding clock pulse.So when without correct clock pulse, PCI-E device performs and operates the operation result that will make a mistake accordingly.Therefore, M375925 case there is no actual solution two kinds of agreement operations under different clock pulse.
[summary of the invention]
The invention provides a kind of transmission system of heterogeneous device, it is characterized in that according to connected equipment and select the host-host protocol of corresponding kind.The transmission system of heterogeneous device of the present invention comprises PCI-E equipment and host side.PCI-E equipment has first interface, microcontroller and first controls module, and microcontroller is coupled to the first control module, and first interface has multiple first pin and multiple second pin; Host side is connected to PCI-E equipment, and host side has the second interface and second and controls module, and the second interface correspondence is arranged at the first interface of PCI-E equipment; Wherein, PCI-E equipment connection is when host side, second controls module is coupled to microcontroller through the first pin, second controls module is coupled to the first control module through the second pin, second controls module drives microcontroller through the first pin, make microcontroller control module to first and send recognition signal, second controls module controls module transmit operation signal through the second pin to first.The present invention separately proposes a kind of external equipment, it is characterized in that connecting PCI-E equipment through USB3.0 interface.
Correct clock pulse required when the transmission system of external equipment of the present invention, heterogeneous device and its method can provide PCI-E equipment to run, the object realizing hot plug that therefore the present invention can be complete.The present invention can be connected outside USB3.0 equipment by USB3.0 interface, also can connect PCI-E equipment, so can reach joint space-efficient object.Characteristics and implementation for the present invention, hereby coordinate and to be graphicly described in detail as follows as most preferred embodiment.
[accompanying drawing explanation]
Fig. 1 is Organization Chart of the present invention.
Fig. 2 is the pin position configuration schematic diagram of first interface of the present invention.
Fig. 3 is operation workflow schematic diagram of the present invention.
Fig. 4 is another kind of operation workflow schematic diagram of the present invention.
[embodiment]
Please refer to shown in the 1st figure, it is Organization Chart of the present invention.The transmission system 100 of heterogeneous device of the present invention comprises PCI-E equipment 110 and host side 120.PCI-E equipment 110 has first interface 111, microcontroller 112 (MicroControlUnit is called for short MCU) controls module 113 (PCI-EHost) with first.Microcontroller 112 is coupled to first interface 111 and first and controls module 113.Relevent information and the driver of PCI-E equipment 110 can be write in microcontroller 112.First interface 111 comprises multiple first pin 114 and the second pin 115.For realizing backward compatible object, so contain USB2.0 pin and USB3.0 pin in USB3.0 interface simultaneously.The each pin each pin of the USB2.0 in first interface 111 being defined as the first pin 114, USB3.0 at this is defined as the second pin 115.First pin 114 is coupled to microcontroller 112 and host side 120.Second pin 115 is coupled to the first control module 113 and host side 120.What first interface 111 adopted is USB3.0 host-host protocol.First interface 111 can adopt USBA type (USBAtype) or USBB type (USBBtype).
Shown in the pin configuration adopted in first interface 111 of the present invention please refer to hereafter, please coordinate shown in the 2nd figure, it is the pin position configuration schematic diagram of first interface of the present invention.First branch connecting pin is the first pin 114, and it is connect the electric power pin (VBus) of USB2.0 and the electric power pin (Vcc) of PCI-E.Second branch connecting pin is the first pin 114, and it is the differential voltage pin (D-) connecting USB2.0.3rd branch connecting pin is the first pin 114, and it is the differential voltage pin (D+) connecting USB2.0.4th branch connecting pin is the first pin 114, and it is connect the ground connection pin (GND) of USB2.0 and the ground connection pin (GND) of PCI-E.
5th branch connecting pin is the second pin 115, and it is the reception pin (RX-) of USB3.0 and the PERn pin (PCIExpressReceiveNegativesignal) of PCI-E.6th branch connecting pin is the second pin 115, and it is connect the reception pin (RX+) of USB3.0 and the PERp pin (PCIExpressReceivePositivesignal) of PCI-E.7th branch connecting pin is the second pin 115, and it is connect the ground connection pin of USB3.0 and the ground connection pin of PCI-E.8th branch connecting pin is the second pin 115, and it is connect the transmission connecting-leg (TX-) of USB3.0 and the PETn pin (PCIExpressTransmitNegativesignal) of PCI-E.9th branch connecting pin is the second pin 115, and it is connect the transmission connecting-leg (TX+) of USB3.0 and the PETp pin (PCIExpressTransmitPositivesignal) of PCI-E.
Host side 120 of the present invention can be but not be defined as PC (PersonalComputer), notebook computer (Notebook) or integrated computer (AllinonePC is called for short AIO).Host side 120 comprises the second interface 121 and second and controls module 122.The second kind system controlling module 122 determined according to the operational process of host side 120.When host side 120 is in start process, second control module 122 is basic input-output system (BasicInput/outputSystem, be called for short BIOS), second controls module 122 can drive platform courses hub (PlatformControllerHub) to process accordingly.If host side 120 has entered in operating system (OperationSystem, be called for short OS), then second control module 122 and change and performed by operating system.What the second interface 121 adopted is also USB3.0 host-host protocol.Generally speaking, the kind system of first interface 111 is relative to the kind of the second interface 121.Or the present invention also can be connected to first interface 111 and the second interface 121 through the stube cable of USB3.0 (Cable).
Host side 120, under different environment of operation, will be served as the second control module 122 by different objects.Be environment of operation to be divided in start process under (Booting) and operating environment in the present invention.If host side 120 is in start process, then control module by BIOS be responsible for.After completing start, host side 120 can running job system.Therefore under the environment of operating system, be then the relevant treatment of the insert-pull detection being responsible for PCI-E equipment 110 by operating system.
For clearly demonstrating the sequence of operations of the present invention in start process, please coordinate shown in the 3rd figure, it is operation workflow schematic diagram of the present invention.The transmission method of heterogeneous device of the present invention comprises the following steps:
Step S310: the second interface extension facility being connected to host side;
Step S320:BIOS judges that the kind of extension facility is USB3.0 equipment or PCI-E equipment;
Step S330: if extension facility is USB3.0 equipment, by BIOS to USB3.0 operate;
Step S340: if extension facility is PCI-E equipment, is driven the microcontroller of PCI-E equipment by BIOS through the first pin of first interface and produces recognition signal;
Step S350:BIOS controls module through multiple second pin transmission operation signals of first interface to first of PCI-E equipment;
Step S360: recognition signal is sent to the first control module; And
Step S370: the first controls module carries out corresponding operation according to recognition signal to operation signal.
For the equipment before difference identification and equipment after identification, at this by when connecting and the device definition of non-identification is extension facility.Extension facility is connected to host side 120 through the mode of cable or joint.Because host side 120 is in open state, the role of the second control module 122 therefore can be responsible for by BIOS.
BIOS can confirm the kind of extension facility through the mode of timing and inquiry unit information.When BIOS is after sending identification requirement, BIOS can wait for the response of microcontroller 112.Owing to having carried the relevent information of this PCI-E equipment 110 or USB3.0 equipment in microcontroller 112, therefore microcontroller 112 has been received identification requirement and can be produced and respond signal accordingly.If after a preset period of time, BIOS receives the response signal of microcontroller 112, then BIOS will identify PCI-E equipment 110.If do not receive response signal yet after preset period of time, BIOS will be considered as USB3.0 equipment the equipment that the second interface 121 connects.If USB3.0 equipment, then BIOS can connect through program originally.
If the extension facility connected is PCI-E equipment 110, then BIOS through first interface 111 the first pin 114 and drive the microcontroller 112 of PCI-E equipment 110 in order to produce recognition signal.Wherein, the kind of recognition signal comprises replacement signal (Reset), wakes signal (Wakeup) and sleep signal (Sleep) up.And the recognition signal system that microcontroller 112 produces coordinates the control of PCI-E equipment 110, therefore PCI-E equipment 110 can coordinate correct sequential when executable operations.And BIOS through first interface 111 multiple second pins 115 transmit operation signals to PCI-E equipment 110 first control module 113.Execution sequence for step S350 and S360 is not only confined to this, also these steps can be performed or exchange sequence simultaneously for this area person.
The present invention, except in aforesaid start process, also can be applied in operating system operation.When operating system is run, because BIOS can not carry out management and control to periphery hardware.So when operating system is run, be the role being served as the second control module 122 by operating system.Please refer to shown in the 4th figure, it is another kind of operation workflow schematic diagram of the present invention.This enforcement aspect comprises the following steps:
Step S410: the second interface extension facility being connected to host side;
Step S420: operating system judges that the kind of extension facility is USB3.0 equipment or PCI-E equipment;
Step S430: if extension facility is USB3.0 equipment, by operating system to USB3.0 operate;
Step S440: if extension facility is PCI-E equipment, is driven the microcontroller of PCI-E equipment by first pin of operating system through first interface and is produced recognition signal;
Step S450: operating system controls module through multiple second pin transmission operation signals of first interface to first of PCI-E equipment;
Step S460: recognition signal is sent to the first control module; And
Step S470: the first controls module carries out corresponding operation according to recognition signal to operation signal.
Because operating system is for the tangible control power of hardware of host side 120, therefore module 122 will be controlled using operating system as second after completing start.When operation systems scan has device to access to the second interface 121, operating system will call relevant interrupt routine.With the difference of authorship system kind, and different implementation may be had for described interrupt routine.
When extension facility is connected to the microcontroller 112 that identification can be required to be sent to through the first pin 114 PCI-E equipment 110 by host side 120 operating system.If extension facility receives identification requirement, then microcontroller 112 will return a response message to host side 120.Operating system is after receiving response message, and operating system can recognize the kind of extension facility according to response message, and calls relevant interrupt processing and carry out this equipment connection.For the windows workspace system (WindowsOS) of Microsoft (Microsoft), windows workspace system can calling system management interrupt (SystemManagementInterrupt, be called for short SMI) or driver (Driver) as PCI-E equipment 110 identification be connected.
Next, driven the microcontroller 112 of PCI-E equipment 110 by first pin 114 of operating system through first interface 111 and produced recognition signal.And the recognition signal system that microcontroller 112 produces coordinates the control of PCI-E equipment 110, therefore PCI-E equipment 110 can coordinate correct sequential when executable operations.And operating system through first interface 111 multiple second pins 115 transmit operation signals to PCI-E equipment 110 first control module 113.Execution sequence for step S450 and S460 is not only confined to this, also these steps can be performed or exchange sequence simultaneously for this area person.
Correct clock pulse required when transmission system 100 and its method of external equipment of the present invention, heterogeneous device can provide PCI-E equipment 110 to run, the object realizing hot plug that therefore the present invention can be complete.The present invention can be connected outside USB3.0 equipment by USB3.0 interface, also can connect PCI-E equipment 110.So can reach outside the object of joint space-efficient, the present invention has also taken into account the object of practicality.
Although the present invention discloses as above with aforementioned preferred embodiment; so itself and be not used to limit the present invention; anyly have the knack of alike those skilled in the art; without departing from the spirit and scope of the invention; when doing a little change and retouching, the scope of patent protection of therefore the present invention must be as the criterion depending on the claim person of defining that this instructions is appended.
Claims (4)
1. a transmission system for heterogeneous device, it is characterized in that according to connected equipment and select the host-host protocol of corresponding kind, the transmission system of this heterogeneous device comprises:
One PCI-E equipment, has a first interface, a microcontroller and one first controls module, and this microcontroller is coupled to this first control module, and this first interface has multiple first pin and multiple second pin; And
One host side, be connected to this PCI-E equipment, this host side has one second interface and one second and controls module, this the second interface correspondence is arranged at this first interface of this PCI-E equipment, and the pin position of this first interface is arranged as: the first branch connecting pin is this first pin, it connects the electric power pin of USB2.0 and the electric power pin of PCI-E; Second branch connecting pin is this first pin, and it connects the differential voltage pin D-of USB2.0; 3rd branch connecting pin is this first pin, and it connects the differential voltage pin D+ of USB2.0; 4th branch connecting pin is this first pin, and it connects the ground connection pin of USB2.0 and the ground connection pin of PCI-E; 5th branch connecting pin is this second pin, and it connects the PERn pin of reception pin RX-and the PCI-E of USB3.0; 6th branch connecting pin is this second pin, and it connects the PERp pin of reception pin RX+ and the PCI-E of USB3.0; 7th branch connecting pin is this second pin, and it connects the ground connection pin of USB3.0 and the ground connection pin of PCI-E; 8th branch connecting pin is this second pin, and it connects the PETn pin (PCIExpressTransmitNegativesignal) of transmission connecting-leg TX-and the PCI-E of USB3.0; 9th branch connecting pin is this second pin, and it connects the PETp pin of transmission connecting-leg TX+ and the PCI-E of USB3.0;
Wherein, this PCI-E equipment connection is when this host side, this the second control module is coupled to this microcontroller through this first pin, this the second control module is coupled to this first control module through this second pin, this the second control module drives this microcontroller through those first pins, make this microcontroller send a recognition signal to this first control module, this second control module sends an operation signal through this second pin to this first control module.
2. the transmission system of heterogeneous device as claimed in claim 1, is characterized in that this second control module is a BIOS or an operating system.
3. the transmission system of heterogeneous device as claimed in claim 2, it is characterized in that this host side is in start process, the kind that this BIOS detects the equipment that this second interface connects is USB3.0 equipment or this PCI-E equipment.
4. the transmission system of heterogeneous device as claimed in claim 2, it is characterized in that this host side is run in this operating system, the kind that this operating system detects the equipment that this second interface connects is USB3.0 equipment or this PCI-E equipment.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310080842.8A CN103207850B (en) | 2013-03-14 | 2013-03-14 | The transmission system of heterogeneous device |
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| CN201310080842.8A CN103207850B (en) | 2013-03-14 | 2013-03-14 | The transmission system of heterogeneous device |
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| CN103207850A CN103207850A (en) | 2013-07-17 |
| CN103207850B true CN103207850B (en) | 2016-01-20 |
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| TWI528138B (en) * | 2013-10-23 | 2016-04-01 | 緯創資通股份有限公司 | Method for determining installation direction of electronic device and electronic system |
| CN104714915A (en) * | 2013-12-16 | 2015-06-17 | 致伸科技股份有限公司 | Electronic device for loading firmware through general sequence bus socket and firmware loading method thereof |
| CN104536915B (en) * | 2014-11-27 | 2017-11-24 | 英业达科技有限公司 | Storage expansion unit automatic recognition system and storage expansion unit automatic identification collocation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN200953125Y (en) * | 2006-09-27 | 2007-09-26 | 精威科技股份有限公司 | Converter for express card switching to universal serial port |
| TWM375925U (en) * | 2009-11-13 | 2010-03-11 | Star Laser Fabrication Co Ltd G | Externally connecting system containing USB 3.0 and PCI-E interfaces |
| CN101976100A (en) * | 2010-11-08 | 2011-02-16 | 昆山五昌新精密电子工业有限公司 | Asynchronous expansion system compatible with PCI (Programmable Communications Interface) interface |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN200953125Y (en) * | 2006-09-27 | 2007-09-26 | 精威科技股份有限公司 | Converter for express card switching to universal serial port |
| TWM375925U (en) * | 2009-11-13 | 2010-03-11 | Star Laser Fabrication Co Ltd G | Externally connecting system containing USB 3.0 and PCI-E interfaces |
| CN101976100A (en) * | 2010-11-08 | 2011-02-16 | 昆山五昌新精密电子工业有限公司 | Asynchronous expansion system compatible with PCI (Programmable Communications Interface) interface |
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