TW201431022A - 封裝體及其製造方法 - Google Patents

封裝體及其製造方法 Download PDF

Info

Publication number
TW201431022A
TW201431022A TW102144776A TW102144776A TW201431022A TW 201431022 A TW201431022 A TW 201431022A TW 102144776 A TW102144776 A TW 102144776A TW 102144776 A TW102144776 A TW 102144776A TW 201431022 A TW201431022 A TW 201431022A
Authority
TW
Taiwan
Prior art keywords
layer
rdl
microbump
inductor
package
Prior art date
Application number
TW102144776A
Other languages
English (en)
Other versions
TWI523169B (zh
Inventor
Hsiao-Tsung Yen
Yu-Ling Lin
Chung-Yu Lu
Chin-Wei Kuo
Tzuan-Horng Liu
Hsien-Pin Hu
Min-Chie Jeng
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Publication of TW201431022A publication Critical patent/TW201431022A/zh
Application granted granted Critical
Publication of TWI523169B publication Critical patent/TWI523169B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H01F17/0013—Printed inductances with stacked layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H01F2017/0086—Printed inductances on semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1206—Inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本發明提供一種封裝體，包括：一第一裝置，包括一第一重配層(RDL)；一微凸塊層，位於第一裝置之上，包括與第一重配層(RDL)連接的一第一微凸塊導線；以及一第一電感，包括第一重配層(RDL)及第一微凸塊導線。本發明也提供一種封裝體的製造方法。

Description

封裝體及其製造方法
本發明係有關於封裝體，且特別是有關於封裝體之電感及變壓器結構。
電子產品的結構可簡單的區分成積體電路(IC)晶片、封裝體、印刷電路板(printed circuit board；PCB)、系統等層次。封裝體是積體電路(IC)晶片和印刷電路板(PCB)之間的界面。積體電路(IC)晶粒由半導體材料像是矽所形成。接著，利用像是導線接合(wiring bonding；WB)、捲帶式自動接合(tape automated bonding；TAB)、或倒裝晶片(flip chip；FC)凸塊組裝技術，將晶粒組裝到封裝體像是四方扁平封裝(quad flat packs；QFP)、針柵陣列(pin grid array；PGA)、球柵陣列(ball grid array；BGA)、三維積體電路(3DIC)、晶圓級封裝(wafer level packages；WLP)、或疊合式封裝(package on package；PoP)裝置之中。接下來，將封裝好的晶粒直接連接到印刷電路板(PCB)或另一個作為第二階段封裝的基板。
三維積體電路(3DIC)技術被稱為垂直內連線封裝技術，因為其利用晶片的垂直方向來降低內連線的長度，並達到更好的整合效果。三維積體電路(3DIC)封裝體的技術包括導 線接合(wire-bonding)、微凸塊(micro-bumps)、通孔(through-vias)等。可利用矽中介片(silicon interposer)來形成三維積體電路(3DIC)封裝體，其中中介片(interposer)為安裝在中介片上的晶粒提供晶粒到晶粒(die-to-die)內連線。例如，兩個晶粒可藉由面對面(face-to-face)或正反面(face-to-back)堆疊以接合在彼此之上，其中較低的晶粒藉由連接器，像是微凸塊(micro-bumps)，與中介片耦合。或者，多個晶粒也可平行地安裝在一中介片之上，且藉由連接器，像是微凸塊(micro-bumps)，與中介片耦合。
電感是一種被動電子元件，可將能量儲存在其磁場中。電感被廣泛運用在類比電路(analog circuits)、訊號處理系統、及無線通訊系統中。電感結合電容及其他元件所形成的電路可過濾掉特定頻率的訊號。變壓器是一種功率轉換器，其可將電子能量從一個電路傳遞到另一個電路。兩個以上的電感與耦合的磁通量(magnetic flux)可形成一變壓器。
形成在積體電路(IC)晶片上的電感和變壓器的性能可能會因為裝置尺寸的縮小而格外受限，像是金屬層與晶片之間縮小的厚度，以及晶片所佔據的較小面積。因此，需要能夠改進電感及變壓器之性能的方法和設備。
根據一實施例，本發明提供一種封裝體，包括：一第一裝置，包括一第一重配層(RDL)；一微凸塊層，位於第一裝置之上，包括與第一重配層(RDL)連接的一第一微凸塊導線；以及一第一電感，包括第一重配層(RDL)及第一微凸塊導 線。
根據另一實施例，本發明提供一種封裝體的製造方法，包括：提供一第一裝置，包括一鈍化層、位於鈍化層之上的一第一重配層(RDL)、位於第一重配層(RDL)上且具有一開口曝露出該第一重配層(RDL)的一絕緣層、及一第一凸塊下金屬(UBM)墊，覆蓋絕緣層的開口並與第一重配層(RDL)連接；形成一第一微凸塊導線，位於第一凸塊下金屬(UBM)墊上，且與第一重配層(RDL)連接；以及形成一第一電感，包括第一重配層(RDL)及第一微凸塊導線。
又根據另一實施例，本發明提供一種封裝體，一第一裝置，包括一第一重配層(RDL)；一微凸塊層，位於該第一裝置之上，包括連接至第一重配層(RDL)的一第一微凸塊導線；一第二裝置，位於微-凸塊層之上，包括連接至第一微凸塊導線的一第二重配層(RDL)；以及一第一電感，包括第一重配層(RDL)、第一微凸塊導線、以及第二重配層(RDL)。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
100‧‧‧封裝體
200、300、400、500‧‧‧電感
202、204‧‧‧輸入埠
206‧‧‧對稱線
301、601‧‧‧裝置、晶粒
302‧‧‧基板
303‧‧‧穿孔
321‧‧‧接觸墊
341‧‧‧鈍化層
361、371‧‧‧絕緣層
381、382‧‧‧重配層
383‧‧‧導孔
391‧‧‧凸塊下金屬(UBM)墊
470‧‧‧第一電感
480‧‧‧第二電感
471‧‧‧銲錫凸塊(層)
473‧‧‧鎳層
475‧‧‧銅層
481、483‧‧‧微凸塊導線
485‧‧‧微凸塊
491‧‧‧區域
571‧‧‧底部填充
600‧‧‧變壓器
603‧‧‧連接器
第1a-1d圖為根據一些實施例顯示利用一微凸塊層形成在封裝體之中的電感的剖面圖及俯視圖。
第2a-2f圖為根據另外一些實施例顯示利用一微凸塊層形成在封裝體之中的電感的剖面圖及俯視圖。
第3a圖為根據一些實施例顯示利用一微凸塊層形成在封裝體之中的變壓器的剖面圖；第3b圖為根據一些實施例顯示利用一微凸塊層形成在封裝體之中的變壓器的俯視圖。
除非特別指明，在不同圖式中相應的數字及符號一般代表相應的部分。各圖式僅用以闡述本發明的概念，將不會依比例繪製。
以下將詳細的討論本發明實施例的製造及使用。然而，應了解的是，本發明提供許多可應用的發明概念，其可應用至各種特定的內容。特定的實施例僅為說明，而非用以限定本發明之範疇。
如下文所揭示，本發明揭露利用微凸塊層來形成具有電感和變壓器的半導體裝置封裝體的方法和設備。微凸塊層可包括微凸塊和微凸塊導線，在頂晶粒和底晶粒之間或是晶粒和中介片之間形成。電感可由底裝置中的重配層(redistribution layer；RDL)以及底裝置之上與重配層(RDL)連接的微凸塊導線形成。電感可為對稱電感、迴旋狀(spiral)電感、垂直結構的螺旋狀(helical)電感，或河曲(meander)電感。相較於晶片中的金屬導線，微凸塊導線較寬，且具有較大的面積及較低的電阻，因此以微凸塊導線形成的電感具有較好的性能，同時也節省成本。具有微凸塊導線的一對電感可以形成一變壓器。
可瞭解的是，當一元件或層被描述為在另一元件或層“上”，或是一元件或層被描述為與另一元件或層“連 接”或“耦合”，其可以是直接位於另一元件或層上，直接與另一元件或層連接或耦合，或者，兩者之間可能存在其他干預的(intervening)元件或層。相反地，當一元件被描述為“直接”位於另一元件或層“上”，“直接”與另一元件或層“連接”或“耦合”時，則不會有干預的(intervening)元件或層存在。
可瞭解的是，儘管可在此使用“第一”、“第二”、“第三”等用詞來描述各種元件、構件(component)、區域、層及/或區段(section)，這些元件、構件(component)、區域、層及/或區段(section)不應被這些用詞所限制。這些用詞只用來區分一元件、構件(component)、區域、層或區段(section)與另一元件、構件(component)、區域、層或區段(section)。因此，以下所討論的第一元件、構件(component)、區域、層或區段(section)可被稱為第二元件、構件(component)、區域、層或區段(section)，而不違背本發明概念的教示。
空間上相關的用詞，像是“底下(beneath)”、“以下(below)”、“較低(lower)”、“以上(above)”、“較高(upper)”、及其類似用詞，可用以簡化對圖式中一元件或特徵與另一元件或特徵之間關係的描述。可瞭解的是，這些空間上相關的用詞是用以包含圖式中所示的方位之外，在使用或操作時裝置的不同方位。例如，若將圖式中所示的裝置顛倒來看，位於其他元件“以下(below)”或“底下(beneath)”的元件或特徵則會變成位於其他元件或特徵“以上(above)”。因此，範例用語“以上(above)”或“以下(below)”可包含以上及以下兩種方位。反之，裝置的方向可被調整(旋轉90度或其他方向)， 而此處所使用的空間相關用詞也隨之調整。
此處所使用的術語(terminology)只是為了描述特定的實施例而非用以限定本發明的概念。除非內文清楚地指明，此處所使用的單數形式“一”、“一個”和“該”也包括複數形式。可進一步瞭解的是，當說明書中使用“包括(comprises)”及/或“包括(comprising)，”等用語，是為了指出所述特徵、整數、步驟、操作、元件、及/或構件(components)的存在，但不排除額外一或多個其他特徵、整數、步驟、操作、元件、構件(components)及/或上述組合的存在。
全文說明書中所指的“一種實施例”或“一實施例”意味著在實施例中描述到的特定特徵、結構、或特色至少包含在一實施例中。因此，全文說明書不同地方所出現的片語“在一種實施例中”或“在一實施例中”所指不一定為相同的實施例。此外，特定的特徵、結構、或特色可在一或多個的實施例中透過任何合適的方法結合。應理解的是，以下的圖式僅為顯示之用途而不一定依照比例繪製。
如第1a圖所示，一半導體裝置封裝體100包括可形成於一裝置301上之一電感。裝置301可包括：一基板302，其具有穿孔(through vias；TV)303、多個接觸墊321、一鈍化層341、一絕緣層361、一重配層(RDL)381、另一絕緣層371、及一凸塊下金屬(UBM)層，其包括覆蓋絕緣層371的開口的凸塊下金屬(UBM)墊391。一微凸塊層可形成於裝置301之上。微凸塊層包括微凸塊導線481及483，置於凸塊下金屬(UBM)墊391上，且進一步在裝置301之中與重配層(RDL)381連接。重配層 (RDL)381、微凸塊導線481及483、及位於微凸塊導線481及483之下的凸塊下金屬(UBM)墊391均為第1b圖俯視圖中所示電感200的一部分。微凸塊層可包括額外的微凸塊485。晶粒601可置於裝置301之上，透過連接器603與微凸塊485連接。底部填充571可將裝置301與晶粒601之間的間隙(gap)填滿，並覆蓋微凸塊導線481及483、微凸塊485、及連接器603。這些構造中的每一個將在以下段落中作更詳細的討論。
裝置301可為一中介片(interposer)，其包括一基板，基板中有穿孔(through vias)形成、多個接觸墊、鈍化層、絕緣層、重配層(RDLs)、及一凸塊下金屬(UBM)層。或者，裝置301可為晶片或積體電路(IC)晶粒的一部分，其可位於晶粒的背側或前側。當裝置301為晶粒的一部分時，置於積體電路(IC)裝置301上的晶粒601會進一步透過連接器，像是微凸塊，與一中介片連接以形成一封裝體，像是一3DIC封裝體。當裝置301為一晶粒的一部分時，其可被稱為一底晶粒(bottom die)，而晶粒601可被稱為一頂晶粒(top die)。當裝置301位於晶粒的背側時，封裝體100是透過晶粒301及601的正反面(face-to-back)堆疊所形成。當裝置301位於晶粒的前側時，封裝體100是透過晶粒301及601的面對面(face-to-face)堆疊所形成。或者，裝置301可為一不具有穿孔(through vias)、上述任何或所有層的封裝體基板。這些裝置及任何其他合適的裝置都可被使用且皆可包括在本發明實施例的範疇中。
裝置301的基板302可例如為一摻雜或未摻雜的矽基板、或一絕緣層上覆矽(silicon-on-insulator；SOI)基板之主 動基板，用以支持裝置301。然而，基板302也可為一玻璃基板、一陶瓷基板、一聚合物基板、或任何其他可提供合適的保護及/或內連線(interconnection)功能的基板。這些及任何其他合適的材料也可用以形成基板302。可有多個主動或被動構件(components)，像是電晶體、電容、電阻、及其類似物，形成於基板302之中，未顯示於第1a圖中。本領域具有通常知識者可理解的是，可使用各式各樣的主動或被動構件(components)產生想要的裝置301結構或功能需求。
多個穿孔(TVs)303可穿過基板302而形成。穿孔(TVs)303可透過合適光阻的塗佈及顯影而形成，接著蝕刻基板302以產生穿孔(TVs)的開口。穿孔(TVs)303的開口的形成可延伸到基板302中，至少達到大於最終所需的高度的深度。因此，此深度可在基板302的表面下介於約1微米至約700微米。穿孔(TVs)303的開口可具有介於約0.5微米至約100微米之一直徑。接著，可利用一製程像是化學氣相沉積(CVD)、電漿化學氣相沉積(PECVD)、濺鍍、或金屬有機化學氣相沉積(MOCVD)等製程，將一阻障層(barrier layer)及一導電材料填入穿孔(TVs)303的開口。穿孔(TVs)303的開口外多餘的阻障層及多餘的導電材料可透過一研磨(grinding)製程像是化學機械平坦化(CMP)來移除。之後，基板302第二側的薄化(thinning)可透過平坦化製程像是化學機械平坦化(CMP)或蝕刻來進行，其目的在於將穿孔(TVs)303的開口曝露出來，並使延伸穿過基板302的導電材料形成穿孔(TVs)。
多個接觸墊321可形成於基板302上。接觸墊321可 由鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、或其他導電材料所形成。利用電解電鍍(electrolytic plating)、濺鍍、物理氣相沉積(PVD)、或無電電鍍(electroless plating)製程進行接觸墊321的沉積。接觸墊321的尺寸、形狀、及位置僅為例示，而非用以限制本發明。多個接觸墊321的尺寸可為相同或不同。鈍化層341可形成於基板302表面上方及接觸墊321之上以作為結構性支撐及物理隔離。鈍化層341可由氮化矽(SiN)、二氧化矽(SiO2)、氮氧化矽(SiON)、聚亞醯胺(polyimide；PI)、苯環丁烯(benzocyclobutene；BCB)、聚苯并噁唑(polybenzoxazole；PBO)、或其他絕緣材料形成。可利用一罩幕定義(mask-defined)光阻蝕刻製程移除一部分的鈍化層以形成鈍化層341的開口，藉此將接觸墊321曝露出來。開口的尺寸、形狀、及位置僅為例示，而非用以限制本發明。
絕緣層361，像是一聚合物層361，可形成於鈍化層341上方及鈍化層開口上方以覆蓋接觸墊321。可形成絕緣層361的開口以曝露出接觸墊321。可利用一罩幕定義(mask-defined)光阻蝕刻製程移除一部分的絕緣層361形成絕緣層361的開口，藉此將接觸墊321曝露出來。開口的尺寸、形狀、及位置僅為例示，而非用以限制本發明。
重配層(RDL)381可在絕緣層361的輪廓化(contour)之後形成。重配層(RDL)381可為連續的且覆蓋曝露的接觸墊321。雖然第1a圖僅顯示單層的介電質及內連線，重配層(RDL)381可由介電質和導電材料的交替層(alternating layers)形成，且可透過任何合適的製程形成，像是沉積、鑲嵌 (damascene)、雙鑲嵌(dual damascene)等製程。重配層(RDL)381可由例如：鋁(Al)、銅(Cu)、或銅合金(Cu alloy)所形成。重配層(RDL)381可由一電解電鍍(electrolytic plating)、濺鍍、物理氣相沉積(PVD)、或無電電鍍(electroless plating)製程形成。重配層(RDL)381可為單一層或使用例如：鈦(Ti)、鎢化鈦(TiW)、氮化鉭(TaN)、鉭(Ta)、或鉻(Cr)為黏著層的多層。裝置301可包括一些重配層(RDL)以形成層間內連線(inter-level interconnection)的網絡，根據半導體裝置的功能，其可與接觸墊321電性連接。
另一絕緣層371可形成於重配層(RDL)381上，其可為裝置301的頂層及表層。可形成絕緣層371的開口以曝露出重配層(RDL)381。可利用一罩幕定義(mask-defined)光阻蝕刻製程移除一部分的絕緣層371以形成絕緣層371的開口，藉此將重配層(RDL)381曝露出來。開口的尺寸、形狀、及位置僅為例示，而非用以限制本發明。絕緣層371可由一聚合物，像是環氧樹脂(epoxy)、聚亞醯胺(polyimide)、苯環丁烯(benzocyclobutene；BCB)、聚苯并噁唑(polybenzoxazole；PBO)、及其類似物所形成，雖然也可使用其他相對軟(soft)、通常為有機的介電材料來形成絕緣層。形成方法包括旋轉塗佈(spin coating)或其他常用的方法。絕緣層371的厚度可例如介於約5微米至約30微米。說明書中所載的尺寸僅為舉例，可隨著積體電路的微縮化(down-scaling)而改變。
凸塊下金屬(UBM)層包括凸塊下金屬(UBM)墊391，其可形成於絕緣層371的開口周圍並與重配層(RDL)381 連接。凸塊下金屬(UBM)墊391可由銅或銅合金所形成，其中銅合金可包括銀、鉻、鎳、錫、金、或前述之組合。額外層可形成於銅層上方，額外層像是鎳層、無鉛預銲層(lead-free pre-solder layer)、或前述之組合。凸塊下金屬(UBM)墊391可具有介於約1微米至約20微米之一厚度。凸塊下金屬(UBM)墊391也可稱為接觸墊。
上述的裝置301可僅為一實施例中的範例。可存在有別於第1a圖及上述所示之不同的裝置。例如，絕緣層361可能不會出現在某一些實施例中，或是在一些實施例中可有多層鈍化層341。在裝置301的絕緣層中可只包含一重配層(RDL)。
當晶粒601與裝置301之間的間隙(gap)被底部填充571所覆蓋時，晶粒601可透過一微凸塊層與裝置301進行封裝。晶粒601與連接器603相連，其中連接器603位於微凸塊層中的微凸塊485上。
連接器603可提供微凸塊485與晶粒601之間的連接。連接器603可為接觸凸塊，像是微凸塊或可控塌陷晶片連接(controlled collapse chip connection；C4)凸塊，且可包括像是錫或是其他合適的材料，例如銀或銅。在連接器603為錫銲錫凸塊(tin solder bump)之一實施例中，連接器603的形成可透過像是蒸鍍(evaporation)、電鍍(electroplating)、印刷(printing)、銲錫轉移(solder transfer)、銲球置放(ball placement)等任何合適的方法先形成一錫層，其較佳的厚度介於20微米至200微米，例如約100微米。一旦錫層形成於結構之上，可進行一回焊製程使材料成為想要的凸塊形狀。
可在晶粒601及裝置301之間使用底部填充571以加強晶粒601及裝置301之間的黏著性，並避免熱應力破壞晶粒601及裝置301之間的連接。一般來說，底部填充571的材料像是有機樹脂，是選來用以控制底部填充571的熱膨脹係數及收縮。一開始，使液體有機樹脂流入晶粒601及裝置301表面之間的間隙(gap)中，液體有機樹脂隨後硬化以控制在硬化(curing)過程中底部填充所產生的收縮現象。
微凸塊層可包括一微凸塊485、微凸塊導線481及483，其中微凸塊485被用來連接其他晶粒像是晶粒601，而微凸塊導線481及483則為電感的一部份。微凸塊導線481及483和微凸塊485可在花費很少或不用額外成本的情況下同時形成，可具有相似的高度，也可由相似的材料形成。微凸塊層的高度可由微凸塊485的高度來定義，而微凸塊485的高度取決於形成封裝體的技術。舉例來說，以目前的技術來說，微凸塊層的高度可介於約10微米至約50微米的範圍內，例如約27微米。
微凸塊485可包括形成於銅層475之上的一銲錫凸塊471。銲錫凸塊471與銅層475之間可視情況包括一鎳層473。銲錫凸塊471可包括一導電銲錫材料，像是錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、銅(Cu)、鉍(bismuthinite；Bi)、前述之合金、或其他導電材料之組合。例如，銲錫凸塊471可為一銅/錫銀(Cu/SnAg)銲錫凸塊。微凸塊485的形成可透過濺鍍、蒸鍍(evaporation)、電鍍(electroplating)、印刷(printing)、銲錫轉移(solder transfer)、或銲球置放(ball placement)等方式先形成厚度例如為15微米之一錫層，接著形成一鎳層473，最後形成 一銲錫層471像是無鉛銲錫錫銀(SnAg)，利用相同或相似的方法依序形成每一層。然後，進行一回焊製程以使銲錫層471形成想要的凸塊形狀，如所示的銲錫凸塊471。任何適合形成微凸塊485的方式都可替換使用。例如，可利用可控塌陷晶片連接新製程(Controlled Collapse Chip Connection New Process；C4NP)來形成微凸塊485。
微凸塊485可位於裝置301的凸塊下金屬(UBM)墊391上，有時在本文中稱為接觸墊。可將凸塊下金屬(UBM)墊391完全或部分的填入絕緣層的開口，絕緣層像是一聚合物層371。凸塊下金屬(UBM)墊391更可連接至一金屬層，像是一重配層(RDL)381或裝置301中凸塊下金屬(UBM)墊391之下的接觸墊321。微凸塊485可具有介於約10微米至約50微米之一高度。隨著特徵尺寸及封裝體尺寸的縮小，實施例中的尺寸可變得比上述的尺寸小。另一方面，取決於特定感興趣的應用，微凸塊485可具有一較大的尺寸，像是倒裝晶片(flip-chip)凸塊或是封裝體凸塊之尺寸。
形成微凸塊導線481及483的材料與形成微凸塊485的材料可大致相似。微凸塊導線481及483可位於裝置301中的凸塊下金屬(UBM)墊391上，並可進一步與重配層(RDL)381或裝置301中的凸塊下金屬(UBM)墊391之下的接觸墊321連接。重配層(RDLs)381、微凸塊導線481及483、及位於微凸塊導線481及483之下的凸塊下金屬(UBM)墊391均為電感200的一部分，如第1b圖的俯視圖所示。如第1b圖所示，電感200為具有兩個輸入埠(input port)202及204的單圈(one-turn)對稱電 感。可利用對稱線206將電感200劃分為位於對稱線206一側包括微凸塊導線481的第一部分(first half)以及位於對稱線206另一側包括微凸塊導線483的第二部分(second half)。
如第1a圖所示，微凸塊導線481及483可包括多層：位於凸塊下金屬(UBM)墊391之上的層475可為一銅層；位於層475之上的層473可為一鎳層；位於層473之上的層471可為一無鉛銲層，像是錫銀(SnAg)。另一方面，微凸塊導線481及483可只有兩層，位於凸塊下金屬(UBM)墊391之上的層475可為一銅層，而層471可為一無鉛銲層，像是錫銀(SnAg)，沒有鎳層473。層471可為由錫銀(SnAg)所形成的無鉛銲層，其中銀(Ag)介於約1%至約2%，且錫(Sn)介於約99%至約98%。層471、473、及475的高度可大約相同或不同，可根據不同的需求而改變。例如，銅層475、鎳層473及無鉛銲層471的高度比可為15/1.5/10。微凸塊導線481及483的總高度可介於約10微米至約50微米的範圍內，例如：約27微米。
微凸塊導線481及483可為具有約10微米至約100微米寬度之矩形。微凸塊導線481及483的寬度可大約相同。微凸塊導線481及483可具有一窄的、寬的、或漸縮(tapered)的形狀。微凸塊導線481及483的主體(body)大致上可具有一固定的厚度。微凸塊導線481及483在俯視角度下可具有其他形狀，像是圓形、八角形、矩形、在相反端具有兩個梯形的拉長六角形、橢圓形、或菱形。
第1c圖顯示第1a圖中封裝體100的簡化視圖。如第1c圖所示，封裝體100可形成於裝置301上。裝置301包括一基 板302、一絕緣層361/371，其代表了第1a圖中的絕緣層361及371、以及絕緣層中的一重配層(RDL)381。微凸塊導線481及483可形成於裝置301上方，且分別與重配層(RDL)381連接。微凸塊導線481及483與連接的重配層(RDL)381均為第1b圖中所示電感200的一部分。底部填充571可覆蓋微凸塊導線481及483。一晶粒可被放置於裝置301及底部填充571之上，並透過連接器與微凸塊連接，未顯示於第1c圖。
第1b圖中所示電感200的另一個實施例以類似的方式顯示在第1d圖中。如第1d圖所示，封裝體100可形成於裝置301上。裝置301包括一基板302及一絕緣層361/371。裝置301更包括一第一重配層(RDL)381及絕緣層中由導孔(vias)383連接的一第二重配層(RDL)382。微凸塊導線481及483可形成於裝置301之上且與重配層(RDL)381連接。微凸塊導線481及483與連接的重配層(RDLs)381及382為第1b圖所示電感200的一部分。底部填充571可覆蓋微凸塊導線481及483。一晶粒可被放置於裝置301及底部填充571之上，並由連接器與微凸塊連接，未顯示於第1d圖。
第2a圖到第2f圖為根據一些額外的實施例顯示由微凸塊層形成於封裝體中的電感之剖面圖及俯視圖。在第2a圖到第2f圖所示的實施例中，電感包括與底裝置上的重配層(RDL)連接的微凸塊導線，及與微凸塊層之上頂裝置中的重配層連接的微凸塊導線，而第1a圖到第1d圖所示的電感包括只與底裝置上的重配層(RDLs)連接的微凸塊導線。
如第2a圖所示，封裝體100可形成於第一裝置301 上，其中第一裝置301可為一底裝置。裝置301包括一基板302及一絕緣層361/371。裝置301更包括絕緣層中的一第一重配層(RDL)381。微凸塊層可包括微凸塊導線481及483，並可形成於第一裝置301之上。第二裝置601可為一頂裝置，且可形成於微凸塊導線481及483之上。裝置601也可包括一基板302、一絕緣層361/371、及絕緣層中的一第二重配層(RDL)381。底部填充571可覆蓋微凸塊導線481及483。
微凸塊導線481及483可與第一裝置301中的第一重配層(RDL)381及第二裝置601中的第二重配層(RDL)381連接。微凸塊導線481及483、第一重配層(RDL)381、及第二重配層(RDL)381均為第1b圖所示電感200的一部分。微凸塊導線481及483可包括多層：層475可為與裝置301中的第一重配層(RDL)381連接的銅(Cu)層，另一層475可為與裝置601中的第二重配層(RDL)381連接的銅(Cu)層，位於層475旁的層473可為鎳(Ni)層，位於層473旁的層471可為無鉛銲層，像是錫銀(SnAg)。微凸塊層的高度可由微凸塊導線481及483的高度定義，其取決於封裝體所使用的技術。例如，以目前的技術來說，微凸塊層的高度可介於約10微米至約50微米的範圍內，例如約27微米。
裝置301可為一中介片(interposer)，且為晶片或積體電路(IC)晶粒的一部分，其可位於晶粒的背側或前側。同樣地，裝置601可為一中介片(interposer)，且為晶片或積體電路(IC)晶粒的一部分，其可位於晶粒或封裝體結構的背側或前側。這些裝置和任何其他合適的裝置可交替的使用且皆可包括在本發明實施例的範疇中。
第2b圖顯示其他的實施例。如第2b圖所示，封裝體100可形成於第一裝置301上，其中第一裝置301可為一底裝置。裝置301包括一基板302及一絕緣層361/371。裝置301更包括位於絕緣層中由導孔383連接的第一重配層(RDL)381及第二重配層(RDL)382。微凸塊層可包括微凸塊導線481及483，並形成於第一裝置301之上。第二裝置601可形成於微凸塊導線481及483之上，且可為一頂裝置。裝置601也可包括一基板302、一絕緣層361/371、及位於絕緣層中的一第三重配層(RDL)381。底部填充571可覆蓋微凸塊導線481及483。
微凸塊導線481及483可與第一裝置301中的第一重配層(RDL)381、第二重配層(RDL)382、及第二裝置601中的第三重配層(RDL)381連接。微凸塊導線481及483、裝置301中的第一重配層(RDL)381和第二重配層(RDL)382、裝置601中的第三重配層(RDL)381均為第1b圖所示電感200的一部分。第2b圖所示實施例的其他部分與第2a圖、第1a圖所描述的對應元件相似。
除了第1b圖所示的對稱電感200，還有許多其他形式的電感。第2c圖的俯視圖顯示出堆疊的迴旋狀(spiral)電感300。對稱迴旋狀(spiral)電感300包括一第一分流繞組(shunt winding)481、一第二分流繞組(shunt winding)483、及代表兩分流繞組(shunt winding)之間交叉範圍的區域491。第2d圖顯示封裝體100中電感300的剖面圖。兩微凸塊導線481代表第2c圖中的第一分流繞組(shunt winding)481，兩微凸塊導線483代表第2c圖中的第二分流繞組(shunt winding)483。微凸塊導線481 及483與第一裝置301中的第一重配層(RDL)381及第二裝置601中的第二重配層(RDL)381連接。微凸塊導線481及483、第一重配層(RDL)381、及第二重配層(RDL)381都為第2c圖中所示電感300的一部分。第2d圖所示實施例的其他部分與第2a圖、第1a圖所描述的對應元件相似。
或者，第2e圖的俯視圖顯示一垂直螺旋狀(helical)電感400。螺旋狀(helical)電感400包括一微凸塊導線481作為垂直連接器，用以連接第一裝置301中的第一重配層(RDL)381及第二裝置601中的第二重配層(RDL)381。第一重配層(RDL)381及第二重配層(RDL)381是由多個圈(multi turns)式的單元形成。第一重配層(RDL)381及第二重配層(RDL)381可形成於裝置中單一重配層或多個重配層區段(section)中，且由層間的導孔連接，未顯示於第2e圖中。微凸塊層481、第一重配層(RDL)381、及第二重配層(RDL)381均為電感400的一部分。
或者，第2f圖顯示一河曲(meander)電感500之剖面圖。河曲(meander)電感500包括由微凸塊導線481所構成之垂直片段(segment)及由底裝置301及頂裝置601中重配層(RDLs)381所構成的水平片段，將上述片段連接以形成類似正弦(sinusoid-like)的河曲(meander)電感500。或者，裝置301及601中可有由層間導孔(vias)連接的多個重配層(RDLs)，未顯示於第2f圖中。第2f圖中所示實施例的其他部分與第2a圖及第1a圖中所述的對應元件相似。
變壓器為將電能從一電路傳遞至另一電路之功率轉換器。如第3a圖之剖面圖及第3b圖之俯視圖所示，變壓器600 是由一第一電感470及一第二電感480所形成。第3b圖顯示一變壓器600形狀的俯視圖。第一電感470包括微凸塊導線481，而第二電感480包括微凸塊導線483。微凸塊導線481及483與底裝置301中的重配層(RDLs)381耦合。底裝置301更包括一基板302、一絕緣層361/371。第一電感470可與地面耦合，標記成“-”，作為兩個互補訊號的差動對(differential pair)的一終端。第二電感480可與一電源耦合，標記成“+”，其可作為差動對(differential pair)的另一個終端。這具有“-”及“+”標記的兩個終端可為反相(out-of-phase)，其可介於約170度至約190度，例如180度。透過可使兩電感之間產生電磁耦合的方式，利用介電材料將第一電感470與第二電感480物理性分離。即使第3b圖所示的電感470及480只有一個圈(turn)，電感470及480可包括多個圈。
第3a圖及第3b圖所示的變壓器600僅為舉例，其中第3b圖只顯示出變壓器600可能具有的形狀之一，也可形成許多其他的變化。例如，裝置301中可具有多個藉由電感470及480連接之重配層(RDLs)。如第2a圖到第2f圖所示，微凸塊導線481及483上方可有一第二裝置，且第二裝置的重配層(RDLs)可為電感的一部分。電感可為各種類型的電感，例如：對稱電感、迴旋狀(spiral)電感、螺旋狀(helical)、及河曲(meander)電感。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為 準。
100‧‧‧封裝體
301、601‧‧‧裝置、晶粒
302‧‧‧基板
303‧‧‧穿孔
321‧‧‧接觸墊
341‧‧‧鈍化層
361、371‧‧‧絕緣層
381‧‧‧重配層
391‧‧‧凸塊下金屬(UBM)墊
471‧‧‧銲錫凸塊(層)
473‧‧‧鎳層
475‧‧‧銅層
481、483‧‧‧微凸塊導線
485‧‧‧微凸塊
571‧‧‧底部填充
603‧‧‧連接器

Claims (10)

  1. 一種封裝體，包括：一第一裝置，包括一第一重配層(RDL)；一微凸塊層，位於該第一裝置之上，包括與該第一重配層(RDL)連接的一第一微凸塊導線；以及一第一電感，包括該第一重配層(RDL)及該第一微凸塊導線。
  2. 如申請範圍第1項所述之封裝體，其中該第一微凸塊導線位於一凸塊下金屬(UBM)墊上，該凸塊下金屬(UBM)墊與該第一重配層(RDL)連接，且該第一電感更包括該凸塊下金屬(UBM)墊，其中該第一裝置更包括一鈍化層，位於該第一重配層下，且一絕緣層位於該第一重配層(RDL)上且曝露出該第一重配層(RDL)以與該凸塊下金屬(UBM)墊連接。
  3. 如申請範圍第1項所述之封裝體，其中該第一微凸塊導線包括一銅層及一焊料層。
  4. 如申請範圍第1項所述之封裝體，其中該第一裝置包括與該第一重配層(RDL)連接的一第二重配層(RDL)，且該第一電感更包括該第二重配層(RDL)。
  5. 如申請範圍第1項所述之封裝體，尚包括一第二裝置，位於該微凸塊層之上，其中該第二裝置包括與該第一微凸塊導線連接的一第三重配層(RDL)，且該第一電感包括該第一重配層(RDL)、該第三重配層(RDL)、及該第一微凸塊導線。
  6. 如申請範圍第5項所述之封裝體，其中該第一裝置中的該第一重配層(RDL)為一螺旋狀(helical)，包括該第一裝置中的多個圈(multi turns)。
  7. 如申請範圍第5項所述之封裝體，尚包括一第二微凸塊導線，其中該第一微凸塊導線為該第一電感的一第一分流繞組(shunt winding)，且該第二微凸塊導線為該第一電感的一第二分流繞組，且該第一電感為一迴旋狀(spiral)電感。
  8. 如申請範圍第5項所述之封裝體，尚包括一第三微凸塊導線，其中該第一電感為一河曲(meander)電感，包括該第一微凸塊導線及該第三微凸塊導線。
  9. 一種封裝體的製造方法，包括：提供一第一裝置，包括一鈍化層、位於該鈍化層之上的一第一重配層(RDL)、位於該第一重配層(RDL)上且具有一開口曝露出該第一重配層(RDL)的一絕緣層、及一第一凸塊下金屬(UBM)墊，覆蓋該絕緣層的該開口並與該第一重配層(RDL)連接；形成一第一微凸塊導線，位於該第一凸塊下金屬(UBM)墊上，且與該第一重配層(RDL)連接；以及形成一第一電感，包括該第一重配層(RDL)及該第一微凸塊導線。
  10. 如申請範圍第9項所述之封裝體的製造方法，尚包括：提供一第二裝置，位於該第一微凸塊導線之上，其中該第二裝置包括一第二重配層(RDL)，以及與該第二重配 層(RDL)連接的一第二凸塊下金屬(UBM)墊；以及連接該第二凸塊下金屬(UBM)墊至該第一微凸塊導線，其中該第一電感包括該第一裝置中的該第一重配層(RDL)，位於該第一裝置與該第二裝置之間的該第一微凸塊導線，以及該第二裝置中的該第二重配層(RDL)。
TW102144776A 2013-01-23 2013-12-06 封裝體及其製造方法 TWI523169B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/747,861 US8896094B2 (en) 2013-01-23 2013-01-23 Methods and apparatus for inductors and transformers in packages

Publications (2)

Publication Number Publication Date
TW201431022A true TW201431022A (zh) 2014-08-01
TWI523169B TWI523169B (zh) 2016-02-21

Family

ID=51207080

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102144776A TWI523169B (zh) 2013-01-23 2013-12-06 封裝體及其製造方法

Country Status (2)

Country Link
US (2) US8896094B2 (zh)
TW (1) TWI523169B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107210231A (zh) * 2014-12-01 2017-09-26 恩都冉科技 具有集成无源组件的开关式功率级
CN110610921A (zh) * 2018-06-15 2019-12-24 台湾积体电路制造股份有限公司 集成电路、半导体器件及其制造方法

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8896094B2 (en) 2013-01-23 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for inductors and transformers in packages
US9171798B2 (en) * 2013-01-25 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for transmission lines in packages
US8941212B2 (en) * 2013-02-06 2015-01-27 Taiwan Semiconductor Manufacturing Co., Ltd. Helical spiral inductor between stacking die
US9449945B2 (en) 2013-03-08 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Filter and capacitor using redistribution layer and micro bump layer
US9269640B2 (en) 2013-10-31 2016-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Repairing monolithic stacked integrated circuits with a redundant layer and lithography process
US9773754B2 (en) 2014-12-05 2017-09-26 Taiwan Semiconductor Manufacturing Co., Ltd. Input output for an integrated circuit
US9299736B2 (en) * 2014-03-28 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding with uniform pattern density
US9412675B2 (en) * 2014-05-19 2016-08-09 Micron Technology, Inc. Interconnect structure with improved conductive properties and associated systems and methods
TWI572007B (zh) * 2014-10-06 2017-02-21 瑞昱半導體股份有限公司 積體電感結構
US10283171B2 (en) 2015-03-30 2019-05-07 Taiwan Semicondutor Manufacturing Company, Ltd. Stacked die semiconductor device with separate bit line and bit line bar interconnect structures
US9653406B2 (en) * 2015-04-16 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive traces in semiconductor devices and methods of forming same
US9543192B2 (en) * 2015-05-18 2017-01-10 Globalfoundries Singapore Pte. Ltd. Stitched devices
US10379156B2 (en) 2015-05-29 2019-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Bump ball testing system and method
US9627411B2 (en) 2015-06-05 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional transistor and methods of manufacturing thereof
US10204205B2 (en) 2016-01-07 2019-02-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of determining colorability of a semiconductor device and system for implementing the same
US10163558B2 (en) 2016-01-21 2018-12-25 Globalfoundries Inc. Vertically stacked inductors and transformers
US10269702B2 (en) * 2016-01-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Info coil structure and methods of manufacturing same
JP2017139316A (ja) * 2016-02-03 2017-08-10 ソニー株式会社 半導体装置および製造方法、並びに電子機器
US10930603B2 (en) 2016-03-22 2021-02-23 Taiwan Semiconductor Manufacturing Co., Ltd. Coaxial through via with novel high isolation cross coupling method for 3D integrated circuits
US10037897B2 (en) 2016-11-29 2018-07-31 Taiwan Semiconductor Manufacturing Co., Ltd. Inter-fan-out wafer level packaging with coaxial TIV for 3D IC low-noise packaging
US10043745B2 (en) 2016-04-01 2018-08-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package devices integrated with inductor
US9905471B2 (en) 2016-04-28 2018-02-27 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit structure and method forming trenches with different depths
US10222412B2 (en) 2016-06-01 2019-03-05 Taiwan Semiconductor Manufacturing Co., Ltd. IC degradation management circuit, system and method
US10539617B2 (en) 2016-06-02 2020-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Scan architecture for interconnect testing in 3D integrated circuits
US10685911B2 (en) 2016-06-30 2020-06-16 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US10043740B2 (en) * 2016-07-12 2018-08-07 Intel Coporation Package with passivated interconnects
US9893189B2 (en) 2016-07-13 2018-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Method for reducing contact resistance in semiconductor structures
KR102628861B1 (ko) 2016-09-13 2024-01-25 삼성전자주식회사 반도체 패키지 및 재배선 패턴 형성 방법
US10541218B2 (en) * 2016-11-29 2020-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution layer structure and fabrication method therefor
US10163690B2 (en) 2016-11-30 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. 2-D interconnections for integrated circuits
US10475718B2 (en) * 2017-05-18 2019-11-12 Advanced Semiconductor Engineering, Inc. Semiconductor device package comprising a dielectric layer with built-in inductor
WO2019066984A1 (en) * 2017-09-30 2019-04-04 Intel Corporation INDUCTIVE PATH FORMATION USING CHIP INTERCONNECTIONS
US10756037B2 (en) * 2018-05-15 2020-08-25 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and fabricating method thereof
US11172142B2 (en) 2018-09-25 2021-11-09 Taiwan Semiconductor Manufacturing Co., Ltd. Image sensor for sensing LED light with reduced flickering
US10861808B2 (en) 2018-11-21 2020-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding structure of dies with dangling bonds
CN111066143B (zh) * 2019-06-03 2023-01-24 深圳市汇顶科技股份有限公司 封装结构及封装方法
WO2020245416A1 (en) * 2019-06-07 2020-12-10 Rockley Photonics Limited Silicon photonic interposer with two metal redistribution layers
US11239193B2 (en) 2020-01-17 2022-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11177065B2 (en) * 2020-03-30 2021-11-16 Qualcomm Incorporated Thermal paths for glass substrates
KR20220022602A (ko) * 2020-08-19 2022-02-28 삼성전자주식회사 반도체 패키지

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5477086A (en) * 1993-04-30 1995-12-19 Lsi Logic Corporation Shaped, self-aligning micro-bump structures
US6614325B1 (en) 2000-08-31 2003-09-02 Northrop Grumman Corporation RF/IF signal distribution network utilizing broadside coupled stripline
US7145411B1 (en) 2002-03-18 2006-12-05 Applied Micro Circuits Corporation Flexible differential interconnect cable with isolated high frequency electrical transmission line
JP3808030B2 (ja) 2002-11-28 2006-08-09 沖電気工業株式会社 半導体装置及びその製造方法
CA2418674A1 (en) 2003-02-07 2004-08-07 Tak Shun Cheung Transmission lines and transmission line components with wavelength reduction and shielding
KR100731544B1 (ko) 2006-04-13 2007-06-22 한국전자통신연구원 다층배선 코플래너 웨이브가이드
US7518229B2 (en) 2006-08-03 2009-04-14 International Business Machines Corporation Versatile Si-based packaging with integrated passive components for mmWave applications
US8028406B2 (en) 2008-04-03 2011-10-04 International Business Machines Corporation Methods of fabricating coplanar waveguide structures
US8163597B2 (en) * 2009-03-24 2012-04-24 Stats Chippac, Ltd. Semiconductor device and method of forming no-flow underfill material around vertical interconnect structure
EP2414801B1 (en) 2009-03-30 2021-05-26 QUALCOMM Incorporated Chip package with stacked processor and memory chips
JP2011100989A (ja) 2009-10-09 2011-05-19 Renesas Electronics Corp 半導体装置
US8519537B2 (en) * 2010-02-26 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US9735113B2 (en) * 2010-05-24 2017-08-15 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming ultra thin multi-die face-to-face WLCSP
US8471358B2 (en) * 2010-06-01 2013-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. 3D inductor and transformer
US8624353B2 (en) * 2010-12-22 2014-01-07 Stats Chippac, Ltd. Semiconductor device and method of forming integrated passive device over semiconductor die with conductive bridge and fan-out redistribution layer
SG183648A1 (en) 2011-02-28 2012-09-27 Agency Science Tech & Res A wafer level package and a method of forming the same
US9160346B2 (en) * 2011-03-15 2015-10-13 Rambus Inc. Area and power efficient clock generation
US8610247B2 (en) * 2011-12-30 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for a transformer with magnetic features
US8907469B2 (en) * 2012-01-19 2014-12-09 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package assembly and method of forming the same
US8754818B2 (en) * 2012-07-05 2014-06-17 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated antenna structure on separate semiconductor die
US9305854B2 (en) * 2012-08-21 2016-04-05 Stats Chippac, Ltd. Semiconductor device and method of forming RDL using UV-cured conductive ink over wafer level package
US20140070404A1 (en) * 2012-09-12 2014-03-13 Shing-Ren Sheu Semiconductor package structure and interposer therefor
US8896094B2 (en) 2013-01-23 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for inductors and transformers in packages
US9449945B2 (en) 2013-03-08 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Filter and capacitor using redistribution layer and micro bump layer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107210231A (zh) * 2014-12-01 2017-09-26 恩都冉科技 具有集成无源组件的开关式功率级
CN107210231B (zh) * 2014-12-01 2019-12-27 朝阳半导体技术江阴有限公司 具有集成无源组件的开关式功率级
US11605580B2 (en) 2014-12-01 2023-03-14 Chaoyang Semiconductor (Shanghai) Co., Ltd Switched power stage with integrated passive components
CN110610921A (zh) * 2018-06-15 2019-12-24 台湾积体电路制造股份有限公司 集成电路、半导体器件及其制造方法

Also Published As

Publication number Publication date
US20150031184A1 (en) 2015-01-29
US8896094B2 (en) 2014-11-25
US20140203397A1 (en) 2014-07-24
US9653531B2 (en) 2017-05-16
TWI523169B (zh) 2016-02-21

Similar Documents

Publication Publication Date Title
TWI523169B (zh) 封裝體及其製造方法
US11978712B2 (en) Method of forming semiconductor package transmission lines with micro-bump lines
US11069539B2 (en) 3D packages and methods for forming the same
US10854567B2 (en) 3D packages and methods for forming the same
TWI552297B (zh) 半導體裝置及其製造方法
KR101485656B1 (ko) 인터포저를 갖는 패키징 방법 및 장치
US9818668B2 (en) Thermal vias disposed in a substrate without a liner layer
US9455237B2 (en) Bowl-shaped solder structure