WO2019066984A1

WO2019066984A1 - Inductive pathway formation using die interconnects

Info

Publication number: WO2019066984A1
Application number: PCT/US2017/054667
Authority: WO
Inventors: Zhiguo QIAN; Kemal Aygun
Original assignee: Intel Corporation
Priority date: 2017-09-30
Filing date: 2017-09-30
Publication date: 2019-04-04

Abstract

System operable to form an inductive pathway. The system includes a first layer and a second layer communicatively coupled to the first layer via a plurality of bumps. Selected bumps in the plurality of bumps are connected via metal connections to form the inductive pathway that provides an inductance for the first layer.

Description

INDUCTIVE PATHWAY FORMATION USING DIE INTERCONNECTS

BACKGROUND

[0001] Integrated circuit packaging can include a stacked die configuration. For example, stacked dies can be electrically coupled to a package substrate. The stacked die configuration can provide a higher component density and has become increasingly popular for small form factor applications. For example, the stacked die configuration can be utilized in mobile phones, personal digital assistants (PDA), digital cameras, etc. The stacked dies can be connected to the package substrate by wire bond connections, or solder balls or bumps in a flip chip configuration. When using wire bonding, the stacked dies can be offset from one another to provide clearance for the wire bond connections.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Features and advantages of technology embodiments will be apparent from the detailed description which follows, taken in conjunction with the accompanying drawings, which together illustrate, by way of example, technology features; and, wherein:

[0003] FIG. 1 illustrates a three dimensional (3D) stacking architecture in accordance with an example embodiment;

[0004] FIG. 2 illustrates an inductive pathway for a stacked die architecture in accordance with an example embodiment;

[0005] FIG. 3 illustrates a two-turn inductive pathway in a stacked die architecture in accordance with an example embodiment;

[0006] FIG. 4 illustrates a two-turn inductive pathway in a stacked die architecture in accordance with an example embodiment;

[0007] FIG. 5 illustrates an inductance of a two-turn inductive pathway in accordance with an example embodiment;

[0008] FIG. 6 illustrates a quality factor of a two-turn inductive pathway in accordance with an example embodiment; [0009] FIG. 7 illustrates a system operable to form an inductive pathway in accordance with an example embodiment;

[0010] FIG. 8 illustrates an electronics package device in accordance with an example embodiment;

[0011] FIG. 9 depicts a flowchart of a method for forming an inductive pathway in an electronics package device in accordance with an example embodiment; and

[0012] FIG. 10 illustrates a computing system that includes a data storage device in accordance with an example embodiment.

[0013] Reference will now be made to the exemplary embodiments illustrated, and specific language will be used herein to describe the same. It will nevertheless be understood that no limitation on technology scope is thereby intended.

DESCRIPTION OF EMBODIMENTS

[0014] Before the disclosed technology embodiments are described, it is to be understood that this disclosure is not limited to the particular structures, process steps, or materials disclosed herein, but is extended to equivalents thereof as would be recognized by those ordinarily skilled in the relevant arts. It should also be understood that terminology employed herein is used for the purpose of describing particular examples or embodiments only and is not intended to be limiting. The same reference numerals in different drawings represent the same element. Numbers provided in flow charts and processes are provided for clarity in illustrating steps and operations and do not necessarily indicate a particular order or sequence.

[0015] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided, such as examples of layouts, distances, network examples, etc., to provide a thorough understanding of various invention embodiments. One skilled in the relevant art will recognize, however, that such detailed embodiments do not limit the overall inventive concepts articulated herein, but are merely representative thereof. [0016] As used in this written description, the singular forms "a," "an" and "the" include express support for plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a bit line" includes a plurality of such bit lines.

[0017] Reference throughout this written description to "an example" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in an example" or "an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment.

[0018] As used herein, a plurality of items, structural elements, compositional elements, and/or materials can be presented in a common list for convenience. However, these lists should be construed as though each member of the list is individually identified as a separate and unique member. Thus, no individual member of such list should be construed as a de facto equivalent of any other member of the same list solely based on their presentation in a common group without indications to the contrary. In addition, various embodiments and examples can be referred to herein along with alternatives for the various components thereof. It is understood that such embodiments, examples, and alternatives are not to be construed as defacto equivalents of one another, but are to be considered as separate and autonomous representations under the present disclosure.

[0019] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided, such as examples of layouts, distances, network examples, etc., to provide a thorough understanding of invention embodiments. One skilled in the relevant art will recognize, however, that the technology can be practiced without one or more of the specific details, or with other methods, components, layouts, etc. In other instances, well-known structures, materials, or operations may not be shown or described in detail to avoid obscuring aspects of the disclosure.

[0020] In this application, "comprises," "comprising," "containing" and "having" and the like can have the meaning ascribed to them in U.S. Patent law and can mean "includes," "including," and the like, and are generally interpreted to be open ended terms. The terms "consisting of or "consists of are closed terms, and include only the components, structures, steps, or the like specifically listed in conjunction with such terms, as well as that which is in accordance with U.S. Patent law. "Consisting essentially of or "consists essentially of have the meaning generally ascribed to them by U.S. Patent law. In particular, such terms are generally closed terms, with the exception of allowing inclusion of additional items, materials, components, steps, or elements, that do not materially affect the basic and novel characteristics or function of the item(s) used in connection therewith. For example, trace elements present in a composition, but not affecting the compositions nature or characteristics would be permissible if present under the "consisting essentially of language, even though not expressly recited in a list of items following such terminology. When using an open ended term in this written description, like "comprising" or "including," it is understood that direct support should be afforded also to "consisting essentially of language as well as "consisting of language as if stated explicitly and vice versa.

[0021] The terms "first," "second," "third," "fourth," and the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that any terms so used are interchangeable under appropriate circumstances such that the embodiments described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Similarly, if a method is described herein as comprising a series of steps, the order of such steps as presented herein is not necessarily the only order in which such steps may be performed, and certain of the stated steps may possibly be omitted and/or certain other steps not described herein may possibly be added to the method.

[0022] As used herein, comparative terms such as "increased," "decreased," "better," "worse," "higher," "lower," "enhanced," "minimized," "reduced," and the like refer to a property of a device, component, or activity that is measurably different from other devices, components, or activities in a surrounding or adjacent area, in a single device (with or without key or identified comparable features or elements), or in multiple comparable devices, in a group or class, in multiple groups or classes, or as compared to the known state of the art. For example, a data region that has an "increased" risk of corruption can refer to a region of a memory device which is more likely to have write errors to it than other regions in the same memory device. A number of factors can cause such increased risk, including location, fabrication process, number of program pulses applied to the region, etc.

[0023] The terms "left," "right," "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

[0024] The term "coupled," as used herein, is defined as directly or indirectly connected in an electrical or nonelectrical manner. "Directly coupled" items or objects are in physical contact and attached to one another. Objects described herein as being

"adjacent to" each other may be in physical contact with each other, in close proximity to each other, or in the same general region or area as each other, as appropriate for the context in which the phrase is used.

[0025] As used herein, the term "substantially" refers to the complete or nearly complete extent or degree of an action, characteristic, property, state, structure, item, or result. For example, an object that is "substantially" enclosed would mean that the object is either completely enclosed or nearly completely enclosed. The exact allowable degree of deviation from absolute completeness may in some cases depend on the specific context. However, generally speaking the nearness of completion will be so as to have the same overall result as if absolute and total completion were obtained. The use of "substantially" is equally applicable when used in a negative connotation to refer to the complete or near complete lack of an action, characteristic, property, state, structure, item, or result. For example, a composition that is "substantially free of particles would either completely lack particles, or so nearly completely lack particles that the effect would be the same as if it completely lacked particles. In other words, a composition that is "substantially free of an ingredient or element may still actually contain such item as long as there is no measurable effect thereof.

[0026] As used herein, the term "about" is used to provide flexibility to a numerical range endpoint by providing that a given value may be "a little above" or "a little below" the endpoint. However, it is to be understood that even when the term "about" is used in the present specification in connection with a specific numerical value, that support for the exact numerical value recited apart from the "about" terminology is also provided.

[0027] Numerical amounts and data may be expressed or presented herein in a range format. It is to be understood that such a range format is used merely for convenience and brevity and thus should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited. As an illustration, a numerical range of "about 1 to about 5" should be interpreted to include not only the explicitly recited values of about 1 to about 5, but also include individual values and sub-ranges within the indicated range. Thus, included in this numerical range are individual values such as 2, 3, and 4 and sub-ranges such as from 1-3, from 2-4, and from 3-5, etc., as well as 1, 1.5, 2, 2.3, 3, 3.8, 4, 4.6, 5, and 5.1 individually.

[0028] This same principle applies to ranges reciting only one numerical value as a minimum or a maximum. Furthermore, such an interpretation should apply regardless of the breadth of the range or the characteristics being described.

Example Embodiments

[0029] An initial overview of technology embodiments is provided below and then specific embodiments are described in further detail later. This initial summary is intended to aid readers in understanding the technology more quickly, but is not intended to identify key or essential technological features nor is it intended to limit the scope of the claimed subject matter. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

[0030] A three-dimensional (3D) integrated circuit (IC) is an integrated circuit that is manufactured by stacking silicon dies (or wafers) and interconnecting the silicon dies vertically using through-silicon vias (TSVs). These stacked silicon dies can behave as a single device, which can achieve performance improvements at reduced power as compared to conventional two-dimensional (2D) ICs. 3D ICs can exploit a z-direction to achieve various electrical performance benefits that were not possible with conventional 2D ICs. In upcoming years, 3D ICs are expected to have a broad impact in areas such as networking, graphics, mobile communications, consumer devices and computing. 3D ICs, as compared to conventional 2D ICs, can ease analog/digital integration challenges, increase interconnect speeds and bandwidth, reduce power constraints and enhance performance.

[0031] In one example, a 3D IC can utilize a multiple die packaging technology, in which multiple silicon dies are mounted on a package substrate. Silicon dies have been attached to a silicon-in-package (SiP) substrate using conventional technologies, such as a wire bond and/or a flip-chip, which can pose various performance, power and density challenges. A newer approach involves a silicon interposer substrate, which can provide finer die-to-die connections. For example, the silicon interposer substrate can include TSVs to provide connections from upper metal layers to backside metal layers within the silicon interposer substrate. The silicon interposer substrate can be positioned between the silicon dies and the package substrate, and can function to effectively connect the silicon dies to the package substrate. In other words, the silicon dies can be connected to the package substrate through the TSVs in the silicon interposer substrate between the silicon dies and the package substrate. This newer approach involving the silicon interposer substrate is sometimes referred to as 2.5D stacking.

[0032] In one configuration, a 3D IC can include one or multiple stacks of dies. Each stack of dies can include two or more dies that are connected together using TSVs. The stack(s) of dies can be connected to the silicon interposer substrate using fine pitch bumps (also referred to as micro bumps), which can have a pitch of 10-80 (in some cases 20-30) micro meters (μπι). The silicon interposer substrate can be connected to the package substrate using coarse pitch bumps (also referred to as flip-chip bumps), which can have a pitch of 50-300 μπι (in some cases 100 μπι). In addition, the package substrate can be connected to a circuit board via package bumps.

[0033] FIG. 1 illustrates an exemplary three dimensional (3D) stacking architecture. The 3D stacking architecture can include dies 110 (or integrated circuits), an interposer 120 (e.g., a silicon interposer) and a package substrate 130. The dies 110 can include a stack of multiple dies. In one example, the dies 110 can be connected to the interposer 120 via interconnects between the dies 110 and the interposer 120. For example, interconnects between the dies 110 and the interposer 120 can include a plurality of fine pitch bumps 135 (e.g., bumps having a pitch of 20-30 μπι). The interposer 120 can be an active interposer or a passive interposer. The interposer 120 can be connected to the package substrate 130 via interconnects between the interposer 120 and the package substrate 130. For example, interconnects between the interposer 120 and the package substrate 130 can include a plurality of coarse pitch bumps 140 (e.g., bumps having a pitch of 100 μπι). In other words, the dies 110 can be bonded to the interposer 120 face- to-face at a finer pitch, and the interposer 120 can be assembled to the package substrate 130 at a coarser pitch.

[0034] In one example, the fine pitch bumps 135 and the coarse pitch bumps 140 can be solder bumps. Alternatively, the fine pitch bumps 135 and the coarse pitch bumps 140 can be formed using an appropriate conductive metal, such as copper, gold, silver, nickel, tungsten, aluminum, etc.

[0035] In one configuration, input/output (I/O) circuits in dies or in an active interposer can utilize an on-die inductor. On-die inductors are widely used in various circuits, such as phase locked loop circuits and equalizer circuits. Recently, on-die inductors can be used to compensate a capacitance to increase a bandwidth of high-speed I/O transceiver circuits. In order to be more effective, these inductors are to be placed very close to the circuit, so the inductors are typically implemented in back end layers of the die.

[0036] In some cases, such inductors have been lateral inductors that used top metal layers in the dies, which consumed a significant area and restricted on-die routing. In other words, inductors were typically constructed laterally using the top metal layers in the dies, which would consume a greater die area and limited on-die connections of signals, powers and grounds.

[0037] In one example, for an increased data rate, a channel bandwidth can be a problem due to a capacitance in the dies caused by I/O circuitry (which can be positioned on top of the dies). This capacitance can be a bandwidth limiter when performing signaling at 30 gigatransfer per second (GT/s) to 100 GT/s (i.e., high data rates). Since this capacitance can be a bandwidth limiter, one solution to compensate for this capacitance is to use an inductor (e.g., a spiral inductor). The inductor can be effective in reducing the capacitance, thereby expanding the channel bandwidth and overcoming the problem of the capacitance being a bandwidth limiter.

[0038] In the present technology, an inductive pathway can be created using abundant fine pitch bumps (or vertical interconnects) and joints in a stacked die architecture. In other words, the stacked die architecture can include a large number of fine pitch bumps and joints, which can be used to form the inductive pathway with a reduced number of on-die connections. Thus, the inductive pathway can be formed vertically using the fine pitch bumps (or vertical interconnects) and joints, thereby resulting in a reduced area of on-die metal for the inductive pathway.

[0039] In one configuration, in the stacked die architecture, die(s) (e.g., a top die) and an interposer can be coupled using fine pitch bumps, and the interposer can be assembled to a package substrate using coarse pitch bumps. While the number of extra coarse pitch bumps can be limited, there can be a number of unused fine pitch bumps (e.g., the number of fine pitch bumps can be more than needed for I/O and power delivery connections). Since there can be an abundant number of fine pitch bumps that are not being used, adjacent fine pitch bumps (and corresponding metal connections) can be used to form inductors for the dies. When using the fine pitch bumps, these inductors can be formed vertically (as opposed to laterally in previous solutions), thereby consuming a reduced die area and not constraining on-die connections of signals, powers and grounds.

[0040] FIG. 2 illustrates an exemplary inductive pathway for a stacked die architecture. The inductive pathway can be formed using bumps (e.g., fine pitch bumps) between layers, such as a first layer and a second layer, as well as corresponding metal connections in the dies or in the die and the interposer, respectively. As a specific example, the inductive pathway can be formed between dies or between a die and an interposer (e.g., the first layer can be a first die and the second layer can be a second die, or the first layer can be a die and the second layer can be an interposer). The bumps can be used along with the corresponding metal connections to form the inductive pathway. In one example, the inductive pathway can be formed using two pairs of adjacent bumps and corresponding metal connections in one or more of the dies or the interposer. The bumps that are used to form the inductive pathway can be extra bumps that are not used for another purpose (e.g., I/O and power delivery connections).

[0041] In one example, the inductive pathway can be formed for the stacked die architecture using a metal connection of a first layer, a pair of bumps (e.g., fine pitch bumps) of the first layer, a pair of solder joints, a pair of bumps of a second layer that is positioned below the first layer, and a metal connection of the second layer. More specifically, the metal connection of the first layer can be coupled to the pair of bumps of the first layer. The pair of bumps of the first layer can be coupled to the pair of solder joints, respectively. The pair of solder joints can be coupled to the pair of bumps of the second layer, respectively. The pair of bumps of the second layer can be coupled to the metal connection of the second layer. The coupling of these components (i.e., the metal connections, bumps, and solder joints) can form the inductive pathway for the stacked die architecture. In addition, since the inductive pathway can be vertically formed using the bumps (or vertical interconnects), as opposed to being formed laterally, the inductive pathway can consume a reduced amount of die area.

[0042] In the example shown in FIG. 2, the inductive pathway can be formed for the stacked die architecture using a top metal of a top die 202, a pair of bumps 204 (e.g., fine pitch bumps) of the top die 202, a pair of solder joints 206, a pair of bumps of a bottom die or interposer 208, and a top metal of the bottom die or interposer 210. More specifically, the top metal of a top die 202 can be coupled to the pair of bumps of the top die 204. The pair of bumps of the top die 204 can be coupled to the pair of solder joints 206, respectively. The pair of solder joints 206 can be coupled to the pair of bumps of the bottom die or interposer 208, respectively. In addition, the pair of bumps of the bottom die or interposer 208 can be coupled to the top metal of the bottom die or interposer 210. Therefore, the inductive pathway can be formed using a pair of bumps associated with a first die (e.g., a top die) and a pair of bumps associated with a second die (e.g., a bottom die), a pair of solder joints, and metal associated with the first die and the second die, respectively. In one example, the inductive pathway formed by the stacked die architecture can be an open loop inductive pathway, as there can be a gap in the top metal of the top die 202. [0043] Alternatively, the inductive pathway can be formed using a pair of bumps associated with a die and a pair of bumps associated with an interposer, a pair of solder joints, and metal associated with the die and the interposer, respectively. In this example, the two pairs of bumps can be a minimum number of bumps necessary to form the inductive pathway.

[0044] In one configuration, the inductive pathway can be formed using an increased number of bumps and corresponding metal connections in order to form a more complex inductive pathway. For example, the inductive pathway can be formed using an array of bumps (e.g., a 2x3 array of bumps, a 4x6 array of bumps, and an 8x10 array of bumps). In some cases, specific bumps within the array of bumps can be depopulated. In other words, depopulated bumps within the array of bumps may not be part of the inductive pathway. Depending on a size of the array of bumps, the inductive pathway can form a defined number of turns (e.g., a single turn, 2 turns, 5 turns, or 10 turns). In one example, an increased number of bumps can be used to form a larger inductive pathway with an increased number of turns, thereby resulting in an increased inductance for the inductive pathway. In other words, increasing the number of bumps and the number of turns can increase the inductance for the inductive pathway. Therefore, depending on a desired amount of inductance for a stacked die architecture, a number of bumps and turns for an inductive pathway can be selected appropriately. In addition, on- die metal connections can be arranged closer to each other to concentrate current flow, thereby leading to an increased amount of inductance for the inductive pathway.

[0045] FIG. 3 illustrates a top view of an exemplary two-turn inductive pathway in a stacked die architecture. The two-turn inductive pathway can be formed using fine pitch bumps, solder joints and corresponding metal connections. The fine pitch bumps can be associated with one or more die(s) or an interposer. The fine pitch bumps can form an array (e.g., a two-dimensional array of fine pitch bumps). In some cases, specific fine pitch bumps within the two-dimensional array of fine pitch bumps can be depopulated. In other words, depopulated fine pitch bumps within the two-dimensional array may not be part of (i.e., be outside of) the two-turn inductive pathway. In a specific example, the two-dimensional array can be a 2x3 array of fine pitch bumps with a middle two fine pitch bumps being populated, and each of the fine pitch bumps can have a bump pitch of 30 μπι. As shown, current can enter into the two-turn inductive pathway and current can exit the two-turn inductive pathway. More specifically, the current can pass through metal connections between the fine pitch bumps, and then the current can exit the two- turn inductive pathway.

[0046] FIG. 4 illustrates a three-dimensional (3D) view of an exemplary two-turn inductive pathway in a stacked die architecture. The two-turn inductive pathway can be formed using fine pitch bumps, solder joints and corresponding metal connections. As shown, current can enter into the two-turn inductive pathway and current can exit the two-turn inductive pathway.

[0047] FIG. 5 illustrates an example of an inductance of a two-turn inductive pathway. The two-turn inductive pathway can be formed using fine pitch bumps and

corresponding metal connections in a stacked die architecture. The inductance (in nanohenry, or nH) of the two-turn inductive pathway can vary depending on a frequency (in GHz). For example, the inductance of the two-turn inductive pathway can be approximately 0.145 nH when the frequency is 0 GHz, the inductance of the two-turn inductive pathway can decrease to approximately 0.11 nH when the frequency is 10 GHz, and the inductance of the two-turn inductive pathway can increase to

approximately 0.125 nH when the frequency is 30 GHz.

[0048] FIG. 6 illustrates an example of a quality factor of a two-turn inductive pathway. The quality factor of an inductor equals the ratio of its inductive reactance to its resistance at a given frequency. In other words, the quality factor can be a measure of the inductor's efficiency. The two-turn inductive pathway can be formed using fine pitch bumps and corresponding metal connections in a stacked die architecture. The quality factor of the two-turn inductive pathway can vary depending on a frequency (in GHz). For example, the quality factor of the two-turn inductive pathway can be approximately 6 when the frequency is 10 GHz, and the quality factor of the two-turn inductive pathway can gradually increase to approximately 8 when the frequency is 30 GHz.

[0049] FIG. 7 illustrates an exemplary system 700 operable to form an inductive pathway 750. The system 700 can include a first layer 710 and a second layer 720. The second layer 720 can be communicatively coupled to the first layer 710 via a plurality of bumps 730. Selected bumps 730 in the plurality of bumps 730 can be connected via metal connections 740 to form the inductive pathway 750 that provides an inductance for the first layer 710.

[0050] FIG. 8 illustrates an exemplary electronics package device 800. The electronics package device 800 can include a die 810. The electronics package device 800 can include an interposer 820. The interposer 820 can be communicatively coupled to the die 810 via a plurality of fine pitch bumps 830. Selected fine pitch bumps 830 in the plurality of fine pitch bumps 830 can be connected via metal connections 840 to form an inductive pathway 850 that provides an inductance for the die 810.

[0051] FIG. 9 depicts an exemplary flowchart of a method 900 for forming an inductive pathway in an electronics package device. The method can include the operation of connecting selected fine pitch bumps of a die in the electronics package device to selected fine pitch bumps of an interposer in the electronics package device via metal connections to form an inductive pathway that provides an inductance for the die, as in block 910.

[0052] FIG. 10 illustrates a general computing system or device 1000 that can be employed in the present technology. The computing system 1000 can include a processor 1002 in communication with a memory 1004. The memory 1004 can include any device, combination of devices, circuitry, and the like that is capable of storing, accessing, organizing and/or retrieving data. Non-limiting examples include SANs (Storage Area Network), cloud storage networks, volatile or non-volatile RAM, phase change memory, optical media, hard-drive type media, and the like, including combinations thereof.

[0053] The computing system or device 1000 additionally includes a local

communication interface 1006 for connectivity between the various components of the system. For example, the local communication interface 1006 can be a local data bus and/or any related address or control busses as may be desired.

[0054] The computing system or device 1000 can also include an I/O (input/output) interface 1008 for controlling the I/O functions of the system, as well as for I/O connectivity to devices outside of the computing system 1000. A network interface 1010 can also be included for network connectivity. The network interface 1010 can control network communications both within the system and outside of the system. The network interface can include a wired interface, a wireless interface, a Bluetooth interface, optical interface, and the like, including appropriate combinations thereof. Furthermore, the computing system 1000 can additionally include a user interface 1012, a display device 1014, as well as various other components that would be beneficial for such a system.

[0055] The processor 1002 can be a single or multiple processors, and the memory 1004 can be a single or multiple memories. The local communication interface 1006 can be used as a pathway to facilitate communication between any of a single processor, multiple processors, a single memory, multiple memories, the various interfaces, and the like, in any useful combination.

[0056] Various techniques, or certain aspects or portions thereof, can take the form of program code (i.e., instructions) embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, non-transitory computer readable storage medium, or any other machine-readable storage medium wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the various techniques. Circuitry can include hardware, firmware, program code, executable code, computer instructions, and/or software. A non-transitory computer readable storage medium can be a computer readable storage medium that does not include signal. In the case of program code execution on programmable computers, the computing device can include a processor, a storage medium readable by the processor (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device. The volatile and non-volatile memory and/or storage elements can be a RAM, EPROM, flash drive, optical drive, magnetic hard drive, solid state drive, or other medium for storing electronic data. The node and wireless device can also include a transceiver module, a counter module, a processing module, and/or a clock module or timer module. One or more programs that can implement or utilize the various techniques described herein can use an application programming interface (API), reusable controls, and the like. Such programs can be implemented in a high level procedural or object oriented programming language to communicate with a computer system. However, the program(s) can be implemented in assembly or machine language, if desired. In any case, the language can be a compiled or interpreted language, and combined with hardware implementations. Exemplary systems or devices can include without limitation, laptop computers, tablet computers, desktop computers, smart phones, computer terminals and servers, storage databases, and other electronics which utilize circuitry and programmable memory, such as household appliances, smart televisions, digital video disc (DVD) players, heating, ventilating, and air conditioning (HVAC) controllers, light switches, and the like.

Examples

[0057] The following examples pertain to specific technology embodiments and point out specific features, elements, or steps that can be used or otherwise combined in achieving such embodiments.

[0058] In one example, there is provided a system operable to form an inductive pathway. The system can include a first layer; and a second layer communicatively coupled to the first layer via a plurality of bumps, wherein selected bumps in the plurality of bumps are connected via metal connections to form the inductive pathway that provides an inductance for the first layer.

[0059] In one example of the system, the first layer is a die and the second layer is an interposer.

[0060] In one example of the system, the first layer is a first die and the second layer is a second die.

[0061] In one example of the system, the plurality of bumps includes fine pitch bumps.

[0062] In one example of the system, the plurality of bumps includes a two-dimensional array of fine pitch bumps.

[0063] In one example of the system, the plurality of bumps includes solder bumps.

[0064] In one example of the system, the selected bumps include a two-dimensional array of fine pitch bumps.

[0065] In one example of the system, one or more bumps in the two-dimensional array of bumps are depopulated to be outside of the inductive pathway.

[0066] In one example of the system, the inductive pathway is formed via a metal connection in the first layer, a pair of bumps in the first layer that are communicatively coupled to the metal connection in the first layer, a pair of joints, a metal connection in the second layer, and a pair of bumps in the second layer that are communicatively coupled to the metal connection in the second layer, wherein the pair of joints communicatively couples the pair of bumps in the first layer with the pair of bumps in the second layer.

[0067] In one example of the system, the inductive pathway includes a defined number of turns that is dependent on a number of bumps used to form the inductive pathway.

[0068] In one example of the system, the defined number of turns in the inductive pathway is increased to increase a level of inductance for the inductive pathway.

[0069] In one example of the system, the inductive pathway is a vertical inductive pathway that reduces a usage area of the first layer for the inductive pathway.

[0070] In one example of the system, the system can further comprise a third layer communicatively coupled to the second layer via a plurality of additional bumps, wherein the third layer includes a package substrate and the plurality of additional bumps includes coarse pitch bumps.

[0071] In one example of the system, the plurality of bumps are utilized for input/output (I/O) signaling and power delivery connections between the first layer and the second layer.

[0072] In one example of the system, the system is a three-dimensional integrated circuit with a stacked architecture.

[0073] In one example, there is provided an electronics package device. The electronics package device can include a die. The electronics package device can include an interposer communicatively coupled to the die via a plurality of fine pitch bumps.

Selected fine pitch bumps in the plurality of fine pitch bumps can be connected via metal connections to form an inductive pathway that provides an inductance for the die.

[0074] In one example of the electronics package device, the selected fine pitch bumps include a two-dimensional array of fine pitch bumps.

[0075] In one example of the electronics package device, one or more fine pitch bumps in the two-dimensional array of fine pitch bumps are depopulated to be outside of the inductive pathway. [0076] In one example of the electronics package device, the inductive pathway is formed via a metal connection in the die, a pair of fine pitch bumps in the die that are communicatively coupled to the metal connection in the die, a pair of solder joints, a metal connection in the interposer, and a pair of fine pitch bumps in the interposer that are communicatively coupled to the metal connection in the interposer, wherein the pair of solder joints communicatively couples the pair of fine pitch bumps in the die with the pair of fine pitch bumps in the interposer.

[0077] In one example of the electronics package device, the inductive pathway includes a defined number of turns that is dependent on a number of fine pitch bumps used to form the inductive pathway.

[0078] In one example of the electronics package device, the defined number of turns in the inductive pathway is increased to increase a level of inductance for the inductive pathway.

[0079] In one example of the electronics package device, the inductive pathway is a vertical inductive pathway that reduces a usage area of the die for the inductive pathway.

[0080] In one example of the electronics package device, the electronics package device further comprises a package substrate communicatively coupled to the interposer via a plurality of coarse pitch bumps.

[0081] In one example of the electronics package device, the plurality of fine pitch bumps are utilized for input/output (I/O) signaling and power delivery connections between the die and the interposer.

[0082] In one example of the electronics package device, the electronics package device is a three-dimensional integrated circuit with a stacked architecture.

[0083] In one example there is provided a method for forming an inductive pathway in an electronics package device. The method can comprise connecting selected fine pitch bumps of a die in the electronics package device to selected fine pitch bumps of an interposer in the electronics package device via metal connections to form an inductive pathway that provides an inductance for the die.

[0084] In one example of the method for forming an inductive pathway in an electronics package device, the method can further comprise forming the inductive pathway via a metal connection in the die, a pair of fine pitch bumps in the die that are communicatively coupled to the metal connection in the die, a pair of solder joints, a metal connection in the interposer, and a pair of fine pitch bumps in the interposer that are communicatively coupled to the metal connection in the interposer, wherein the pair of solder joints communicatively couples the pair of fine pitch bumps in the die with the pair of fine pitch bumps in the interposer.

[0085] In one example of the method for forming an inductive pathway in an electronics package device, the method can further comprise forming a defined number of turns in the inductive pathway, wherein an increased number of turns are formed in the inductive pathway to increase an amount of inductance for the inductive pathway.

[0086] In one example of the method for forming an inductive pathway in an electronics package device, the method can further comprise utilizing fine pitch bumps of the die and fine pitch bumps of the interposer for input/output (I/O) signaling and power delivery connections between the die and the interposer.

[0087] While the forgoing examples are illustrative of the principles of invention embodiments in one or more particular applications, it will be apparent to those of ordinary skill in the art that numerous modifications in form, usage and details of implementation can be made without the exercise of inventive faculty, and without departing from the principles and concepts of the disclosure.

Claims

CLAIMS What is claimed is:

1. A system operable to form an inductive pathway, comprising:

a first layer; and

a second layer communicatively coupled to the first layer via a plurality of bumps,

wherein selected bumps in the plurality of bumps are connected via metal connections to form the inductive pathway that provides an inductance for the first layer.

2. The system of claim 1, wherein the first layer is a die and the second layer is an interposer.

3. The system of claim 1, wherein the first layer is a first die and the second layer is a second die.

4. The system of claim 1, wherein the plurality of bumps includes fine pitch bumps.

5. The system of claim 1, wherein the plurality of bumps includes a two- dimensional array of fine pitch bumps.

6. The system of claim 1, wherein the plurality of bumps includes solder

bumps.

7. The system of claim 1, wherein the selected bumps include a two- dimensional array of fine pitch bumps.

8. The system of claim 7, wherein one or more bumps in the two-dimensional array of bumps are depopulated to be outside of the inductive pathway.

9. The system of claim 1, wherein the inductive pathway includes a metal connection in the first layer, a pair of bumps in the first layer that are communicatively coupled to the metal connection in the first layer, a pair of joints, a metal connection in the second layer, and a pair of bumps in the second layer that are communicatively coupled to the metal connection in the second layer, wherein the pair of joints communicatively couples the pair of bumps in the first layer with the pair of bumps in the second layer.

10. The system of claim 1, wherein the inductive pathway includes a defined number of turns that is dependent on a number of bumps used to form the inductive pathway.

11. The system of claim 10, wherein the defined number of turns in the inductive pathway is increased to increase a level of inductance for the inductive pathway.

12. The system of claim 1, wherein the inductive pathway is a vertical inductive pathway that reduces a usage area of the first layer for the inductive pathway.

13. The system of claim 1, further comprising a third layer communicatively coupled to the second layer via a plurality of additional bumps, wherein the third layer includes a package substrate and the plurality of additional bumps includes coarse pitch bumps.

14. The system of claim 1, wherein the plurality of bumps are utilized for

input/output (I/O) signaling and power delivery connections between the first layer and the second layer.

15. The system of claim 1, wherein the system is a three-dimensional integrated circuit with a stacked architecture.

16. An electronics package device, comprising: a die; and

an interposer communicatively coupled to the die via a plurality of fine pitch bumps,

wherein selected fine pitch bumps in the plurality of fine pitch bumps are connected via metal connections to form an inductive pathway that provides an inductance for the die.

17. The electronics package device of claim 16, wherein the selected fine pitch bumps include a two-dimensional array of fine pitch bumps.

18. The electronics package device of claim 17, wherein one or more fine pitch bumps in the two-dimensional array of fine pitch bumps are depopulated to be outside of the inductive pathway.

19. The electronics package device of claim 16, wherein the inductive pathway is includes a metal connection in the die, a pair of fine pitch bumps in the die that are communicatively coupled to the metal connection in the die, a pair of solder joints, a metal connection in the interposer, and a pair of fine pitch bumps in the interposer that are communicatively coupled to the metal connection in the interposer, wherein the pair of solder joints

communicatively couples the pair of fine pitch bumps in the die with the pair of fine pitch bumps in the interposer.

The electronics package device of claim 16, wherein the inductive pathway includes a defined number of turns that is dependent on a number of fine pitch bumps used to form the inductive pathway.

The electronics package device of claim 20, wherein the defined number of turns in the inductive pathway is increased to increase a level of inductance for the inductive pathway.

22. The electronics package device of claim 16, wherein the inductive pathway is a vertical inductive pathway that reduces a usage area of the die for the inductive pathway.

23. The electronics package device of claim 16, further comprising a package substrate communicatively coupled to the interposer via a plurality of coarse pitch bumps.

24. The electronics package device of claim 16, wherein the plurality of fine pitch bumps are utilized for input/output (I/O) signaling and power delivery connections between the die and the interposer.

25. The electronics package device of claim 16, wherein the electronics package device is a three-dimensional integrated circuit with a stacked architecture.

26. A method for forming an inductive pathway in an electronics package

device, the method comprising:

connecting selected fine pitch bumps of a die in the electronics package device to selected fine pitch bumps of an interposer in the electronics package device via metal connections to form an inductive pathway that provides an inductance for the die.

27. The method of claim 26, further comprising forming the inductive pathway via a metal connection in the die, a pair of fine pitch bumps in the die that are communicatively coupled to the metal connection in the die, a pair of solder joints, a metal connection in the interposer, and a pair of fine pitch bumps in the interposer that are communicatively coupled to the metal connection in the interposer, wherein the pair of solder joints communicatively couples the pair of fine pitch bumps in the die with the pair of fine pitch bumps in the interposer. The method of claim 26, further comprising forming a defined number of turns in the inductive pathway, wherein an increased number of turns are formed in the inductive pathway to increase an amount of inductance for the inductive pathway.

The method of claim 26, further comprising utilizing fine pitch bumps of the die and fine pitch bumps of the interposer for input/output (I/O) signaling and power delivery connections between the die and the interposer.