TW201428728A - A driving module with a common control node - Google Patents
A driving module with a common control node Download PDFInfo
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- TW201428728A TW201428728A TW102101424A TW102101424A TW201428728A TW 201428728 A TW201428728 A TW 201428728A TW 102101424 A TW102101424 A TW 102101424A TW 102101424 A TW102101424 A TW 102101424A TW 201428728 A TW201428728 A TW 201428728A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0283—Arrangement of drivers for different directions of scanning
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Crystallography & Structural Chemistry (AREA)
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
Description
本發明係有關於一種驅動電路，特別是指一種具共用控制端之驅動模組。
The invention relates to a driving circuit, in particular to a driving module with a common control end.
隨著現今科技蓬勃發展，資訊商品種類推陳出新，滿足了大眾不同的需求。由於液晶顯示裝置（Liquid Crystal Display，LCD）具有輕薄短小、低輻射劑量與低耗電量等優點，而傳統顯示裝置具有體積大、高耗電量與高輻射劑量，因此，現今市面上的顯示裝置漸漸將由液晶顯示裝置取代傳統顯示裝置，也因此液晶顯示裝置成為目前顯示裝置市場的主流。無論哪一類型液晶顯示裝置皆是需要設置驅動電路，用以驅動液晶面板，而在薄膜電晶體(Thin-Film Transistor，TFT)面板上，雙向掃描驅動電路用以控制畫素結構之TFT是否接收來自資料驅動電路所提供之資料訊號，藉此以讓畫素結構之畫素電極具對應資料訊號之電壓，因而構成共同電極與畫素電極之間形成電場，以驅動位於共同電極與畫素電極之間的液晶轉動，同時藉由電場的強度變化而調整液晶的轉動角度，由於雙向掃描驅動電路為輸出掃描訊號至TFT之閘極，用以驅動薄膜電晶體，因此雙向掃描驅動電路亦可稱為閘極驅動電路。With the rapid development of today's technology, the variety of information products has been updated to meet the different needs of the public. Since the liquid crystal display (LCD) has the advantages of light and thin, low radiation dose and low power consumption, the conventional display device has a large volume, high power consumption and high radiation dose, so the display on the market today The device will gradually replace the conventional display device by the liquid crystal display device, and thus the liquid crystal display device has become the mainstream of the current display device market. No matter which type of liquid crystal display device needs to be provided with a driving circuit for driving the liquid crystal panel, on the thin film transistor (TFT) panel, the bidirectional scanning driving circuit is used to control whether the TFT of the pixel structure is received. The data signal provided by the data driving circuit, so that the pixel electrode of the pixel structure has a voltage corresponding to the data signal, thereby forming an electric field between the common electrode and the pixel electrode to drive the common electrode and the pixel electrode. The liquid crystal rotates while adjusting the rotation angle of the liquid crystal by the intensity change of the electric field. Since the bidirectional scanning driving circuit outputs the scanning signal to the gate of the TFT to drive the thin film transistor, the bidirectional scanning driving circuit can also be called It is a gate drive circuit.
一般傳統薄膜電晶體液晶顯示器(TFT-LCD)面板是由一片薄膜電晶體(TFT)面板玻璃，與另一片彩色濾光片(Color Filter)玻璃貼合而成，二層玻璃中間再灌入液晶分子。而為了減少元件數目並降低製造成本，近年來逐漸發展成將驅動電路結構直接製作於顯示面板上，例如採用將閘極驅動電路(gate driver)整合於液晶面板(gate on array,GOA)之技術，也就是將雙向掃描驅動電路整合於液晶面板上，其為新型的量產技術，是在TFT面板的玻璃完成薄膜電晶體陣列(Array)製程後，再接著進行彩色濾光片的製程，且可提昇面板的畫素開口率並可有效提昇面板的亮度。A conventional thin film transistor liquid crystal display (TFT-LCD) panel is formed by a thin film transistor (TFT) panel glass laminated with another color filter glass, and a liquid crystal is poured into the second layer of glass. molecule. In order to reduce the number of components and reduce the manufacturing cost, in recent years, the driver circuit structure has been developed directly on the display panel, for example, a technology of integrating a gate driver into a gate on array (GOA). That is, the bidirectional scan driving circuit is integrated on the liquid crystal panel, which is a new mass production technology, which is a process of performing a color filter after the glass panel of the TFT panel completes the thin film transistor array (Array) process, and It can increase the panel aperture ratio and effectively increase the brightness of the panel.
如此，雙向掃描驅動電路在要求反應迅速且輕薄化設計的液晶面板需求下，又支援雙向掃描，需減低電路元件之間的相互影響，並需減低訊號之間的干擾，因此雙向掃描驅動電路既需簡化雙向掃描之控制電路布局。此外，隨著液晶顯示裝置之尺寸為了因應市場需求，而日漸增加，設置於液晶顯示裝置之驅動電路所占用之電路面積亦須依據液晶顯示裝置之尺寸而增加，因而導致驅動電路影響到液晶顯示裝置之電性，並且影響到液晶顯示裝置之邊框大小。In this way, the bidirectional scan driving circuit supports bidirectional scanning under the demand of a liquid crystal panel that requires a quick response and is light and thin, and needs to reduce the mutual influence between circuit components and reduce the interference between signals, so the bidirectional scan driving circuit is The control circuit layout of the two-way scanning needs to be simplified. In addition, as the size of the liquid crystal display device increases in response to market demand, the circuit area occupied by the driving circuit of the liquid crystal display device must also increase according to the size of the liquid crystal display device, thereby causing the driving circuit to affect the liquid crystal display. The electrical properties of the device and affect the frame size of the liquid crystal display device.
有鑑於此，本發明提出一種具共用控制端之驅動模組，其共用控制端而合併輸出單元，以減少驅動電路之使用面積，又可應用於GOA技術而讓驅動電路設置於薄型面板，又可支援雙向掃描。
In view of the above, the present invention provides a driving module with a shared control terminal, which shares the control terminal and combines the output units to reduce the use area of the driving circuit, and can be applied to the GOA technology to allow the driving circuit to be disposed on the thin panel. Can support two-way scanning.
本發明之一目的，在於提供一種具共用控制端之驅動模組，其縮減驅動電路之使用面積。It is an object of the present invention to provide a drive module having a shared control terminal that reduces the area of use of the drive circuit.
本發明之一目的，在於提供一種具共用控制端之驅動模組，其提供雙向掃描之掃描訊號。It is an object of the present invention to provide a drive module having a shared control terminal that provides a scan signal for two-way scanning.
本發明之一目的，在於提供一種具共用控制端之驅動模組，其提供複數時脈訊號至驅動電路而減少電晶體之操作時間，以降低功率消耗。An object of the present invention is to provide a driving module with a common control terminal, which provides a plurality of clock signals to the driving circuit to reduce the operating time of the transistor to reduce power consumption.
本發明係提供一種具共用控制端之驅動模組，其接收複數時脈訊號並接收一第一輸入電壓與一第二輸入電壓，驅動模組產生複數掃描訊號並依序輸出至一顯示面板，驅動模組包含複數輸出單元、一正向輸入單元與一反向輸入單元，其中該些輸出單元一併耦接至一控制端，正向輸入單元與反向輸入單元經控制端耦接該些輸出單元。正向輸入單元接收第一輸入電壓與n-1級以上的任一該些驅動模組之一前正向掃描訊號，正向輸入單元依據第一輸入電壓與前正向掃描訊號對控制端充放電；反向輸入單元接收第二輸入電壓與n+1級以上的任一該些驅動模組之一後反向掃描訊號，反向輸入單元依據第二輸入電壓與後反向掃描訊號對控制端充放電。該些輸出單元接收該些時脈訊號，以在正向輸入單元對該輸出單元充電時，依序產生複數正向掃描訊號並依序輸出，並在反向輸入單元對控制端充電時，依序產生複數反向掃描訊號並依序輸出。The invention provides a driving module with a shared control terminal, which receives a plurality of clock signals and receives a first input voltage and a second input voltage, and the driving module generates a plurality of scanning signals and sequentially outputs the signals to a display panel. The driving module includes a plurality of output units, a forward input unit and a reverse input unit, wherein the output units are coupled to a control end, and the forward input unit and the reverse input unit are coupled to each other via the control end. Output unit. The forward input unit receives the first forward voltage and one of the driving modules of the n-1 level or higher, and the forward input unit charges the control terminal according to the first input voltage and the front forward scanning signal. Discharging; the reverse input unit receives the second input voltage and one of the driving modules of the n+1 level or more, and then reverses the scanning signal, and the reverse input unit controls the second input voltage and the backward reverse scanning signal pair according to the second input voltage Charge and discharge. The output units receive the clock signals to sequentially generate a plurality of forward scan signals and output them sequentially when the output unit is charged by the forward input unit, and when the reverse input unit charges the control terminal, The sequence generates complex reverse scan signals and outputs them in sequence.
茲為使 貴審查委員對本發明之結構特徵及所達成之功效更有進一步之瞭解與認識，謹佐以較佳之實施例圖及配合詳細之說明，說明如後：
In order to give the review board members a better understanding and understanding of the structural features and the efficacies of the present invention, please refer to the preferred embodiment diagrams and the detailed descriptions as follows:
10．．．顯示裝置10. . . Display device
20．．．雙向掃描驅動電路20. . . Bidirectional scan drive circuit
22．．．驅動模組twenty two. . . Drive module
22a．．．第1驅動模組22a. . . First drive module
22b．．．第2驅動模組22b. . . Second drive module
22c．．．第3驅動模組22c. . . 3rd drive module
22x．．．第198驅動模組22x. . . 198th drive module
22y．．．第199驅動模組22y. . . 199th drive module
22z．．．第200驅動模組22z. . . 200th drive module
221．．．正向輸入單元221. . . Positive input unit
222．．．反向輸入單元222. . . Reverse input unit
223．．．輸出單元223. . . Output unit
223a．．．第一輸出單元223a. . . First output unit
223b．．．第二輸出單元223b. . . Second output unit
223c．．．第三輸出單元223c. . . Third output unit
223d．．．第四輸出單元223d. . . Fourth output unit
224．．．雜訊消除單元224. . . Noise cancellation unit
225．．．電晶體225. . . Transistor
226．．．電晶體226. . . Transistor
230．．．輸出電容230. . . Output capacitor
230a．．．第一輸出電容230a. . . First output capacitor
230b．．．第二輸出電容230b. . . Second output capacitor
230c．．．第三輸出電容230c. . . Third output capacitor
230d．．．第四輸出電容230d. . . Fourth output capacitor
231．．．控制電容231. . . Control capacitor
30．．．資料驅動電路30. . . Data drive circuit
40．．．顯示面板40. . . Display panel
402．．．畫素結構402. . . Pixel structure
50．．．驅動電路50. . . Drive circuit
52．．．第n-1驅動模組52. . . The n-1th drive module
54．．．第n驅動模組54. . . Nth drive module
56．．．第n+1驅動模組56. . . The n+1th driving module
An．．．控制端An. . . Control terminal
CLK1．．．第一時脈訊號CLK1. . . First clock signal
CLK2．．．第二時脈訊號CLK2. . . Second clock signal
CLK3．．．第三時脈訊號CLK3. . . Third clock signal
CLK4．．．第四時脈訊號CLK4. . . Fourth clock signal
OUT_1(n)．．．第一輸出端OUT_1(n). . . First output
OUT_2(n)．．．第二輸出端OUT_2(n). . . Second output
OUT_3(n)．．．第三輸出端OUT_3(n). . . Third output
OUT_4(n)．．．第四輸出端OUT_4(n). . . Fourth output
OUT_3(n_1)．．．前輸出端OUT_3(n_1). . . Front output
OUT_2(n+1)．．．後輸出端OUT_2(n+1). . . Rear output
O1(n-1)．．．第一輸出訊號O 1 (n-1). . . First output signal
O2(n-1)．．．第二輸出訊號O 2 (n-1). . . Second output signal
O3(n-1)．．．第三輸出訊號O 3 (n-1). . . Third output signal
O4(n-1)．．．第四輸出訊號O 4 (n-1). . . Fourth output signal
O1(n)．．．第一輸出訊號O 1 (n). . . First output signal
O2(n)．．．第二輸出訊號O 2 (n). . . Second output signal
O3(n)．．．第三輸出訊號O 3 (n). . . Third output signal
O4(n)．．．第四輸出訊號O 4 (n). . . Fourth output signal
O1(n+1)．．．第一輸出訊號O 1 (n+1). . . First output signal
O2(n+1)．．．第二輸出訊號O 2 (n+1). . . Second output signal
O3(n+1)．．．第三輸出訊號O 3 (n+1). . . Third output signal
O4(n+1)．．．第四輸出訊號O 4 (n+1). . . Fourth output signal
Vdd_f．．．第一輸入電壓Vdd_f. . . First input voltage
Vdd_r．．．第二輸入電壓Vdd_r. . . Second input voltage
Vss．．．參考電位Vss. . . Reference potential
第一A圖為本發明之一實施例之顯示裝置的方塊圖；
第一B圖為本發明之一實施例之驅動模組的方塊圖；
第二A圖為本發明之一實施例之驅動訊號於正向掃描的波形圖；
第二B圖為本發明之一實施例之驅動訊號於反向掃描的波形圖；以及
第三圖為本發明之一實施例之雙向掃瞄驅動電路的方塊圖。
1A is a block diagram of a display device according to an embodiment of the present invention;
1B is a block diagram of a driving module according to an embodiment of the present invention;
2A is a waveform diagram of a driving signal in a forward scan according to an embodiment of the present invention;
2B is a waveform diagram of a driving signal in reverse scanning according to an embodiment of the present invention; and a third diagram is a block diagram of a bidirectional scanning driving circuit according to an embodiment of the present invention.
請參閱第一A圖，其為本發明之一實施例之顯示裝置的方塊圖。如圖所示，顯示裝置10包含一雙向掃描驅動電路20、一資料驅動電路30與一顯示面板40，雙向掃描驅動電路20包含複數驅動模組22，本實施例之驅動模組22係以一第1驅動模組22a、一第2驅動模組22b、一第三驅動模組22c以及依序列至一第198驅動模組22x、一第199驅動模組22y與一第200驅動模組22z，本實施例之顯示裝置10係以800條掃描線作為舉例，並以每一驅動模組22分別輸出4個掃描訊號作為舉例，因此驅動模組22個數為200個。顯示面板40包含複數畫素結構402。Please refer to FIG. 1A, which is a block diagram of a display device according to an embodiment of the present invention. As shown in the figure, the display device 10 includes a bidirectional scan driving circuit 20, a data driving circuit 30 and a display panel 40. The bidirectional scanning driving circuit 20 includes a plurality of driving modules 22. The driving module 22 of the embodiment is a The first driving module 22a, the second driving module 22b, the third driving module 22c, and the sequence to a 198th driving module 22x, a 199th driving module 22y and a 200th driving module 22z, The display device 10 of the present embodiment is exemplified by 800 scan lines, and each of the drive modules 22 outputs four scan signals as an example. Therefore, the number of the drive modules 22 is 200. Display panel 40 includes a complex pixel structure 402.
顯示面板40上設有複數掃描線GL與複數資料線DL，雙向掃描驅動電路20之該些驅動模組22係分別經4條掃描線GL耦接至部分該些畫素結構402，但本發明不限於此，驅動模組22更可依據使用需求而增加掃描線GL之連接數量，且本發明每一驅動模組22最少可耦接三條掃描線GL。資料驅動電路30經該些資料線DL耦接至該些畫素結構402。顯示裝置10藉由該些驅動模組22依序輸出複數掃描訊號至所連接之該些畫素結構402，以驅動該些畫素結構402接收資料驅動電路30所輸出之資料訊號。本發明之顯示裝置10係支援雙向掃描，亦即雙向掃描驅動電路20輸出掃描訊號之順序可依正向掃描方向而讓該些驅動模組22由上往下依序輸出掃描訊號，例如以依序從第1驅動模組22a產生掃描訊號至第200驅動模組22z產生掃描訊號，亦可依反向掃描方向而讓該些驅動模組22由下往上依序輸出掃描訊號，例如以依序從第200驅動模組22z產生掃描訊號至第1驅動模組22a產生掃描訊號。The display panel 40 is provided with a plurality of scanning lines GL and a plurality of data lines DL. The driving modules 22 of the bidirectional scanning driving circuit 20 are respectively coupled to the plurality of pixel structures 402 via four scanning lines GL, but the present invention The driving module 22 can increase the number of connections of the scanning lines GL according to the use requirements, and each driving module 22 of the present invention can be coupled to at least three scanning lines GL. The data driving circuit 30 is coupled to the pixel structures 402 via the data lines DL. The display device 10 sequentially outputs the plurality of scanning signals to the connected pixel structures 402 by the driving modules 22 to drive the pixel structures 402 to receive the data signals output by the data driving circuit 30. The display device 10 of the present invention supports bidirectional scanning, that is, the sequence of outputting the scanning signals by the bidirectional scanning driving circuit 20 allows the driving modules 22 to sequentially output the scanning signals from the top to the bottom according to the forward scanning direction, for example, The scanning signal is generated from the first driving module 22a to the 200th driving module 22z to generate a scanning signal, and the driving modules 22 are sequentially outputted from the bottom to the top according to the reverse scanning direction, for example, The scanning signal is generated from the 200th driving module 22z to the first driving module 22a to generate a scanning signal.
請一併參閱第一B圖，其為本發明之一實施例之驅動模組的方塊圖。如圖所示，本發明之驅動模組22為應用於一驅動電路，例如:雙向掃描驅動電路，驅動模組22係包含一正向輸入單元221、一反向輸入單元222與複數輸出單元223，本實施例係以四個輸出單元223為例，也就是一第一輸出單元223a、一第二輸出單元223b、一第三輸出單元223c與一第四輸出單元223d。此外，驅動模組22更包含一雜訊消除單元224與複數輸出電容230，其中，本實施例係以四個輸出電容230為例，也就是一第一輸出電容230a、一第二輸出電容230b、一第三輸出電容230c與一第四輸出電容230d，且雜訊消除單元224包含一第一電晶體225、一第二電晶體226與一控制電容231。Please refer to FIG. B, which is a block diagram of a driving module according to an embodiment of the present invention. As shown in the figure, the driving module 22 of the present invention is applied to a driving circuit, for example, a bidirectional scanning driving circuit. The driving module 22 includes a forward input unit 221, a reverse input unit 222, and a complex output unit 223. In this embodiment, four output units 223 are taken as an example, that is, a first output unit 223a, a second output unit 223b, a third output unit 223c, and a fourth output unit 223d. In addition, the driving module 22 further includes a noise canceling unit 224 and a plurality of output capacitors 230. The present embodiment is exemplified by four output capacitors 230, that is, a first output capacitor 230a and a second output capacitor 230b. A third output capacitor 230c and a fourth output capacitor 230d, and the noise canceling unit 224 includes a first transistor 225, a second transistor 226 and a control capacitor 231.
該控制端An耦接至第一輸出單元223a之一第一端、第二輸出單元223b之一第一端、第三輸出單元223c之一第一端與第四輸出單元223d之第一端，正向輸入單元221之一第一端耦接至n-1級以上的任一驅動模組之一前輸出端OUT_3(n-1)，例如:如第一A圖所示，第200驅動模組22z之正向輸入單元耦接至第199驅動模組22y之第三輸出端。正向輸入單元221之一第二端接收第一輸入電壓Vdd_f，而反向輸入單元222之一第一端耦接至n+1級以上的任一驅動模組之一後輸出端OUT_2(n+1)，例如:如第一A圖所示，第1驅動模組22a之反向輸入單元耦接至第2驅動模組22b之第二輸出端。The control terminal An is coupled to one of the first end of the first output unit 223a, the first end of the second output unit 223b, the first end of the third output unit 223c, and the first end of the fourth output unit 223d. The first end of the forward input unit 221 is coupled to one of the front output terminals OUT_3(n-1) of any one of the n-1 stages or higher, for example, as shown in FIG. The forward input unit of the group 22z is coupled to the third output of the 199th drive module 22y. The second input end of the forward input unit 221 receives the first input voltage Vdd_f, and the first end of the reverse input unit 222 is coupled to one of the driving modules of the n+1 level or higher and the output end OUT_2 (n) +1), for example, as shown in FIG. A, the reverse input unit of the first driving module 22a is coupled to the second output end of the second driving module 22b.
反向輸入單元222之一第二端接收該第二輸入電壓Vdd_r，且正向輸入單元221之第三端與反向輸入單元222之第三端分別耦接一控制端An。第一輸出單元223a之一第二端接收一第一時脈訊號CLK1，第一輸出單元223a之一第三端耦接至一第一輸出端OUT_1(n)，第二輸出單元223b之一第二端接收一第二時脈訊號CLK2，第二輸出單元223b之一第三端耦接至一第二輸出端OUT_2(n)，第三輸出單元223c之一第二端接收一第三時脈訊號CLK3，第三輸出單元223c之一第三端耦接至一第三輸出端OUT_3(n)，第四輸出單元223d之一第二端接收一第四時脈訊號CLK4，第四輸出單元223d之一第三端耦接至一第四輸出端OUT_4(n)。The second end of the inverting input unit 222 receives the second input voltage Vdd_r, and the third end of the forward input unit 221 and the third end of the reverse input unit 222 are respectively coupled to a control end An. The second end of the first output unit 223a receives a first clock signal CLK1, and the third end of the first output unit 223a is coupled to a first output terminal OUT_1(n), and the second output unit 223b The second terminal receives a second clock signal CLK2, the third terminal of the second output unit 223b is coupled to a second output terminal OUT_2(n), and the second terminal of the third output unit 223c receives a third clock. The third end of the third output unit 223c is coupled to a third output terminal OUT_3(n), and the second end of the fourth output unit 223d receives a fourth clock signal CLK4, and the fourth output unit 223d One of the third ends is coupled to a fourth output terminal OUT_4(n).
第一輸出電容230a耦接於控制端An與第一輸出端OUT_1(n)之間，也就是第一輸出電容230a之一第一端耦接控制端An，第一輸出電容230a之一第二端耦接第一輸出端OUT_1(n)，第二輸出電容230b耦接於控制端An與第二輸出端OUT_2(n)之間，也就是第二輸出電容230b之一第一端耦接控制端An，第二輸出電容230b之一第二端耦接第二輸出端OUT_2(n)，第三輸出電容230c耦接於控制端An與第三輸出端OUT_3(n)之間，也就是第三輸出電容230c之一第一端耦接控制端An，第三輸出電容230c之一第二端耦接第三輸出端OUT_3(n)，第四輸出電容230d耦接於控制端An與第四輸出端OUT_4(n)之間，也就是第四輸出電容230d之一第一端耦接控制端An，第四輸出電容230d之一第二端耦接第四輸出端OUT_4(n)。The first output capacitor 230a is coupled between the control terminal An and the first output terminal OUT_1(n), that is, the first end of the first output capacitor 230a is coupled to the control terminal An, and the first output capacitor 230a is second. The first output terminal OUT_1(n) is coupled to the first output terminal OUT_1(n), and the second output capacitor 230b is coupled between the control terminal An and the second output terminal OUT_2(n), that is, the first end of the second output capacitor 230b is coupled to the first end. The second output terminal 230b is coupled to the second output terminal OUT_2(n), and the third output capacitor 230c is coupled between the control terminal An and the third output terminal OUT_3(n), that is, the first The first end of the third output capacitor 230c is coupled to the control terminal An. The second output terminal 230c is coupled to the third output terminal OUT_3(n), and the fourth output capacitor 230d is coupled to the control terminal An and the fourth terminal. The first end of the output terminal OUT_4(n), that is, the fourth output capacitor 230d, is coupled to the control terminal An, and the second end of the fourth output capacitor 230d is coupled to the fourth output terminal OUT_4(n).
雜訊消除單元224係耦接於控制端An，因此雜訊消除單元224耦接該正向輸入單元221、該反向輸入單元222與該輸出單元223，且雜訊消除單元224亦接收第一時脈訊號CLK1，其中，控制電容231接收第一時脈訊號CLK1並耦接第一電晶體225與第二電晶體226，第一電晶體225與第二電晶體226分別耦接至控制端An以及耦接參考電位Vss，其中第一電晶體225之一第一端耦接控制端An，第一電晶體225之一第二端耦接控制電容231，第一電晶體225之一第三端耦接至參考電位Vss，第二電晶體226之一第一端耦接於控制電容231與第一電晶體225之第二端之間，第二電晶體226之一第二端耦接控制端An，第二電晶體226之一第三端耦接參考電位Vss。The noise cancellation unit 224 is coupled to the control terminal An. Therefore, the noise cancellation unit 224 is coupled to the forward input unit 221, the reverse input unit 222, and the output unit 223, and the noise cancellation unit 224 also receives the first The clock signal CLK1, wherein the control capacitor 231 receives the first clock signal CLK1 and is coupled to the first transistor 225 and the second transistor 226. The first transistor 225 and the second transistor 226 are respectively coupled to the control terminal An. And coupling the reference potential Vss, wherein the first end of the first transistor 225 is coupled to the control end An, the second end of the first transistor 225 is coupled to the control capacitor 231, and the third end of the first transistor 225 The first end of the second transistor 226 is coupled between the control capacitor 231 and the second end of the first transistor 225, and the second end of the second transistor 226 is coupled to the control end. An third terminal of the second transistor 226 is coupled to the reference potential Vss.
正向輸入單元221經前輸出端OUT_3(n-1)接收一前正向掃描訊號，以依據第一輸入電壓Vdd_f與前正向掃描訊號而對控制端An充放電，且正向輸入單元221在依據第一輸入電壓Vdd_f與前正向掃描訊號而對該控制端An充電時，該些輸出單元223a、223b、223c與223d即分別依據所接收之第一時脈訊號CLK1、第二時脈訊號CLK2、第三時脈訊號CLK3與第四時脈訊號CLK4而依序產生複數正向掃描訊號至該些輸出端OUT_1(n)、OUT_2(n)、OUT_3(n)與OUT_4(n)；當該正向輸入單元221對該控制端An充電以讓該些輸出單元223輸出該正向掃描訊號時，該反向輸入單元222於該些輸出單元223a、223b、223c與223d產生該些正向掃描訊號一段時間後對該控制端An放電，特別是，該反向輸入單元222於該些輸出單元223a、223b、223c與223d產生該些正向掃描訊號後經一個時脈週期時間(clock cycle time)對該控制端An進行放電，因而讓控制端An之電位下拉，例如:如第二A圖所示，該些輸出單元223a、223b、223c與223d於T2至T5時脈週期時間依序產生正向掃描訊號，並於T7時脈週期時間放電。如此用以運作驅動電路之正向掃描模式，例如:如第一A圖所示，自第1驅動模組22a至第200驅動模組22z依序產生複數掃描訊號至該些掃描線GL，以正向掃描該些畫素結構402。The forward input unit 221 receives a front forward scan signal via the front output terminal OUT_3(n-1) to charge and discharge the control terminal An according to the first input voltage Vdd_f and the front forward scan signal, and the forward input unit 221 When the control terminal An is charged according to the first input voltage Vdd_f and the front forward scan signal, the output units 223a, 223b, 223c and 223d respectively depend on the received first clock signal CLK1 and the second clock. The signal CLK2, the third clock signal CLK3 and the fourth clock signal CLK4 sequentially generate a plurality of forward scan signals to the output terminals OUT_1(n), OUT_2(n), OUT_3(n) and OUT_4(n); When the forward input unit 221 charges the control terminal An to cause the output units 223 to output the forward scan signal, the reverse input unit 222 generates the positive outputs at the output units 223a, 223b, 223c and 223d. After the scanning signal is turned on for a period of time, the control terminal An is discharged. In particular, the reverse input unit 222 generates the forward scanning signals after the output units 223a, 223b, 223c and 223d, and then passes a clock cycle time (clock). Cycle time) discharging the control terminal An, thus The potential of the control terminal An is pulled down. For example, as shown in FIG. 2A, the output units 223a, 223b, 223c and 223d sequentially generate a forward scan signal at the clock cycle time of T2 to T5, and at the T7 clock. Cycle time discharge. In the forward scanning mode for operating the driving circuit, for example, as shown in FIG. A, the plurality of scanning signals are sequentially generated from the first driving module 22a to the 200th driving module 22z to the scanning lines GL. The pixel structures 402 are scanned forward.
反向輸入單元222依據第二輸入電壓Vdd_r與後反向掃描訊號對控制端An充放電，其中反向輸入單元222依據第二輸入電壓Vdd_r與後反向掃描訊號對控制端An充電，而該些輸出單元223a、223b、223c與223d產生複數反向掃描訊號至該些輸出端OUT_1(n)、OUT_2(n)、OUT_3(n)與OUT_4(n)；當該反向輸入單元222對該控制端An充電以讓該些輸出單元223a、223b、223c與223d輸出該些反向掃描訊號時，該正向輸入單元221於該些輸出單元223a、223b、223c與223d產生該反向掃描訊號一段時間後對該些輸出單元223a、223b、223c與223d之該控制端An放電，特別是，該正向輸入單元221於該些輸出單元223a、223b、223c與223d產生該些反向掃描訊號後經一個時脈週期時間對控制端An放電，例如:如第二B圖所示，該些輸出單元223d、223c、223b與223a於T2至T5時脈週期時間依序產生反向掃描訊號，並於T7時脈週期時間放電。如此用以運作驅動電路之反向掃描模式，例如:如第一A圖所示，自第200驅動模組22z至第1驅動模組22a依序產生複數掃描訊號至該些掃描線GL，以反向掃描該些畫素結構402。The reverse input unit 222 charges and discharges the control terminal An according to the second input voltage Vdd_r and the backward reverse scan signal, wherein the reverse input unit 222 charges the control terminal An according to the second input voltage Vdd_r and the backward reverse scan signal, and the The output units 223a, 223b, 223c and 223d generate complex reverse scan signals to the output terminals OUT_1(n), OUT_2(n), OUT_3(n) and OUT_4(n); when the reverse input unit 222 When the control terminal An is charged to output the reverse scan signals to the output units 223a, 223b, 223c and 223d, the forward input unit 221 generates the reverse scan signal at the output units 223a, 223b, 223c and 223d. After a period of time, the control terminals An of the output units 223a, 223b, 223c, and 223d are discharged. In particular, the forward input unit 221 generates the reverse scan signals at the output units 223a, 223b, 223c, and 223d. Afterwards, the control terminal An is discharged through a clock cycle time. For example, as shown in FIG. 2B, the output units 223d, 223c, 223b and 223a sequentially generate reverse scan signals at clock cycle times of T2 to T5. And discharge at T7 clock cycle time. In the reverse scan mode for operating the driving circuit, for example, as shown in FIG. A, the plurality of scanning signals are sequentially generated from the 200th driving module 22z to the first driving module 22a to the scanning lines GL. The pixel structures 402 are scanned in reverse.
此外，復參閱第一B圖，雜訊消除單元224濾除控制端An之雜訊，其中，控制電容231依據該第一時脈訊號CLK1產生一控制準位Bn，第一電晶體225依據控制端An之電位而濾除控制準位Bn是否下拉至參考電位Vss，進而控制第二電晶體226濾除控制端An之雜訊。In addition, referring to the first B diagram, the noise cancellation unit 224 filters out the noise of the control terminal An, wherein the control capacitor 231 generates a control level Bn according to the first clock signal CLK1, and the first transistor 225 is controlled according to the control. The potential of the terminal An filters out whether the control level Bn is pulled down to the reference potential Vss, thereby controlling the second transistor 226 to filter out the noise of the control terminal An.
請一併參閱第一B圖、第二A圖與第二B圖，其為本發明之一實施例之驅動訊號於正向掃描與反向掃描的波形圖。如第二A圖所示，其為一驅動電路操作於正向掃描模式下所呈現之波形圖。驅動模組22於正向掃描模式下時，正向輸入單元221為用以對控制端An充電，而反向輸入單元222於正向掃描模式下，卻是在該些輸出單元223a、223b、223c與223d產生正向掃描訊號後經一個時脈週期時間，以對控制端An進行放電，因此第一輸入電壓Vdd_f為高準位(Vdd)，而第二輸入電壓Vdd_r為低準位，本實施例是將第二輸入電壓Vdd_r下拉至參考電位Vss。Please refer to the first B diagram, the second A diagram and the second B diagram, which are waveform diagrams of the driving signal in the forward scanning and the reverse scanning according to an embodiment of the present invention. As shown in FIG. 2A, it is a waveform diagram presented by a driving circuit operating in a forward scanning mode. When the driving module 22 is in the forward scanning mode, the forward input unit 221 is used to charge the control terminal An, and the reverse input unit 222 is in the forward scanning mode, but in the output units 223a, 223b, 223c and 223d generate a forward scan signal and then pass a clock cycle time to discharge the control terminal An, so the first input voltage Vdd_f is a high level (Vdd), and the second input voltage Vdd_r is a low level, An embodiment is to pull down the second input voltage Vdd_r to the reference potential Vss.
復一併參閱第一B圖與第二A圖，當執行T1時脈週期時間時，正向輸入單元221依據前輸出端OUT_3(n-1)之第四掃描訊號而導通，以對控制端An充電，同時該些輸出端OUT_1(n)、OUT_2(n)、OUT_3(n)與OUT_4(n)為低電位，當執行T2時脈週期時間時，控制端An為浮接點(floating point)，因此控制端An不再受到正向輸入單元221之充電，同時基於控制端An之高電位而驅使輸出單元223接收第一時脈訊號CLK1並將第一時脈訊號CLK1之電壓傳送至第一輸出端OUT_1(n)，並透過第一輸出電容230a抬升控制端An之電位，而讓第一輸出單元223a對第一輸出端OUT_1(n)快速充電，當執行T3時脈週期時間時，控制端An為浮接點，基於控制端An之高電位而驅使第二輸出單元223b接收第二時脈訊號CLK2並將第二時脈訊號CLK2之電壓傳送至第二輸出端OUT_2(n)，並透過第二輸出電容230b抬升控制端An之電位，而讓第二輸出單元223b對第二輸出端OUT_2(n)快速充電，此外，第一輸出端OUT_1(n)之電位經第一輸出端OUT_1(n)放電至低電位，也就是Vss電位。Referring to the first B picture and the second A picture, when the T1 clock cycle time is executed, the forward input unit 221 is turned on according to the fourth scan signal of the front output terminal OUT_3 (n-1) to the control terminal. An charging, at the same time, the output terminals OUT_1(n), OUT_2(n), OUT_3(n) and OUT_4(n) are low. When the T2 clock cycle time is executed, the control terminal An is a floating point (floating point). Therefore, the control terminal An is no longer charged by the forward input unit 221, and at the same time, based on the high potential of the control terminal An, the output unit 223 is driven to receive the first clock signal CLK1 and transmit the voltage of the first clock signal CLK1 to the first An output terminal OUT_1(n) is used to raise the potential of the control terminal An through the first output capacitor 230a, and the first output unit 223a is quickly charged to the first output terminal OUT_1(n) when the T3 clock cycle time is executed. The control terminal An is a floating point, and the second output unit 223b is driven to receive the second clock signal CLK2 and transmit the voltage of the second clock signal CLK2 to the second output terminal OUT_2(n) based on the high potential of the control terminal An. And raising the potential of the control terminal An through the second output capacitor 230b, and letting the second output unit 223b rapidly charges the second output terminal OUT_2(n), and further, the potential of the first output terminal OUT_1(n) is discharged to a low potential, that is, a Vss potential, through the first output terminal OUT_1(n).
當執行T4時脈週期時間時，控制端An為浮接點，基於控制端An之高電位而驅使第三輸出單元223c接收第三時脈訊號CLK3並將第三時脈訊號CLK3之電壓傳送至第三輸出端OUT_3(n)，並透過第三輸出電容230c抬升控制端An之電位，而讓第三輸出單元223c對第三輸出端OUT_3(n)快速充電，此外，第二輸出端OUT_2(n)之電位經第二輸出端OUT_2(n)放電至低電位；當執行T5時脈週期時間時，控制端An為浮接點，基於控制端An之高電位而驅使第四輸出單元223d接收第四時脈訊號CLK4並將第三時脈訊號CLK4之電壓傳送至第四輸出端OUT_4(n)，並透過第四輸出電容230d抬升控制端An之電位，而讓第四輸出單元223d對第四輸出端OUT_4(n)快速充電，此外，第三輸出端OUT_3(n)之電位經第三輸出端OUT_3(n)放電至低電位，當執行T6時脈週期時間時，控制端An為浮接點，第四輸出端OUT_4經放電至低電位，當執行T7時脈週期時間時，控制端An經反向輸入單元222放電至低電位，之後執行至T8時脈週期時間時，控制端An會基於輸出單元223之寄生電容而產生雜訊，但同時雜訊消除單元22a之第二電晶體226導通，而將控制端An穩定於低電位，而消除寄生電容之雜訊。When the T4 clock cycle time is executed, the control terminal An is a floating contact point, and based on the high potential of the control terminal An, the third output unit 223c is driven to receive the third clock signal CLK3 and transmit the voltage of the third clock signal CLK3 to The third output terminal OUT_3(n) transmits the potential of the control terminal An through the third output capacitor 230c, and causes the third output unit 223c to quickly charge the third output terminal OUT_3(n), and further, the second output terminal OUT_2 ( The potential of n) is discharged to a low potential through the second output terminal OUT_2(n); when the T5 clock cycle time is executed, the control terminal An is a floating contact point, and the fourth output unit 223d is driven to receive based on the high potential of the control terminal An. The fourth clock signal CLK4 transmits the voltage of the third clock signal CLK4 to the fourth output terminal OUT_4(n), and raises the potential of the control terminal An through the fourth output capacitor 230d, and causes the fourth output unit 223d to The four output terminals OUT_4(n) are quickly charged. In addition, the potential of the third output terminal OUT_3(n) is discharged to a low potential through the third output terminal OUT_3(n). When the T6 clock cycle time is executed, the control terminal An is floated. Contact, the fourth output terminal OUT_4 is discharged to a low potential when performing T7 At the pulse cycle time, the control terminal An is discharged to the low potential through the reverse input unit 222, and then after the execution to the T8 clock cycle time, the control terminal An generates noise based on the parasitic capacitance of the output unit 223, but at the same time, the noise is eliminated. The second transistor 226 of the cell 22a is turned on, and the control terminal An is stabilized at a low potential to eliminate noise of the parasitic capacitance.
請一併參閱第一B圖與第二B圖，其中第二B圖為該驅動電路操作於反向掃描模式下所呈現之波形圖。由於第二B圖為第二A圖之相反情況，所以變成反向輸入單元222對控制端An充電，而正向輸入單元221是在該些輸出單元223a、223b、223c、223d產生該些反向掃描訊號後經一個時脈週期時間(clock cycle time)，以對該輸出單元223之該控制端An進行放電，因此第二輸入電壓Vdd_r為高準位(Vdd)，而第一輸入電壓Vdd_f為低準位，本實施例是將第一輸入電壓Vdd_f下拉至參考電位Vss。復參閱第二B圖，驅動模組22於T1至T7時脈週期時間改以反向輸入單元222對控制端An充電，而由正向輸入單元221對控制端An放電，其餘操作方式同於第二A圖之實施例所述。Please refer to the first B picture and the second B picture together, wherein the second B picture is a waveform diagram presented by the driving circuit operating in the reverse scanning mode. Since the second B picture is the reverse of the second A picture, the reverse input unit 222 is charged to the control terminal An, and the forward input unit 221 is generated at the output units 223a, 223b, 223c, 223d. After the scan signal is passed through a clock cycle time, the control terminal An of the output unit 223 is discharged, so the second input voltage Vdd_r is at a high level (Vdd), and the first input voltage Vdd_f For the low level, the present embodiment pulls down the first input voltage Vdd_f to the reference potential Vss. Referring to FIG. 2B, the driving module 22 changes the clock cycle time of T1 to T7 to the inverting input unit 222 to charge the control terminal An, and the positive input unit 221 discharges the control terminal An, and the rest of the operation is the same as The embodiment of Figure 2A is as described.
由以上所述可知，本發明之驅動模組22藉由正向輸入單元221與反向輸入單元222分別對控制端An充電，以驅動該些輸出單元223a、223b、223c與223d提供不同掃描模式之掃描訊號，且本發明之驅動模組22在任一掃描模式僅需正向輸入單元221與反向輸入單元222輪替對控制端An充放電，因而簡化電路。再者，由於雜訊消除單元224為透過控制電容231接收時脈訊號CLK1，因而避免時脈訊號之電壓、電流直接流通至參考電位Vss，以減低非必要之直流消耗。又，由於驅動模組為依據至少三個以上時脈訊號進行運作，所以避免輸出單元223與第一雜訊消除單元224依據時脈訊號持續導通/截止，因而避免輸出單元223與第一雜訊消除單元224於非運作期間產生非必要功率消耗。As can be seen from the above, the driving module 22 of the present invention charges the control terminal An by the forward input unit 221 and the reverse input unit 222 to drive the output units 223a, 223b, 223c and 223d to provide different scanning modes. The scanning signal, and the driving module 22 of the present invention only needs to charge and discharge the control terminal An in the forward input unit 221 and the reverse input unit 222 in any scanning mode, thereby simplifying the circuit. Moreover, since the noise cancellation unit 224 receives the clock signal CLK1 through the control capacitor 231, the voltage and current of the clock signal are prevented from directly flowing to the reference potential Vss to reduce unnecessary DC consumption. Moreover, since the driving module operates according to at least three clock signals, the output unit 223 and the first noise removing unit 224 are continuously turned on/off according to the clock signal, thereby avoiding the output unit 223 and the first noise. Elimination unit 224 generates non-essential power consumption during non-operational periods.
請參閱第三圖，其為本發明之一實施例之雙向掃瞄驅動電路的方塊圖。如圖所示，本發明之驅動電路50係包含複數驅動模組，本實施例係以一第n-1驅動模組52、一第n驅動模組54與一第n+1驅動模組56作為舉例，第n-1驅動模組52、第n驅動模組54與第n+1驅動模組56之詳細電路係同於前一實施例所述之驅動模組22。由於第n-1驅動模組52於本實施例為起始之驅動模組，而未有第n-2驅動模組可供第n-1驅動模組52電性連接，因此第n-1驅動模組52接收一輸入訊號IN1，第n-1驅動模組52至第n+1驅動模組56即如同第一A圖與第一B圖之第1驅動模組22a至第3驅動模組22c之運作方式，第n-1驅動模組52至第n+1驅動模組56分別接收第一時脈訊號CLK1至第四時脈訊號CLK4，且第n-1驅動模組52、第n驅動模組54與第n+1驅動模組56皆為耦接至第一輸入電壓Vdd_f與第二輸入電壓Vdd_r，並皆耦接至參考電位Vss，其中參考電位Vss相當於掃描電路之低電位，例如:1V電位。其中，第n-1驅動模組52所輸出之第一輸出訊號O1(n-1)至第四輸出訊號O4(n-1)、第n驅動模組54所輸出之第一輸出訊號O1(n)至第四輸出訊號O4(n)，以及第n+1驅動模組56所輸出之第一輸出訊號O1(n+1)至第四輸出訊號O4(n+1)，即為畫素結構402之掃描訊號。Please refer to the third figure, which is a block diagram of a bidirectional scan driving circuit according to an embodiment of the present invention. As shown in the figure, the driving circuit 50 of the present invention includes a plurality of driving modules. In this embodiment, an n-1th driving module 52, an nth driving module 54 and an n+1th driving module 56 are provided. For example, the detailed circuits of the n-1th driving module 52, the nth driving module 54, and the n+1th driving module 56 are the same as those of the driving module 22 described in the previous embodiment. Since the n-1th driving module 52 is the initial driving module in this embodiment, and the n-2th driving module is not available for the n-1th driving module 52 to be electrically connected, the n-1th The driving module 52 receives an input signal IN1, and the n-1th driving module 52 to the n+1th driving module 56 are like the first driving circuit 22a to the third driving mode of the first A picture and the first B picture. In the operation mode of the group 22c, the n-1th driving module 52 to the n+1th driving module 56 respectively receive the first clock signal CLK1 to the fourth clock signal CLK4, and the n-1th driving module 52, The n-th driving module 54 and the n+1th driving module 56 are both coupled to the first input voltage Vdd_f and the second input voltage Vdd_r, and are all coupled to the reference potential Vss, wherein the reference potential Vss is equivalent to the low of the scanning circuit. Potential, for example: 1V potential. The first output signal O 1 (n-1) to the fourth output signal O 4 (n-1) output by the n-1th driving module 52 and the first output signal output by the nth driving module 54 O 1 (n) to fourth output signal O 4 (n), and the first output signal O 1 (n+1) to the fourth output signal O 4 (n+1) output by the n+1th driving module 56 ), which is the scan signal of the pixel structure 402.
當開始順向掃描時，第n-1驅動模組52係依序輸出第一輸出訊號O1(n-1)至第四輸出訊號O4(n-1)至畫素結構402，也就是第n-1驅動模組52將其第一掃描訊號至第四掃描訊號輸出至畫素結構402，同時，第n-1驅動模組52將第三輸出訊號O3(n-1)傳送至第n驅動模組54，也就是第n-1驅動模組52將其第三掃描訊號輸出至第n驅動模組54，第n驅動模組54亦依序輸出第一輸出訊號O1(n)至第四輸出訊號O4(n)至畫素結構402，也就是第n驅動模組54將其第一掃描訊號至第四掃描訊號輸出至畫素結構402，且第n驅動模組54亦同時將第三輸出訊號O3(n)傳送至第n+1驅動模組56，也就是第n驅動模組54將其第三掃描訊號輸出至第n+1驅動模組56，第n+1驅動模組56於接收到第三輸出訊號O3(n)時，即輸出第一輸出訊號O1(n+1)至第四輸出訊號O4(n+1)至畫素結構402，也就是第n+1驅動模組56將其第一掃描訊號至第四掃描訊號輸出至畫素結構402，同時，第n+1驅動模組56將第三輸出訊號O3(n+1)傳送至下一級驅動模組，亦即將第三輸出訊號O3(n+1)傳送至第n+2驅動模組(圖未示)，也就是第n+1驅動模組56將其第三掃描訊號輸出至第n+2驅動模組。When the forward scan is started, the n-1th driving module 52 sequentially outputs the first output signal O 1 (n-1) to the fourth output signal O 4 (n-1) to the pixel structure 402, that is, The n-1th driving module 52 outputs the first scanning signal to the fourth scanning signal to the pixel structure 402, and the n-1th driving module 52 transmits the third output signal O 3 (n-1) to n-th driving module 54, i.e. the n-1 drive module 52 to the third scan signal output to the n-th driving module 54, the n-th driving module 54 also sequentially outputs a first output signal O 1 (n The fourth output signal O 4 (n) to the pixel structure 402, that is, the nth driving module 54 outputs its first to fourth scanning signals to the pixel structure 402, and the nth driving module 54 At the same time, the third output signal O 3 (n) is transmitted to the n+1th driving module 56, that is, the nth driving module 54 outputs the third scanning signal to the n+1th driving module 56, nth When receiving the third output signal O 3 (n), the +1 driving module 56 outputs the first output signal O 1 (n+1) to the fourth output signal O 4 (n+1) to the pixel structure 402. , that is, the n+1th driving module 56 sends its first scan signal to Four scan signal is output to the pixel structure 402, while the n + 1 module 56 driving the third output signal O 3 (n + 1) is transmitted to the next stage driving module, i.e., the third output signal O 3 (n +1) is transmitted to the n+2th driving module (not shown), that is, the n+1th driving module 56 outputs its third scanning signal to the n+2th driving module.
此外，本實施例係以三個驅動模組作為舉例，但本發明不限於此，本實施例更可設置超過三個驅動模組用於提供掃描訊號，用以正向掃描或反向掃描。由上述實施例可知，本發明藉由輸出單元共用控制端，而讓每一驅動模組皆可輸出複數掃描訊號，如此即可縮減驅動模組之使用面積。綜上所述，本發明為一種具共用控制端之驅動模組，其藉由正向輸入單元與反向輸入單元分別於正向掃描模式與反向掃描模式中對控制端充放電，以在正向輸入單元對控制端充電時，驅使複數輸出單元依序產生複數正向掃描訊號，並在反向輸入單元對控制端充電時，驅使該些輸出單元依序產生複數反向掃描訊號，因而支援雙向掃描。再者，本發明藉由複數輸出單元共用控制端，而簡化控制端的充放電機制與驅動模組之電路布局。In addition, the present embodiment is exemplified by three driving modules, but the present invention is not limited thereto. In this embodiment, more than three driving modules can be disposed for providing scanning signals for forward scanning or reverse scanning. It can be seen from the above embodiments that the output unit shares the control terminal, and each of the driving modules can output a plurality of scanning signals, thereby reducing the use area of the driving module. In summary, the present invention is a driving module with a shared control terminal, which charges and discharges the control terminal in the forward scanning mode and the reverse scanning mode by the forward input unit and the reverse input unit, respectively. When the forward input unit charges the control terminal, the plurality of output units are driven to sequentially generate the plurality of forward scan signals, and when the reverse input unit charges the control terminal, the output units are driven to sequentially generate the plurality of reverse scan signals, thereby Support for two-way scanning. Furthermore, the present invention simplifies the charging and discharging mechanism of the control terminal and the circuit layout of the driving module by sharing the control terminals by the plurality of output units.
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.
22．．．驅動模組twenty two. . . Drive module
221．．．正向輸入單元221. . . Positive input unit
222．．．反向輸入單元222. . . Reverse input unit
223．．．輸出單元223. . . Output unit
223a．．．第一輸出單元223a. . . First output unit
223b．．．第二輸出單元223b. . . Second output unit
223c．．．第三輸出單元223c. . . Third output unit
223d．．．第四輸出單元223d. . . Fourth output unit
224．．．雜訊消除單元224. . . Noise cancellation unit
225．．．第一電晶體225. . . First transistor
226．．．第二電晶體226. . . Second transistor
230．．．輸出電容230. . . Output capacitor
230a．．．第一輸出電容230a. . . First output capacitor
230b．．．第二輸出電容230b. . . Second output capacitor
230c．．．第三輸出電容230c. . . Third output capacitor
230d．．．第四輸出電容230d. . . Fourth output capacitor
231．．．控制電容231. . . Control capacitor
Claims (8)
複數輸出單元，其一併耦接一控制端，並接收該些時脈訊號；
一正向輸入單元，其耦接該控制端，並接收該第一輸入電壓與任一n-1級以上驅動模組之輸出單元的一前正向掃描訊號，該正輸入單元依據該第一輸入電壓與該前正向掃描訊號對該控制端充放電；以及
一反向輸入單元，其耦接該控制端，並接收該第二輸入電壓與任一n+1級以上驅動模組之輸出單元的一後反向掃描訊號，該反輸入單元依據該第二輸入電壓與該後反向掃描訊號對該控制端充放電；
其中，該正輸入單元依據該第一輸入電壓與該前正向掃描訊號對該控制端充電，而分別依據該些時脈訊號與該控制端產生複數正向掃描訊號並依序順向輸出，該反輸入單元依據該第二輸入電壓與該後反向掃描訊號對該控制端充電，而分別依據該些時脈訊號與該控制端產生複數反向掃描訊號並依序反向輸出。A driving module having a shared control end, which sequentially generates a plurality of scanning signals and sequentially outputs the same to a display panel, wherein the driving module receives the plurality of clock signals and respectively receives a first input voltage and a second input voltage The drive module includes:
a plurality of output units coupled to a control terminal and receiving the clock signals;
a forward input unit coupled to the control terminal and receiving a forward forward scan signal of the first input voltage and an output unit of any n-1 or higher drive module, the positive input unit being according to the first The input voltage and the front forward scan signal charge and discharge the control terminal; and a reverse input unit coupled to the control terminal and receiving the output of the second input voltage and any n+1 or higher drive module a back scan signal of the unit, the reverse input unit charges and discharges the control terminal according to the second input voltage and the back reverse scan signal;
The positive input unit charges the control terminal according to the first input voltage and the front forward scan signal, and generates a plurality of forward scan signals according to the clock signals and the control end, and sequentially outputs the signals in sequence. The reverse input unit charges the control terminal according to the second input voltage and the back reverse scan signal, and generates a complex reverse scan signal according to the clock signals and the control terminal, and sequentially outputs the signals in reverse.
一雜訊清除單元，其耦接該正輸入單元、該反輸入單元與該輸出單元，並接收該第一時脈訊號，該無雜訊單元濾除該輸出單元之該控制端之雜訊。For example, the driving module described in claim 1 of the patent scope further includes:
A noise clearing unit is coupled to the positive input unit, the reverse input unit and the output unit, and receives the first clock signal, and the noise-free unit filters out noise of the control terminal of the output unit.
一控制電容，其一第一端接收該第一時脈訊號，該控制電容依據該第一時脈訊號產生一控制準位；
一第一電晶體，其一第一端耦接該控制電容之一第二端，該第一電晶體之一第二端耦接該正輸入單元、該反輸入單元與該控制端；以及
一第二電晶體，其一第一端耦接該正輸入單元、該反輸入單元與該控制端，該第二電晶體之一第二端耦接該第一電晶體之該第一端與該控制電容之該第二端，該第一電晶體之一第三端與該第二電晶體之一第三端耦接至一參考準位。The driving module of claim 2, wherein the noise clearing unit comprises:
a first capacitor receives a first clock signal, and the control capacitor generates a control level according to the first clock signal;
a first transistor is coupled to the second end of the control capacitor, a second end of the first transistor is coupled to the positive input unit, the reverse input unit and the control end; a second transistor having a first end coupled to the positive input unit, the reverse input unit and the control end, and a second end of the second transistor coupled to the first end of the first transistor and the second transistor The second end of the first transistor is coupled to a third end of the second transistor to a reference level.
複數輸出電容，其第一端分別耦接該控制端，該些輸出電容之第二端分別耦接該些輸出單元之第三端。For example, the driving module described in claim 1 of the patent scope further includes:
The first output of the output capacitor is coupled to the control end, and the second ends of the output capacitors are respectively coupled to the third ends of the output units.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102101424A TWI490844B (en) | 2013-01-15 | 2013-01-15 | A driving module with a common control node |
| CN201310036350.9A CN103927995B (en) | 2013-01-15 | 2013-01-29 | Drive module with shared control end |
| JP2013042231A JP5757969B2 (en) | 2013-01-15 | 2013-03-04 | Drive module sharing a control node |
| US13/870,187 US9064474B2 (en) | 2013-01-15 | 2013-04-25 | N-th stage driving module with common control node |
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| TW102101424A TWI490844B (en) | 2013-01-15 | 2013-01-15 | A driving module with a common control node |
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| TW201428728A true TW201428728A (en) | 2014-07-16 |
| TWI490844B TWI490844B (en) | 2015-07-01 |
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| US (1) | US9064474B2 (en) |
| JP (1) | JP5757969B2 (en) |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI606435B (en) * | 2017-04-06 | 2017-11-21 | 敦泰電子股份有限公司 | Gate line drive circuit and display device having the same |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102622983B (en) * | 2012-03-30 | 2013-11-06 | 深圳市华星光电技术有限公司 | Gate driving circuit of display |
| CN106297619B (en) * | 2015-05-14 | 2019-09-20 | 凌巨科技股份有限公司 | Single-stage gate drive circuit with multi output |
| CN106328076B (en) * | 2015-06-29 | 2019-05-21 | 凌巨科技股份有限公司 | Bilateral scanning gate drive module |
| US9626895B2 (en) * | 2015-08-25 | 2017-04-18 | Chunghwa Picture Tubes, Ltd. | Gate driving circuit |
| CN105118469B (en) * | 2015-09-25 | 2017-11-10 | 深圳市华星光电技术有限公司 | Scan drive circuit and the liquid crystal display device with the circuit |
| CN105869566B (en) * | 2016-06-21 | 2019-12-03 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driving circuit and display device |
| KR102565459B1 (en) * | 2016-07-14 | 2023-08-09 | 삼성디스플레이 주식회사 | Gate driving circuit and display device having the same |
| CN106297636B (en) * | 2016-09-12 | 2018-05-11 | 武汉华星光电技术有限公司 | Flat display apparatus and its scan drive circuit |
| CN108346402B (en) * | 2017-01-22 | 2019-12-24 | 京东方科技集团股份有限公司 | Grid driving circuit, driving method thereof and display device |
| CN106935181A (en) * | 2017-05-22 | 2017-07-07 | 厦门天马微电子有限公司 | Gate driving circuit |
| CN108154835B (en) * | 2018-01-02 | 2020-12-25 | 京东方科技集团股份有限公司 | Shifting register unit, driving method thereof, grid driving circuit and display device |
| CN108682398B (en) * | 2018-08-08 | 2020-05-29 | 京东方科技集团股份有限公司 | Shift register unit, grid driving circuit, display device and driving method |
| CN114170943B (en) * | 2021-12-09 | 2023-11-21 | 上海中航光电子有限公司 | Shift register circuit, display panel and display device |
| KR20230103639A (en) * | 2021-12-31 | 2023-07-07 | 엘지디스플레이 주식회사 | Scan Signal Generation Circuit and Display Device including the same |
Family Cites Families (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3750734B2 (en) * | 2001-07-27 | 2006-03-01 | セイコーエプソン株式会社 | Scan line driving circuit, electro-optical device, electronic apparatus, and semiconductor device |
| KR101080352B1 (en) * | 2004-07-26 | 2011-11-04 | 삼성전자주식회사 | Display device |
| JP2007148086A (en) * | 2005-11-29 | 2007-06-14 | Toshiba Matsushita Display Technology Co Ltd | Flat panel display device |
| US7738622B2 (en) * | 2006-06-23 | 2010-06-15 | Lg Display Co., Ltd. | Shift register |
| CN101872585B (en) * | 2007-01-22 | 2013-07-17 | 株式会社日立显示器 | Display device |
| JP5078533B2 (en) * | 2007-10-10 | 2012-11-21 | 三菱電機株式会社 | Gate line drive circuit |
| US8023611B2 (en) * | 2008-09-17 | 2011-09-20 | Au Optronics Corporation | Shift register with embedded bidirectional scanning function |
| JP2010192019A (en) * | 2009-02-17 | 2010-09-02 | Sharp Corp | Shift register and scanning signal line driving circuit provided with the same, and display device |
| JP5610778B2 (en) * | 2009-07-06 | 2014-10-22 | 三菱電機株式会社 | Scan line drive circuit |
| KR101250158B1 (en) * | 2009-11-04 | 2013-04-05 | 샤프 가부시키가이샤 | Shift register, scanning signal line drive circuit provided with same, and display device |
| TWI420495B (en) * | 2010-01-22 | 2013-12-21 | Innolux Corp | Shift register circuit and dual direction gate drive circuit |
| CN102214428B (en) * | 2010-04-01 | 2013-12-18 | 瀚宇彩晶股份有限公司 | Gate driving circuit and driving method therefor |
| KR101373979B1 (en) | 2010-05-07 | 2014-03-14 | 엘지디스플레이 주식회사 | Gate shift register and display device using the same |
| TWI433459B (en) * | 2010-07-08 | 2014-04-01 | Au Optronics Corp | Bi-directional shift register |
| JP2012189752A (en) * | 2011-03-10 | 2012-10-04 | Japan Display East Co Ltd | Display device |
| KR101810517B1 (en) * | 2011-05-18 | 2017-12-20 | 삼성디스플레이 주식회사 | Gate driving circuit and display apparatus having the same |
| CN102629444B (en) * | 2011-08-22 | 2014-06-25 | 北京京东方光电科技有限公司 | Circuit of gate drive on array, shift register and display screen |
| TWI462475B (en) * | 2011-12-29 | 2014-11-21 | Au Optronics Corp | Bidirectional shift register and driving method thereof |
| KR101354365B1 (en) * | 2011-12-30 | 2014-01-23 | 하이디스 테크놀로지 주식회사 | Shift Register and Gate Driving Circuit Using the Same |
| JP5496270B2 (en) * | 2012-06-29 | 2014-05-21 | 三菱電機株式会社 | Gate line drive circuit |
| TWI475538B (en) * | 2012-08-29 | 2015-03-01 | Giantplus Technology Co Ltd | A driving circuit for bi-direction scanning. |
-
2013
- 2013-01-15 TW TW102101424A patent/TWI490844B/en active
- 2013-01-29 CN CN201310036350.9A patent/CN103927995B/en active Active
- 2013-03-04 JP JP2013042231A patent/JP5757969B2/en active Active
- 2013-04-25 US US13/870,187 patent/US9064474B2/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI606435B (en) * | 2017-04-06 | 2017-11-21 | 敦泰電子股份有限公司 | Gate line drive circuit and display device having the same |
| CN108694895A (en) * | 2017-04-06 | 2018-10-23 | 敦泰电子股份有限公司 | Gate line driving circuit and display device including the same |
| US10116225B1 (en) | 2017-04-06 | 2018-10-30 | Focaltech Systems Co., Ltd. | Gate line drive circuit and display device having the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103927995B (en) | 2016-08-03 |
| US20140198022A1 (en) | 2014-07-17 |
| CN103927995A (en) | 2014-07-16 |
| JP2014137591A (en) | 2014-07-28 |
| US9064474B2 (en) | 2015-06-23 |
| TWI490844B (en) | 2015-07-01 |
| JP5757969B2 (en) | 2015-08-05 |
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