CN106297619B - Single-stage gate drive circuit with multi output - Google Patents

Single-stage gate drive circuit with multi output Download PDF

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Publication number
CN106297619B
CN106297619B CN201510245554.2A CN201510245554A CN106297619B CN 106297619 B CN106297619 B CN 106297619B CN 201510245554 A CN201510245554 A CN 201510245554A CN 106297619 B CN106297619 B CN 106297619B
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signal
scanning
circuit
level
control
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CN106297619A (en
Inventor
刘柏村
郑光廷
张哲豪
周凯茹
吴哲耀
赖谷皇
康镇玺
陈品充
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Lingju Sci & Tech Co Ltd
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Lingju Sci & Tech Co Ltd
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Abstract

The present invention is a kind of single-stage gate drive circuit with multi output, single-stage gate drive circuit has one first scanning circuit and one second scanning circuit, first scanning circuit includes a setup unit and a driving unit, and setup unit receives an initial signal and generates a control signal.Driving unit receives control signal and a first frequency signal, and controlling signal and first frequency signal makes driving unit generate one first scanning signal.Driving unit drives the first scanning signal to be promoted to one first level according to first frequency signal, and driving unit drives the first scanning signal to be reduced to a second electrical level according to first frequency signal.Second scanning circuit receives the first scanning signal and a second frequency signal, and the second scanning circuit generates one second scanning signal according to the first scanning signal and second frequency signal.

Description

Single-stage gate drive circuit with multi output
Technical field
The present invention is about a kind of single-stage gate drive circuit, especially with respect to a kind of single-stage gate drive with multi output Circuit.
Background technique
TFT thin film transistor monitor has become the mainstream of display sci-tech product now, be applied especially to have on mobile phone it is light and handy and The features such as being convenient for carrying, and amorphous silicon film transistor uses amorphous silicon membrane for polycrystalline SiTFT Display made by transistor can reduce production cost, and can be produced at low temperature on the glass substrate of large area, And improve throughput rate.
As the concept of system combination formula glass panel proposes successively, recent many products will be in circuit of display driving Gate scanning circuit is incorporated on glass, as GOA (Gate-Driver-on-Array) circuit, and GOA circuit has many excellent Gesture can more reduce the use of gate scan drive circuit IC other than it can reduce the area of display frame.
In view of the demand of display narrow frame, the present invention proposes to reduce the technology of single-stage gate drive circuit area requirements.
Summary of the invention
An object of the present invention can promote scan line charge and discharge speed to provide a kind of single-stage gate drive circuit Degree.
An object of the present invention reaches range of distribution using multi output design to provide a single-stage gate drive circuit Long-pending reduction.
To achieve these objectives, the present invention provides a kind of single-stage gate drive circuit with multi output, sweeps with multiple Scanning circuit and designed for multi output, wherein one first scanning circuit includes a setup unit and a driving unit, setup unit connect It receives an initial signal and generates a control signal, driving unit coupling setup unit simultaneously receives control signal and first frequency letter Number, controlling signal and first frequency signal makes driving unit generate one first scanning signal.Driving unit is believed according to first frequency Number the first scanning signal of driving is promoted to one first level, and driving unit drives the first scanning signal drop according to first frequency signal Down to a second electrical level, the first level is higher than second electrical level.One second scanning circuit couples the first scanning circuit, and receives first Scanning signal and a second frequency signal, the second scanning circuit generate one second according to the first scanning signal and second frequency signal Scanning signal.
In order to achieve the above object, the present invention proposes following technical scheme:
A kind of single-stage gate drive circuit with multi output, the single-stage gate drive circuit have multiple scanning circuits, Include:
One first scanning circuit, it includes:
One setup unit receives an initial signal, generates a control signal;
One driving unit couples the setup unit, receives the control signal and a first frequency signal, the control signal and The first frequency signal makes the driving unit generate one first scanning signal, which drives according to the first frequency signal First scanning signal is promoted to one first level, which drives first scanning signal according to the first frequency signal It is reduced to a second electrical level, which is higher than the second electrical level;And
One second scanning circuit couples first scanning circuit, receives first scanning signal and a second frequency signal, Second scanning circuit generates one second scanning signal according to first scanning signal and the second frequency signal;
Wherein, which exports first scanning signal and second scanning signal to multiple pixels, Control the pixel.
The single-stage gate drive circuit with multi output proposed according to the present invention, which includes:
One first assignment component, has an input terminal, a control terminal and an output end, which receives one first electricity Source, the control terminal receive the initial signal, which couples the driving unit, and first assignment component is according to the initial signal And first power supply generates the control signal;And
One second assignment component, has an input terminal, a control terminal and an output end, which receives one second electricity Source, the control terminal receive a third scanning signal, which couples the driving unit, and second assignment component is according to the third Scanning signal and the second source set the control signal.
The single-stage gate drive circuit with multi output proposed according to the present invention, which includes:
One driving assembly, has an input terminal, a control terminal and an output end, which receives first frequency letter Number, which couples the setup unit, which couples second scanning circuit, and the driving assembly is according to the first frequency Signal and the control signal and generate first scanning signal;And
One capacitor is coupled between the control terminal of the driving assembly and the output end, according to the control signal and is somebody's turn to do The level of first frequency signal boost first scanning signal.
The single-stage gate drive circuit with multi output proposed according to the present invention, further includes:
One noise suicide circuit couples first scanning circuit and second scanning circuit, receives the first frequency signal, drop The noise of low first scanning circuit and the noise of second scanning circuit.
The single-stage gate drive circuit with multi output proposed according to the present invention, which includes:
One control unit receives one first power supply, the first frequency signal and the control signal, and control signal control should Noise suicide circuit not enabled antinoise work, first power supply and the first frequency signal control the noise suicide circuit and enable anti-noise Sound work.
The single-stage gate drive circuit with multi output proposed according to the present invention, the noise suicide circuit include an antinoise Unit, which includes:
One the first transistor, has an input terminal, a control terminal and an output end, which couples the first scanning electricity The driving unit on road, the control terminal couple the control unit, which couples a reference level, which makes this The level equalization of one control terminal of the driving unit of the first scanning circuit is in the reference level;
One second transistor, has an input terminal, a control terminal and an output end, which couples the first scanning electricity The driving unit on road, the control terminal couple the control unit, which couples the reference level, which makes this The level equalization of one output end of the driving unit of the first scanning circuit is in the reference level;
One third transistor, has an input terminal, a control terminal and an output end, which couples the second scanning electricity One driving unit on road, the control terminal couple the control unit, which couples the reference level, which makes this The level equalization of one control terminal of the driving unit of the second scanning circuit is in the reference level;And
One the 4th transistor, has an input terminal, a control terminal and an output end, which couples the second scanning electricity The driving unit on road, the control terminal couple the control unit, which couples the reference level, and the 4th transistor makes this The level equalization of one output end of the driving unit of the second scanning circuit is in the reference level.
The single-stage gate drive circuit with multi output proposed according to the present invention, which includes:
One protection location, have an input terminal, a control terminal and an output end, the input terminal couple the first transistor, The second transistor, the third transistor and the 4th transistor, the control terminal receive a third frequency signal, the output end coupling The reference level is connect, the protection location is according to the third frequency signal and periodically by the first transistor, second crystal The control terminal of pipe, the third transistor and the 4th transistor is maintained at the reference level.
The single-stage gate drive circuit with multi output proposed according to the present invention, the driving list of first scanning circuit The driving that one control terminal of member penetrates a setup unit of second scanning circuit and is electrically connected second scanning circuit is single One control terminal of member.
The single-stage gate drive circuit with multi output proposed according to the present invention, there is the single-stage gate of multi output to drive for this Dynamic circuit is a simple scanning.
The single-stage gate drive circuit with multi output proposed according to the present invention a, wherein display has multiple single-stages Gate drive circuit, a third frequency signal control one first single-stage gate drive electricity of the single-stage gate drive circuit simultaneously Road electric discharge is charged with one second single-stage gate drive circuit, which controls the single-stage gate drive circuit simultaneously The second single-stage gate drive circuit electric discharge with a third single-stage gate drive circuit charge.
Detailed description of the invention
Fig. 1 is the diagram of an embodiment of the concatenation of multistage gate drive circuit of the invention;
Fig. 2 is the circuit diagram of an embodiment of the single-stage gate drive circuit with multi output of the invention;
Fig. 3 is the timing diagram of the single-stage gate drive circuit with multi output of the invention;
Fig. 4 is the circuit diagram of the multi output design of the next stage gate drive circuit of Fig. 2 of the present invention;
Description of symbols: 1- the first single-stage gate drive circuit;2- the second single-stage gate drive circuit;3- third single-stage Gate drive circuit;10- setup unit;11- driving unit;12- setup unit;13- driving unit;14- control unit;15- Antinoise unit;16- protection location;A- controls signal;B- controls signal;C- controls signal;CLK1- first frequency signal; CLK2- second frequency signal;CLK3- third frequency signal;The 4th frequency signal of CLK4-;D- controls signal;E- controls signal; F- controls signal;The first assignment component of M1-;The second assignment component of M2-;M3- driving assembly;M4- assignment component (goes out in the drawings It is existing, but do not pointed out in specification);M5- driving assembly;M6- transistor;M7- transistor;M8- transistor;M9- first crystal Pipe;M10- second transistor;M11- third transistor;The 4th transistor of M12-;M13- transistor;REF- reference level;S0- rises Beginning signal;The first scanning signal of S1-;The second scanning signal of S2-;S3- third scanning signal;The 4th scanning signal of S4-;S5- Five scanning signals;The 6th scanning signal of S6-;The 7th scanning signal of S7-;T1- first interval;T2- second interval;T3- third area Between;The 4th section T4-;The 5th section T5-;The 6th section T6-;Between T7- District 7;Between T8- Section Eight;The 9th section T9-; The tenth section T10-;The 11st section T11-;The first power supply of VDD-;VSS- second source.
Specific embodiment
To make auditor to feature of the invention and the effect of being reached has a better understanding and awareness, careful assistant is with reality Example and cooperation detailed description are applied, is illustrated as after:
Referring to Fig. 1, the diagram of the embodiment for the concatenation of multistage gate drive circuit of the invention.It as shown is Multistage gate drive circuit 1,2,3 concatenates, and every level-one gate drive circuit 1,2,3 all exports two scanning signal S1-respectively S6.First lock stage drive circuit 1 of the invention, which receives an initial signal S0, a first frequency signal CLK1 and a second frequency, to be believed It is saturating that number CLK2 generates one first scanning signal S1 and one second scanning signal S2, the first scanning signal S1 and the second scanning signal S2 It crosses multiple scan lines and controls multiple pixels, wherein the second scanning signal S2 is also the starting of one second single-stage gate drive circuit 2 Signal, similarly the scanning signal S4 of the second single-stage gate drive circuit 2 output is also the starting of third single-stage gate drive circuit 3 Signal.I other words if not single-stage gate drive circuit 1 can equally receive previous stage lock when single-stage 1 first order of gate drive circuit The scanning signal of stage drive circuit is as initial signal S0.
Referring to Fig. 2, the circuit diagram of the embodiment for the single-stage gate drive circuit with multi output of the invention.Such as Shown in figure, the first single-stage gate drive circuit 1 tool there are two scanning circuit, one first scanning circuit include a setup unit 10 with One driving unit 11, one second scanning circuit include a setup unit 12 and a driving unit 13.Setup unit 10 receives starting Signal S0 and one first power vd D and generate a control signal A, driving unit 11 couple setup unit 10 simultaneously receive control signal A and first frequency signal CLK1, control signal A control driving unit 11 generate the first scanning letter according to first frequency signal CLK1 Number S1, i other words, control signal A and first frequency signal CLK1 make driving unit 11 generate the first scanning signal S1.Second sweeps The setup unit 12 of scanning circuit couples the driving unit 11 of the first scanning circuit, and receives the first scanning signal S1 and the first power supply VDD and generate a control signal B.Driving unit 13 couples setup unit 12, and receives control signal B and second frequency signal CLK2, control signal B control driving unit 13 generate the second scanning signal S2 according to second frequency signal CLK2, i other words, control Signal B processed and second frequency signal CLK2 makes driving unit 13 generate the second scanning signal S2.First single-stage so of the invention Gate drive circuit 1 exports the first scanning signal S1 and the second scanning signal S2, and is that a single-stage gate with multi output drives Dynamic circuit.
Again refering to fig. 1 with Fig. 2, the setup unit 10 of the first scanning circuit includes that one first assignment component M1 is set with one second Determining component M2, the first assignment component M1 has an input terminal, a control terminal and an output end, and input terminal receives the first power vd D, Control terminal receives initial signal S0, and output end couples driving unit 11, and the first assignment component M1 is according to initial signal S0 and first Power vd D generates control signal A.Second assignment component M2 has an input terminal, a control terminal and an output end, and input terminal receives One second source VSS, control terminal receive a third scanning signal S3 of one second single-stage gate drive circuit 2 output, output end Driving unit 11 is coupled, the second assignment component M2 is according to third scanning signal S3 and second source VSS setting control signal A, i.e., It is to say, control signal A is set as the level of second source VSS by third scanning signal S3.If the level of second source VSS is one Ground potential, then control signal A is set as ground potential by third scanning signal S3, and such third scanning signal S3 makes to control signal A It discharges and is reduced to ground potential, so driving unit 11 will not generate the first scanning signal S1.
Furthermore the driving unit 11 of the first scanning circuit includes a driving assembly M3 and a capacitor C1, driving assembly M3 With an input terminal, a control terminal and an output end, input terminal receives first frequency signal CLK1, and control terminal couples setup unit 10, output end couples the setup unit 12 of the second scanning circuit, and driving assembly M3 is according to first frequency signal CLK1 and control letter Number A and generate the first scanning signal S1.In this way, the output end of the driving unit 11 of the first scanning circuit exports the first scanning signal S1, the first scanning signal S1 couple the setup unit 12 of the second scanning circuit, so that the second scanning circuit generates the second scanning letter Number S2.
Referring to Fig.2, the first scanning circuit also includes a capacitor C1, capacitor C1 is coupled to the control terminal of driving assembly M3 Between output end.Therefore, when control signal A does not control driving assembly M3 conducting, the level of a first end of capacitor C1 For the level for controlling signal A, when controlling signal A control driving assembly M3 conducting, the level of a second end of capacitor C1 is The level of first frequency signal CLK1, and the level of the first end of capacitor C1 is changed to the level of control signal A plus first The level of frequency signal CLK1.In this way, the first end of capacitor C1 is control when first frequency signal CLK1 is a high level The level of signal A adds the level of first frequency signal CLK1;That is capacitor C1 is according to control signal A and first frequency signal CLK1 promotes the level of the first scanning signal S1.
Accept it is above-mentioned, when first frequency signal CLK1 is a low level (such as: a ground potential), the first of capacitor C1 End is the level of control signal A.I other words the control terminal of driving assembly M3 can according to first frequency signal CLK1 lift level or It reduces level and generates the first scanning signal S1, or it may be said that single-stage gate drive circuit 1 of the invention utilizes driving unit 11,13 the charge and discharge work of scan line can be completed, and circuit area is greatly decreased and promotes the charging to scan line Speed.
In addition, as shown in Fig. 2, the control signal A of the first scanning circuit only needs to control driving assembly M3 and need not control Driving assembly M5, the control signal B of the second scanning circuit equally only need to control driving assembly M5 and need not control other drivings Component, so the output loading of single-stage gate drive circuit 1 of the invention is lower, so that single-stage gate drive circuit 1 is defeated Output capacity is preferable.
It is multiple referring to Fig.2, single-stage gate drive circuit 1 of the invention has a noise suicide circuit, noise suicide circuit coupling the One scanning circuit and the second scanning circuit, and first frequency signal CLK1 is received to reduce the noise and of the first scanning circuit 1 The noise of two scanning circuits, the signified place that noise occurs is the control terminal of driving assembly M3, M5 and the noise of output end herein. Noise suicide circuit includes a control unit 14, antinoise unit 15 and a protection location 16, and control unit 14 receives the first power supply VDD, first frequency signal CLK1 and control signal A.
Accept it is above-mentioned, control unit 14 include multiple transistor M6-M8, the first power vd D control transistor M7 be in leads Logical state, it is on or off state that first frequency signal CLK1, which controls transistor M6, likewise, control signal A controls crystal Pipe M8 is on or off state.Wherein, when control signal A control transistor M8 conducting, control signal C is reference level REF, Therefore noise suicide circuit not enabled antinoise work, i other words, control signal A controls noise suicide circuit not enabled antinoise work Make.When controlling signal A control transistor M8 cut-off, if first frequency signal CLK1 control transistor M6 conducting, controls letter Number C is the level of the first power vd D, and such noise suicide circuit enables antinoise work, i other words, the first power vd D and first Frequency signal CLK1 controls noise suicide circuit and enables antinoise work.
Referring to Fig.2, antinoise unit 15 includes a first transistor M9, a second transistor M10, a third transistor M11 and one the 4th transistor M12, the first transistor M9 have an input terminal, a control terminal and an output end, input terminal coupling the The driving unit 11 of one scanning circuit, control terminal couple control unit 14, and output end couples a reference level REF, first crystal Pipe M9 makes the level equalization of a control terminal of the driving unit 11 of the first scanning circuit in reference level REF.Second transistor M10 With an input terminal, a control terminal and an output end, input terminal couples the driving unit 11 of the first scanning circuit, control terminal coupling Control unit 14, output end couple reference level REF, and second transistor M10 makes the defeated of the driving unit 11 of the first scanning circuit The level equalization of outlet is in reference level REF.
Accept it is above-mentioned, third transistor M11 have an input terminal, a control terminal and an output end, input terminal coupling second One driving unit 13 of scanning circuit, control terminal couple control unit 14, and output end couples reference level REF, third transistor M11 makes the level equalization of the control terminal of the driving unit 13 of the second scanning circuit in reference level REF.4th transistor M12 tool There are an input terminal, a control terminal and an output end, input terminal couples the driving unit 13 of the second scanning circuit, control terminal coupling control Unit 14 processed, output end couple reference level REF, and the 4th transistor M12 makes the output of the driving unit 13 of the second scanning circuit The level equalization at end is in reference level REF.I other words when the control terminal and output end of control signal C control driving unit 11,13 When for reference level REF, the current potential of the control terminal and output end that can make driving unit 11,13 is stable and avoids the shadow of noise It rings, such scan line will not be coupled by signal to be influenced.
Referring to Fig.2, protection location 16 can be a transistor M13, transistor M13 have an input terminal, a control terminal and One output end, input terminal couple the first transistor M9, second transistor M10, third transistor M11 and the 4th transistor M12, control End processed receives a third frequency signal CLK3, and output end couples reference level REF.When first frequency signal CLK1 and second frequency Signal CLK2 is non-when being a reference level (such as: ground potential), and first frequency signal CLK1 and second frequency signal CLK2 is to sweeping It retouches line and has coupled noise, therefore third frequency signal CLK3 control transistor M13 cut-off, control signal C is made to be maintained at high electricity It is flat, allow the output of the first scanning circuit and the second scanning circuit to be maintained at reference level REF, and coupled noise is reduced to scan line Influence.
Accept it is above-mentioned, it is anti-, when first frequency signal CLK1 and second frequency signal CLK2 is a reference level REF, First frequency signal CLK1 and second frequency signal CLK2 do not have coupled noise, therefore third frequency signal CLK3 to scan line Transistor M13 electric discharge is controlled, control signal C is made to change into reference level REF.I other words 16 foundation of protection location of the invention Third frequency signal CLK3 and it is periodically that the first transistor M9, second transistor M10, third transistor M11 and the 4th is brilliant The control terminal of body pipe M12 is maintained at reference level REF, to avoid coupled noise.
A noise suicide circuit is shared based on above-mentioned, of the invention the first scanning circuit and the second scanning circuit, and is reduced The layout area of noise suicide circuit.Furthermore noise suicide circuit of the invention can be by the control terminal and output end of driving unit 11,13 It being reset and is maintained at reference level REF, such single-stage gate drive circuit 1,2,3 can reduce the setting of resetting component, And layout area can also be reduced.I other words noise suicide circuit of the invention accomplishes the function of antinoise and resetting simultaneously.Therefore The present invention reduces many places layout area of gate drive circuit and achievees the purpose that narrow frame.
Referring to Fig. 3, being the timing diagram of the single-stage gate drive circuit with multi output of the invention.Timing diagram is this The timing diagram of invention single-stage gate drive circuit, that is to say, that the first single-stage gate drive circuit 1, the second single-stage gate of Fig. 1 The mode of operation of driving circuit 2 and third single-stage gate drive circuit 3 and timing can all refer to Fig. 3.
It is high level in first interval T1, initial signal S0, the first assignment component M1 and transistor M8 are on state;Such as This, the level of control signal A is charged to the level of the first power vd D, and because first frequency signal CLK1 and second frequency Signal CLK2 is reference level REF, does not have coupled noise, so control signal C is with reference to electricity via transistor M8 electric discharge Flat REF;Noise suicide circuit not enabled at this time, and the first scanning signal S1 and first frequency signal CLK1 are similarly reference level REF.High level is changed into second interval T2, first frequency signal CLK1, and believes control via the charging of capacitor C1 The level boost of number A is that the level of the first power vd D adds the level of first frequency signal CLK1, at this time the first scanning signal S1 It can also be promoted to high level, scan line is simultaneously charged to high level by the first scanning signal S1;Furthermore the first scanning signal S1 meeting The transistor M5 conducting of the second scanning circuit is controlled, therefore the level for controlling signal B can promote the level of the first power vd D;This When the first scanning circuit and the second scanning circuit work in, so noise suicide circuit not enabled antinoise work.
It is reduced to reference level REF in 3rd interval T3, first frequency signal CLK1, then the level for controlling signal A reduces To the level of the first power vd D, and the first scanning signal S1 is reduced to reference level REF;Second frequency signal CLK2 is by referring to Level REF changes into high level, therefore the level that the level for controlling signal B is the first power vd D adds second frequency signal The level of CLK2;The second scanning signal S2 can also be promoted to high level and the scan line that charges at this time;Similarly, the second scanning signal S2 can control the setup unit of next stage lock stage drive circuit.Reference is reduced in the 4th section T4, second frequency signal CLK2 The level of level REF, control signal B are also reduced to the level of the first power vd D, and the second scanning signal S2 is also reduced to reference Level REF;Furthermore because third frequency signal CLK3 is high level, so the third of the second single-stage gate drive circuit 2 (Fig. 1) Scanning signal S3 is promoted to high level, and third scanning signal S3 more controls the second assignment component M2 of the first scanning circuit, will Control signal A level from the level of the first power vd D be reduced to second source VSS level (such as: reference level REF).
In the 5th section T5, the first electricity is maintained in the level for controlling signal B in the first single-stage gate drive circuit 1 at this time The level of source VDD, and the 4th frequency signal CLK4 controls the second single-stage gate drive circuit 2 and generates the 4th scanning signal S4.In 6th section T6, first frequency signal CLK1 is again periodically high level at this time, and controls the transistor M10 of control unit 14 Conducting, the level for so controlling signal C is the level of the first power vd D;Moreover, because 1 mesh of the first single-stage gate drive circuit It is preceding not work, so this section does not utilize discharge mechanism to drop to avoid first frequency signal CLK1 from having coupled noise to scan line The level of low control signal C, and control signal C control antinoise unit 15 and enable antinoise work, it can so make to drive The control terminal and output end of unit 11,13 are reference level REF, and reduce the coupled noise of first frequency signal CLK1.
The T7 between District 7, first frequency signal CLK1 be low level (such as: reference level REF), then transistor M6 is Off state, second frequency signal CLK2 is periodic not only but also is high level, but controls the level of signal C not via electric discharge And reduce, so antinoise unit 15 still executes in antinoise work, and second frequency signal CLK2 can't have scan line Coupled noise.The T8 between Section Eight, third frequency signal CLK3 control transistor M13 conducting, and the level for controlling signal C is dropped Down to reference level REF, then antinoise unit 15 stops executing antinoise work;Furthermore therefore first frequency signal in section CLK1 and second frequency signal CLK2 is low level, so not having coupled noise, and need not enable antinoise work.Subsequent Nine section T9 are no longer covered in this and are stated to the explanation of the 11st section T11 such as aforementioned 5th section T5 to T7 between District 7.
By above description it is known that when multiple single-stage gate drive circuits 1,2,3, Yu Yunzuo of display, third frequency Rate signal CLK3 controls the electric discharge of the first single-stage gate drive circuit 1 and the second single-stage of single-stage gate drive circuit 1,2,3 simultaneously Gate drive circuit 2 charges, and first frequency signal CLK1 controls the second single-stage gate of single-stage gate drive circuit 1,2,3 simultaneously The electric discharge of driving circuit 2 is charged with third single-stage gate drive circuit 3.
Referring to Fig. 4, the circuit diagram of the multi output design for the next stage gate drive circuit of Fig. 3 of the present invention.As schemed Show, be the second single-stage gate drive circuit 2, Fig. 4 is intended to show from unlike Fig. 2, and the gate drive circuit 2 of Fig. 4 is transported When making received signal be the second scanning signal S2 of previous stage gate drive circuit 1, rear stage one the 5th scanning signal S5, Third frequency signal CLK3, the 4th frequency signal CLK4 and first frequency signal CLK1, but its function mode with it is shown in Fig. 2 Gate drive circuit 1 is identical.Furthermore this difference can be refering to fig. 1, so that it may which the second single-stage gate drives when significantly finding out running In place of dynamic 2 received signal of circuit and the difference of the first single-stage gate drive circuit 1.
In conclusion the present invention provides a kind of single-stage gate drive circuit, it is multi output with multiple scanning circuits Design, wherein one first scanning circuit includes a setup unit and a driving unit, setup unit receives an initial signal and generates One control signal, driving unit coupling setup unit simultaneously receive control signal and a first frequency signal, control signal and first Frequency signal makes driving unit generate one first scanning signal.Driving unit drives the first scanning signal according to first frequency signal It is promoted to one first level, driving unit drives the first scanning signal to be reduced to a second electrical level according to first frequency signal, the One level is higher than second electrical level.One second scanning circuit couples the first scanning circuit, and receives the first scanning signal and one second Frequency signal, the second scanning circuit generate one second scanning signal according to the first scanning signal and second frequency signal.
Described above to be merely exemplary for the purpose of the present invention, and not restrictive, those of ordinary skill in the art understand, In the case where not departing from spirit and scope defined by claims appended below, many modifications can be made, are changed, or wait Effect, but fall in protection scope of the present invention.

Claims (4)

1. a kind of display, which has multiple single-stage gate drive circuits, and single-stage gate drive circuit includes:
One first scanning circuit, it includes:
One setup unit receives an initial signal, generates a control signal;
One driving unit couples the setup unit, receives the control signal and a first frequency signal, the control signal and this One frequency signal makes the driving unit generate one first scanning signal, the driving unit according to the first frequency signal drive this Scan signal is promoted to one first level, which drives first scanning signal reduction according to the first frequency signal To a second electrical level, which is higher than the second electrical level;
One second scanning circuit couples first scanning circuit, receives first scanning signal and a second frequency signal, this Two scanning circuits generate one second scanning signal according to first scanning signal and the second frequency signal;And
One noise suicide circuit couples first scanning circuit and second scanning circuit, receives the first frequency signal, and reducing should The noise of the noise of first scanning circuit and second scanning circuit,
In the display interior, a third frequency signal controls one first single-stage gate drive of single-stage gate drive circuit simultaneously Circuit discharging and one second single-stage gate drive circuit charge, which controls single-stage gate drive circuit simultaneously Second single-stage gate drive circuit electric discharge is charged with a third single-stage gate drive circuit,
The noise suicide circuit includes a control unit, which receives one first power supply, the first frequency signal and the control Signal processed, the control signal control noise suicide circuit not enabled antinoise work, first power supply and the first frequency signal It controls the noise suicide circuit and enables antinoise work,
The noise suicide circuit includes primary antibody element of noise, which includes:
One the first transistor, has an input terminal, a control terminal and an output end, which couples first scanning circuit The driving unit, the control terminal couple the control unit, the output end couple a reference level, the first transistor make this first The level equalization of one control terminal of the driving unit of scanning circuit is in the reference level;
One second transistor, has an input terminal, a control terminal and an output end, which couples first scanning circuit The driving unit, the control terminal couple the control unit, which couples the reference level, the second transistor make this first The level equalization of one output end of the driving unit of scanning circuit is in the reference level;
One third transistor, has an input terminal, a control terminal and an output end, which couples second scanning circuit One driving unit, the control terminal couple the control unit, which couples the reference level, the third transistor make this second The level equalization of one control terminal of the driving unit of scanning circuit is in the reference level;And
One the 4th transistor, has an input terminal, a control terminal and an output end, which couples second scanning circuit The driving unit, the control terminal couple the control unit, which couples the reference level, the 4th transistor make this second The level equalization of one output end of the driving unit of scanning circuit in the reference level,
The noise suicide circuit includes a protection location, which has an input terminal, a control terminal and an output end, this is defeated Enter end and couple the first transistor, the second transistor, the third transistor and the 4th transistor, the control terminal receive this Three frequency signals, the output end couple the reference level, which periodically should according to the third frequency signal The first transistor, the second transistor, the third transistor and the control terminal of the 4th transistor are maintained at the reference level,
Wherein, single-stage gate drive circuit exports first scanning signal and second scanning signal to multiple pixels, controls institute Pixel is stated,
Single-stage gate drive circuit is a simple scanning circuit.
2. display as described in claim 1, which is characterized in that the setup unit includes:
One first assignment component has an input terminal, a control terminal and an output end, which receives one first power supply, should Control terminal receives the initial signal, which couples the driving unit, and first assignment component is according to the initial signal and is somebody's turn to do First power supply generates the control signal;And
One second assignment component has an input terminal, a control terminal and an output end, which receives a second source, should Control terminal receives a third scanning signal, which couples the driving unit, which scans according to the third Signal and the second source set the control signal.
3. display as described in claim 1, which is characterized in that the driving unit includes:
One driving assembly has an input terminal, a control terminal and an output end, which receives the first frequency signal, should Control terminal couples the setup unit, which couples second scanning circuit, and the driving assembly is according to the first frequency signal And the control signal and generate first scanning signal;And
One capacitor is coupled between the control terminal of the driving assembly and the output end, according to the control signal and this first Frequency signal promotes the level of first scanning signal.
4. display as described in claim 1, which is characterized in that an output end of the driving unit of first scanning circuit A control terminal of a driving unit of second scanning circuit is electrically connected by a setup unit of second scanning circuit.
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CN106847225B (en) 2017-04-12 2020-05-08 京东方科技集团股份有限公司 Display device, gate drive circuit and drive unit
CN108182917B (en) * 2018-01-02 2020-07-07 京东方科技集团股份有限公司 Shift register, driving method thereof and grid driving circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102982760A (en) * 2012-02-23 2013-03-20 友达光电股份有限公司 Gate driver used in liquid crystal display
CN104299583A (en) * 2014-09-26 2015-01-21 京东方科技集团股份有限公司 Shifting register, drive method of shifting register, drive circuit and display device
CN104599620A (en) * 2014-12-10 2015-05-06 华南理工大学 Inverter of grid integrated driving circuit, grid integrated driver and driving method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI490844B (en) * 2013-01-15 2015-07-01 Giantplus Technology Co Ltd A driving module with a common control node
KR20150006732A (en) * 2013-07-09 2015-01-19 삼성디스플레이 주식회사 Driver, display device comprising the same
CN204720147U (en) * 2015-05-14 2015-10-21 凌巨科技股份有限公司 The multi output design of single-stage gate drive circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102982760A (en) * 2012-02-23 2013-03-20 友达光电股份有限公司 Gate driver used in liquid crystal display
CN104299583A (en) * 2014-09-26 2015-01-21 京东方科技集团股份有限公司 Shifting register, drive method of shifting register, drive circuit and display device
CN104599620A (en) * 2014-12-10 2015-05-06 华南理工大学 Inverter of grid integrated driving circuit, grid integrated driver and driving method

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