JP2010192019A - Shift register and scanning signal line driving circuit provided with the same, and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a shift register changing the order of scanning signal lines while suppressing increase in circuit area or increase in current consumption. <P>SOLUTION: Each stage constituting the shift register includes: a thin-film transistor TS for increasing a potential of an output terminal 61 based on a first clock CKA; thin-film transistors T1/T2 for increasing a potential of an area netA connected to a gate terminal of the thin-film transistor TS based on status signals output from a prestage/poststage; and thin-film transistors T3/T4 for lowering the potential of the area netA based on the status signals output from a stage next to the poststage/stage before the prestage. As for an initial stage of the shift register, the area netA is charged based on a first gate start pulse signal given from the outside, and for a final stage of the shift register, the area netA is charged based on a second gate start pulse signal given from the outside. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a shift register provided in a drive circuit of an active matrix display device, and more particularly to a shift register that can shift an input signal bidirectionally.

  In recent years, a display device in which a display unit including a pixel circuit and a gate driver for driving a gate bus line (scanning signal line) are formed on the same substrate in order to reduce the size and cost of the display device. Development is underway. FIG. 27 is a block diagram showing a configuration example of the gate driver of such a conventional display device. FIG. 28 is a circuit diagram showing a configuration example of one stage of the shift register constituting the gate driver.

  As shown in FIG. 27, the gate driver includes a shift register 90 having a plurality of stages (stages equal to the number of gate bus lines). Each stage of the shift register 90 is in one of two states (first state and second state) at each time point and outputs a signal indicating the state as a scanning signal. It is a circuit. As described above, the shift register 90 includes a plurality of bistable circuits SR. Each bistable circuit SR has an input terminal for receiving a two-phase clock signal CKA (hereinafter referred to as “first clock”) and CKB (hereinafter referred to as “second clock”), and a low-level power supply voltage. An input terminal for receiving VSS, an input terminal for receiving set signal SET, an input terminal for receiving reset signal RESET, and an output terminal for outputting scanning signal GOUT are provided. The scanning signal GOUT output from each stage (bistable circuit) is given to the next stage as a set signal and given to the previous stage as a reset signal.

  As shown in FIG. 28, the bistable circuit includes four thin film transistors T91, T92, T93, and T94, and a capacitor C9. The bistable circuit has four input terminals 91 to 94 and one output terminal 95 in addition to the input terminal for the low-level power supply voltage VSS. The source terminal of the thin film transistor T91, the drain terminal of the thin film transistor T92, and the gate terminal of the thin film transistor T93 are connected to each other. A region (wiring) in which these are connected to each other is referred to as “netA” for convenience.

  As for the thin film transistor T91, the gate terminal and the drain terminal are connected to the input terminal 91 (that is, diode connection), and the source terminal is connected to netA. As for the thin film transistor T92, the gate terminal is connected to the input terminal 92, the drain terminal is connected to netA, and the source terminal is connected to the power supply voltage VSS. As for the thin film transistor T93, the gate terminal is connected to netA, the drain terminal is connected to the input terminal 93, and the source terminal is connected to the output terminal 95. As for the thin film transistor T94, the gate terminal is connected to the input terminal 94, the drain terminal is connected to the output terminal 95, and the source terminal is connected to the power supply voltage VSS. The capacitor C9 has one end connected to the netA and the other end connected to the output terminal 95.

  In the above configuration, each stage (bistable circuit) of the shift register 90 operates as follows. As shown in FIG. 29A, the input terminal 93 is supplied with a first clock CKA that becomes a high level every other horizontal scanning period. As shown in FIG. 29B, the input terminal 94 is supplied with a second clock CKB that is 180 degrees out of phase with the first clock CKA. In a period before time t0, the potential of netA and the potential of the scanning signal GOUT (output terminal 95) are at a low level.

  At time t0, a pulse of the set signal SET is given to the input terminal 91. Since the thin film transistor T91 is diode-connected as shown in FIG. 28, the thin film transistor T91 is turned on by the pulse of the set signal SET, and the capacitor C9 is charged. As a result, the potential of netA changes from the low level to the high level, and the thin film transistor T93 is turned on. Here, during the period from t0 to t1, the first clock CKA is at a low level. Therefore, the scanning signal GOUT is maintained at a low level during this period. During this period, since the reset signal RESET is at a low level, the thin film transistor T92 is maintained in an off state. For this reason, the potential of netA does not decrease during this period.

  At time t1, the first clock CKA changes from the low level to the high level. At this time, since the thin film transistor T93 is in the ON state, the potential of the output terminal 95 increases as the potential of the input terminal 93 increases. Here, as shown in FIG. 28, since the capacitor C9 is provided between the netA-output terminal 95, the potential of the netA rises as the potential of the output terminal 95 rises (netA is bootstrapped). As a result, a large voltage is applied to the thin film transistor T93, and the potential of the scanning signal GOUT rises to the high level potential of the first clock CKA. As a result, the gate bus line connected to the output terminal 95 of this bistable circuit is selected. During the period from t1 to t2, the second clock CKB is at a low level. Therefore, since the thin film transistor T94 is maintained in the off state, the potential of the scanning signal GOUT does not decrease during this period.

  At time t2, the first clock CKA changes from the high level to the low level. As a result, the potential at the output terminal 95 decreases with a decrease in the potential at the input terminal 93, and the potential at netA also decreases through the capacitor C9. At time t2, a pulse of the reset signal RESET is given to the input terminal 92. As a result, the thin film transistor T92 is turned on. As a result, the potential of netA changes from the high level to the low level. At time t2, the second clock CKB changes from the low level to the high level. As a result, the thin film transistor T94 is turned on. As a result, the potential of the output terminal 95, that is, the potential of the scanning signal GOUT becomes low level.

  The scanning signal GOUT output from each stage (bistable circuit) as described above is given to the next stage as a set signal as shown in FIG. As a result, the plurality of gate bus lines provided in the display device are sequentially selected by one horizontal scanning period.

  With respect to the display device as described above, a configuration that enables switching of the scanning order (scanning direction) of the gate bus lines has been proposed. FIG. 30 is a block diagram showing a configuration of a shift register disclosed in US Pat. No. 6,778,626. In this shift register, circuits (circuits for inputting a select signal SW that is a signal corresponding to the scanning order) 310, 312, and 314 are provided for each stage. Then, the scanning order is switched by a select signal SW given to the circuits 310, 312, and 314.

  FIG. 31 is a block diagram showing a configuration of a shift register in the liquid crystal display device disclosed in Japanese Patent Application Laid-Open No. 2004-157508. In this shift register, two select signals (first selection signal VSEL1 and second selection signal VSEL2) are applied to each stage. When the first selection signal VSEL1 is at a high level, forward scanning is performed, and when the second selection signal VSEL2 is at a high level, backward scanning is performed.

  Note that the purpose of enabling switching of the scanning order of the gate bus lines is as follows. For example, when a liquid crystal display module is incorporated into a television by a user at a shipping destination, the mounting direction may differ depending on the shipping destination (for example, upside down). In such a case, if the shipping order can be switched at the shipping destination, an image desired by the user can be displayed. In addition, televisions that allow the image reflected in the mirror to be viewed have been proposed, and if the scan order can be switched, the user can view the normal image on the screen reflected in the mirror. Become.

US Pat. No. 6,778,626 JP 2004-157508 A

  However, according to the configuration described in US Pat. No. 6,778,626, as described above, circuits 310, 312, and 314 for switching the scanning order are required for each stage of the shift register. For this reason, the circuit area and current consumption increase, and the cost increases. Further, the circuits 310, 312 and 314 for switching the scanning order are configured such that the switches are switched by the select signal SW. According to such a configuration, the transistors that constitute the switches during the operation of the display device. Will be kept on. For this reason, when a thin film transistor using amorphous silicon or the like is employed as a switch, the threshold voltage of the transistor may shift during high-temperature aging, and abnormal operation may occur. Therefore, high reliability is not ensured. Further, as described above, in the shift register of the liquid crystal display device disclosed in Japanese Patent Application Laid-Open No. 2004-157508, two select signals (first selection signal VSEL1 and second selection signal VSEL2) are given to each stage. It has a configuration. That is, a drive circuit and signal wiring for these two select signals are required. For this reason, the circuit area and current consumption increase, and the cost increases.

  Therefore, an object of the present invention is to realize a shift register capable of switching the scanning order of scanning signal lines while suppressing an increase in circuit area and an increase in current consumption.

The first invention includes a plurality of bistable circuits having a first state and a second state and connected in series to each other, and a high level potential and a low level applied from outside each bistable circuit A shift register in which the plurality of bistable circuits sequentially enter a first state based on at least two-phase clock signals including first and second clock signals that periodically repeat a potential;
Each bistable circuit is
An output node that outputs a state signal representing either the first state or the second state;
An output control switching element in which the first clock signal is applied to a second electrode, and a third electrode is connected to the output node;
A first first-node charging unit for charging a first node connected to the first electrode of the output control switching element based on a state signal output from a bistable circuit preceding the bistable circuit. When,
A second first-node charging unit for charging the first node based on a state signal output from a bistable circuit subsequent to the bistable circuit;
A first first-node discharge unit for discharging the first node based on a state signal output from the bistable circuit of the next stage of each bistable circuit;
And a second first node discharging unit for discharging the first node based on a state signal output from a bistable circuit preceding the bistable circuit.

According to a second invention, in the first invention,
In the first stage bistable circuit among the plurality of bistable circuits,
The first first node charging unit charges the first node based on a first scanning start signal given from the outside instead of the state signal output from the bistable circuit in the previous stage,
The second first node discharge unit discharges the first node based on a predetermined signal given from the outside instead of the state signal output from the bistable circuit of the preceding stage,
In the second stage bistable circuit among the plurality of bistable circuits,
The second first node discharge unit discharges the first node based on a predetermined signal given from the outside instead of the state signal output from the bistable circuit of the preceding stage,
Among the plurality of bistable circuits, in the bistable circuit in the previous stage of the final stage,
The first first node discharge unit discharges the first node based on a predetermined signal given from the outside instead of the state signal output from the bistable circuit of the next stage,
In the last stage bistable circuit among the plurality of bistable circuits,
The second first node charging unit charges the first node based on a second scanning start signal supplied from the outside instead of the state signal output from the next stage bistable circuit,
The first first node discharge unit discharges the first node based on a predetermined signal given from the outside instead of a state signal output from a bistable circuit of the next stage.

According to a third invention, in the first or second invention,
In each bistable circuit,
In the first first-node charging unit, a state signal output from a bistable circuit preceding the bistable circuit is supplied to the first electrode and the second electrode, and a third electrode is connected to the first node. Including a first switching element
In the second first node charging unit, a state signal output from a bistable circuit next to the bistable circuit is provided to the first electrode and the second electrode, and a third electrode is provided to the first node. Including a connected second switching element;
In the first first-node discharge unit, a state signal output from a bistable circuit subsequent to each bistable circuit is supplied to a first electrode, a second electrode is connected to the first node, A third switching element in which a low-level potential is applied to the three electrodes;
In the second first node discharge unit, a state signal output from the bistable circuit preceding the bistable circuit is supplied to the first electrode, the second electrode is connected to the first node, It includes a fourth switching element in which a low-level potential is applied to the third electrode.

According to a fourth invention, in any one of the first to third inventions,
Each bistable circuit is
A fifth switching element having a second electrode connected to the first node and a low-level potential applied to the third electrode;
A second node control unit configured to control a potential of a second node connected to the first electrode of the fifth switching element based on the second clock signal and the potential of the first node; Features.

A fifth invention is the fourth invention,
The second node controller is
A sixth switching element in which the second clock signal is applied to the first electrode and the second electrode, and a third electrode is connected to the second node;
A seventh switching element in which a logic inversion signal of a signal indicating the potential of the first node is applied to the first electrode, a second electrode is connected to the second node, and a low-level potential is applied to the third electrode; It is characterized by comprising.

According to a sixth invention, in the fifth invention,
The second node control unit includes a ninth switching element in which the first clock signal is applied to a first electrode, the second electrode is connected to the second node, and a low-level potential is applied to a third electrode. Is further included.

According to a seventh invention, in any one of the first to sixth inventions,
The plurality of bistable circuits further receive a third clock signal as a signal which is given from outside each bistable circuit and periodically repeats a high level potential and a low level potential, and the first clock signal and The first state is sequentially set based on at least three-phase clock signals including the second clock signal and the third clock signal.

According to an eighth invention, in any one of the first to third inventions,
The plurality of bistable circuits further receive a third clock signal and a fourth clock signal as a signal which is given from the outside of each bistable circuit and periodically repeats a high level potential and a low level potential, The first state is sequentially set based on a four-phase clock signal including the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal,
The first clock signal and the third clock signal are 180 degrees out of phase, the second clock signal and the fourth clock signal are 180 degrees out of phase, and the first clock signal And the second clock signal are shifted in phase by 90 degrees.

In a ninth aspect based on the eighth aspect,
Each bistable circuit is
A fifth switching element having a second electrode connected to the first node and a low-level potential applied to the third electrode;
Second node control for controlling the potential of the second node connected to the first electrode of the fifth switching element based on the second clock signal, the fourth clock signal, and the potential of the first node. And a portion.

A tenth invention is the ninth invention,
The second node controller is
A sixth switching element in which the second clock signal is applied to the first electrode and the second electrode, and a third electrode is connected to the second node;
An eighth switching element in which the fourth clock signal is applied to the first electrode and the second electrode, and the third electrode is connected to the second node;
A seventh switching element in which a logic inversion signal of a signal indicating the potential of the first node is applied to the first electrode, a second electrode is connected to the second node, and a low-level potential is applied to the third electrode; It is characterized by comprising.

In an eleventh aspect based on the tenth aspect,
In the second node control unit, the first clock signal or the third clock signal is supplied to a first electrode, the second electrode is connected to the second node, and a low-level potential is applied to the third electrode. It further includes a ninth switching element provided.

In a twelfth aspect of the invention based on any of the eighth to eleventh aspects of the invention,
Each bistable circuit is
An eleventh switching element in which the third clock signal is applied to the first electrode, the second electrode is connected to the output node, and a low-level potential is applied to the third electrode;
A twelfth switching element having the fourth clock signal applied to the first electrode, the second electrode connected to the output node, and a low-level potential applied to the third electrode; .

In a thirteenth invention according to any one of the first to twelfth inventions,
Each bistable circuit further includes a tenth switching element in which the second clock signal is applied to the first electrode, the second electrode is connected to the output node, and a low-level potential is applied to the third electrode. It is characterized by that.

In a fourteenth aspect of the invention, any one of the first to thirteenth aspects of the invention,
The second first node discharge unit of the first stage bistable circuit of the plurality of bistable circuits and the first first node discharge unit of the last stage bistable circuit of the plurality of bistable circuits The first node is discharged based on the same signal.

In a fifteenth aspect of the invention based on any one of the first to fourteenth aspects of the invention,
Each bistable circuit further includes a capacitor having one end connected to the first node and the other end connected to the output node.

According to a sixteenth aspect of the invention, in any one of the first to fifteenth aspects,
It is formed using amorphous silicon.

According to a seventeenth aspect of the invention, in any one of the first to fifteenth aspects,
It is formed using microcrystalline silicon.

According to an eighteenth invention, in any one of the first to fifteenth inventions,
It is formed using polycrystalline silicon.

A nineteenth aspect of the present invention is a scanning signal line driving circuit for a display device for driving a plurality of scanning signal lines arranged in a display unit,
A shift register according to any one of the first to eighteenth inventions;
The plurality of bistable circuits are provided in one-to-one correspondence with the plurality of scanning signal lines,
Each bistable circuit supplies a state signal output from the output node as a scanning signal to a scanning signal line corresponding to each bistable circuit.

A twentieth invention is a display device,
A scanning signal line driving circuit according to a nineteenth aspect of the invention is provided, including the display section.

  According to the first aspect, each stage (bistable circuit) of the shift register has a first output control switching element that controls the potential of the output node (the potential of the state signal output from each stage). As a signal for charging the first node connected to the electrode (typically the gate electrode), a state signal output from the previous stage and a state signal output from the next stage are given, and the first node is discharged. As a signal for this purpose, a status signal output from the previous stage and a status signal output from the subsequent stage are provided. That is, the status signal output from each stage of the shift register functions to charge the first node of the previous stage and the next stage, and functions to discharge the first node of the previous stage and the subsequent stage. The second clock (typically the drain electrode) of the output control switching element is supplied with a first clock signal that periodically repeats a high level potential and a low level potential. For this reason, when the first node is charged at the first stage of the shift register for the first time, the status signals output from the stages of the shift register in the forward order (from the first stage to the last stage) are 1 state. On the other hand, when the first node is charged in the final stage of the shift register for the first time, the status signals output from the respective stages of the shift register are in the reverse order (the order of “the final stage to the first stage”). 1 state. In this way, the shift can be performed without providing the configuration that is conventionally required to switch the shift direction (such as “a configuration in which a switch is switched by a select signal”, “a drive circuit or signal wiring for a select signal”). A shift register capable of switching the direction is realized. For this reason, for example, when the display device is configured so that the scanning order of the scanning signal lines can be switched, an increase in circuit area, an increase in current consumption, an increase in cost, and the like are suppressed. In addition, since a switch for switching the scanning order (shift direction) becomes unnecessary, the occurrence of malfunction due to the shift of the threshold voltage of the switch (transistor) during high-temperature aging is suppressed.

  According to the second aspect, the first node is charged in the first stage of the shift register based on the first scanning start signal given from outside, and the second node given from outside in the last stage of the shift register. The first node is charged based on the scan start signal. For this reason, when the shift operation of the shift register is started based on the first scanning start signal, the state signals output from the respective stages of the shift register become the first state in the forward order. On the other hand, when the shift operation of the shift register is started based on the second scanning start signal, the state signals output from the respective stages of the shift register become the first state in the reverse order. Thereby, the same effect as the first aspect of the invention can be obtained.

  According to the third invention, the first first node charging unit, the second first node charging unit, the first first node discharging unit, and the second first node discharging unit include the switching element. In the configuration, the same effect as the first or second invention can be obtained.

  According to the fourth aspect of the invention, the potential of the second node for controlling the potential of the first node is set to the high level every other horizontal scanning period while the potential of the first node is at the low level. be able to. As a result, the fifth switching element is turned on every other horizontal scanning period while the potential of the first node is at the low level. For this reason, for example, even when the threshold voltage of the switching element for output control is shifted due to high temperature aging, and the leakage current in the switching element becomes large, the potential of the first node is reliably set to the low level every other horizontal scanning period. The abnormal pulse output from the output node can be suppressed.

  According to the fifth aspect, in the configuration in which the switching element is included in the second node control unit, the same effect as in the fourth aspect can be obtained.

  According to the sixth aspect, the potential of the second node is set to the low level based on the first clock signal. For this reason, the shift of the threshold voltage of the switching element in which the first electrode is connected to the second node is suppressed.

  According to the seventh aspect, the shift register operates based on clock signals of three phases or more. Therefore, the timing at which the first clock signal changes from the low level to the high level and the timing at which the signal for discharging the first node changes (for example, the timing at which the first node changes from the low level to the high level) are set to different timings. be able to. Thus, unlike when the shift register operates based on a two-phase clock signal, even if the waveform of the signal for discharging the first node is rounded, the first node should be discharged during the period. An abnormal pulse is not output from the output node due to the first clock signal changing from the low level to the high level. In addition, when the switching element to which the clock signal is applied to the first electrode is included in the bistable circuit, the malfunction of the shift register due to the deterioration of the switching element is suppressed.

  According to the eighth aspect, the shift register operates based on a four-phase clock signal. Therefore, as in the seventh aspect, even if the waveform of the signal for discharging the first node is distorted, the first clock signal is changed from the low level to the high level during the period in which the first node is to be discharged. An abnormal pulse is not output from the output node due to the change to the level. In addition, when the bistable circuit includes a switching element to which a clock signal is applied to the first electrode, the ON duty (ratio of a period in which the switching element is turned on) of the switching element is 25%. For this reason, the occurrence of malfunction of the shift register due to the deterioration of the switching element is effectively suppressed.

  According to the ninth aspect, in the shift register that operates based on the four-phase clock signal, the same effect as in the fourth aspect can be obtained.

  According to the tenth aspect, in the configuration in which the switching element is included in the second node control unit, the same effect as in the ninth aspect can be obtained.

  According to the eleventh aspect, the potential of the second node is set to a low level based on the first clock signal or the third clock signal. For this reason, the shift of the threshold voltage of the switching element in which the first electrode is connected to the second node is suppressed.

  According to the twelfth aspect of the invention, even if an off leak occurs in the output control switching element, the potential of the output node becomes low level based on the third clock signal and the fourth clock signal. Abnormal pulse output is effectively suppressed.

  According to the thirteenth aspect of the present invention, even if an off leak occurs in the output control switching element, the potential of the output node becomes low level based on the second clock signal, so that the output of the abnormal pulse from the output node is effective. Is suppressed.

  According to the fourteenth aspect, the shift operation is stopped by the same signal when the shift operation is performed in the forward order and when the shift operation is performed in the reverse order. As a result, signal wiring necessary for stopping the shift operation is reduced, and effects such as reduction in circuit area, reduction in current consumption, and reduction in cost are further enhanced.

  According to the fifteenth aspect, when the potential of the output node rises, the potential of the first node rises via the capacitor (the first node is bootstrapped). For this reason, during the period in which the bistable circuit is to be maintained in the first state, a decrease in the potential of the first node is suppressed, and a large voltage is applied to the first electrode of the output control switching element. . Thereby, the waveform of the state signal output from the output node is stabilized.

  According to the sixteenth aspect, in the shift register formed using amorphous silicon, the same effect as in any of the first to fifteenth aspects can be obtained.

  According to the seventeenth aspect, in the shift register formed using microcrystalline silicon, the same effect as any of the first to fifteenth aspects can be obtained.

  According to the eighteenth aspect of the invention, the same effect as that of any of the first to fifteenth aspects of the invention can be obtained in a shift register formed using polycrystalline silicon.

  According to the nineteenth aspect of the invention, a scanning signal line drive circuit including a shift register that can achieve the same effects as any of the first to eighteenth aspects of the invention is realized.

  According to the twentieth aspect of the invention, a display device including a scanning signal line drive circuit that can achieve the same effects as the nineteenth aspect of the invention is realized.

FIG. 2 is a circuit diagram showing a configuration of a bistable circuit included in a shift register in a gate driver of the active matrix type liquid crystal display device according to the first embodiment of the present invention. In the said 1st Embodiment, it is a block diagram which shows the whole structure of a liquid crystal display device. In the said 1st Embodiment, it is a block diagram for demonstrating the structure of a gate driver. FIG. 3 is a block diagram showing a configuration of a shift register in a gate driver in the first embodiment. In the said 1st Embodiment, it is a figure for demonstrating the input-output signal of the bistable circuit of the k-th stage of a shift register. 4 is a timing chart for explaining the operation of each stage of the shift register when forward scanning is performed in the first embodiment. 6 is a timing chart for explaining the operation of each stage of the shift register when reverse scanning is performed in the first embodiment. 4 is a timing chart for explaining the overall operation of the shift register when forward scanning is performed in the first embodiment. 6 is a timing chart for explaining the overall operation of the shift register when reverse scanning is performed in the first embodiment. In the 2nd Embodiment of this invention, it is a block diagram which shows the structure of the shift register in a gate driver. In the said 2nd Embodiment, it is a figure for demonstrating the input-output signal of the bistable circuit of the k-th stage of a shift register. FIG. 6 is a circuit diagram showing a configuration of a bistable circuit in the second embodiment. 9 is a timing chart for explaining the operation of each stage of the shift register when forward scanning is performed in the second embodiment. 12 is a timing chart for explaining the operation of each stage of the shift register when reverse scanning is performed in the second embodiment. 10 is a timing chart for explaining the overall operation of the shift register when forward scanning is performed in the second embodiment. 10 is a timing chart for explaining the overall operation of the shift register when reverse scanning is performed in the second embodiment. In the 3rd Embodiment of this invention, it is a circuit diagram which shows the structure of a bistable circuit. 10 is a timing chart for explaining the operation of each stage of the shift register when forward scanning is performed in the third embodiment. In the said 3rd Embodiment, it is a timing chart for demonstrating operation | movement of each stage of a shift register at the time of reverse direction scanning. In the 4th Embodiment of this invention, it is a circuit diagram which shows the structure of a bistable circuit. 10 is a timing chart for explaining the operation of each stage of the shift register when forward scanning is performed in the fourth embodiment. 10 is a timing chart for explaining the operation of each stage of the shift register when reverse scanning is performed in the fourth embodiment. In the modification of the said 4th Embodiment, it is a circuit diagram which shows the structure of a bistable circuit. In the 5th Embodiment of this invention, it is a block diagram which shows the structure of the shift register in a gate driver. In the said 5th Embodiment, it is a timing chart for demonstrating the operation | movement of the whole shift register when a forward scan is performed. In the said 5th Embodiment, it is a timing chart for demonstrating the operation | movement of the whole shift register when reverse scanning is performed. It is a block diagram which shows one structural example of the gate driver of the conventional display apparatus. In the conventional example, it is a circuit diagram which shows the structural example for one stage of the shift register which comprises a gate driver. 10 is a timing chart for explaining the operation of each stage of the shift register in the conventional example. FIG. 6 is a block diagram illustrating a configuration of a shift register disclosed in US Pat. No. 6,778,626. FIG. 11 is a block diagram showing a configuration of a shift register in a liquid crystal display device disclosed in Japanese Patent Application Laid-Open No. 2004-157508.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the gate terminal (gate electrode) of the thin film transistor corresponds to the first electrode, the drain terminal (drain electrode) corresponds to the second electrode, and the source terminal (source electrode) corresponds to the third electrode. To do.

<1. First Embodiment>
<1.1 Overall configuration and operation>
FIG. 2 is a block diagram showing the overall configuration of the active matrix liquid crystal display device according to the first embodiment of the present invention. As shown in FIG. 2, the liquid crystal display device includes a display unit 10, a display control circuit 20, a source driver (video signal line driving circuit) 30, and a gate driver (scanning signal line driving circuit) 40. The display control circuit 20 is formed on the control board 2. The source driver 30 is formed on the flexible substrate 3. The gate driver 40 is formed on the display panel 4 including the display unit 10 using amorphous silicon, polycrystalline silicon, microcrystalline silicon, or the like. That is, in the present embodiment, the gate driver 40 has a monolithic configuration.

  The display unit 10 includes a plurality (m) of source bus lines (video signal lines) SL1 to SLm, a plurality (n) of gate bus lines (scanning signal lines) GL1 to GLn, and their source buses. A plurality of (n × m) pixel forming portions provided corresponding to the intersections of the lines SL1 to SLm and the gate bus lines GL1 to GLn are included.

  The plurality of pixel forming portions are arranged in a matrix to form a pixel array, and each pixel forming portion has a gate bus connected to a gate bus line passing through a corresponding intersection and a source bus passing through the intersection. A thin film transistor (TFT) 11 which is a switching element having a source terminal connected to a line, a pixel electrode connected to the drain terminal of the thin film transistor 11, and a counter electrode provided in common to the plurality of pixel forming portions It consists of a certain common electrode Ec and a liquid crystal layer provided in common to the plurality of pixel forming portions and sandwiched between the pixel electrode and the common electrode Ec. A pixel capacitor Cp is constituted by a liquid crystal capacitor formed by the pixel electrode and the common electrode Ec. Normally, an auxiliary capacitor is provided in parallel with the liquid crystal capacitor in order to reliably hold the voltage in the pixel capacitor Cp. However, since the auxiliary capacitor is not directly related to the present invention, its description and illustration are omitted.

  The display control circuit 20 receives an image signal DAT and a timing signal group TG such as a horizontal synchronization signal and a vertical synchronization signal sent from the outside, and receives a digital video signal DV and a source start pulse for controlling image display on the display unit 10. The signal SSP, the source clock signal SCK, the latch strobe signal LS, the first gate start pulse signal GSP1 as the first scan start signal, the second gate start pulse signal GSP2 as the second scan start signal, the first The gate end pulse signal GEP1, the second gate end pulse signal GEP2, the first gate clock signal GCK1, and the second gate clock signal GCK2 are output.

  The source driver 30 receives the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the display control circuit 20, and supplies the driving video signal S to the source bus lines SL1 to SLm. (1) to S (m) are applied.

  The gate driver 40 includes a first gate start pulse signal GSP1, a second gate start pulse signal GSP2, a first gate end pulse signal GEP1, a second gate end pulse signal GEP2, and a second gate end pulse signal GEP2 output from the display control circuit 20. Based on one gate clock signal GCK1 and second gate clock signal GCK2, the application of the active scanning signals GOUT (1) to GOUT (n) to the gate bus lines GL1 to GLn is repeated in one vertical scanning period. Repeat as. In the present embodiment, the first gate start pulse signal GSP1, the second gate start pulse signal GSP2, the first gate end pulse signal GEP1, and the second gate end pulse signal GEP2 are generated according to the generation timing of the pulses. , Forward scan (scan in the order of “GL1, GL2,... GLn−1, GLn”) and reverse scan (in the order of “GLn, GLn-1,..., GL2, GL1”). Switching). A detailed description of the gate driver 40 will be given later.

  As described above, the driving video signals S (1) to S (m) are applied to the source bus lines SL1 to SLm, and the scanning signals GOUT (1) to GOUT (n) are applied to the gate bus lines GL1 to GLn. Is applied, an image based on the image signal DAT sent from the outside is displayed on the display unit 10.

<1.2 Configuration of gate driver>
Next, the configuration of the gate driver 40 in this embodiment will be described with reference to FIGS. As shown in FIG. 3, the gate driver 40 includes an n-stage shift register 410. When the display unit 10 has a pixel matrix of n rows × m columns, each stage of the shift register 410 is provided so as to correspond to each row of the pixel matrix on a one-to-one basis. Each stage of the shift register 410 is in one of two states (first state and second state) at each time point, and scans a signal (state signal) indicating the state. It is a bistable circuit that outputs as a signal. As described above, the shift register 410 includes n bistable circuits SR (1) to SR (n). In this embodiment, if the bistable circuit is in the first state, a high level (H level) state signal is output from the bistable circuit as a scanning signal, and the bistable circuit is in the second state. In this state, a low level (L level) state signal is output as a scanning signal from the bistable circuit. In the following description, it is assumed that the shift register 410 includes eight bistable circuits.

  FIG. 4 is a block diagram showing a configuration of the shift register 410 in the gate driver 40. FIG. 5 is a diagram for explaining input / output signals of the k-th stage bistable circuit SR (k) of the shift register 410. As shown in FIG. 4, the shift register 410 includes eight bistable circuits SR (1) to SR (8). Each bistable circuit includes an input terminal for receiving two-phase clock signals CKA (hereinafter referred to as “first clock”) and CKB (hereinafter referred to as “second clock”), and a low-level power supply voltage VSS. , An input terminal for receiving a first set signal SET1, which is a signal for starting scanning during forward scanning, and a second signal for starting scanning during backward scanning. An input terminal for receiving the set signal SET2, an input terminal for receiving the first reset signal RESET1, which is a signal for ending the scanning at the time of forward scanning, and a signal for ending the scanning at the time of backward scanning Are provided with an input terminal for receiving the second reset signal RESET2 and an output terminal for outputting the scanning signal GOUT.

  Hereinafter, signals given to the input terminals of each stage (each bistable circuit) will be described. Note that the low-level power supply voltage VSS is commonly applied to all the stages SR (1) to SR (n) as shown in FIG.

  The first clock CKA and the second clock CKB are as follows (see FIG. 4). For the first stage SR (1), the first gate clock signal GCK1 is given as the first clock CKA, and the second gate clock signal GCK2 is given as the second clock CKB. For the second stage SR (2), the second gate clock signal GCK2 is supplied as the first clock CKA, and the first gate clock signal GCK1 is supplied as the second clock CKB. For the third and subsequent stages, the same configuration as the first and second stages described above is repeated two stages.

  The first set signal SET1 and the second set signal SET2 are as follows. Focusing on the k-th stage SR (k), the scanning signal GOUT (k−1) at the previous stage is given as the first set signal SET1, and the scanning signal GOUT (k + 1) at the next stage is given as the second set signal SET2. (See FIG. 5). However, for the first stage SR (1), the first gate start pulse signal GSP1 is given as the first set signal SET1, and for the eighth stage (final stage) SR (8), the second gate The start pulse signal GSP2 is given as the second set signal SET2 (see FIG. 4).

  The first reset signal RESET1 and the second reset signal RESET2 are as follows. Focusing on the k-th stage SR (k), the next-stage scanning signal GOUT (k + 2) is given as the first reset signal RESET1, and the previous-stage scanning signal GOUT (k-2) is given as the second reset signal RESET2. (See FIG. 5). However, for the first stage SR (1), the second gate end pulse signal GEP2 is given as the second reset signal RESET2, and for the second stage SR (2), the first gate start pulse signal GSP1 is For the seventh stage SR (7), the second gate start pulse signal GSP2 is provided as the first reset signal RESET1, and the eighth stage (final stage) SR (8 ), The first gate end pulse signal GEP1 is given as the first reset signal RESET1 (see FIG. 4).

  Next, a signal output from the output terminal of each stage (each bistable circuit) will be described. A scanning signal GOUT (k) for setting the k-th gate bus line GLk to the selected state is output from the output terminal of the k-th stage SR (k). The scanning signal GOUT (k) is given to the (k−2) stage as the first reset signal RESET1, and is given to the (k−1) stage as the second set signal SET2, and the first set signal It is given to the (k + 1) stage as SET1, and is given to the (k + 2) stage as the second reset signal RESET2 (see FIG. 5).

<1.3 Bistable circuit configuration>
FIG. 1 is a circuit diagram showing the configuration of the bistable circuit included in the shift register 410 described above (configuration of one stage of the shift register 410). As shown in FIG. 1, this bistable circuit includes six thin film transistors TS (output control switching elements), T1 (first switching elements), T2 (second switching elements), and T3 (third switching elements). Element), T4 (fourth switching element), T10 (tenth switching element), and a capacitor C1. The bistable circuit has six input terminals 41 to 46 and one output terminal (output node) 61 in addition to the input terminal for the low-level power supply voltage VSS. An input terminal that receives the first set signal SET1 is denoted by reference numeral 41, an input terminal that receives the second set signal SET2 is denoted by reference numeral 42, and an input terminal that receives the first reset signal RESET1 is denoted by 42. The input terminal that receives the second reset signal RESET2 is denoted by reference numeral 43, the input terminal that receives the first clock CKA is denoted by reference numeral 45, and the input terminal that receives the second clock CKB is denoted by reference numeral 43. The code | symbol 46 is attached | subjected. Hereinafter, the connection relationship between the components in the bistable circuit will be described.

  The source terminal of the thin film transistor T1, the source terminal of the thin film transistor T2, the drain terminal of the thin film transistor T3, the drain terminal of the thin film transistor T4, and the gate terminal of the thin film transistor TS are connected to each other. A region (wiring) in which these are connected to each other is referred to as “netA” (first node) for convenience.

  As for the thin film transistor T1, the gate terminal and the drain terminal are connected to the input terminal 41 (ie, diode connection), and the source terminal is connected to netA. As for the thin film transistor T2, the gate terminal and the drain terminal are connected to the input terminal 42 (that is, diode connection), and the source terminal is connected to netA. As for the thin film transistor T3, the gate terminal is connected to the input terminal 43, the drain terminal is connected to netA, and the source terminal is connected to the power supply voltage VSS. As for the thin film transistor T4, the gate terminal is connected to the input terminal 44, the drain terminal is connected to netA, and the source terminal is connected to the power supply voltage VSS. As for the thin film transistor TS, the gate terminal is connected to netA, the drain terminal is connected to the input terminal 45, and the source terminal is connected to the output terminal 61. As for the thin film transistor T10, the gate terminal is connected to the input terminal 46, the drain terminal is connected to the output terminal 61, and the source terminal is connected to the power supply voltage VSS. The capacitor C1 has one end connected to the netA and the other end connected to the output terminal 61.

  Next, the function of each component in this bistable circuit will be described. The thin film transistor T1 sets the potential of netA to high level when the first set signal SET1 is at high level. The thin film transistor T2 sets the potential of netA to a high level when the second set signal SET2 is at a high level. The thin film transistor T3 sets the potential of netA to a low level when the first reset signal RESET1 is at a high level. The thin film transistor T4 sets the potential of netA to a low level when the second reset signal RESET2 is at a high level. The thin film transistor TS applies the potential of the first clock CKA to the output terminal 61 when the potential of netA is at a high level. The thin film transistor T10 sets the potential of the scanning signal GOUT (the potential of the output terminal 61) to a low level when the second clock CKB is at a high level. The capacitor C1 functions as a compensation capacitor for maintaining the potential of netA at a high level during the period when the gate bus line connected to the bistable circuit is in a selected state.

  In the present embodiment, a first first node charging unit is realized by the thin film transistor T1, and a second first node charging unit is realized by the thin film transistor T2. Further, a first first node discharge unit is realized by the thin film transistor T3, and a second second node discharge unit is realized by the thin film transistor T4.

<1.4 Shift register operation>
Next, the operation of the shift register 410 in this embodiment will be described. The generation timing of the first gate start pulse signal GSP1, the second gate start pulse signal GSP2, the first gate end pulse signal GEP1, and the second gate end pulse signal GEP2 given from the display control circuit 20 Accordingly, different operations are performed during forward scanning and backward scanning.

<1.4.1 Operation of each stage (bistable circuit)>
First, the operation of each stage (bistable circuit) of the shift register 410 will be described with reference to FIG. 1, FIG. 6, and FIG. FIG. 6 is a timing chart when forward scanning is performed, and FIG. 7 is a timing chart when backward scanning is performed. In the following description, the period from time t2 to time t3 in FIGS. 6 and 7 is the period during which the gate bus line connected to the output terminal 61 of the bistable circuit is to be selected (selection period). Suppose that

<1.4.1.1 Operation during forward scanning>
The operation of the bistable circuit when forward scanning is performed will be described. During the operation of the liquid crystal display device, the input terminal 45 is supplied with the first clock CKA having a waveform as shown in FIG. 6A, and the input terminal 46 is supplied with the second clock having a waveform as shown in FIG. CKB is given. Thus, in the present embodiment, two-phase clock signals whose phases are shifted by 180 degrees are given to the bistable circuit.

  In a period before time t0, the potential of netA and the potential of the scanning signal GOUT (the potential of the output terminal 61) are at a low level. At time t0, a pulse of the second reset signal RESET2 is given to the input terminal 44. As a result, the thin film transistor T4 is turned on, and the potential of the netA is maintained at a low level. At time t1, a pulse of the first set signal SET1 is given to the input terminal 41. Since the thin film transistor T1 is diode-connected as shown in FIG. 1, the thin film transistor T1 is turned on by the pulse of the first set signal SET1, and the capacitor C1 is charged. As a result, the potential of netA changes from the low level to the high level, and the thin film transistor TS is turned on. Incidentally, during the period from t1 to t2, the first clock CKA is at a low level. Therefore, the scanning signal GOUT is maintained at a low level during this period. Further, during this period, since the first reset signal RESET1 and the second reset signal RESET2 are at the low level, the thin film transistors T3 and T4 are maintained in the off state. For this reason, the potential of netA does not decrease during this period.

  At time t2, the first clock CKA changes from the low level to the high level. At this time, since the thin film transistor TS is in the on state, the potential of the output terminal 61 increases as the potential of the input terminal 45 increases. Here, as shown in FIG. 1, since the capacitor C1 is provided between the netA-output terminal 61, the potential of the netA rises as the potential of the output terminal 61 rises (netA is bootstrapped). As a result, a large voltage is applied to the thin film transistor TS, and the potential of the scanning signal GOUT rises to the high level potential of the first clock CKA. As a result, the gate bus line connected to the output terminal 61 of the bistable circuit is selected. During the period from t2 to t3, the second clock CKB is at a low level. Therefore, the thin film transistor T10 is turned off, and the potential of the scanning signal GOUT does not decrease during this period.

  At time t3, the first clock CKA changes from the high level to the low level. As a result, the potential of the output terminal 61 decreases as the potential of the input terminal 45 decreases, and the potential of netA also decreases via the capacitor C1. At time t3, the second clock CKB changes from the low level to the high level. Accordingly, the thin film transistor T10 is turned on, and the potential of the output terminal 61, that is, the potential of the scanning signal GOUT becomes low level. Further, at time t3, a pulse of the second set signal SET2 is given to the input terminal. Since the thin film transistor T2 is diode-connected as shown in FIG. 1, the potential of netA is maintained at a high level by the pulse of the second set signal SET2. During the period from t3 to t4, the first reset signal RESET1 and the second reset signal RESET2 are at the low level, so that the thin film transistors T3 and T4 are maintained in the off state. For this reason, the potential of netA does not fall to a low level during this period.

  At time t4, a pulse of the first reset signal RESET1 is given to the input terminal 43. As a result, the thin film transistor T3 is turned on, and the potential of netA changes from the high level to the low level.

  As described above, during forward scanning, the first set signal SET1 functions as a signal for raising the potential of netA from a low level to a high level to generate an active scanning signal GOUT. 1 reset signal RESET1 functions as a signal for lowering the potential of netA, which is at a high level, to a low level. Then, the active clock signal GOUT is output from the bistable circuit when the first clock CKA goes high during the period when the potential of netA is high.

<1.4.1.2 Operation during reverse scanning>
Next, the operation of the bistable circuit when reverse scanning is performed will be described. During the operation of the liquid crystal display device, as in the case of forward scanning, the input terminal 45 is supplied with the first clock CKA having the waveform as shown in FIG. 7A, and the input terminal 46 is supplied with the signal shown in FIG. A second clock CKB having a waveform as shown is given.

  In a period before time t0, the potential of netA and the potential of the scanning signal GOUT (the potential of the output terminal 61) are at a low level. At time t0, a pulse of the first reset signal RESET1 is given to the input terminal 43. As a result, the thin film transistor T3 is turned on, and the potential of netA is maintained at a low level. At time t1, a pulse of the second set signal SET2 is given to the input terminal. Since the thin film transistor T2 is diode-connected as shown in FIG. 1, the potential of the netA changes from the low level to the high level by the pulse of the second set signal SET2. As a result, the thin film transistor TS is turned on. Incidentally, during the period from t1 to t2, the first clock CKA is at a low level. Therefore, the scanning signal GOUT is maintained at a low level during this period. Further, during this period, since the first reset signal RESET1 and the second reset signal RESET2 are at the low level, the thin film transistors T3 and T4 are maintained in the off state. For this reason, the potential of netA does not decrease during this period.

  At time t2, the first clock CKA changes from the low level to the high level. At this time, since the thin film transistor TS is in the on state, the potential of the output terminal 61 increases as the potential of the input terminal 45 increases. Here, as shown in FIG. 1, since the capacitor C1 is provided between the netA-output terminal 61, the potential of the netA rises as the potential of the output terminal 61 rises (netA is bootstrapped). As a result, a large voltage is applied to the thin film transistor TS, and the potential of the scanning signal GOUT rises to the high level potential of the first clock CKA. As a result, the gate bus line connected to the output terminal 61 of the bistable circuit is selected. During the period from t2 to t3, the second clock CKB is at a low level. Therefore, the thin film transistor T10 is turned off, and the potential of the scanning signal GOUT does not decrease during this period.

  At time t3, the first clock CKA changes from the high level to the low level. As a result, the potential of the output terminal 61 decreases as the potential of the input terminal 45 decreases, and the potential of netA also decreases via the capacitor C1. At time t3, the second clock CKB changes from the low level to the high level. Accordingly, the thin film transistor T10 is turned on, and the potential of the output terminal 61, that is, the potential of the scanning signal GOUT becomes low level. Further, at time t3, a pulse of the first set signal SET1 is given to the input terminal 41. Since the thin film transistor T1 is diode-connected as shown in FIG. 1, the potential of netA is maintained at a high level by the pulse of the first set signal SET1. During the period from t3 to t4, the first reset signal RESET1 and the second reset signal RESET2 are at the low level, so that the thin film transistors T3 and T4 are maintained in the off state. For this reason, the potential of netA does not fall to a low level during this period.

  At time t4, a pulse of the second reset signal RESET2 is given to the input terminal 44. As a result, the thin film transistor T4 is turned on, and the potential of netA changes from the high level to the low level.

  As described above, during backward scanning, the second set signal SET2 functions as a signal for raising the potential of netA from a low level to a high level to generate an active scanning signal GOUT. 2 reset signal RESET2 functions as a signal for lowering the potential of netA, which is at high level, to low level. Then, the active clock signal GOUT is output from the bistable circuit when the first clock CKA goes high during the period when the potential of netA is high.

<1.4.2 Operation of entire shift register>
Next, the operation of the entire shift register 410 based on the operation in each stage (bistable circuit) will be described with reference to FIG. 1, FIG. 4, FIG. 8, and FIG. 8 is a timing chart when forward scanning is performed, and FIG. 9 is a timing chart when backward scanning is performed.

<1.4.2.1 Operation during forward scanning>
The overall operation of the shift register 410 when forward scanning is performed will be described. During the operation of the liquid crystal display device, the shift register 410 has a first gate clock signal GCK1 having a waveform as shown in FIG. 8A and a second gate clock signal GCK2 having a waveform as shown in FIG. And given.

  In a period before time ta, the potential of netA is low in all stages, and the potential of the scanning signal GOUT output from all stages is low. At time ta, the pulse of the first gate start pulse signal GSP1 is supplied to the shift register 410. As shown in FIG. 4, the first gate start pulse signal GSP1 is given to the first stage SR (1) as the first set signal SET1, and the second stage SR (2) as the second reset signal RESET2. Given to. As a result, the potential of netA in the first stage SR (1) changes from the low level to the high level as shown in FIG. The potential of netA of the second stage SR (2) is maintained at a low level.

  At time tb, the first gate clock signal GCK1 changes from low level to high level. At this time, in the first stage SR (1), the potential of the input terminal 45 (see FIG. 1) changes from the low level to the high level, so that the potential of netA of the first stage SR (1) further increases. To do. As a result, during the period from tb to tc, the scanning signal GOUT (1) output from the first stage SR (1) is at the high level.

  As shown in FIG. 4, the scanning signal GOUT (1) of the first stage SR (1) is given to the second stage SR (2) as the first set signal SET1, and three stages as the second reset signal RESET2. Given to eye SR (3). Thus, during the period from tb to tc, the potential of netA is set to the high level in the second stage SR (2) as shown in FIG. 8 (g), and in the third stage SR (3), FIG. ), The potential of netA is maintained at a low level.

  At time tc, the first gate clock signal GCK1 changes from the high level to the low level. As a result, the potential of netA of the first stage SR (1) decreases. At the time tc, the second gate clock signal GCK2 changes from the low level to the high level. At this time, in the first stage SR (1), the potential of the input terminal 46 (see FIG. 1) changes from the low level to the high level, so the scanning signal GOUT output from the first stage SR (1). (1) is low level. Further, since the second gate clock signal GCK2 is supplied to the second stage SR (2) as the first clock CKA, the second stage SR (2) is changed by changing the second gate clock signal GCK2 to the high level. The netA potential further rises, and during the period from tc to td, the scanning signal GOUT (2) output from the second stage SR (2) becomes high level.

  When reaching the time point td, the first gate clock signal GCK1 changes from the low level to the high level. At this time, since the potential of the input terminal 45 changes from the low level to the high level in the third stage SR (3), the potential of netA in the third stage SR (3) further increases. As a result, during the period from td to te, the scanning signal GOUT (3) output from the third stage SR (3) becomes high level. The scanning signal GOUT (3) output from the third stage SR (3) is given to the first stage (1) as the first reset signal RESET1, and the second stage SR (2) as the second set signal SET2. To the fourth stage SR (4) as the first set signal SET1, and to the fifth stage as the second reset signal RESET2. As a result, the potential of netA at the first stage (1) changes from the high level to the low level, and the potential of netA at the second stage SR (2) is maintained at the high level, and the netA of the fourth stage SR (4). Is changed from a low level to a high level, and the potential of netA of the fifth stage SR (5) is maintained at a low level.

  As described above, the scanning signals GOUT (1) to GOUT (8) sequentially become high level for each horizontal scanning period from the first stage SR (1) to the eighth stage SR (8). At time tj, the pulse of the second gate start pulse signal GSP2 is applied to the shift register 410. As shown in FIG. 4, the second gate start pulse signal GSP2 is given to the seventh stage SR (7) as the first reset signal RESET1, and the eighth stage SR (8) as the second set signal SET2. Given to. As a result, the potential of netA of the seventh stage SR (7) changes from the high level to the low level as shown in FIG. 8 (q). The potential of netA of the eighth stage SR (8) is maintained at a high level.

  At time tk, the pulse of the first gate end pulse signal GEP1 is supplied to the shift register 410. The first gate end pulse signal GEP1 is provided to the eighth stage SR (8) as the first reset signal RESET1, as shown in FIG. As a result, the potential of netA of the eighth stage SR (8) changes from the high level to the low level as shown in FIG. 8 (s).

  As described above, the first gate start pulse signal GSP1 is used as a signal for starting scanning of the gate bus lines GL1 to GLn included in the liquid crystal display device, and the first gate end pulse is used as a signal for ending the scanning. By using the signal GEP1, forward scanning of the gate bus lines GL1 to GLn is performed.

<1.4.2.2 Operation during reverse scanning>
Next, the operation of the entire shift register 410 when reverse scanning is performed will be described. During the operation of the liquid crystal display device, as in the case of forward scanning, the shift register 410 has a first gate clock signal GCK1 having a waveform as shown in FIG. 9A and a waveform as shown in FIG. 9B. Of the second gate clock signal GCK2.

  In a period before time ta, the potential of netA is low in all stages, and the potential of the scanning signal GOUT output from all stages is low. At time ta, the pulse of the second gate start pulse signal GSP2 is applied to the shift register 410. As shown in FIG. 4, the second gate start pulse signal GSP2 is given to the eighth stage SR (8) as the second set signal SET2, and the seventh stage SR (7) as the first reset signal RESET1. Given to. As a result, the potential of netA of the eighth stage SR (8) changes from the low level to the high level as shown in FIG. 9 (s). The potential of netA of the seventh stage SR (7) is maintained at the low level.

  At time tb, the second gate clock signal GCK2 changes from the low level to the high level. At this time, since the potential of the input terminal 45 (see FIG. 1) changes from the low level to the high level in the eighth stage SR (8), the potential of netA of the eighth stage SR (8) further increases. To do. As a result, during the period from tb to tc, the scanning signal GOUT (8) output from the eighth stage SR (8) becomes high level.

  As shown in FIG. 4, the scanning signal GOUT (8) of the eighth stage SR (8) is given to the seventh stage SR (7) as the second set signal SET2, and the sixth stage as the first reset signal RESET1. Given to the eye SR (6). Accordingly, during the period from tb to tc, the potential of netA is set to the high level in the seventh stage SR (7) as shown in FIG. 9 (q), and in the sixth stage SR (6), FIG. ), The potential of netA is maintained at a low level.

  At time tc, the second gate clock signal GCK2 changes from high level to low level. As a result, the potential of netA of the eighth stage SR (8) decreases. At the time tc, the first gate clock signal GCK1 changes from the low level to the high level. At this time, since the potential of the input terminal 46 (see FIG. 1) changes from the low level to the high level in the eighth stage SR (8), the scanning signal GOUT output from the eighth stage SR (8). (8) is low level. Further, since the first gate clock signal GCK1 is given to the seventh stage SR (7) as the first clock CKA, the first stage clock signal GCK1 changes to the high level, so that the seventh stage SR (7). The netA potential further rises, and during the period from tc to td, the scanning signal GOUT (7) output from the seventh stage SR (7) becomes high level.

  At time td, the second gate clock signal GCK2 changes from low level to high level. At this time, since the potential of the input terminal 45 changes from the low level to the high level in the sixth stage SR (6), the potential of netA of the sixth stage SR (6) further increases. As a result, during the period from td to te, the scanning signal GOUT (6) output from the sixth stage SR (6) is at a high level. The scanning signal GOUT (6) output from the sixth stage SR (6) is given to the eighth stage (8) as the second reset signal RESET2, and the seventh stage SR (7) as the first set signal SET1. To the fifth stage SR (5) as the second set signal SET2, and to the fourth stage as the first reset signal RESET1. As a result, the potential of the netA of the eighth stage (8) changes from the high level to the low level, the potential of the netA of the seventh stage SR (7) is maintained at the high level, and the netA of the fifth stage SR (5). Changes from low level to high level, and the potential of netA in the fourth stage SR (4) is maintained at low level.

  As described above, the scanning signals GOUT (8) to GOUT (1) sequentially become high level for each horizontal scanning period from the eighth stage SR (8) to the first stage SR (1). At time tj, the pulse of the first gate start pulse signal GSP1 is given to the shift register 410. As shown in FIG. 4, the first gate start pulse signal GSP1 is given to the second stage SR (2) as the second reset signal RESET2, and the first stage SR (1) as the first set signal SET1. Given to. As a result, the potential of netA in the second stage SR (2) changes from the high level to the low level as shown in FIG. 9 (g). The potential of netA in the first stage SR (1) is maintained at a high level.

  At time tk, the pulse of the second gate end pulse signal GEP2 is supplied to the shift register 410. The second gate end pulse signal GEP2 is provided to the first stage SR (1) as the second reset signal RESET2, as shown in FIG. As a result, the potential of netA in the first stage SR (1) changes from the high level to the low level as shown in FIG.

  As described above, the second gate start pulse signal GSP2 is used as a signal for starting scanning of the gate bus lines GL1 to GLn included in the liquid crystal display device, and the second gate end pulse is used as a signal for ending the scanning. By using the signal GEP2, reverse scanning of the gate bus lines GL1 to GLn is performed.

<1.5 Effect>
According to this embodiment, each stage SR (k) of the shift register 410 is supplied with the scanning signal GOUT (k−2) output from the previous stage SR (k−2) as the second reset signal RESET2. The scanning signal GOUT (k−1) output from the previous stage SR (k−1) is given as the first set signal SET1, and the scanning signal GOUT (k + 1) output from the next stage SR (k + 1) is the first. 2 is provided as the reset signal RESET2, and the scanning signal GOUT (k + 2) output from the next stage SR (k + 2) is provided as the first reset signal RESET1. The first stage SR (1) is supplied with the first gate start pulse signal GSP1 as the first set signal SET1, and the eighth stage (final stage) SR (8) has the second gate start pulse signal. The signal GSP2 is given as the second set signal SET2. For this reason, when a pulse of the first gate start pulse signal GSP1 is given to the shift register 410 to start scanning of the gate bus lines GL1 to GLn, “first stage, second stage,... A pulse of the first set signal SET1 is given to each stage in the order of "7th stage, 8th stage", and forward scanning of the gate bus lines GL1 to GLn is performed. On the other hand, when the pulse of the second gate start pulse signal GSP2 is applied to the shift register 410 to start scanning of the gate bus lines GL1 to GLn, “8th stage, 7th stage,. The pulse of the second set signal SET2 is given to each stage in the order of “stage, first stage”, and the gate bus lines GL1 to GLn are scanned in the reverse direction. Here, in this embodiment, each stage of the shift register 410 receives the two set signals SET1, SET2 and the two reset signals RESET1, RESET2, so that the scanning order of the gate bus lines GL1 to GLn is changed. Switching is possible. As described above, according to the present embodiment, the configuration conventionally required for switching the scanning order of the gate bus lines GL1 to GLn (“configuration for switching the switch with the select signal”, “for the select signal”). No need for a driving circuit and signal wiring ”. For this reason, when realizing a shift register capable of switching the scanning order of the gate bus lines GL1 to GLn, it is possible to suppress an increase in circuit area, an increase in current consumption, and an increase in cost. In addition, since a switch for switching the scanning order is not required, the occurrence of malfunction due to the shift of the threshold voltage of the switch (transistor) during high-temperature aging is suppressed.

<1.6 Modification>
In the first embodiment, the capacitor C1 is provided between the netA and the output terminal 61, but the present invention is not limited to this. The capacitor C1 is provided for stabilizing the waveform of the scanning signal GOUT, and may be configured without this capacitor C1. In the first embodiment, the thin film transistor T10 whose on / off is controlled by the second clock CKB is provided. However, the present invention is not limited to this. The thin film transistor T10 is also provided for stabilizing the waveform of the scanning signal GOUT, and may be configured without this thin film transistor T10.

<2. Second Embodiment>
<2.1 Overall configuration and gate driver configuration>
In the present embodiment, the overall configuration and the schematic configuration of the gate driver are substantially the same as those in the first embodiment shown in FIGS. However, in the first embodiment, the two-phase clock signals (the first gate clock signal GCK1 and the second gate clock signal GCK2) are sent from the display control circuit 20 to the gate driver 40. On the other hand, in the present embodiment, the display control circuit 20 to the gate driver 40 send four-phase clock signals (first gate clock signal GCK1, second gate clock signal GCK2, third gate clock signal GCK3, and third gate clock signal GCK3). 4 gate clock signal GCK4).

  FIG. 10 is a block diagram showing a configuration of the shift register 411 in the gate driver 40. FIG. 11 is a diagram for explaining input / output signals of the k-th bistable circuit of the shift register 411. As shown in FIG. 10, the shift register 411 includes eight bistable circuits SR (1) to SR (8). Each bistable circuit includes an input terminal for receiving four-phase clock signals CKA, CKB, CKC (hereinafter referred to as “third clock”) and CKD (hereinafter referred to as “fourth clock”), An input terminal for receiving the level power supply voltage VSS, an input terminal for receiving the first set signal SET1, an input terminal for receiving the second set signal SET2, and a first reset signal RESET1 Input terminal, an input terminal for receiving the second reset signal RESET2, and an output terminal for outputting the scanning signal GOUT.

  Hereinafter, the four-phase clock signals CKA, CKB, CKC, and CKD input to each stage (each bistable circuit) will be described. The first set signal SET1, the second set signal SET2, the first reset signal RESET1, the second reset signal RESET2, and the power supply voltage VSS are the same as those in the first embodiment, and therefore will be described. Is omitted.

  For the first stage SR (1) and the fifth stage SR (5), the first gate clock signal GCK1 is provided as the first clock CKA, and the second gate clock signal GCK2 is provided as the second clock CKB. The third gate clock signal GCK3 is given as the third clock CKC, and the fourth gate clock signal GCK4 is given as the fourth clock CKD.

  For the second stage SR (2) and the sixth stage SR (6), the second gate clock signal GCK2 is provided as the first clock CKA, and the third gate clock signal GCK3 is provided as the second clock CKB. The fourth gate clock signal GCK4 is supplied as the third clock CKC, and the first gate clock signal GCK1 is supplied as the fourth clock CKD.

  For the third stage SR (3) and the seventh stage SR (7), the third gate clock signal GCK3 is provided as the first clock CKA, and the fourth gate clock signal GCK4 is provided as the second clock CKB. The first gate clock signal GCK1 is given as the third clock CKC, and the second gate clock signal GCK2 is given as the fourth clock CKD.

  For the fourth stage SR (4) and the eighth stage SR (8), the fourth gate clock signal GCK4 is provided as the first clock CKA, and the first gate clock signal GCK1 is provided as the second clock CKB. The second gate clock signal GCK2 is supplied as the third clock CKC, and the third gate clock signal GCK3 is supplied as the fourth clock CKD.

<2.2 Bistable circuit configuration>
FIG. 12 is a circuit diagram showing a configuration of the bistable circuit in the present embodiment. In this embodiment, in addition to the components in the first embodiment shown in FIG. 1, two thin film transistors T11 (11th switching element), T12 (12th switching element), and a third clock An input terminal 47 for receiving CKC and an input terminal 48 for receiving the fourth clock CKD are provided. As for the thin film transistor T11, the gate terminal is connected to the input terminal 47, the drain terminal is connected to the output terminal 61, and the source terminal is connected to the power supply voltage VSS. As for the thin film transistor T12, the gate terminal is connected to the input terminal 48, the drain terminal is connected to the output terminal 61, and the source terminal is connected to the power supply voltage VSS. The thin film transistor T11 sets the potential of the scanning signal GOUT to a low level when the third clock CKC is at a high level. The thin film transistor T12 sets the potential of the scanning signal GOUT to a low level when the fourth clock CKD is at a high level.

<2.3 Shift register operation>
Next, the operation of the shift register 411 in this embodiment will be described. Only differences from the first embodiment will be described in detail, and the same points as in the first embodiment will be described briefly.
<2.3.1 Operation of each stage (bistable circuit)>
First, the operation of each stage (bistable circuit) of the shift register 411 will be described with reference to FIG. 12, FIG. 13, and FIG. FIG. 13 is a timing chart when forward scanning is performed, and FIG. 14 is a timing chart when backward scanning is performed.

<2.3.1.1 Operation during forward scanning>
The operation of the bistable circuit when forward scanning is performed will be described. During the operation of the liquid crystal display device, the input terminal 45 is supplied with the first clock CKA having a waveform as shown in FIG. 13A, and the input terminal 46 is supplied with the second clock having a waveform as shown in FIG. The third clock CKC having a waveform as shown in FIG. 13C is given to the input terminal 47, and the fourth clock CKD having a waveform as shown in FIG. 13D is given to the input terminal 48. Given. Thus, in the present embodiment, a four-phase clock signal whose phase is shifted by 90 degrees is given to the bistable circuit.

  In the period before time t1, the same operation as in the first embodiment is performed. At time t1, a pulse of the first set signal SET1 is given to the input terminal 41. As a result, the potential of netA changes from the low level to the high level, and the thin film transistor TS is turned on. Since the first clock CKA is at the low level during the period from t1 to t2, the scanning signal GOUT is maintained at the low level. Further, during this period, since the first reset signal RESET1 and the second reset signal RESET2 are at the low level, the potential of the netA does not decrease.

  At time t2, the first clock CKA changes from the low level to the high level. As a result, as in the first embodiment, the potential of the scanning signal GOUT rises to the high level potential of the first clock CKA. As a result, the gate bus line connected to the output terminal 61 of the bistable circuit is selected. During the period from t2 to t3, the second clock CKB, the third clock CKC, and the fourth clock CKD are all at a low level. For this reason, the potential of the scanning signal GOUT does not decrease during this period.

  At time t3, the first clock CKA changes from the high level to the low level. As a result, the potential of netA decreases. At time t3, the second clock CKB changes from the low level to the high level. As a result, the potential of the output terminal 61, that is, the potential of the scanning signal GOUT becomes low level. Further, at time t3, a pulse of the second set signal SET2 is given to the input terminal. As a result, the potential of netA is maintained at a high level. Note that, during the period from t3 to t4, the first reset signal RESET1 and the second reset signal RESET2 are at the low level, so that the potential of the netA does not decrease to the low level. At time t4, a pulse of the first reset signal RESET1 is given to the input terminal 43. As a result, the potential of netA changes from the high level to the low level.

<2.3.1.2 Operation during reverse scanning>
Next, the operation of the bistable circuit when reverse scanning is performed will be described. During the operation of the liquid crystal display device, the input terminal 45 is supplied with the first clock CKA having a waveform as shown in FIG. 14A, and the input terminal 46 is supplied with the second clock having a waveform as shown in FIG. CKB is applied, a third clock CKC having a waveform as shown in FIG. 14C is applied to the input terminal 47, and a fourth clock CKD having a waveform as shown in FIG. 14D is applied to the input terminal 48. Given. As can be understood from FIG. 13 and FIG. 14, during forward scanning, these four-phase clock signals are in the order of “first clock CKA, second clock CKB, third clock CKC, fourth clock CKD”. A clock pulse is applied to this bistable circuit, but in the case of reverse scanning, these four-phase clock signals are sequentially output in the order of “fourth clock CKD, third clock CCK, second clock CKB, first clock CKA”. Clock pulses are applied to this bistable circuit. The display control circuit 20 switches the generation order of such clock pulses.

  In the period before time t1, the same operation as in the first embodiment is performed. At time t1, a pulse of the second set signal SET2 is given to the input terminal. As a result, the potential of netA changes from the low level to the high level, and the thin film transistor TS is turned on. Since the first clock CKA is at the low level during the period from t1 to t2, the scanning signal GOUT is maintained at the low level. Further, during this period, since the first reset signal RESET1 and the second reset signal RESET2 are at the low level, the potential of the netA does not decrease.

  At time t2, the first clock CKA changes from the low level to the high level. As a result, as in the first embodiment, the potential of the scanning signal GOUT rises to the high level potential of the first clock CKA. As a result, the gate bus line connected to the output terminal 61 of the bistable circuit is selected. During the period from t2 to t3, the second clock CKB, the third clock CKC, and the fourth clock CKD are all at a low level. For this reason, the potential of the scanning signal GOUT does not decrease during this period.

  At time t3, the first clock CKA changes from the high level to the low level. As a result, the potential of netA decreases. Further, at the time point t3, the fourth clock CKD changes from the low level to the high level. For this reason, the thin film transistor T12 is turned on. As a result, the potential of the output terminal 61, that is, the potential of the scanning signal GOUT becomes low level. Further, at time t3, a pulse of the first set signal SET1 is given to the input terminal 41. As a result, the potential of netA is maintained at a high level. Note that, during the period from t3 to t4, the first reset signal RESET1 and the second reset signal RESET2 are at the low level, so that the potential of the netA does not decrease to the low level. At time t4, a pulse of the second reset signal RESET2 is given to the input terminal 44. As a result, the potential of netA changes from the high level to the low level.

<2.3.2 Operation of entire shift register>
Next, the operation of the entire shift register 411 based on the operation in each stage (bistable circuit) will be described with reference to FIG. 10, FIG. 12, FIG. 15, and FIG. FIG. 15 is a timing chart when forward scanning is performed, and FIG. 16 is a timing chart when backward scanning is performed.

<2.3.2.1 Operation during forward scanning>
The overall operation of the shift register 411 when forward scanning is performed will be described. During the operation of the liquid crystal display device, the shift register 411 has a first gate clock signal GCK2 having a waveform as shown in FIG. 15A and a second gate clock signal GCK2 having a waveform as shown in FIG. , A third gate clock signal GCK3 having a waveform as shown in FIG. 15C and a fourth gate clock signal GCK4 having a waveform as shown in FIG.

  In the period before time td, the same operation as in the first embodiment is performed. At time td, the third gate clock signal GCK3 changes from the low level to the high level. At this time, since the potential of the input terminal 45 changes from the low level to the high level in the third stage SR (3), the potential of netA in the third stage SR (3) further increases. As a result, during the period from td to te, the scanning signal GOUT (3) output from the third stage SR (3) becomes high level. Then, based on the scanning signal GOUT (3) set to the high level, the potential of the netA of the first stage (1) changes from the high level to the low level, and the potential of the netA of the second stage SR (2) is high. The potential of netA of the fourth stage SR (4) changes from the low level to the high level, and the potential of netA of the fifth stage SR (5) is maintained at the low level.

  At time te, the fourth gate clock signal GCK4 changes from the low level to the high level. At this time, since the potential of the input terminal 45 changes from the low level to the high level in the fourth stage SR (4), the potential of netA in the fourth stage SR (4) further increases. As a result, during the period from te to tf, the scanning signal GOUT (4) output from the fourth stage SR (4) becomes high level. Then, based on the scanning signal GOUT (4) set to the high level, the potential of the netA of the second stage (2) changes from the high level to the low level, and the potential of the netA of the third stage SR (3) is high. The potential of netA of the fifth stage SR (5) changes from the low level to the high level, and the potential of netA of the sixth stage SR (6) is maintained at the low level.

  As described above, the scanning signals GOUT (1) to GOUT (8) sequentially become high level for each horizontal scanning period from the first stage SR (1) to the eighth stage SR (8). Then, during the period after time tj, the same operation as in the first embodiment is performed.

<2.3.2.2 Operation during reverse scanning>
Next, the operation of the entire shift register 410 when reverse scanning is performed will be described. During the operation of the liquid crystal display device, the shift register 411 has a first gate clock signal GCK2 having a waveform as shown in FIG. 16A and a second gate clock signal GCK2 having a waveform as shown in FIG. , A third gate clock signal GCK3 having a waveform as shown in FIG. 16C and a fourth gate clock signal GCK4 having a waveform as shown in FIG.

  In the period before the time point tb, the same operation as in the first embodiment is performed. At time tb, the fourth gate clock signal GCK4 changes from the low level to the high level. At this time, since the potential of the input terminal 45 changes from the low level to the high level in the eighth stage SR (8), the potential of netA of the eighth stage SR (8) further increases. As a result, during the period from tb to tc, the scanning signal GOUT (8) output from the eighth stage SR (8) becomes high level.

  At time tc, the fourth gate clock signal GCK4 changes from the high level to the low level. As a result, the potential of netA of the eighth stage SR (8) decreases. At the time tc, the third gate clock signal GCK3 changes from the low level to the high level. At this time, since the potential of the input terminal 48 changes from the low level to the high level at the eighth stage SR (8), the scanning signal GOUT (8) output from the eighth stage SR (8) is low. Become a level. Further, since the third gate clock signal GCK3 is supplied as the first clock CKA to the seventh stage SR (7), the third stage clock signal GCK3 changes to the high level, so that the seventh stage SR (7). The netA potential further rises, and during the period from tc to td, the scanning signal GOUT (7) output from the seventh stage SR (7) becomes high level.

  At time td, the second gate clock signal GCK2 changes from low level to high level. At this time, since the potential of the input terminal 45 changes from the low level to the high level in the sixth stage SR (6), the potential of netA of the sixth stage SR (6) further increases. As a result, during the period from td to te, the scanning signal GOUT (6) output from the sixth stage SR (6) is at a high level. Then, based on the scanning signal GOUT (6) set to the high level, the potential of the netA at the eighth stage (8) changes from the high level to the low level, and the potential of the netA at the seventh stage SR (7) is high. The potential of netA of the fifth stage SR (5) changes from the low level to the high level, and the potential of netA of the fourth stage SR (4) is maintained at the low level.

  As described above, the scanning signals GOUT (8) to GOUT (1) sequentially become high level for each horizontal scanning period from the eighth stage SR (8) to the first stage SR (1). Then, during the period after time tj, the same operation as in the first embodiment is performed.

<2.4 Effect>
According to the present embodiment, as in the first embodiment, when realizing a shift register capable of switching the scanning order of the gate bus lines GL1 to GLn, it is possible to suppress an increase in circuit area, an increase in current consumption, Cost increase can be suppressed. Further, the occurrence of malfunction due to the shift of the threshold voltage of the switch (transistor) during high temperature aging is suppressed.

  Furthermore, according to the present embodiment, the occurrence of malfunction due to the rounding of the pulse of the scanning signal GOUT based on the wiring capacitance and wiring resistance is suppressed. This will be described below. When the shift register operates with a two-phase clock signal as in the first embodiment, for example, the first reset signal RESET1 (scanning signal output from the next stage of each stage) at time t4 in FIG. When the pulse is rounded, the potential of netA is at the high level at time t4. Therefore, the potential of the output terminal 61 rises when the first clock CKA changes from the low level to the high level. In addition, since the capacitor C1 is provided between the netA and the output terminal 61, the potential of the netA increases as the potential of the output terminal 61 increases. In this way, until the pulse of the first reset signal RESET1 rises, the potential of netA does not decrease to the low level even after time t4, and an abnormal pulse is output from the output terminal 61. On the other hand, according to the present embodiment, the shift register operates with a four-phase clock signal, and the first clock CKA is maintained at a low level at time t4 in FIG. For this reason, even if the pulse of the first reset signal RESET1 occurs at time t4, the potential of the output terminal 61 is maintained at a low level, and the potential of netA does not rise via the capacitor C1. Then, at the time when the pulse of the first reset signal RESET1 rises, the potential of netA is set to the low level. As a result, the occurrence of malfunction due to the rounding of the pulse of the scanning signal GOUT is suppressed.

  Furthermore, according to the present embodiment, the ON duty (ratio of the period in which the transistor is on) of the thin film transistor (for example, the thin film transistor T10) that is controlled to be turned on / off by the clock signal is 25%. Thus, since the ON duty is halved compared to the first embodiment, the threshold voltage shift of the thin film transistor is suppressed.

<2.5 Modification>
In the second embodiment, the shift register operates with a four-phase clock signal. However, the number of phases of the clock signal supplied to the shift register may be three. Five or more phases may be used. Moreover, the structure which does not have capacitor C1 and thin-film transistor T10, T11, T12 may be sufficient.

<3. Third Embodiment>
<3.1 Overall configuration and gate driver configuration>
In the present embodiment, the overall configuration, the schematic configuration of the gate driver, and the configuration of the shift register are the same as those in the first embodiment shown in FIGS.

<Configuration of bistable circuit>
FIG. 17 is a circuit diagram showing a configuration of a bistable circuit in the present embodiment. In the present embodiment, in addition to the components in the first embodiment shown in FIG. 1, three thin film transistors T5 (fifth switching element), T6 (sixth switching element), and T7 (first switching element) are provided. 7) and an input terminal 49 for receiving the second clock CKB. Note that the input terminal 46 and the input terminal 49 may be the same terminal (one terminal). The source terminal of the thin film transistor T6, the drain terminal of the thin film transistor T7, and the gate terminal of the thin film transistor T5 are connected to each other. A region (wiring) in which these are connected to each other is referred to as “netB” (second node) for convenience.

  As for the thin film transistor T5, the gate terminal is connected to netB, the drain terminal is connected to netA, and the source terminal is connected to the power supply voltage VSS. As for the thin film transistor T6, the gate terminal and the drain terminal are connected to the input terminal 49 (that is, diode connection), and the source terminal is connected to netB. As for the thin film transistor T7, the gate terminal is connected to netA, the drain terminal is connected to netB, and the source terminal is connected to the power supply voltage VSS. Accordingly, the circuit indicated by reference numeral 70 in FIG. 17 is an AND circuit that outputs a logical product of the logically inverted signal of the signal indicating the potential of netA and the second clock CKB. In the present embodiment, a second node control unit is realized by this AND circuit.

  The thin film transistor T5 sets the potential of netA to a low level when the potential of netB is at a high level. The thin film transistor T6 sets the potential of netB to high level when the second clock CKB is at high level. The thin film transistor T7 sets the potential of netB to a low level when the potential of netA is at a high level. From the above, when the potential of the first node is at a low level and the second clock CKB is at a high level, the potential of netA is set to a low level.

<3.3 Shift register operation>
Next, the operation of each stage (bistable circuit) of the shift register in the present embodiment will be described with reference to FIGS. 17, 18, and 19. FIG. FIG. 18 is a timing chart when the forward scanning is performed, and FIG. 19 is a timing chart when the backward scanning is performed. Since the operation of the entire shift register is the same as that of the first embodiment, description thereof is omitted.

<3.3.1 Operation during forward scanning>
In the period before time t1, the same operation as in the first embodiment is performed except that the potential of netB becomes high level every other horizontal scanning period and the thin film transistor T5 is turned on. At time t1, a pulse of the first set signal SET1 is given to the input terminal 41. As a result, as in the first embodiment, the potential of netA changes from the low level to the high level, and the thin film transistor TS is turned on. As in the first embodiment, the scanning signal GOUT is maintained at a low level during the period from t1 to t2. By the way, in this embodiment, the gate terminal of the thin film transistor T7 is connected to netA. For this reason, when the potential of netA becomes high level, the thin film transistor T7 is turned on. Accordingly, since the potential of netB becomes low level, the thin film transistor T5 is turned off. Therefore, during the period from t1 to t2, “the thin film transistor T5 is turned on and the potential of the netA is not lowered”.

  At time t2, the first clock CKA changes from the low level to the high level. As a result, as in the first embodiment, the potential of netA increases. Then, the potential of the scanning signal GOUT rises to the high level potential of the first clock CKA, and the gate bus line connected to the output terminal 61 of this bistable circuit is selected. By the way, since the potential of netA is at a high level from the time point t1, the thin film transistor T7 is maintained in the on state. Further, since the second clock CKB is at a low level during the period from t2 to t3, the thin film transistor T6 is in an off state. Therefore, during the period from t2 to t3, the potential of netB is at a low level, and the thin film transistor T5 is turned off. Therefore, during the period from t2 to t3, “the thin film transistor T5 is turned on and the potential of the netA is not lowered”.

  At time t3, as in the first embodiment, the potential of the scanning signal GOUT becomes a low level. The netA potential is maintained at a high level although it is lower than the period from t2 to t3. Therefore, the thin film transistor T7 is turned on during the period from t3 to t4. Accordingly, since the potential of netB becomes low level, the thin film transistor T5 is turned off. Therefore, during the period from t3 to t4, “the thin film transistor T5 is turned on and the potential of the netA is not lowered”.

  In the period after time t4, the same operation as in the first embodiment is performed except that the potential of netB becomes high level every other horizontal scanning period and the thin film transistor T7 is turned on.

<3.3.2 Operation during reverse scanning>
In the period before time t1, the same operation as in the first embodiment is performed except that the potential of netB becomes high level every other horizontal scanning period and the thin film transistor T5 is turned on. At time t1, a pulse of the second set signal SET2 is given to the input terminal. As a result, as in the first embodiment, the potential of netA changes from the low level to the high level, and the thin film transistor TS is turned on. As in the first embodiment, the scanning signal GOUT is maintained at a low level during the period from t1 to t2. Similarly to the forward scanning, during the period from t1 to t2, the “thin film transistor T5 is turned on and the potential of netA does not decrease”.

  At time t2, the first clock CKA changes from the low level to the high level. As a result, as in the first embodiment, the potential of netA increases. Then, the potential of the scanning signal GOUT rises to the high level potential of the first clock CKA, and the gate bus line connected to the output terminal 61 of this bistable circuit is selected. Further, the potential of netA is at a high level from time t1, and as in the case of forward scanning, during the period from t2 to t3, “the thin film transistor T5 is turned on and the potential of netA decreases”. There is nothing.

  At time t3, as in the first embodiment, the potential of the scanning signal GOUT becomes a low level. The netA potential is maintained at a high level although it is lower than the period from t2 to t3. Therefore, as in the case of forward scanning, during the period from t3 to t4, there is no case that “the thin film transistor T5 is turned on and the potential of the netA is lowered”. In the period after time t4, the same operation as in the first embodiment is performed except that the potential of netB becomes high level every other horizontal scanning period and the thin film transistor T5 is turned on.

<3.4 Effects>
According to the present embodiment, the potential of netB becomes a high level every other horizontal scanning period in the period before the time t0 and the period after the time t5 in both the forward scanning and the backward scanning. . Therefore, in the period, the thin film transistor T5 is turned on every other horizontal scanning period. Thereby, for example, even when the threshold voltage of the thin film transistor TS is shifted due to high temperature aging and the leakage current in the thin film transistor TS becomes large, the potential of the netA is reliably set to the low level every other horizontal scanning period, and the output terminal 61 The output of abnormal pulses from is suppressed. In addition, the occurrence of an abnormal operation of the shift register due to the sequential application of such abnormal pulses to the subsequent stage is suppressed.

<3.5 Modification>
In addition to the structure shown in FIG. 17, a structure may be provided that includes a thin film transistor that sets the potential of netB to a low level when the first clock CKA is at a high level (see FIG. 23 described later). Thereby, the potential of netB is reliably set to the low level during the period when the first clock CKA is at the high level, so that the threshold voltage shift of the thin film transistor T5 is suppressed.

<4. Fourth Embodiment>
<4.1 Overall configuration and gate driver configuration>
In the present embodiment, the overall configuration and the schematic configuration of the gate driver are the same as those in the second embodiment, and a description thereof will be omitted.

<4.2 Bistable circuit configuration>
FIG. 20 is a circuit diagram showing a configuration of the bistable circuit in the present embodiment. The configuration in the present embodiment is a configuration in which the configuration in the second embodiment shown in FIG. 12 and the configuration in the third embodiment shown in FIG. 17 are substantially combined. However, in addition to the components in the second embodiment and the third embodiment, a thin film transistor T8 (eighth switching element) and an input terminal 50 for receiving the fourth clock CKD are provided. As for the thin film transistor T8, the gate terminal and the drain terminal are connected to the input terminal 50 (that is, diode connection), and the source terminal is connected to netB. The thin film transistor T8 sets the potential of netB to a high level when the fourth clock CKD is at a high level. In the present embodiment, the second node control unit is realized by a circuit indicated by reference numeral 71 in FIG. Note that the input terminal 48 and the input terminal 50 may be the same terminal (one terminal).

<4.3 Shift register operation>
Next, the operation of each stage (bistable circuit) of the shift register in the present embodiment will be described with reference to FIGS. 20, 21, and 22. FIG. FIG. 21 is a timing chart when forward scanning is performed, and FIG. 22 is a timing chart when backward scanning is performed. In the present embodiment, four-phase clock signals (first clock CKA, second clock CKB, third clock CKC, and fourth clock CKD) are provided to the bistable circuit as in the second embodiment. For this reason, the same operation as that of the second embodiment is performed during the period from t0 to t5 in both the forward scanning and the backward scanning. In the present embodiment, a thin film transistor T6 for setting the potential of netB to a high level based on the second clock CKB and a thin film transistor T8 for setting the potential of netB to a high level based on the fourth clock CKD are provided. It has been. For this reason, in both the forward scanning and the backward scanning, the potential of netB becomes high every other horizontal scanning period in the period before time t0 and the period after time t5.

<4.4 Effects>
According to the present embodiment, as in the first embodiment, when realizing a shift register capable of switching the scanning order of the gate bus lines GL1 to GLn, it is possible to suppress an increase in circuit area, an increase in current consumption, Cost increase can be suppressed. Further, the occurrence of malfunction due to the shift of the threshold voltage of the switch (transistor) during high temperature aging is suppressed. Further, as in the second embodiment, a threshold voltage shift is caused for a thin film transistor in which on / off control is performed by the occurrence of a malfunction due to the pulse rounding of the scanning signal GOUT based on the wiring capacitance or the wiring resistance or the clock signal. Is suppressed. Furthermore, as in the third embodiment, the output of the abnormal pulse from the output terminal 61 and the occurrence of the abnormal operation of the shift register due to the sequential application of such an abnormal pulse to the subsequent stage are suppressed.

<4.5 Modification>
FIG. 23 is a circuit diagram showing a configuration of a bistable circuit in a modification of the fourth embodiment. In this modification, a thin film transistor T9 (9th switching element) is provided in addition to the components in the fourth embodiment shown in FIG. As for the thin film transistor T9, the gate terminal is connected to the input terminal 45, the drain terminal is connected to netB, and the source terminal is connected to the power supply voltage VSS. The thin film transistor T9 sets the potential of netB to a low level when the first clock CKA is at a high level.

  In the fourth embodiment, the period other than the period in which the second clock CKB or the fourth clock CKD is at the high level among the period before the time t0 and the period after the time t5 (see FIGS. 21 and 22). The netB is in a floating state. On the other hand, according to the present modification, the potential of netB is reliably set to the low level during the period when the first clock CKA is at the high level. For this reason, the shift of the threshold voltage of the thin film transistor T5 whose gate terminal is connected to netB is suppressed. In order to further enhance such an effect, a structure may be provided that includes a thin film transistor for setting the potential of netB to a low level when the third clock CKC is at a high level.

<5. Fifth Embodiment>
<5.1 Overall configuration and gate driver configuration>
In the present embodiment, the overall configuration and the schematic configuration of the gate driver are substantially the same as those in the first embodiment shown in FIGS. However, in the first embodiment, the first gate end pulse signal GEP1 and the second gate end pulse signal GEP2 are sent from the display control circuit 20 to the gate driver as signals for ending the scanning of the gate bus lines GL1 to GLn. In contrast, in the present embodiment, only one gate end pulse signal GEP is sent from the display control circuit 20 to the gate driver 40 as a signal for ending the scanning of the gate bus lines GL1 to GLn.

  FIG. 24 is a block diagram showing a configuration of the shift register 412 in the gate driver 40 in the present embodiment. As shown in FIG. 24, the shift register 412 includes eight bistable circuits SR (1) to SR (8). Each bistable circuit has an input terminal for receiving the two-phase clock signals CKA and CKB, an input terminal for receiving the low-level power supply voltage VSS, and an input terminal for receiving the first set signal SET1. An input terminal for receiving the second set signal SET2, an input terminal for receiving the first reset signal RESET1, an input terminal for receiving the second reset signal RESET2, and a scanning signal GOUT. And an output terminal. The configuration of each stage (bistable circuit) of the shift register 412 is the same as the configuration in the first embodiment shown in FIG.

  In the first embodiment, as shown in FIG. 4, the first gate end pulse signal GEP1 is given to the eighth stage SR (8) as the first reset signal RESET1, and the second gate end pulse The signal GEP2 was given to the first stage SR (1) as the second reset signal RESET2. On the other hand, in the present embodiment, as shown in FIG. 24, the gate end pulse signal GEP is given to the eighth stage SR (8) as the first reset signal RESET1, and the first stage as the second reset signal RESET2. Given to the eye SR (1).

<5.2 Shift register operation>
Next, the operation of the entire shift register 412 in this embodiment will be described. FIG. 25 is a timing chart when forward scanning is performed, and FIG. 26 is a timing chart when backward scanning is performed. In the present embodiment, the same operation as that of the first embodiment is performed in the period before the time tk, both in the forward scan and in the reverse scan. At time tk, as shown in FIGS. 25 (c) and 26 (c), a pulse of the gate end pulse signal GEP is generated. When forward scanning is performed, the netA potential of the eighth stage (final stage) SR (8) is set to a low level by the pulse of the gate end pulse signal GEP. When reverse scanning is performed, the potential of netA of the first stage SR (1) is set to a low level by the pulse of the gate end pulse signal GEP.

<5.3 Effects>
According to the present embodiment, only one gate end pulse signal GEP is provided as a signal for ending the scanning of the gate bus lines GL1 to GLn. For this reason, compared with the first embodiment, signal wiring is reduced, and signals to be generated by the display control circuit 20 are reduced. Thereby, effects such as a reduction in circuit area, a reduction in current consumption, and a reduction in cost are further enhanced.

<6. Other>
In the above embodiments, the liquid crystal display device has been described as an example, but the present invention is not limited to this. The present invention can also be applied to other display devices such as an organic EL (Electro Luminescence) as long as it has a shift register that can switch the scanning order of the gate bus lines.

DESCRIPTION OF SYMBOLS 10 ... Display part 20 ... Display control circuit 30 ... Source driver (video signal line drive circuit)
40. Gate driver (scanning signal line driving circuit)
41-50 (input terminal of bistable circuit) 61 ... output terminal (of bistable circuit) 410-412 ... shift register SR (1) -SR (n) ... bistable circuit TS, T1-T12 ... thin film transistor C1 ... Capacitors GL1 to GLn ... Gate bus lines SL1 to SLm ... Source bus lines GSP1 ... First gate start pulse signal GSP2 ... Second gate start pulse signal GEP ... Gate end pulse signal GEP1 ... First gate end pulse signal GEP2 ... Second gate end pulse signal GCK1... First gate clock signal GCK2... Second gate clock signal CKA, CKB, CKC, CKD... First clock, second clock, third clock, fourth clock GOUT (1) ... GOUT (n)... Scanning signal SET1... First set signal S T2 ... the second of the set signal RESET1 ... the first reset signal RESET2 ... the second reset signal

Claims (20)

A plurality of bistable circuits having a first state and a second state and connected in series with each other, wherein a high-level potential and a low-level potential supplied from outside each bistable circuit are periodically A shift register in which the plurality of bistable circuits sequentially enter a first state based on at least two-phase clock signals including first and second clock signals to be repeated;
Each bistable circuit is
An output node that outputs a state signal representing either the first state or the second state;
An output control switching element in which the first clock signal is applied to a second electrode, and a third electrode is connected to the output node;
A first first-node charging unit for charging a first node connected to the first electrode of the output control switching element based on a state signal output from a bistable circuit preceding the bistable circuit. When,
A second first-node charging unit for charging the first node based on a state signal output from a bistable circuit subsequent to the bistable circuit;
A first first-node discharge unit for discharging the first node based on a state signal output from the bistable circuit of the next stage of each bistable circuit;
A shift register comprising: a second first node discharging unit for discharging the first node based on a state signal output from a bistable circuit preceding the bistable circuit; . In the first stage bistable circuit among the plurality of bistable circuits,
The first first node charging unit charges the first node based on a first scanning start signal given from the outside instead of the state signal output from the bistable circuit in the previous stage,
The second first node discharge unit discharges the first node based on a predetermined signal given from the outside instead of the state signal output from the bistable circuit of the preceding stage,
In the second stage bistable circuit among the plurality of bistable circuits,
The second first node discharge unit discharges the first node based on a predetermined signal given from the outside instead of the state signal output from the bistable circuit of the preceding stage,
Among the plurality of bistable circuits, in the bistable circuit in the previous stage of the final stage,
The first first node discharge unit discharges the first node based on a predetermined signal given from the outside instead of the state signal output from the bistable circuit of the next stage,
In the last stage bistable circuit among the plurality of bistable circuits,
The second first node charging unit charges the first node based on a second scanning start signal supplied from the outside instead of the state signal output from the next stage bistable circuit,
The first first node discharge unit discharges the first node based on a predetermined signal given from the outside instead of a state signal output from a bistable circuit of the next stage. Item 4. The shift register according to Item 1. In each bistable circuit,
In the first first-node charging unit, a state signal output from a bistable circuit preceding the bistable circuit is supplied to the first electrode and the second electrode, and a third electrode is connected to the first node. Including a first switching element
In the second first node charging unit, a state signal output from a bistable circuit next to the bistable circuit is provided to the first electrode and the second electrode, and a third electrode is provided to the first node. Including a connected second switching element;
In the first first-node discharge unit, a state signal output from a bistable circuit subsequent to each bistable circuit is supplied to a first electrode, a second electrode is connected to the first node, A third switching element in which a low-level potential is applied to the three electrodes;
In the second first node discharge unit, a state signal output from the bistable circuit preceding the bistable circuit is supplied to the first electrode, the second electrode is connected to the first node, The shift register according to claim 1, further comprising a fourth switching element in which a low-level potential is applied to the third electrode. Each bistable circuit is
A fifth switching element having a second electrode connected to the first node and a low-level potential applied to the third electrode;
A second node control unit configured to control a potential of a second node connected to the first electrode of the fifth switching element based on the second clock signal and the potential of the first node; The shift register according to claim 1, wherein the shift register is characterized by the following. The second node controller is
A sixth switching element in which the second clock signal is applied to the first electrode and the second electrode, and a third electrode is connected to the second node;
A seventh switching element in which a logic inversion signal of a signal indicating the potential of the first node is applied to the first electrode, a second electrode is connected to the second node, and a low-level potential is applied to the third electrode; The shift register according to claim 4, comprising:   The second node control unit includes a ninth switching element in which the first clock signal is applied to a first electrode, the second electrode is connected to the second node, and a low-level potential is applied to a third electrode. The shift register according to claim 5, further comprising:   The plurality of bistable circuits further receive a third clock signal as a signal which is given from outside each bistable circuit and periodically repeats a high level potential and a low level potential, and the first clock signal and 7. The first state according to claim 1, wherein the first state is sequentially set based on at least three-phase clock signals including the second clock signal and the third clock signal. The shift register according to item 1. The plurality of bistable circuits further receive a third clock signal and a fourth clock signal as a signal which is given from the outside of each bistable circuit and periodically repeats a high level potential and a low level potential, The first state is sequentially set based on a four-phase clock signal including the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal,
The first clock signal and the third clock signal are 180 degrees out of phase, the second clock signal and the fourth clock signal are 180 degrees out of phase, and the first clock signal 4. The shift register according to claim 1, wherein phases of the second clock signal and the second clock signal are shifted by 90 degrees. 5. Each bistable circuit is
A fifth switching element having a second electrode connected to the first node and a low-level potential applied to the third electrode;
Second node control for controlling the potential of the second node connected to the first electrode of the fifth switching element based on the second clock signal, the fourth clock signal, and the potential of the first node. The shift register according to claim 8, further comprising: The second node controller is
A sixth switching element in which the second clock signal is applied to the first electrode and the second electrode, and a third electrode is connected to the second node;
An eighth switching element in which the fourth clock signal is applied to the first electrode and the second electrode, and the third electrode is connected to the second node;
A seventh switching element in which a logic inversion signal of a signal indicating the potential of the first node is applied to the first electrode, a second electrode is connected to the second node, and a low-level potential is applied to the third electrode; The shift register according to claim 9, comprising:   In the second node control unit, the first clock signal or the third clock signal is supplied to a first electrode, the second electrode is connected to the second node, and a low-level potential is applied to the third electrode. The shift register according to claim 10, further comprising a ninth switching element provided. Each bistable circuit is
An eleventh switching element in which the third clock signal is applied to the first electrode, the second electrode is connected to the output node, and a low-level potential is applied to the third electrode;
A twelfth switching element having the fourth clock signal applied to the first electrode, the second electrode connected to the output node, and a low-level potential applied to the third electrode; The shift register according to any one of claims 8 to 11.   Each bistable circuit further includes a tenth switching element in which the second clock signal is applied to the first electrode, the second electrode is connected to the output node, and a low-level potential is applied to the third electrode. The shift register according to any one of claims 1 to 12, characterized in that:   The second first node discharge unit of the first stage bistable circuit of the plurality of bistable circuits and the first first node discharge unit of the last stage bistable circuit of the plurality of bistable circuits The shift register according to any one of claims 1 to 13, wherein the first node is discharged based on the same signal.   15. The bistable circuit according to claim 1, further comprising a capacitor having one end connected to the first node and the other end connected to the output node. 15. Shift register.   The shift register according to claim 1, wherein the shift register is formed using amorphous silicon.   The shift register according to claim 1, wherein the shift register is formed using microcrystalline silicon.   The shift register according to any one of claims 1 to 15, wherein the shift register is formed using polycrystalline silicon. A scanning signal line driving circuit for a display device for driving a plurality of scanning signal lines arranged in a display unit,
A shift register according to any one of claims 1 to 18, comprising:
The plurality of bistable circuits are provided in one-to-one correspondence with the plurality of scanning signal lines,
Each bistable circuit supplies a state signal output from the output node as a scanning signal to a scanning signal line corresponding to each bistable circuit.   A display device comprising the display unit and the scanning signal line driving circuit according to claim 19.

Images