KR101641446B1 - Display device - Google Patents

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Publication number
KR101641446B1
KR101641446B1 KR1020147023232A KR20147023232A KR101641446B1 KR 101641446 B1 KR101641446 B1 KR 101641446B1 KR 1020147023232 A KR1020147023232 A KR 1020147023232A KR 20147023232 A KR20147023232 A KR 20147023232A KR 101641446 B1 KR101641446 B1 KR 101641446B1
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KR
South Korea
Prior art keywords
potential
electrode
signal
node
control node
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KR1020147023232A
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Korean (ko)
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KR20140140019A (en
Inventor
야스시 사사키
유이치로 무라카미
다카히로 야마구치
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샤프 가부시키가이샤
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Priority to JP2012080597 priority Critical
Priority to JPJP-P-2012-080597 priority
Application filed by 샤프 가부시키가이샤 filed Critical 샤프 가부시키가이샤
Priority to PCT/JP2013/055336 priority patent/WO2013146058A1/en
Publication of KR20140140019A publication Critical patent/KR20140140019A/en
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Publication of KR101641446B1 publication Critical patent/KR101641446B1/en

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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3674Details of drivers for scan electrodes
    • G09G3/3677Details of drivers for scan electrodes suitable for active matrices only
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores
    • G11C19/28Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores using semiconductor elements
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243Details of the generation of driving signals
    • G09G2310/0245Clearing or presetting the whole screen independently of waveforms, e.g. on power-on
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/0286Details of a shift registers arranged for use in a driving circuit
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/02Improving the quality of display appearance
    • G09G2320/0257Reduction of after-image effects
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02Details of power systems and of start or stop of display operation
    • G09G2330/021Power management, e.g. power saving
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02Details of power systems and of start or stop of display operation
    • G09G2330/025Reduction of instantaneous peaks of current
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04Display protection

Abstract

A display device capable of performing the entire selection drive of the gate bus line without lowering the reliability of the breakdown voltage without increasing the number of circuit elements compared to the conventional one is realized. In the single-stage circuit constituting the shift register in the gate driver, the thin film transistor Tr4 and the scanning signal OUT for lowering the QB node provided for setting the scanning signal OUT to the low level are set to the high level The entire selection signal ALL-ON for simultaneously selecting all the gate bus lines as a low potential power supply is applied to the source terminal of the thin film transistor Tr3 for setting the Q node provided for setting the Q node to the low level do. Wiring (ALL-ON wiring) for supplying a low potential power to the gate driver and wiring (VSS wiring) for supplying a low potential power to circuits other than the gate driver are independent power supply lines.

Description

 Display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a display device having a function of making all scan signal lines active at the same time.

In general, an active matrix type liquid crystal display device is provided with a liquid crystal panel including two substrates for holding a liquid crystal layer therebetween. One of the two substrates is provided with a plurality of gate bus lines (scanning signal lines) A plurality of pixel forming portions arranged in a matrix form corresponding to the intersections of the plurality of gate bus lines and the plurality of source bus lines are provided. Each pixel forming portion includes a thin film transistor (TFT), which is a switching element in which a gate terminal is connected to a gate bus line passing through a corresponding intersection and a source terminal is connected to a source bus line passing through the intersection, And the like. A common electrode, which is an opposing electrode provided in common to the plurality of pixel defining portions, is provided on the other of the two substrates. The active matrix type liquid crystal display device further includes a gate driver (scanning signal line driver circuit) for driving the plurality of gate bus lines and a source driver (video signal line driver circuit) for driving the plurality of source bus lines.

The video signal representing the pixel value is transmitted by the source bus line but each source bus line can not transmit the video signal representing the pixel value of the multiple times at the same time. As a result, the writing of the video signals into the pixel capacities in the pixel forming section arranged in the above-mentioned matrix shape is sequentially performed one row at a time. Therefore, the gate driver is composed of a plurality of stages of shift registers so that a plurality of gate bus lines are sequentially selected for predetermined periods. By sequentially outputting active scanning signals from the respective stages of the shift register (hereinafter, the circuit constituting each stage of the shift register is also referred to as a " stage constituent circuit "), The writing of the video signal of one row is sequentially performed.

In such a liquid crystal display device, although the power is turned off by the user, the display is not immediately cleared and an image such as a residual image may remain. This is because when the power supply of the apparatus is turned off, the discharge path of the charge held in the pixel capacitance is cut off, and the residual charge is accumulated in the pixel forming portion. Further, when the power of the apparatus is turned on in the state where the residual charge is accumulated in the pixel forming portion, flicker due to the deflection of the impurity based on the residual charge is generated, and the display quality is lowered.

Accordingly, a liquid crystal display device has been proposed in which all the gate bus lines are made to be in the selected state (active state) when the power supply is turned off or the power supply is turned on, thereby discharging the residual charges in all the pixel forming portions (refer to International Publication No. 2009/028353 ). The drive for selecting all gate bus lines is hereinafter referred to as " all selection drive ".

In the liquid crystal display device disclosed in the pamphlet of International Publication WO2009 / 028353, the schematic structure of the gate driver is as shown in Fig. The gate driver is constituted by a shift register composed of a plurality of stages as described above. 16 shows the single-ended circuits SR (n-1) to SR (n + 2) from the (n-1) th stage to the (n + 2) th stage. The set signal S, the reset signal R, the clock signal CK (one of the first gate clock signal GCK1 and the second gate clock signal GCK2), and the entire selection signal ALL-ON are input to each stage circuit. The set signal S is a signal for making the constituent circuit active, and the reset signal R is a signal for making the constituent circuit inactive. Further, the scanning signal OUT is outputted from each of the single-stage circuits. The scan signal OUT output from each stage circuit is applied not only to the corresponding gate bus line but also to the stage circuit of the next stage as a set signal S as shown in Fig. As a reset signal R. That is, the high-level scanning signal outputted from each of the single-stage circuits makes the single-stage circuit of the next stage active and deactivates the single-stage circuit of the previous stage. The schematic configuration of the single-stage circuit is as shown in Fig. In the logic section, two signals (referred to as " Q signal " and " QB signal " for convenience) are generated. The Q signal controls the state of the switch SW1 in the output section, and the QB signal controls the state of the switch SW2 in the output section. From the output section, the scanning signal OUT is outputted in accordance with the state of the switch SW1, the switch SW2, the clock signal CK, and the entire selection signal ALL-ON.

In the above configuration, in a normal state, the entire selection signal ALL-ON is held at a low level (see FIG. 18). In normal operation, when the single-stage circuit is inactive, the Q signal is at the low level and the QB signal is at the high level. As a result, the switch SW1 is in the OFF state and the switch SW2 is in the ON state, so that the scanning signal OUT becomes low level. On the other hand, at the time of normal operation, when the single-stage circuit is active, the Q signal is at a high level and the QB signal is at a low level. As a result, the switch SW1 is in an ON state and the switch SW2 is in an OFF state, so that during a period in which the clock signal CK is at a high level, the scanning signal OUT becomes a high level. As described above, in the normal state, by giving the clock signal (the first gate clock signal GCK1 and the second gate clock signal GCK2) having the waveform shown in Fig. 18 to the gate driver, The scanning signals output from the single-stage circuit are sequentially set to the high level for a predetermined period of time. When the switch SW1 is in the OFF state and the switch SW2 is in the ON state, when the entire selection signal ALL-ON becomes the high level, the scanning signal OUT outputted from this single-stage circuit becomes the high level. Therefore, when the entire selection drive is desired, by setting the entire selection signal ALL-ON to the high level, all the scanning signals can be set to the high level as shown in Fig. 18 in the state in which the respective stage constituent circuits are inactive . In this manner, the residual charge in all the pixel defining portions in the display portion is removed.

International Publication No. 2009/028353

According to the related art, when the entire selection drive is performed, a voltage exceeding the breakdown voltage (the limit voltage which does not cause the insulation breakdown) is applied to the thin film transistor in the single-phase circuit, and reliability is lowered in some cases. This will be described below.

19 is a diagram showing a configuration example of a conventional stage configuration circuit. This single-stage circuit includes six thin film transistors Tr91 to Tr96. The single-stage circuit has four input terminals 91 to 94 and one output terminal 99 in addition to the high-potential power supply input terminal. Reference numeral 91 is assigned to an input terminal for receiving the entire selection signal ALL-ON, reference numeral 92 is assigned to an input terminal for receiving the clock signal CK, reference numeral 93 is assigned to an input terminal for receiving the set signal S, An input terminal for receiving R is indicated by reference numeral 94. The region (wiring) where the source terminal of the thin film transistor Tr91, the drain terminal of the thin film transistor Tr93, and the gate terminal of the thin film transistor Tr95 are connected to each other is referred to as a "Q node" for convenience's sake. The region (wiring) where the source terminal of the thin film transistor Tr92, the gate terminal of the thin film transistor Tr93, the drain terminal of the thin film transistor Tr94, and the gate terminal of the thin film transistor Tr96 are connected to each other is referred to as a "QB node" for convenience.

Referring to Part A of FIG. 19 and FIG. 20, the operation of the conventional single-stage circuit at normal time will be described. It is assumed that the period from time t3 to time t4 in Fig. 20 is a period during which the gate bus line connected to this single-stage circuit should be selected. It is also assumed that the first gate clock signal GCK1 is applied to the input terminal 92 of the single-stage circuit.

During the period before time t1, the potential of the Q node is maintained at a low level, and the potential of the QB node is maintained at a high level. When the set signal S changes from the low level to the high level at time point t1, the thin film transistors Tr91 and Tr94 are turned on. As the thin film transistor Tr91 is turned on, the potential of the Q node changes from the low level to the high level. Further, when the thin film transistor Tr94 is turned on, the potential of the QB node changes from high level to low level.

The first gate clock signal GCK1 changes from the low level to the high level when the set signal S changes from the high level to the low level at the time point t2 and then reaches the time point t3. At this time, since the thin film transistor Tr95 is turned on, the potential of the output terminal 99 (potential of the scanning signal OUT) increases with the potential of the input terminal 92 rises. Since the parasitic capacitance exists between the gate and the source of the thin film transistor Tr95 and between the gate and the drain, the potential of the Q node rises (the Q node is bootstrapped) as the potential of the output terminal 99 rises. As a result, the potential of the Q node becomes "VDD x 2-Vth" (Vth is the threshold voltage of the thin film transistor Tr91). As a result, a large voltage is applied to the gate terminal of the thin film transistor Tr95 to generate a so-called threshold voltage drop (the source potential does not rise only up to a level lower than the drain potential by the threshold voltage) The potential of the terminal 99 rises to the high level of the first gate clock signal GCK1. In this manner, the gate bus line connected to the output terminal 99 of the single-stage circuit is in the selected state.

As described above, the potential of the Q node significantly rises by the bootstrap. As a result, a voltage exceeding the breakdown voltage may be applied between the drain and the source of the thin film transistor Tr93. Therefore, by providing the thin film transistor Tr97 between the gate terminal of the thin film transistor Tr95 and the drain terminal of the thin film transistor Tr93, the application of a voltage exceeding the breakdown voltage to the thin film transistor Tr93 is suppressed. This is because the potential of the node Q2 connected to the drain terminal of the thin film transistor Tr93 does not become higher than VDD even if the thin film transistor Tr97 functions as the voltage dividing means and the potential of the Q node becomes higher than VDD.

Next, the operation of the conventional single-stage circuit at the time of full selection driving will be described with reference to FIG. 19 and FIG. 20B. It is assumed that the period from time t11 to time t12 in FIG. 20 is a period during which all the gate bus lines are to be selected. During the period before the time point t11, the potential of the Q node is at the low level and the potential of the QB node is at the high level. At time t11, the entire selection signal ALL-ON changes from a low level to a high level. At this time, the potential of the QB node rises from VDD to "VDD x 2-Vth" due to the bootstrap caused by the parasitic capacitance of the thin film transistor Tr96. Thereby, a large voltage is applied to the gate terminal of the thin film transistor Tr96, so-called threshold voltage drop does not occur, and the potential of the output terminal 99 (potential of the scanning signal OUT) reaches the potential of the entire selection signal ALL- . This operation is performed in all the single-stage circuits, and all the gate bus lines are selected in the period from the time t11 to the time t12.

Since the potential of the source terminal of the thin film transistor Tr93 and the thin film transistor Tr94 is VSS, a voltage exceeding the breakdown voltage may be applied to the thin film transistor Tr93 or the thin film transistor Tr94 in the period from the time point t11 to the time point t12. When a voltage exceeding the breakdown voltage is applied to the thin film transistor in the single circuit, the reliability of the circuit is lowered. Therefore, it is considered that the thin film transistor Tr98 is provided between the gate terminal of the thin film transistor Tr96 and the drain terminal of the thin film transistor Tr94 as shown in Fig. However, since the number of circuit elements in the single circuit increases, it is difficult to downsize and reduce the cost.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to realize a display device capable of performing all selective driving of a gate bus line without decreasing the reliability of the breakdown voltage without increasing the number of circuit elements.

A first aspect of the present invention is a display device including a display section in which a plurality of scanning signal lines and a plurality of video signal lines are arranged, a scanning signal line driving circuit for driving the plurality of scanning signal lines, and a video signal line driving circuit for driving the plurality of video signal lines A display device comprising:

The display panel includes a first first potential supply line for supplying a first potential supply to the scanning signal line driving circuit and a second potential supply for supplying a first potential supply to a circuit other than the scanning signal line driving circuit A power line,

Wherein the scanning signal line driving circuit includes a plurality of stages of shift registers for sequentially outputting on-level scanning signals to the plurality of scanning signal lines based on a clock signal,

Wherein the single-stage circuit constituting each stage of the shift register comprises:

An output node connected to the scanning signal line,

An output control node for controlling the potential of the scanning signal output from the output node;

The potential of the output control node is changed toward the off level based on the potential of the first electrode to which the second electrode is connected to the output control node and the third electrode is connected to the first potential supply line A switching element for output control node turn-off

Lt; / RTI &

When the potential of the second potential power supply supplied to the scanning signal line driving circuit is higher than the potential of the first potential power supply supplied to the scanning signal line driving circuit, A potential higher than the potential of the potential power source can be applied,

When the potential of the second potential power supply supplied to the scanning signal line driving circuit is lower than the potential of the first potential power supply supplied to the scanning signal line driving circuit, A potential lower than the potential of the potential power source can be applied,

And the first first potential supply line and the second first potential supply line are independent power supply lines.

According to a second aspect of the present invention, in the first aspect of the present invention,

Wherein the single-stage circuit comprises:

An output for changing the potential of the output node toward the off level based on the potential of the first electrode, to which the second electrode is connected, and the third electrode is connected to the first first potential power supply line A switching element for turning off the node,

A first control node connected to the first electrode of the switching element for turning off the output node as the output control node,

A first control node turn-on section for changing the potential of the first control node toward an on level,

The first control node is connected to a second electrode, and the third electrode is connected to the first first potential power supply line, the potential of the first control node is set to the off level A first control node turn-off switching element as a switching element for turning off the output control node,

.

According to a third aspect of the present invention, in the second aspect of the present invention,

Wherein the single-stage circuit comprises:

An output node turn-on switching element for changing the potential of the output node toward the on level based on the potential of the first electrode, to which the clock signal is given to the second electrode and the third electrode is connected to the output node; ,

A second control node connected to the first electrode of the switching element for turning on the output node as the output control node,

A second control node turn-on section for changing the potential of the second control node toward the on level,

The second control node is connected to the second control node directly or through a voltage divider, and the third electrode is connected to the first first power supply line, and the second control node Off switching element for turning off the output of the second control node as the switching element for turning off the output control node

Lt; / RTI >

And the first electrode of the switching element for turning off the second control node is connected to the first control node.

According to a fourth aspect of the present invention, in the third aspect of the present invention,

The scanning signal line driving circuit is configured to be able to perform all selection driving for outputting an on-level scanning signal to all of the plurality of scanning signal lines,

An all-selection signal for controlling whether to perform the entire selection driving is given to the first potential supply line,

The second control node turn-on section included in the single-stage circuit changes the potential of the second control node toward the on level based on the start instruction signal or the scan signal output from the output node of the previous stage,

Wherein the start instruction signal or the scan signal output from the output node of the previous stage is applied to the first electrode of the first control node turn-off switching element included in the single-stage circuit,

The entire selection signal, the clock signal, and the start instruction signal are turned on at the time of the entire selection driving.

According to a fifth aspect of the present invention, in the third aspect of the present invention,

And the second electrode of the second control node turn-off switching element is connected to the second electrode, and the third electrode is connected to the second electrode of the output And a switching element for partial pressure connected to the first electrode of the switching element for node turn-on.

According to a sixth aspect of the present invention, in the third aspect of the present invention,

Wherein the shift register is configured to be switchable between an inverse sequence and a reverse sequence in which an on-level scan signal is given to the plurality of scan signal lines,

Wherein the single-stage circuit is provided with a switching control signal changing between an on-level and an off-level for switching a sequence of applying an on-level scanning signal to the plurality of scanning signal lines,

The second control node turn-on section included in the single-stage circuit includes:

The potential of the second control node is set at the on level (high level) based on the potential of the first electrode, to which the high potential power is applied to the second electrode, and the third electrode is connected to the second control node, A second switching element for turning on the control node for changing the voltage of the control node toward the second control node,

A fourth control node connected to the first electrode of the switching element for turning on the second control node,

And a second switching control element for switching control, to which the switching control signal is given to the first electrode, a scanning signal to be outputted from the output node of the other stage is given to the second electrode, and a third electrode is connected to the fourth control node and,

And a signal line for applying an off-level potential to the switching control signal is connected to the first potential supply line.

According to a seventh aspect of the present invention, in the sixth aspect of the present invention,

Wherein the first control node turn-on section included in the single-

A first control for changing the potential of the first control node toward the on level based on the potential of the first electrode to which the high potential power is applied to the second electrode and the third electrode is connected to the first control node A switching element for turning on the node,

A third control node connected to the first electrode of the switching element for turning on the first control node,

A first switching control element is provided with a switching control signal for the first electrode, a scanning signal outputted from the output node of the other stage is applied to the second electrode, and a third electrode is connected to the third control node .

According to an eighth aspect of the present invention, in the sixth or seventh aspect of the present invention,

The scanning signal line driving circuit is configured to be able to perform all selection driving for outputting an on-level scanning signal to all of the plurality of scanning signal lines,

An all-selection signal for controlling whether to perform the entire selection driving is given to the first potential supply line,

And the entire selection signal and the switching control signal are turned on at the time of the entire selection driving.

According to a ninth aspect of the present invention, in the second aspect of the present invention,

The single-stage circuit further includes an initialization switching element configured such that a high-potential power supply is applied to the second electrode, a third electrode is connected to the first control node, and a predetermined initializing signal is given to the first electrode .

According to a tenth aspect of the present invention, in the ninth aspect of the present invention,

The scanning signal line driving circuit is configured to be able to perform all selection driving for outputting an on-level scanning signal to all of the plurality of scanning signal lines,

An all-selection signal for controlling whether to perform the entire selection driving is given to the first potential supply line,

And the entire selection signal and the initialization signal are turned on at the time of the entire selection driving.

An eleventh aspect of the present invention provides, in a first aspect of the present invention,

The scanning signal line driving circuit is configured to be able to perform all selection driving for outputting an on-level scanning signal to all of the plurality of scanning signal lines,

An all-selection signal for controlling whether to perform the entire selection driving is given to the first potential supply line,

And the entire selection signal is turned on at the time of the entire selection driving.

According to a twelfth aspect of the present invention, in the eleventh aspect of the present invention,

The entire selection drive is performed at the time of inspection of the display panel.

A thirteenth aspect of the present invention is the eleventh aspect of the present invention,

Further comprising a panel control circuit connected to the first first potential power supply line for controlling the operation of the display panel,

And the panel control circuit sets the entire selection signal to the ON level when supply of the power from the outside is started or stopped.

According to the first aspect of the present invention, in the display panel, a first potential power source (a low potential power source when an n-channel transistor is employed as a switching element, and a p-channel transistor as a switching element are adopted as the scanning signal line driving circuit And a second first potential power supply line for supplying a first potential power supply to a circuit other than the scanning signal line driving circuit is provided. The single-stage circuit constituting the shift register in the scanning signal line driving circuit includes an output node, an output control node for controlling the potential of the scanning signal, and an output control node for turning the potential of the output control node toward the off level Off switching element. And the third electrode of the switching element for output control node turn-off is connected to the first first potential power supply line. Here, the first first potential supply line and the second first potential supply line are independent from each other. Therefore, even if the potential of the power source supplied by the first first potential power supply line is changed to control the state of the scanning signal, the abnormal operation in the circuit other than the scanning signal line driving circuit is not caused. Further, according to the potential change of the output control node, it is possible to change the potential of the third electrode of the switching element for turning off the output control node, so that the switching element for output control node turn- The application of a voltage exceeding the breakdown voltage of the capacitor C is suppressed.

According to the second aspect of the present invention, there is provided a display device in which a switching element or node for setting the potential of the output node to an off level is provided in a single-stage circuit constituting a shift register, The decrease in the internal pressure reliability is suppressed.

According to the third aspect of the present invention, there is provided a display device in which a switching element or a node for setting the potential of the output node to the ON level is provided in the single-stage circuit constituting the shift register, The decrease in the internal pressure reliability is suppressed.

According to the fourth aspect of the present invention, when the entire selection drive is performed, not only the entire selection signal, but also the clock signal and the start instruction signal are also turned on, so that the breakdown voltage of the switching element provided in the single- It is possible to reliably suppress the application of the voltage.

According to the fifth aspect of the present invention, it is possible to suppress the potential rise of the second electrode of the second control node turn-off switching element when the potential of the second control node rises greatly. Thereby, application of a voltage exceeding the breakdown voltage to the second control node turn-off switching element is suppressed.

According to the sixth aspect of the present invention, in the display device capable of switching the scanning order of the scanning signal lines, the same effects as those of the first to third aspects of the present invention can be obtained.

According to the seventh aspect of the present invention, in the display device capable of switching the scanning order of the scanning signal lines, the same effects as those of the first to third aspects of the present invention can be obtained.

According to an eighth aspect of the present invention, in a display device capable of switching the scanning order of scanning signal lines, when the entire selection driving is performed, the application of a voltage exceeding the breakdown voltage to the switching element provided for switching the scanning order is suppressed do.

According to the ninth aspect of the present invention, it is possible to initialize the single-stage circuit constituting the shift register at a desired timing.

According to the tenth aspect of the present invention, when all selection driving is performed, application of a voltage exceeding the breakdown voltage to the switching element provided for initializing the shift register is suppressed.

According to the eleventh aspect of the present invention, a display device capable of performing all selective driving of a scanning signal line without reducing the reliability of the breakdown voltage without increasing the number of circuit elements compared with the conventional one is realized.

According to the twelfth aspect of the present invention, it is possible to prevent the presence of the residual charge in the pixel defining portion from affecting the inspection result of the display panel.

According to the thirteenth aspect of the present invention, the residual charge in the pixel defining portion is removed when the power is turned on or the power is turned off, so that the degradation of the display quality due to the presence of the residual charge is suppressed.

1 is a circuit diagram showing a configuration of a single-stage circuit (configuration of one end of a shift register) in an active matrix liquid crystal display device according to a first embodiment of the present invention.
2 is a block diagram showing the entire configuration of a liquid crystal display device in the first embodiment.
3 is a block diagram for explaining the configuration of a gate driver in the first embodiment.
4 is a signal waveform diagram for explaining the operation of the gate driver in the first embodiment.
5 is a signal waveform diagram for explaining the operation of the single-stage circuit in the first embodiment.
6 is a circuit diagram showing a configuration of a single-stage circuit in a modified example of the first embodiment.
7 is a circuit diagram showing a configuration of a single-stage circuit according to a second embodiment of the present invention.
8 is a circuit diagram showing a circuit configuration for generating an inverse order instruction signal in the second embodiment.
9 is a circuit diagram showing the configuration of a single-stage circuit in the case of the second embodiment in which the QB node is charged based on the clock signal CKB.
10 is a circuit diagram showing a configuration of a single-stage circuit according to a third embodiment of the present invention.
Fig. 11 is a circuit diagram showing a configuration of a single-stage circuit in the case where the QB node is charged based on the clock signal CKB in the third embodiment.
12 is a circuit diagram showing an example of the configuration of a single-stage circuit when a p-channel transistor is used.
Fig. 13 is a signal waveform diagram for explaining the operation of the single-stage circuit when a p-channel transistor is used.
14 is a view showing a modification of the entire configuration of the liquid crystal panel.
Fig. 15 is a diagram for explaining an example in which the entire selection drive is performed at the time of inspection of the liquid crystal panel.
16 is a schematic configuration diagram of a gate driver.
17 is a schematic configuration diagram of a single-stage circuit in the conventional example.
18 is a signal waveform diagram for explaining the operation of the gate driver in the conventional example.
19 is a diagram showing a configuration example of a conventional single-stage circuit.
20 is a signal waveform diagram for explaining the operation of the single-stage circuit in the conventional example.
21 is a diagram showing a configuration example of a conventional single-stage circuit.
22 is a diagram showing a configuration example of a conventional single-stage circuit.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the gate terminal (gate electrode) of the thin film transistor corresponds to the first electrode, the drain terminal (drain electrode) corresponds to the second electrode, and the source terminal (source electrode) corresponds to the third electrode . In general, the higher one of the drain and the source is referred to as a drain. In the following description, however, one side is defined as a drain and the other side is defined as a source, so that the source potential may be higher than the drain potential. Unless otherwise mentioned, the thin film transistors provided in the shift register are all n-channel transistors.

<1. First Embodiment>

<1.1 Overall Configuration and Operation>

2 is a block diagram showing the entire configuration of an active matrix liquid crystal display device according to the first embodiment of the present invention. This liquid crystal display device is constituted by a liquid crystal panel 5 and a control substrate 6. The liquid crystal panel 5 includes a display unit 100, a gate driver 200 (scanning signal line driving circuit), a source driver 300 (video signal line driving circuit), a protection circuit 400 for protecting circuits in the panel from static electricity, And control circuits 501 and 502 such as a level shifter are included. The control board 6 includes a panel control circuit 600.

A plurality of (j) source bus lines (video signal lines) SL1 to SLj, a plurality of (i) gate bus lines (scanning signal lines) GL1 to GLi and their source bus lines SL1 to SLj (Ixj) pixel forming portions provided corresponding to the intersections of the gate bus lines GL1 to GLi, respectively. Each pixel forming portion is provided with a thin film transistor (TFT) 10 in which a gate terminal is connected to a gate bus line GL passing through a corresponding intersection and a source terminal is connected to a source bus line SL passing through the intersection, A pixel electrode 11 connected to the drain terminal of the pixel electrode 10 and a common electrode 14 and a storage capacitor electrode 15 commonly provided to the plurality of pixel forming units and a common electrode 14 And a storage capacitor 13 formed by the pixel electrode 11 and the storage capacitor electrode 15. The liquid crystal capacitor 12 includes a pixel electrode 11 and a storage capacitor electrode 13. [ In addition, a pixel capacitor is formed by the liquid crystal capacitor 12 and the storage capacitor 13. [ When a gate terminal of each thin film transistor 10 receives an active scanning signal from the gate bus line GL, on the basis of a video signal received from the source bus line SL by the source terminal of the thin film transistor 10, The voltage representing the value is maintained. In the display portion 100 of Fig. 2, only the components corresponding to one pixel forming portion are shown.

The panel control circuit 600 receives the supply of the power PW to generate a high-potential power supply VDD and a low-potential power supply VSS which are required in each circuit in the liquid crystal panel 5, and generates the entire selection signal ALL-ON . The panel control circuit 600 also receives a timing signal group TG such as an image signal DAT sent from the outside and a horizontal synchronizing signal or a vertical synchronizing signal and supplies the timing signal group TG to the gate driver 200 and the source And generates various control signals (not shown) for controlling the operation of the driver 300. Various control signals include a gate start pulse signal for controlling the operation of the gate driver 200, a gate clock signal, a source start pulse signal for controlling the operation of the source driver 300, a source clock signal, and the like. The high-potential power supply VDD, the low-potential power supply VSS, the entire selection signal ALL-ON, the digital video signal, and various control signals generated by the panel control circuit 600 are supplied to the liquid crystal panel 5 Circuit. For convenience of explanation, the wiring for supplying the entire selection signal ALL-ON is called "ALL-ON wiring" and the wiring for supplying the low potential power supply VSS is called "VSS wiring". In Fig. 2, reference numeral L1 is assigned to the ALL-ON wiring, and reference numeral L2 is assigned to the VSS wiring. ALL-ON wiring L1 and VSS wiring L2 are electrically separated from each other. That is, the ALL-ON wiring L1 and the VSS wiring L2 are independent of each other. The input terminals for the low potential power supply of the gate driver 200 are connected only to the ALL-ON wiring L1 and the input terminals for the low potential power supply are connected to the circuits other than the gate driver 200 The input terminal for the low potential power supply of the circuit of FIG.

The protection circuit 400 protects the circuit in the liquid crystal panel 5 from static electricity. The control circuits 501 and 502 perform level conversion of power source potential, for example, so that the gate driver 200 and the source driver 300 perform a desired operation. The gate driver 200 repeats the application of the active scanning signal to each of the gate bus lines GL1 to GLi based on the control signal output from the panel control circuit 600, with one vertical scanning period as a cycle. The source driver 300 applies a driving video signal to each of the source bus lines SL1 to SLj based on the digital video signal and the control signal output from the panel control circuit 600. [

As described above, a driving video signal is applied to each of the source bus lines SL1 to SLj, and a scanning signal is applied to each of the gate bus lines GL1 to GLi, whereby an image based on the image signal DAT sent from the outside is output to the display unit 100. [ . In the present embodiment, the first first potential power supply line is realized by the ALL-ON wiring L1, and the second first potential power supply line is realized by the VSS wiring L2. The low potential power supply corresponds to the first potential power supply, and the high potential power supply corresponds to the second potential power supply.

<1.2 Configuration and Operation of Gate Driver>

Next, the structure and operation of the gate driver 200 in this embodiment will be outlined with reference to Figs. 3, 4, and 16. Fig. As shown in Fig. 3, the gate driver 200 is constituted by a shift register 210 having a plurality of stages. In the display section 100, a pixel matrix of i rows x j columns is formed. And each stage of the shift register 210 is provided so as to correspond to each row of the pixel matrix on a one-to-one basis. That is, the shift register 210 includes i-stage constituent circuits SR (1) to SR (i). The i stage unit circuits SR (1) to SR (i) are connected in series with each other.

The schematic configuration of the gate driver 200 is similar to that of the conventional one as shown in Fig. Each stage circuit includes an input terminal for receiving the set signal S, an input terminal for receiving the clock signal CK, an input terminal for receiving the entire selection signal ALL-ON, an input for receiving the reset signal R And an output terminal for outputting the scanning signal OUT are provided. In each stage circuit, the scanning signal OUT outputted from the single stage circuit at the previous stage is given as the set signal S and the scanning signal OUT outputted from the stage circuit at the next stage is given as the reset signal R. The all selection signal ALL-ON is commonly assigned to all the single-stage circuits. As the clock signal CK, the first gate clock signal GCK1 and the second gate clock signal GCK2 are given to the single-stage circuit alternately one by one. Further, a gate start pulse signal (start instruction signal) is given as the set signal S to the first-stage single-stage circuit.

When the pulse of the gate start pulse signal as the set signal S is applied to the first stage of the shift register 210 in the above-described configuration, the first gate clock signal GCK1 and the second gate clock signal GCK2 whose on- Based on the clock signal GCK2, the pulse included in the gate start pulse signal is sequentially transferred from the first stage to the i-th stage. In accordance with the transfer of the pulses, the scanning signals OUT output from the respective stages are sequentially brought to the high level. As a result, as shown in Fig. 4, the scanning signals OUT1 to OUTi which are sequentially set to the high level for a predetermined period are given to the gate bus lines GL1 to GLi in the display unit 100, respectively.

&Lt; 1.3 Configuration of short circuit >

1 is a circuit diagram showing a configuration of a single-stage circuit (configuration of one end of a shift register 210) in the present embodiment. As shown in Fig. 1, this single-stage circuit includes seven thin film transistors Tr1 to Tr7. The single-stage circuit has four input terminals 21 to 24 and one output terminal 39 in addition to the high-potential power supply input terminal. Here, reference numeral 21 is assigned to an input terminal for receiving the entire selection signal ALL-ON, reference numeral 22 is assigned to an input terminal for receiving the clock signal CK, reference numeral 23 is assigned to an input terminal for receiving the set signal S, The input terminal for receiving the reset signal R is indicated by reference numeral 24.

Next, the connection relationship among the constituent elements in the single-stage circuit will be described. The source terminal of the thin film transistor Tr2, the gate terminal of the thin film transistor Tr3, the drain terminal of the thin film transistor Tr4, and the gate terminal of the thin film transistor Tr6 are connected to each other. The region (wiring) where these are connected to each other is referred to as &quot; QB node &quot; for the sake of convenience. The gate terminal of the thin film transistor Tr5 and the source terminal of the thin film transistor Tr7 are connected to each other. The region (wiring) where these are connected to each other is referred to as a &quot; Q node &quot; for the sake of convenience. The source terminal of the thin film transistor Tr1, the drain terminal of the thin film transistor Tr3, and the drain terminal of the thin film transistor Tr7 are connected to each other. The region (wiring) where these are connected to each other is referred to as &quot; Q2 node &quot; for the sake of convenience.

For the thin film transistor Tr1, the gate terminal is connected to the input terminal 23, the drain terminal is connected to the input terminal for the high potential power supply, and the source terminal is connected to the node Q2. For the thin film transistor Tr2, the gate terminal is connected to the input terminal 24, the drain terminal is connected to the input terminal for the high potential power supply, and the source terminal is connected to the QB node. For the thin film transistor Tr3, the gate terminal is connected to the QB node, the drain terminal is connected to the node Q2, and the source terminal is connected to the input terminal 21. [ For the thin film transistor Tr4, the gate terminal is connected to the input terminal 23, the drain terminal is connected to the QB node, and the source terminal is connected to the input terminal 21. [ For the thin film transistor Tr5, the gate terminal is connected to the Q node, the drain terminal is connected to the input terminal 22, and the source terminal is connected to the output terminal 39. [ For the thin film transistor Tr6, the gate terminal is connected to the QB node, the drain terminal is connected to the output terminal 39, and the source terminal is connected to the input terminal 21. [ For the thin film transistor Tr7, the gate terminal is connected to the input terminal for the high potential power supply, the drain terminal is connected to the node Q2, and the source terminal is connected to the Q node.

Next, the function of each constituent element at the time of normal operation will be described. The thin film transistor Tr1 changes the potential of the node Q2 toward the high level when the set signal S is at the high level. The thin film transistor Tr2 changes the potential of the QB node toward the high level when the reset signal R is at the high level. The thin film transistor Tr3 changes the potential of the node Q2 toward the low level when the potential of the QB node is at the high level. The thin film transistor Tr4 changes the potential of the QB node toward the low level when the set signal S is at the high level. The thin film transistor Tr5 applies the potential of the clock signal CK to the output terminal 39 when the potential of the Q node is at the high level. The thin film transistor Tr6 changes the potential of the output terminal 39 toward the low level when the potential of the QB node is at the high level. The thin film transistor Tr7 functions as a voltage dividing means so that a voltage higher than the breakdown voltage is not applied between the drain and the source of the thin film transistor Tr3 even if the potential of the Q node becomes significantly high.

In the present embodiment, the second control node turn-on section is realized by the thin film transistor Tr1, the first control node turn-on section is realized by the thin film transistor Tr2, and the second control node turn- And a switching element for turning off the first control node is realized by the thin film transistor Tr4. Further, the thin film transistor Tr5 realizes a switching element for output node turn-on, and the thin film transistor Tr6 realizes a switching element for output node turn-off. Further, a switching element for partial pressure is realized by the thin film transistor Tr7. Further, an output node is realized by the output terminal 39, a first control node is realized by the QB node, and a second control node is realized by the Q node.

<1.4 Operation of short circuit at normal operation>

Next, the operation of the single-stage circuit at the time of normal operation will be described with reference to Part A of Fig. 1 and Fig. It is also assumed that the period from the time point t3 to the time point t4 is the period during which the gate bus line connected to this stage circuit is to be selected. It is also assumed that the first gate clock signal GCK1 is applied to the input terminal 22 of the single-stage circuit. Regarding the all selection signal ALL-ON, it is normally held at a low level.

During the period before the time t1, the potential of the Q node and the potential of the Q2 node are maintained at the low level, and the potential of the QB node is maintained at the high level. When the set signal S changes from the low level to the high level at time point t1, the thin film transistors Tr1 and Tr4 are turned on. When the thin film transistor Tr1 is turned on, the potential of the node Q2 changes from the low level to the high level. At this time, the thin film transistor Tr7 is in the ON state, and the potential of the Q node also changes from the low level to the high level. Further, when the thin film transistor Tr4 is turned on, the potential of the QB node changes from high level to low level.

The first gate clock signal GCK1 changes from the low level to the high level when the set signal S changes from the high level to the low level at the time point t2 and then reaches the time point t3. At this time, since the thin film transistor Tr5 is in the ON state, the potential of the output terminal 39 (potential of the scanning signal OUT) increases with the potential of the input terminal 22 rises. Since the parasitic capacitance exists between the gate and the source of the thin film transistor Tr5 and between the gate and the drain, the potential of the Q node rises along with the potential rise of the output terminal 39 (the Q node is bootstrapped). As a result, the potential of the Q node becomes "(VDD x 2) -Vth ". As a result, a large voltage is applied to the gate terminal of the thin film transistor Tr5, so that the potential of the output terminal 39 rises up to the high level of the first gate clock signal GCK1 without causing a so-called threshold voltage drop. In this manner, the gate bus line connected to the output terminal 39 of the single-stage circuit is in the selected state.

During the period from the time t3 to the time t4, the reset signal R is at the low level, so that the thin film transistor Tr2 is kept in the OFF state. As a result, during this period, the QB node is held at the low level, and the thin film transistors Tr3 and Tr6 are held in the off state. Therefore, during this period, the potentials of the Q2 node, the Q node, and the output terminal 39 are not lowered. Further, in the present embodiment, the thin film transistor Tr7 is provided between the gate terminal of the thin film transistor Tr5 and the drain terminal of the thin film transistor Tr3. Therefore, even if the potential of the Q node becomes higher than VDD due to the bootstrap during the period from the time point t3 to the time point t4, the thin film transistor Tr7 functions as the voltage dividing means, so that the voltage exceeding the breakdown voltage is not applied to the thin film transistor Tr3 .

At time t4, the first gate clock signal GCK1 changes from a high level to a low level. As a result, the potential of the output terminal 39 decreases with the decrease of the potential of the input terminal 22. As a result, the potential of the Q node also drops through the parasitic capacitance of the thin film transistor Tr5. Along with this, the potential of the node Q2 also decreases. At time point t5, the reset signal R changes from the low level to the high level. Thus, the thin film transistor Tr2 is turned on. As a result, the potential of the QB node is changed from the low level to the high level. As a result, since the thin film transistor Tr3 is turned on, the potential of the node Q2 and the potential of the node Q are further lowered. Further, since the thin film transistor Tr6 is turned on, the potential of the output terminal 39 is pulled to the low level.

As described above, the scan signals OUT1 to OUTi which are sequentially set to the high level for a predetermined period of time are sequentially applied to the gate bus lines GL1 to GLi (not shown) in the display unit 100, .

<1.5 Operation of short circuit at all selection drive>

Next, the operation of the single-stage circuit at the time of the entire selection driving will be described with reference to B section of FIG. 1 and FIG. It is also assumed that the period from the time point t11 to the time point t12 is a period during which all the gate bus lines must be in a selected state. During the period before the time point t11, the potential of the Q node is at the low level and the potential of the QB node is at the high level. At time t11, the entire selection signal ALL-ON changes from a low level to a high level. At this time, the potential of the QB node rises from VDD to "VDD x 2-Vth " due to the bootstrap caused by the parasitic capacitance of the thin film transistor Tr6. As a result, a large voltage is applied to the gate terminal of the thin film transistor Tr6 to cause no so-called threshold voltage drop, and the potential of the output terminal 39 (the potential of the scanning signal OUT) . This operation is performed in all the single-stage circuits, and all the gate bus lines are selected in the period from the time t11 to the time t12. Here, in the present embodiment, the source terminal of the thin film transistor Tr3 and the source terminal of the thin film transistor Tr4 are connected to the input terminal 21 for receiving the entire selection signal ALL-ON. As a result, even if the potential of the QB node rises to "VDD x 2-Vth", a voltage exceeding the breakdown voltage is not applied to the thin film transistor Tr3 or the thin film transistor Tr4.

Since the scanning signal OUT outputted from the single-stage circuit at the previous stage is given as the set signal S to the single-stage circuit, during the period in which the entire selection drive is performed, the thin film transistor Tr1 is turned on, The potential of the transistor Q1 becomes a high level. Thus, the thin film transistor Tr5 is turned on. Further, as described above, the thin film transistor Tr6 is also turned on. As a result, during the period from the time point t11 to the time point t12, the first gate clock signal GCK1 and the second gate clock signal GCK2 become high level. This is because an overcurrent flows between the input terminal 21 and the input terminal 22 when the first gate clock signal GCK1 and the second gate clock signal GCK2 become low level, for example.

During the period from the time t11 to the time t12, the set signal S (the gate start pulse signal or the scanning signal OUT output from the single stage circuit at the previous stage) is at a high level and the reset signal R So that a so-called threshold voltage drop occurs in the Q2 node, the Q node, and the QB node, but the high-potential power supply VDD is supplied. Therefore, in each stage circuit, there is no floating node (node in an electrically floating state). This keeps all gate bus lines selected for a long period of time.

<1.6 Effect>

According to the present embodiment, in the liquid crystal display device including the gate driver 200 capable of selecting and driving all the gate bus lines, a part of the gate driver 200 in the shift register 210 included in the single- The source terminal of the thin-film transistor of the first embodiment is connected to the input terminal 21 for the entire selection signal ALL-ON. More specifically, as shown in Fig. 1, a source of a thin film transistor Tr3 having a gate terminal connected to a QB node (node connected to the gate terminal of the thin film transistor Tr6 for lowering the potential of the output terminal 39) And the source terminal of the thin film transistor Tr4 to which the drain terminal is connected to the QB node are connected to the input terminal 21 for the entire selection signal ALL-ON. Therefore, even if the potential of the QB node significantly increases due to the change of the entire selection signal ALL-ON from the low level to the high level, the voltage exceeding the breakdown voltage is not applied to the thin film transistor Tr3 or the thin film transistor Tr4. In the prior art, in order to prevent a voltage exceeding the breakdown voltage from being applied to the thin film transistor when the potential of the QB node significantly rises, a thin film transistor (thin film transistor Tr98 of FIG. 22 ). On the other hand, in the present embodiment, the thin film transistor corresponding to the thin film transistor Tr98 in Fig. 22 is not provided in the single circuit. From the above, it is possible to perform the entire selection drive of the gate bus line without decreasing the reliability of the breakdown voltage, without increasing the number of circuit elements compared to the conventional one.

In the present embodiment, the ALL-ON wiring L1 for supplying the entire selection signal ALL-ON and the VSS wiring L2 for supplying the low-potential power supply VSS are electrically separated from each other. Only the input terminal for the low potential power supply to the gate driver 200 is connected to the ALL-ON wiring L1, and the input terminal for the low potential power supply to the circuits other than the gate driver 200 is connected to the VSS wiring L2. Therefore, even if the entire selection signal ALL-ON is changed from the low level to the high level at the time of the entire selecting operation, the abnormal operation (for example, the malfunction of the control circuits 501 and 502 or the overcurrent An abnormal operation due to an abnormality).

<1.7 Modifications>

In the first embodiment, the QB node is configured to be charged based on the reset signal R, but the present invention is not limited to this. For example, even if the QB node is charged based on the clock signal CKB different from the clock signal given to the input terminal 22 among the two-phase clock signals (the first gate clock signal GCK1 and the second gate clock signal GCK2) do. 6, the gate terminal of the thin film transistor Tr2 is connected to the input terminal 25 for receiving the clock signal CKB, and the drain terminal of the thin film transistor Tr2 is connected to the high- And is connected to an input terminal. According to the present variation, the clock signal CKB is set to the high level during the entire selection driving. Thereby, a so-called threshold voltage drop occurs in the QB node, but the high-potential power supply VDD is supplied. In this manner, also in this modification, it is possible to maintain the selected state of all the gate bus lines for a long time when the entire selection drive is performed.

<2. Second Embodiment>

<2.1 Configuration>

A second embodiment of the present invention will be described. Only points different from those of the first embodiment will be described, and description of the same points as those of the first embodiment will be omitted. In the present embodiment, the scanning order of the gate bus lines can be switched. The switching of the scanning sequence is a process of switching from the other end of the display section 100 to the forward scanning in which the gate bus line is selected one by one from one end (for example, the upper end) to the other end Order scanning in which the gate bus lines are selected one by one at one end.

7 is a circuit diagram showing a configuration of a single-stage circuit in the present embodiment. As shown in Fig. 7, this single-stage circuit has four thin film transistors Tr8 to Tr11 and six input terminals 26 to 31, in addition to the components in the first embodiment. The forward instruction signal UD which is set to the high level during the forward scanning is inputted to the input terminal 26. [ The positive set main set signal SU is input to the input terminal 27. The reverse order instruction signal UDB, which becomes high level in the inverse-order scanning, is inputted to the input terminal 28. [ The input terminal 29 is supplied with the reverse order main set signal SD. An input main reset signal RU is input to the input terminal 30. The input terminal 31 is supplied with a reverse order main reset signal RD. The region (wiring) where the gate terminal of the thin film transistor Tr1, the gate terminal of the thin film transistor Tr4, the source terminal of the thin film transistor Tr8, and the source terminal of the thin film transistor Tr9 are connected to each other is referred to as a "QS node" for convenience. The region (wiring) where the gate terminal of the thin film transistor Tr2, the source terminal of the thin film transistor Tr10, and the source terminal of the thin film transistor Tr11 are connected to each other is referred to as a "QR node" for convenience's sake.

Further, the second switching control switching element is realized by the thin film transistors Tr8 and Tr9, and the first switching control switching element is realized by the thin film transistors Tr10 and Tr11. In addition, the switching control signal is realized by the forward instruction signal UD and the reverse order instruction signal UDB.

Next, the connection relationship among the constituent elements in the single-stage circuit will be described. The thin film transistors Tr3 to Tr7 are the same as those in the first embodiment. For the thin film transistor Tr1, the gate terminal is connected to the QS node, the drain terminal is connected to the input terminal for the high potential power supply, and the source terminal is connected to the node Q2. For the thin film transistor Tr2, the gate terminal is connected to the QR node, the drain terminal is connected to the input terminal for the high potential power source, and the source terminal is connected to the QB node. For the thin film transistor Tr8, the gate terminal is connected to the input terminal 26, the drain terminal is connected to the input terminal 27, and the source terminal is connected to the QS node. For the thin film transistor Tr9, the gate terminal is connected to the input terminal 28, the drain terminal is connected to the input terminal 29, and the source terminal is connected to the QS node. For the thin film transistor Tr10, the gate terminal is connected to the input terminal 26, the drain terminal is connected to the input terminal 30, and the source terminal is connected to the QR node. For the thin film transistor Tr11, the gate terminal is connected to the input terminal 28, the drain terminal is connected to the input terminal 31, and the source terminal is connected to the QR node.

In the present embodiment, in each of the single-stage circuits, the scanning signal OUT outputted from the single-stage circuit at the previous stage is given to the input terminal 27 as the regular main set signal SU, and the backward main use reset signal RD To the input terminal 31 as shown in Fig. Also, in each stage circuit, the scanning signal OUT output from the single stage circuit at the next stage is given to the input terminal 29 as the reverse order main set signal SD and input as the regular main reset signal RU And is applied to the terminal 30.

<Operation of 2.2-stage circuit>

In normal operation, when the forward scanning is performed, the forward instruction signal UD is at the high level and the reverse order instruction signal UDB is at the low level. At this time, the thin film transistors Tr8 and Tr10 are turned on, and the thin film transistors Tr9 and Tr11 are turned off. Thereby, the single-stage circuit operates on the basis of the regular main use set signal SU and the regular scan reset signal RU. At the time of normal operation, when the reverse order scanning is performed, the forward instruction signal UD is at the low level and the reverse order instruction signal UDB is at the high level. At this time, the thin film transistors Tr8 and Tr10 are turned off, and the thin film transistors Tr9 and Tr11 are turned on. Thereby, the single-stage circuit operates based on the reverse order main set signal SD and the reverse order main use reset signal RD. In this manner, the signal given to the QS node functions as the set signal S in the first embodiment, and the signal given to the QR node functions as the reset signal R in the first embodiment, In the circuit, the same operation as in the first embodiment is performed.

At the time of full selection driving, the entire selection signal ALL-ON changes from a low level to a high level as in the first embodiment. At this time, the potential of the QS node becomes higher than VDD by the bootstrap caused by the parasitic capacitance of the thin film transistor Tr4. Similarly, by the bootstrap caused by the parasitic capacitance of the thin film transistor Tr2, the potential of the QR node becomes higher than VDD. Here, for example, when the forward scanning is performed, since the reverse order indication signal UDB is at a low level, a voltage exceeding the breakdown voltage may be applied between the gate and source of the thin film transistors Tr9 and Tr11. Therefore, in the present embodiment, the forward instruction signal UD and the reverse order instruction signal UDB become high level during a period in which the entire selection signal ALL-ON is held at the high level.

By providing the circuitry shown in Fig. 8 inside the gate driver 200, it is relatively easy to generate the reverse order instruction signal UDB based on the forward instruction signal UD in the gate driver 200 It becomes possible. In the configuration shown in Fig. 8, when the all-selection signal ALL-ON is at the low level, that is, at normal time, when the positive order indication signal UD is at the high level, the thin film transistor Tr20 is turned on, UDB becomes low level. In addition, when the positive order indication signal UD is at the low level, the thin film transistor Tr20 is turned off, so that the reverse order indication signal UDB goes high level. In addition, when the entire selection signal ALL-ON is at the high level, that is, during the entire selection driving, the reverse order indication signal UDB goes high level regardless of the logical level of the positive order indication signal UD.

<Effect of 2.3>

According to the present embodiment, in the liquid crystal display device capable of switching the scanning order of the gate bus lines, the total selection drive of the gate bus line is performed without decreasing the reliability of the breakdown voltage without increasing the number of circuit elements Lt; / RTI &gt; Also in the present embodiment, the QB node may be charged based on the clock signal CKB as in the first embodiment (see FIG. 9).

<3. Third Embodiment>

A third embodiment of the present invention will be described. In the present embodiment, the shift register 210 can be initialized. 10 is a circuit diagram showing a configuration of a single-stage circuit in the present embodiment. 10, the monolithic circuit according to the present embodiment includes, in addition to the components in the second embodiment (see Fig. 7), a thin film transistor Tr12 for deactivating the monolithic circuit, A terminal 33 is provided. Further, a switching element for initialization is realized by the thin film transistor Tr12. For the thin film transistor Tr12, the gate terminal is connected to the input terminal 33 for receiving the initialization signal INIT, the drain terminal is connected to the input terminal for the high potential power supply, and the source terminal is connected to the QB node. In addition, a common initialization signal INIT is given to all the single-stage circuits constituting the shift register 210. [ In such a configuration, for example, immediately after the power supply of the apparatus is turned on, the initialization signal INIT becomes a high level. As a result, the thin film transistor Tr12 is turned on, and the potential of the QB node becomes a high level. When the potential of the QB node becomes a high level, the thin film transistor Tr3 is turned on, so that the potential of the node Q2 and the potential of the Q node become low level. As described above, the potential of the node Q2 is low and the potential of the node QB is high. As described above, in the present embodiment, all of the single-stage circuits constituting the shift register 210 can be inactivated by setting the initialization signal INIT to high level.

In the above-described configuration, as in the first embodiment, the potential of the QB node is significantly increased during the entire selection drive. That is, the potential of the QB node becomes higher than VDD. For this reason, when the initialization signal INIT is at a low level, for example, a voltage exceeding the breakdown voltage may be applied between the gate and the source of the thin film transistor Tr12. Therefore, in the present embodiment, the initialization signal INIT becomes a high level during a period in which the entire selection signal ALL-ON is maintained at a high level. Thus, the application of a voltage exceeding the breakdown voltage to the thin film transistor Tr12 is suppressed.

Also in the present embodiment, as in the first and second embodiments, the QB node may be charged based on the clock signal CKB (see FIG. 11).

<4. Variations, Other>

&Lt; 4.1 Thin Film Transistor Type >

In each of the above-described embodiments, the case where the thin film transistor in each of the single-stage circuits is an n-channel transistor is described as an example, but the present invention is not limited thereto. If the power source (high potential / low potential) and the signal logic (high / low) are reversed from the above embodiments, a p-channel transistor may be employed as the thin film transistor in each of the single-stage circuits. For example, when a p-channel transistor is used to realize a circuit equivalent to the single-stage circuit shown in Fig. 1, the circuit configuration is as shown in Fig. In this case, at the time of the entire selection driving, as shown in Fig. 13, the entire selection signal ALL-ON changes from the high level to the low level. At this time, the potential of the QB node drops to a remarkably low level due to the bootstrap caused by the parasitic capacitance of the thin film transistor Tr6. Thereby, the potential of the output terminal 69 (potential of the scanning signal OUT) is lowered to the front of the entire selection signal ALL-ON without causing a so-called threshold voltage drop. This operation is performed in all the single-stage circuits, and all the gate bus lines are selected in the period from the time t11 to the time t12. Further, in this modification, the high potential power supply corresponds to the first potential power supply, and the low potential power supply corresponds to the second potential power supply.

<4.2 Overall Configuration of Liquid Crystal Panel>

The configuration in which the control circuits 501 and 502 are provided between the protection circuit 400 and the gate driver 200 and between the protection circuit 400 and the source driver 300 is illustrated in FIG. The present invention is not limited thereto. The present invention can be applied to a case where a control circuit independent of the gate driver 200 or the source driver 300 is not provided in the liquid crystal panel 5 as shown in Fig. However, in this case as well, the ALL-ON wiring L1 and the VSS wiring L2 are electrically separated from each other, so that only the low-potential power source input terminal of the gate driver 200 is connected to the ALL-ON wiring L1.

&Lt; 4.3 Timing at which all selection drive is performed >

<4.3.1 Case 1>

Typical timings at which the entire selection drive is performed are when the power of the apparatus is turned off and when the apparatus is powered on. That is, typically, the entire selection drive is built in during the power-off sequence (a series of processes executed when the power is turned off) or a power-on sequence (a series of processes executed when the power is turned on).

As shown in Fig. 2, the panel control circuit 600 receives supply of power PW from the outside. During the period in which the panel control circuit 600 receives supply of the power PW from the outside, the panel control circuit 600 maintains the entire selection signal ALL-ON at a low level. On the other hand, when the supply of the power PW from the outside is started or blocked, the panel control circuit 600 sets the entire selection signal ALL-ON to the high level (on level). In this way, the entire selection drive is performed at the time of driving or stopping the apparatus, and the residual charges in all the pixel defining portions in the display portion are removed.

<4.3.2 Second case>

The entire selection drive may be performed at the time of inspection of the liquid crystal panel 5. [ For example, in various inspections of the liquid crystal panel 5, it is desired that the residual charge in the pixel forming portion does not affect the inspection result. In this case, the high-level potential is applied to the all-selection terminal ALL-ON (see Fig. 15) among the terminals provided in the liquid crystal panel 5, thereby eliminating the residual charges in all the pixel forming portions in the display portion. In addition, since it is possible to inspect without inserting a clock or the like, it can be easily inspected.

5: liquid crystal panel
100:
200: gate driver
210: Shift register
400: Protection circuit
600: panel control circuit
Tr1 to Tr12: thin film transistors
ALL-ON: All selection signal
CK: clock signal
OUT: scan signal
S: set signal
R: Reset signal

Claims (15)

  1. A display device comprising a display panel including a display section in which a plurality of scanning signal lines and a plurality of video signal lines are arranged, a scanning signal line driving circuit for driving the plurality of scanning signal lines, and a video signal line driving circuit for driving the plurality of video signal lines as,
    The display panel includes a first first potential supply line for supplying a first potential supply to the scanning signal line driving circuit and a second potential supply for supplying a first potential supply to a circuit other than the scanning signal line driving circuit A power line,
    Wherein the scanning signal line driving circuit includes a plurality of stages of shift registers for sequentially outputting on-level scanning signals to the plurality of scanning signal lines based on a clock signal,
    Wherein the single-stage circuit constituting each stage of the shift register comprises:
    An output node connected to the scanning signal line,
    An output control node for controlling the potential of the scanning signal output from the output node;
    The potential of the output control node is changed toward the off level based on the potential of the first electrode to which the second electrode is connected to the output control node and the third electrode is connected to the first potential supply line And a switching element for output control node turn-off,
    The first first potential supply line and the second first potential supply line are independent power supply lines,
    Wherein the single-stage circuit comprises:
    An output for changing the potential of the output node toward the off level based on the potential of the first electrode, to which the second electrode is connected, and the third electrode is connected to the first first potential power supply line A switching element for turning off the node,
    A first control node connected to the first electrode of the switching element for turning off the output node as the output control node,
    A first control node turn-on section for changing the potential of the first control node toward an on level,
    The first control node is connected to a second electrode, and the third electrode is connected to the first first potential power supply line, the potential of the first control node is set to the off level A first control node turn-off switching element as a switching element for turning off the output control node,
    And the display device.
  2. delete
  3. The method according to claim 1,
    Wherein the single-stage circuit comprises:
    An output node turn-on switching element for changing the potential of the output node toward the on level based on the potential of the first electrode, to which the clock signal is given to the second electrode and the third electrode is connected to the output node; ,
    A second control node connected to the first electrode of the switching element for turning on the output node as the output control node,
    A second control node turn-on section for changing the potential of the second control node toward the on level,
    The second control node is connected to the second control node directly or through a voltage divider, and the third electrode is connected to the first first power supply line, and the second control node Off switching element for turning off the output of the second control node as the switching element for turning off the output control node
    Lt; / RTI &gt;
    And the first electrode of the switching element for turning off the second control node is connected to the first control node.
  4. The method of claim 3,
    The scanning signal line driving circuit is configured to be able to perform all selection driving for outputting an on-level scanning signal to all of the plurality of scanning signal lines,
    An all-selection signal for controlling whether to perform the entire selection driving is given to the first potential supply line,
    The second control node turn-on section included in the single-stage circuit changes the potential of the second control node toward the on level based on the start instruction signal or the scan signal output from the output node of the previous stage,
    Wherein the start instruction signal or the scan signal output from the output node of the previous stage is applied to the first electrode of the first control node turn-off switching element included in the single-stage circuit,
    Wherein the all selection signal, the clock signal, and the start instruction signal are turned on at the time of the all selection driving.
  5. The method of claim 3,
    And the second electrode of the second control node turn-off switching element is connected to the second electrode, and the third electrode is connected to the second electrode of the output And a switching element for partial voltage to which the first electrode of the switching element for turning on the node is connected.
  6. The method of claim 3,
    Wherein the shift register is configured so that a sequence of applying an on-level scan signal to the plurality of scan signal lines is switchable between a normal sequence and a reverse sequence,
    Wherein the single-stage circuit is provided with a switching control signal changing between an on-level and an off-level for switching a sequence of applying an on-level scanning signal to the plurality of scanning signal lines,
    The second control node turn-on section included in the single-stage circuit includes:
    The potential of the second control node is set at the on level (high level) based on the potential of the first electrode, to which the high potential power is applied to the second electrode, and the third electrode is connected to the second control node, A second switching element for turning on the control node for changing the voltage of the control node toward the second control node,
    A fourth control node connected to the first electrode of the switching element for turning on the second control node,
    And a second switching control element for switching control, to which the switching control signal is given to the first electrode, a scanning signal to be outputted from the output node of the other stage is given to the second electrode, and a third electrode is connected to the fourth control node and,
    And a signal line for applying a potential of the off-level to the switching control signal is connected to the first potential supply line of the first potential.
  7. The method according to claim 6,
    Wherein the first control node turn-on section included in the single-
    A first control for changing the potential of the first control node toward the on level based on the potential of the first electrode to which the high potential power is applied to the second electrode and the third electrode is connected to the first control node A switching element for turning on the node,
    A third control node connected to the first electrode of the switching element for turning on the first control node,
    A first switching control element is provided with a switching control signal for the first electrode, a scanning signal outputted from the output node of the other stage is applied to the second electrode, and a third electrode is connected to the third control node And the display device.
  8. 8. The method according to claim 6 or 7,
    The scanning signal line driving circuit is configured to be able to perform all selection driving for outputting a scanning signal of an on level to all of the plurality of scanning signal lines,
    An all-selection signal for controlling whether to perform the entire selection driving is given to the first potential supply line,
    And the entire selection signal and the switching control signal are turned on at the time of the entire selection driving.
  9. The method according to claim 1,
    The single-stage circuit further includes an initialization switching element configured such that a high-potential power supply is applied to the second electrode, a third electrode is connected to the first control node, and a predetermined initializing signal is given to the first electrode .
  10. 10. The method of claim 9,
    The scanning signal line driving circuit is configured to be able to perform all selection driving for outputting a scanning signal of an on level to all of the plurality of scanning signal lines,
    An all-selection signal for controlling whether to perform the entire selection driving is given to the first potential supply line,
    Wherein the all selection signal and the initialization signal are turned on at the time of the entire selection driving.
  11. The method according to claim 1,
    The scanning signal line driving circuit is configured to be able to perform all selection driving for outputting a scanning signal of an on level to all of the plurality of scanning signal lines,
    An all-selection signal for controlling whether to perform the entire selection driving is given to the first potential supply line,
    And the entire selection signal is turned on at the time of the entire selection driving.
  12. 12. The method of claim 11,
    And the entire selection drive is performed at the time of inspection of the display panel.
  13. 12. The method of claim 11,
    Further comprising a panel control circuit connected to the first first potential power supply line for controlling the operation of the display panel,
    Wherein the panel control circuit sets the entire selection signal to an on level when supply of external power is started or stopped.
  14. The method according to claim 1,
    The potential of the second potential power supply supplied to the scanning signal line driving circuit is higher than the potential of the first potential power supply supplied to the scanning signal line driving circuit,
    And a potential higher than a potential of a second potential power supply supplied to the scanning signal line driving circuit can be given to the output control node.
  15. The method according to claim 1,
    The potential of the second potential power supply supplied to the scanning signal line driving circuit is lower than the potential of the first potential power supply supplied to the scanning signal line driving circuit,
    And a potential lower than a potential of a second potential power supply supplied to the scanning signal line driving circuit can be given to the output control node.
KR1020147023232A 2012-03-30 2013-02-28 Display device KR101641446B1 (en)

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WO2013146058A1 (en) 2013-10-03
EP2833350A4 (en) 2015-04-15
EP2833350A1 (en) 2015-02-04
CN104137170B (en) 2017-03-15
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US20150015558A1 (en) 2015-01-15
KR20140140019A (en) 2014-12-08

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