TW201418933A - Apparatus and method of controlling clock signals - Google Patents

Abstract

The invention discloses an apparatus and a method of controlling clock signals for a master device and a slave device. The apparatus includes a first connection port coupled to a first clock line of the master device; a second connection port coupled to a second clock line of the slave device; and a control module receiving a first clock signal from the master device through the first connection port, producing a second clock signal according to the first clock signal, and transmitting the second clock signal to the slave device through the second connection port; wherein when the first clock signal switches from a first logic level to a second logic level, the control module makes the first connection port retain the second logic level in a time interval.

Description

Clock signal control device and control method

The invention relates to a control device and a control method, in particular to a control device and a control method for a clock signal.

Common serial bus interface, using two signal control lines: serial data line (SDA) and serial clock line (SCL) clock signal, in multiple products The connection between the master and slave devices and the data transfer between the bulk circuits or the wafers, such as the interconnection of internal integrated circuits (I ² C).

In the prior art, the master device and the slave device, such as the internal integrated circuit connection, can control the level on the clock line directly connected to each other, thereby generating a clock signal with high and low level changes to achieve data between the master and slave devices. Synchronous clock control for transmission, etc.

However, some electronic components, such as electronically erasable rewritable read-only memory (EEPROM), are often limited in their available address space, so that when several of these electronic components are used as slave devices, they may occur due to insufficient address space. Addressing repetition or conflicting errors; in order to solve this problem, it is conventional practice to control the switching connection through a switching device between the master device and the slave device, but the additional switching device incurs a cost burden and design complexity. Moreover, the addition of other control means between the master device and the slave device may cause problems in that the clock control between the master device and the slave device is not synchronized.

The master-slave device is not synchronized because the adding control device is disposed between the master device and the slave device, so that the clock line directly connected between the master device and the slave device is interrupted, so that the master device cannot directly judge from the clock line whether the slave device has Complete the current Work, therefore, it is necessary to further develop the control technology of the clock signal.

The invention provides a control device, which is suitable for a main device and a slave device. The control device comprises: a first connection port connected to one of the first clock lines of the main device; and a second connection port connected to the slave device a second clock line; and a control module, the first port receives a first clock signal sent by the master device, and generates a second clock signal corresponding to the first clock signal, and the second The clock signal is transmitted from the second port to the slave device. When the first clock signal is switched from a first logic level to a second logic level, the control module controls the first port to be maintained for a time. The second logical level.

The present invention further provides a control method, which is applicable to a master device and a slave device, and includes the following steps: receiving, by a control module, a first clock signal sent by the master device through a first port; the control module is based on The first clock signal correspondingly generates a second clock signal, and sends a second clock signal to the slave device through a second port; the control module detects the first port, when the first clock signal is When the logic level is switched to a second logic level, the control module controls the first port to maintain the second logic level; and after a lapse of time, the control module stops controlling the first port to make the first connection埠Respond to the first logical level.

In general, most electronic devices or electronic products use related control devices or components to control and execute related functions. The control device or component may be a complex programmable logic device (CPLD), a field programmable gate array. (FPGA), or a microcontroller, so the present invention uses this existing control device to design and control the clock signal of the master and slave devices. Therefore, the cost of additionally setting the switching device can be saved, and the control method disclosed by the present invention further solves the problem that the clock control may be asynchronous after the control device is involved in the master-slave device.

In order to be able to further understand and understand the features, objects and functions of the present invention, the following detailed description will be made in conjunction with the drawings: FIG. 1 is a first embodiment of the present invention, and the control device 130 is applied to an internal integrated circuit (I). ² C) Block diagram of the wiring system 100, the internal integrated circuit wiring system 100 includes a main device 110 and a slave device 120. The control device 130 includes a first port 131, a second port 132, and a control module 135. The first port 131 is connected to the host device 110 by a first clock line 116. The second connection The 埠132 is connected to the slave device 120 by a second clock line 126; thereby, the control device 130 is adapted to the master device 110 and the slave device 120 of the internal integrated circuit wiring system 100. The first clock line 116 and the second clock line 126 are serial clock lines used by the main device 110 and the slave device 120 for interconnecting the internal integrated circuit, respectively, and the serial data of the master device 110 and the slave device 120. The manner of connecting the wires is not limited in the present invention. In addition, the control device 130 can be implemented by using a programmable logic component, such as a complex programmable logic component or a field programmable gate array, or a microcontroller, and the first port 131 and the second port 132 are The corresponding input/output (I/O) 埠, and the control module 135 is a unit or module having processing functions such as calculation, judgment, and control, but the present invention does not limit this.

Referring to FIG. 1, when the main device 110 sends a first clock signal (not shown) The control module 135 receives the first clock signal by the first port 131 and the first clock line 116, and performs clock signal processing according to the first clock signal, and correspondingly generates a second The clock signal (not shown) will be described later in detail; the control module 135 transmits the second clock signal to the slave device 120 via the second port 132 and the second clock line 126.

In this embodiment, the control device 130 of the present embodiment forcibly extends the logical low-level clock of the first clock signal of the main device 110 in order to prevent the problem that the master-slave device of the internal integrated circuit is not synchronized. The clock signal of the master device 110 can be applied to each of the slave devices 120 having different clock cycle lengths. Therefore, when the first clock signal received by the first port 131 is switched from a logic high level to a logic low level, the control module 135 will control the first port 116 to maintain a logic low level. The time is extended to extend the logic low level state of the serial clock line of the master device 110, so that the slave devices 120 have sufficient time to complete the current work without occurrence of out of synchronization.

To extend the logic low level state of the first port 131, this embodiment discloses two approaches. First, the control device 130 changes the setting of the output/input port as the first port 131; for example, the control module 135 changes the setting of the first port 131 to the output port, and further directly sets the first port. The output of 131 is a logic low level signal (not shown). Another method of direct grounding, as shown in FIG. 2, the control device 130 further includes a grounding port 133. The control module 135 connects the first port 131 to the grounding port 133 to force the first port 131 to be maintained. The logic low level state; it should be noted that the control connection of the control module 135 to the first port 131 and the ground port 133 may be directly performed inside the control device 130, for example, the complex programmable logic device directly connects the two Feet, or The control of the connection between the first port 131 and the ground port 133 of the control module 135 may be performed by other circuits outside the control device 130, but the invention is not limited thereto.

The length of time for maintaining the logic low level state of the first port 131 may be a preset time of a fixed length or dynamically adjusted by the slave devices 120 to maintain the length of time. If the length of time is fixed, the control module 135 directly sets the preset time by the program command to control the first port 131 to maintain the logic low level state within the preset time. The time to maintain the low level is a dynamically adjustable aspect, which will be detailed later.

In this embodiment, after the control module 135 receives the first clock signal sent by the main device 110 via the first port 131, the switching device is not directly and unswitched to transmit to the slave device 120 as is conventional. Instead, the control module 135 processes the clock signal to generate a corresponding second clock signal according to the first clock signal, and transmits the second clock signal to the slave device 120 via the second port 132. In order to generate the second clock signal to the slave device 120, the embodiment of the present invention discloses two modes. The first mode is that the control module 135 can directly write the output signal as the second clock signal to the second connection.埠132, the method directly sets the second clock signal to a logic low level signal or a logic high level signal, wherein the logic low level signal is a logic “0” signal, which is grounded in this embodiment. The bit high, and the logic high level signal is a logic "1" signal, which is the level of the voltage source in this embodiment, but the invention is not limited thereto.

In the second mode, referring to FIG. 2, if a second clock signal of a logic low level signal is generated, the control module 135 can connect the second port 132 to the ground port 133, and the second connection. Generate a second clock on 埠132 The logic low level signal of the signal; and if a logic high level signal is to be generated, the control device 130 may further include a high level bias voltage 134 connected to a voltage source through a pull-high impedance 138. Vcc, and the control module 135 generates a logic high level signal of the second clock signal by connecting the second port 132 to the high level bias 埠 134. Please note that the control technology of the control device 130 for the related pin connection is not described in detail in the foregoing embodiment, and the logic low level signal and the logic high level signal of the embodiment may be generated by the foregoing One mode or the second mode or a combination of interactions thereof, such as generating a logic high level signal by setting an output signal and generating a logic low level signal by connecting to a ground ,, but the present invention combines the same The situation is not limited.

As shown in FIG. 2, when the control device 130 includes both the ground 埠 133 and the high level bias 埠 134, the time for extending the logic low level state of the first port 131 can be dynamically adjusted. When the first clock signal received by the first port 131 is switched from the logic high level to the logic low level, the control module 135 is connected to the second port 132 to the ground port 133 to correspondingly generate the second clock signal. The logic low level signal, the second clock line 126 is controlled by the slave device 120, and the control module 135 switches the second port 132 to the high level bias 埠 134 and detects the second connection.埠132, if the slave device 120 is still in operation, it will control the second clock line 126 to maintain the low level state, until the slave device 120 finishes working, then the control of the second clock line 126 is released, so that the second connection is made. The 埠132 will return to the logic high level by the logic low level because it is connected to the high level 埠134, so that the control module 135 stops the control of the first port 131 by this, and the detection of each slave device 120 is achieved. When the first port 131 is dynamically adjusted to maintain the logic low level Length between.

3 is a flow chart of a clock signal control method 300 according to a second embodiment of the present invention, which is directed to controlling the clock signal of a master device and a slave device of an internal integrated circuit. The control method 300 includes the following steps: (step 320) receiving, by a control module, a first logic high level signal sent by the master device through a first port; (step 340) controlling the module according to the first logic level The bit signal correspondingly generates a second logic high level signal, and sends a second logic high level signal to the slave device through a second port; (step 360) the control module detects a logic level change of the first port When the master device switches to send a first logic low level signal, the control module controls the first port to maintain a logic low level, and generates and sends a second logic low according to the first logic low level signal. After the level of the signal to the slave device; and (step 380), the control module stops controlling the first port, and causes the first port to reply to receive the first logic high level signal.

In order to more clearly describe the embodiment of the control method 300, reference is made to the block diagram of the main device 410 and the slave device 420 for the internal integrated circuit connection of FIG. 4 and the timing diagram of the clock signal operation thereof. The internal integrated circuit connection of the embodiment is transmitted through the control device 430 having the first connection port 431, the second connection port 432, and the control module 435, and the operation of the clock signal is performed by using the control method 300 of the embodiment. Take control. In this embodiment, the clock signal sent by the main device 410 is preset to a logic high level. When the control module 435 receives the logic high level signal (ie, the first logic high level signal described in step 320) through the first port 431, correspondingly generates the second logic high level signal described in step 340, and Transmitted to the slave device 420 through the second port 432. When the clock signal of the main device 410 is switched to a logic low level The control module 435 detects the logic level change on the first port 431 (ie, the first logic low level signal sent by the host device 410 in step 360), and maintains the first port 431. The logic low level state is a period of time; at the same time, the control module 435 correspondingly generates the second logic low level signal described in step 360, and sends the signal to the slave device 420. After a period of time, the control module 435 stops the control of the first port 431, and returns the first port 431 to the logic high level state (ie, after a lapse of time as described in step 380, the control module Suspending the control of the first port 埠) and restoring the clock signal of the internal integrated circuit connection to the aforementioned preset condition. The left clock picture at the bottom of FIG. 4 is the clock signal on the first port 431, and the right clock picture is the clock signal on the second port 432; wherein the solid line indicates that the clock signal of the time is Controlled by the control module 435, the dotted line indicates that the signal for this period of time is determined by the control of the host device 410.

The manner in which the master device 410 generates the clock signal may be based on a technique of interconnecting the internal integrated circuit, generating a logic high level through a pull-up impedance 438 connected to the voltage source Vcc, and generating a logic low level through the ground. However, it is not limited to this; therefore, the length of time that the clock signal is maintained after being grounded to the logic low level state is controlled by the control module 435, so even if the master device 410 has the clock line and The ground connections are separated, but the clock line is still controlled by the control module 435 and maintained at a logic low level.

In this embodiment, the control module 435 performs signal processing on the clock signal sent from the host device 410, and generates and transmits another clock signal to the slave device 420. The manner in which the control module 435 generates the clock signals of the logic high level signal and the logic low level signal to the slave device 420 is as described in the foregoing embodiment and will not be repeated. Control module 435 maintains or extends the main The manner in which the device 410 is in the logic low level state is as described in the foregoing embodiment and will not be repeated. The length of time that the control module 435 extends to the low-level state of the main device 410 may be a fixed time length and a fixed time. If the length of the extended time is fixed, it will not be repeated as explained in the foregoing embodiment.

If the control device 430 of the foregoing embodiment has both a high-level bias voltage and a ground 埠, the length of the extended time can be adjusted dynamically. 5A to 5D are timing diagrams of the main device 410 and the slave device 420 connected to the internal integrated circuit and the timing diagram of the clock signal operation thereof. As shown in FIG. 5A, the labels on the clock signal correspond to the foregoing. The operational steps of the examples. First, the master device 410 transmits a logic high level clock signal (step 320). When the control module 435 receives the logic high level signal through the first port 431, the second port 432 is connected to the high level voltage 埠 434 to generate a logic high level signal and send it to the slave. Apparatus 420 (step 340). As shown in FIG. 5B, when the clock signal of the main device 410 is switched to the logic low level (one of the steps 360, as shown in FIG. 360-1), the control module 435 detects the first connection port 431. The logic level changes, and the second port 432 is switched to the ground 埠 433 to generate a logic low level signal and sent to the slave device 420 (step 360 bis, as shown in FIG. 360-2); as shown in FIG. 5C The control module 435 maintains a logic low level state on the first port 431 (step 360, as shown in FIG. 360-3). Due to the logic level of the clock line between the slave device 420 and the control module 435, the slave device 420 has been controlled to the logic low level by way of connection to the ground or the like according to the specifications of the internal integrated circuit connection; The control module 435 then switches the second port 432 to the high level bias 埠 434 and detects the clock change on the second port 432 (step 360, As shown in the figure 360-4). As shown in FIG. 5D, when the slave device 420 releases the control of the logic level of the pulse at this time (one of the steps 380, as shown in FIG. 380-1), the second port 432 also returns to the logic high level. The state (step 380 bis, as shown in FIG. 380-2), the control module 435 also detects that the second port 432 returns from the logic low level to the logic high level, and stops controlling the first port 431, so that The first port 431 returns to the logic high level state (step 380-1). Thereby, the effect of dynamically adjusting the logic low level state of the first port 431 for a length of time by detecting the logic level state of each of the second ports 432 is achieved.

The control device of the embodiment of the present invention is controlled for the master-slave device of the serial bus interface, which can save the cost of additionally setting the switch device, and solves the problem that some electronic components may become insufficient due to insufficient address space when acting as a slave device. In the meantime, the control method disclosed in the embodiment of the present invention solves the problem that the clock control may be out of synchronization after the intervention of the control device by setting and controlling the extension time of a level state.

The operation description of each of the above embodiments is exemplified by the internal integrated circuit connection of the serial bus interface, and the case where the clock signal is switched from the logic high level to the logic low level is taken as an example. A logic level is set to a high level, and a second logic level is set to a low level; however, the invention is not limited thereto, and the technique of the present invention can also be applied to other connection protocols or specifications of a serial bus interface. Therefore, the present invention can also be applied to the case where the clock signal is switched from the logic low level to the logic high level, or the communication technology other than the internal integrated circuit connection. The clock signal control technology disclosed in the present invention can be directly Realize the control of high and low logic levels. In addition, various avoidance designs for reversing the clock signal path of the internal integrated circuit wiring are also included in the disclosure of the present invention.

The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto. It is to be understood that the scope of the present invention is not limited by the spirit and scope of the present invention.

100‧‧‧Internal integrated circuit wiring system

110/410‧‧‧Main device

116‧‧‧First Timeline

120/420‧‧‧ slave device

126‧‧‧second clock line

130/430‧‧‧Control device

131/431‧‧‧First port埠

132/432‧‧‧Second connection埠

135/435‧‧‧Control Module

133/433‧‧‧ Grounding埠

134/434‧‧‧High-level bias voltage埠

138/438‧‧‧Upper impedance

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing the wiring of an internal integrated circuit in accordance with a first embodiment of the present invention.

2 is a block diagram showing another internal integrated circuit connection according to the first embodiment of the present invention.

3 is a flow chart showing a method of controlling the wiring of an internal integrated circuit according to a second embodiment of the present invention.

4 is a timing diagram of a wiring diagram of an internal integrated circuit and a timing signal operation thereof according to a second embodiment of the present invention.

5A to 5D are timing diagrams showing another internal integrated circuit wiring block diagram and its operation of the clock signal according to the second embodiment of the present invention.

410‧‧‧Main device

420‧‧‧ slave device

430‧‧‧Control device

431‧‧‧First port

432‧‧‧Second connection

435‧‧‧Control Module

438‧‧‧Upper impedance

Claims (14)

A control device is applicable to a master device and a slave device, the control device comprising: a first port connected to a first clock line of the main device; and a second port connected to the slave device a second clock line; and a control module, the first port receives a first clock signal sent by the master device, and generates a second clock signal corresponding to the first clock signal, and Transmitting the second clock signal from the second port to the slave device, wherein the control module controls the first clock signal when the first clock signal is switched from a first logic level to a second logic level The first connection maintains the second logic level for a period of time. The control device of claim 1, wherein the control module controls the first port to maintain the second logic level to set the first port as an output port, and sets the first connection The output of 埠 is a second logic level signal. The control device of claim 1, further comprising a grounding 埠 and a high-level bias 埠, the high-level bias 连接 being connected to a voltage source through a pull-up impedance, wherein the control mode The group controls the first port to maintain the second logic level to connect the first port to the ground or the high level bias. The control device of claim 1, wherein the control module generates the second clock signal to set the second clock signal as a first logic level signal or a second logic level signal. . The control device of claim 1, further comprising a grounding 埠 and a high-level bias 埠, the high-level bias 埠 being transmitted through a pull-up resistor The connection is connected to a voltage source, wherein the control module generates the second clock signal to connect the second port to the ground or the high level bias. The control device of claim 1, wherein the control module controls the first connection to maintain the second logic level within the time, the time being a preset time. The control device of claim 5, wherein the first logic level is a high logic level, the second logic level is a low logic level, and the control module is connected to the second connection. The grounding port is configured to generate a low logic level signal of the second clock signal, and the control module further switches to connect the second port to the high level bias port, when the second port is connected When the low logic level is switched to the high logic level, the control module stops controlling the first port. A control method is applicable to a master device and a slave device, comprising the steps of: receiving, by a control module, a first clock signal sent by the master device through a first port; the control module is configured according to the first The first clock signal generates a second clock signal, and the second clock signal is sent to the slave device through a second port; the control module detects the first port, when the first clock When the signal is switched from a first logic level to a second logic level, the control module controls the first port to maintain the second logic level; and after a lapse of time, the control module stops controlling the The first port is configured to cause the first port to reply to the first logic level. The control method of claim 8, wherein the control module controls the first port to maintain the second logic level according to a preset time. The control method of claim 8, wherein the control module generates and transmits the second clock signal, and the control module sets the output of the second port as a first logic Bit signal or a second logic level signal. The control method of claim 8, wherein the control module generates and transmits the second clock signal, and the control module connects the second port to a high level bias. Or a ground 埠, wherein the high level bias 连接 is connected to a voltage source through a pull-up impedance. The control method of claim 8, wherein the control module controls the first port to maintain the second logic level, and the control module sets the first port as an output.埠, and set the output of the first port as a second logic level signal. The control method of claim 8, wherein the control module controls the first port to maintain the second logic level, and the control module connects the first port to a ground埠 or a high-level bias 埠, wherein the high-level bias 连接 is connected to a voltage source through a pull-up impedance. The control method of claim 11, further comprising the following steps: when the first logic level is a high logic level, and the second logic level is a low logic level, the control module Connecting the second connection port to the ground 埠 to correspondingly generate a low logic level of the second clock signal The control module further switches the second port to the high-level bias voltage; and when the second port returns to the high logic level by the low logic level, the control module stops Controlling the first port.