TW201418732A - Testing method for chip package and its system - Google Patents

Abstract

A testing method for chip package and its system, the method includes packing a chip installed on a motherboard. Providing an operating power through a power supply unit and making the motherboard operation. Establishing communication channel between the t motherboard and a controlling-device and sending a test signal to the motherboard for testing chip. Finally, checking the chip is normal operation in accordance with the testing results of the chip. By the way to head off defective products to ensure quality of products, and controlling production real-time to save the testing time of production.

Description

Chip package test method and system thereof

The present invention relates to a wafer package test method and system thereof, and more particularly to a chip package test method and system for powering a motherboard to directly test whether the wafer is functioning normally after the wafer is attached to the motherboard.

Since the quality and condition of the wafer used in the Multi-Chip Package (MCP) are different, it is necessary to determine the quality of the integrated circuit (IC) by a complete test method. Conventionally, in general integrated circuit (IC) application manufacturers must use special Ball Grid Array (BGA) fixtures and applications to determine the quality of the integrated circuit (IC) test. Therefore, even if it is a good integrated circuit (IC) that is determined before the attachment, it is still difficult to determine whether it is a working integrated circuit (IC) after the patch is placed on the mainboard (MB). At this time, the motherboard (MB) and the machine must be installed as a complete machine, and functional tests must be performed to determine whether the integrated circuit (IC) of the chip to the motherboard (MB) can be used.

When the motherboard (MB) and the machine are installed as a complete machine, if the integrated circuit (IC) on the motherboard (MB) is found to be inoperable (or defective), it will require a large maintenance cost to repair, so even if it is known The chip is faulty. Since the defective chip has been packaged into a machine with the motherboard (MB), it must be disassembled and reassembled, resulting in loss of production efficiency, increased inventory defects, increased repair costs, and impaired performance. influences.

The invention provides a chip packaging test method and a system thereof, which enable the integrated circuit on the motherboard to be directly tested after being attached, so as to improve the convenience of testing and achieve the purpose of cost saving.

The invention provides a chip packaging test method, and the steps include: Mounting a chip on a motherboard, providing a working power through a power supply unit, causing the motherboard to operate, then establishing a communication channel between the motherboard and a control device, and transmitting a test signal by using the control device Go to the motherboard for wafer testing, and finally, verify that the wafer is functioning properly based on the test results of the wafer.

In an embodiment of the invention, the chip is mounted on the chip The step on the motherboard further includes: establishing a board including a plurality of motherboards; and installing a chip on each of the motherboards of the board.

In an embodiment of the invention, the chip is mounted on the chip The step on the motherboard further includes: placing the motherboard on which the wafer is mounted into a device to be inspected.

In an embodiment of the invention, the step of establishing a communication pipeline The method includes: connecting one of the wireless communication units of the device to be detected through one of the wireless communication units of the control device, and establishing a communication device between the control device and the device to be detected by wireless communication.

In an embodiment of the invention, the step of establishing a communication pipeline The method includes: connecting a communication unit of one of the control devices and one of the devices to be detected through a cable, and establishing a communication device of the control device and the device to be detected by electrical connection.

The invention provides a chip package test system, including a host A board, a power supply device and a control device. The motherboard is provided with a chip, and the power supply device provides a working power to make the motherboard display a working state. The control device establishes a communication pipeline with the motherboard through a communication unit to send a test signal to the motherboard for testing the chip. According to the test results of the wafer, it is checked whether the wafer is in normal operation.

In an embodiment of the invention, the plurality of motherboard boards are connected Into a board, the board is placed in a tool for wafer testing.

In an embodiment of the present invention, a device to be detected is further included The motherboard with the chip is mounted, and the device to be tested is provided with a communication port.

In an embodiment of the invention, the communication unit and the communication unit It is one of a Bluetooth device and an infrared device.

In an embodiment of the invention, the communication unit and the communication unit The system is a universal serial bus connection port, and is connected to a universal serial bus connection port of the communication port and the communication unit through a cable, so that the communication port and the communication unit establish a communication pipe.

The invention can be carried out without assembling the motherboard into the electronic device Testing, thus saving the cost of hardware testing instruments in the production process, and also eliminating manual operations, effectively intercepting the outflow of defective products, improving product quality, realizing immediate control of production, saving test time and improving product delivery time. Production efficiency.

100‧‧‧Device to be tested

110‧‧‧Communication埠

120‧‧‧ motherboard

130‧‧‧ wafer

200‧‧‧Control device

201‧‧‧Control program

210‧‧‧Communication unit

220‧‧‧ display unit

300‧‧‧Power supply unit

310‧‧‧正正

320‧‧‧negative

400‧‧‧ cable

420‧‧‧ 联板

S110~S160‧‧‧Step procedure

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of components of a wafer package test system of the present invention.

2A is a schematic diagram of an embodiment of the present invention for testing using wireless communication.

2B is a schematic diagram of an embodiment of the present invention for testing using wired communication.

Fig. 3 is a schematic view showing a connecting board formed by connecting a plurality of motherboards in the present invention.

4 is a flow chart corresponding to the steps of the wafer package test method of FIG. 1.

5 to 7 are schematic flow charts showing a method of testing a wafer package according to an embodiment of the present invention.

The above described features and advantages of the present invention will be more apparent from the following description.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of components of a wafer package test system of the present invention. in In FIG. 1, the chip package test system includes a device to be detected 100, a control device 200, and a power supply device 300. The device to be tested 100 includes a communication port 110 and a motherboard 120. A chip 130 is packaged on the motherboard 120. The power supply device 300 provides an operational power to cause the motherboard 120 to assume an operational state.

The control device 200 is established with the motherboard 120 through a communication unit 210. A communication pipe, the communication pipe can be wireless communication or wired communication, and the relevant communication mode should be explained later. The control program 201 of the control device 200 transmits a test signal to the device to be detected 100 through the communication unit 210, and receives the test signal through the communication port 110 of the device 100 to be detected, to perform the performance test of the chip 130 on the motherboard 120, and according to the chip. The performance test result of 130 checks whether the wafer 130 is operating normally. If it is in a normal operation state, the motherboard 120 on the device to be tested 100 is assembled with the electronic device; if it is not in a normal operation state, the wafer 130 is self-supported. The 120 is removed to replace the new wafer 130.

In this embodiment, in this embodiment, further, please Referring to FIG. 3, FIG. 3 is a board 420 (printed circuit board) formed by connecting the above-mentioned motherboard 120 with a plurality of motherboards 120, and the slab 420 is placed in a metallurgical tool, and the slab is made by using a metallurgical tool. Capacitance testing, performance, and operation of the wafer on a printed circuit board (PCB).

Please refer to FIG. 2A and FIG. 2B simultaneously, FIG. 2A is a wireless device of the present invention. A schematic diagram of an embodiment of communication testing. 2B is a schematic diagram of an embodiment of the present invention for testing using wired communication.

In FIG. 2A, the communication port 110 of the device to be detected 100 is a blue The bud device or an infrared device, and the communication unit 210 of the control device 200 is disposed corresponding to the communication port 110 of the device 100 to be detected, and the communication port 110 and the communication unit 210 are simultaneously a Bluetooth device, or the communication port 110 and the communication unit 210. At the same time, it is an infrared device, whereby the device to be detected 100 and the control device 200 establish a communication pipe through the Bluetooth device or the infrared device, so that the device to be detected 100 and the control device 200 transmit data through the communication pipe.

The difference between FIG. 2B and FIG. 2A lies in the communication of the device to be detected 100. The 埠110 is a universal serial bus connection port, and the communication unit 210 of the control device 200 is also a universal serial bus connection port. The two are electrically connected through a cable 400, so that the communication device 110 of the device to be detected 100 The communication unit 210 of the control device 200 establishes a communication pipe through the electrical connection of the cable 400, and uses the cable 400 to enable the device to be detected 100 and the control device 200 to transmit data through the communication pipe.

Please refer to FIG. 4, which illustrates the flow of the test project management method corresponding to FIG. FIG. 5 to FIG. 7 are schematic diagrams showing details of a wafer package test method according to an embodiment of the present invention. Please refer to Figure 1 to Figure 3 for help. The method flow is as follows: Figure 4 is a flow chart corresponding to the steps of an embodiment of the present invention. In FIG. 4, the main steps are as follows: Step S110: A wafer 130 is mounted on a motherboard 120, and the motherboard 120 on which the wafer 130 is mounted is placed in a device 100 to be inspected, and even more A plurality of motherboards 120 are coupled into a single board 420 to place the board 420 in a tool for testing the wafer 130.

As shown in FIG. 3, a plurality of motherboards 120 can be connected into a single board 420. For the test, the detailed implementation of this step is as shown in FIG. 5, and a board 420 including a plurality of motherboards 120 is established (step S111) and installed on each motherboard 120 of the board 420. A wafer 130 (step S119).

Step S120: providing a working power through a power supply unit 300 The power supply unit 300 is preferably in a running state, and the power supply unit 300 is preferably a continuous power source, and simultaneously transmits the positive power 310 and the negative power 320 to the motherboard 120 to cause the motherboard 120 to assume an operational state.

Step S130: re-transmitting through one of the control units 200 of the communication unit 210 A communication port 110 of the device to be detected 100 is connected to establish a communication pipe of the control device and the device to be detected. In this step, the details of the steps are different depending on the manner of wired or wireless communication.

As shown in Figure 2A, if the communication pipe is established by wireless communication, then this The detailed implementation of the step is as shown in FIG. 6, through a wireless communication unit of a control device to connect one of the wireless communication devices of the device to be detected (step S131), and the wireless communication unit and the wireless communication device are preferably Bluetooth devices. Or an infrared device. A wireless communication pipe of the control device and the device to be detected is established (step S139).

As shown in Figure 2B, if the communication pipeline is established by wired communication, then this The detailed implementation of the step is as shown in FIG. 7, and a communication unit of one of the control devices and one of the devices to be detected are connected via a cable 400 (step S132), the communication list Preferably, the meta-communication port is a universal serial bus port, and the two are electrically connected through a cable 400 to establish a communication pipe (step S139).

Step S140: Send a test signal to the control device 200 to wait for The motherboard 120 of the device 100 is tested for testing of the wafer 130.

Step S150: judging whether the wafer is positive according to the test result of the chip In the normal operation state, the motherboard 120 on the device to be tested 100 is assembled with the electronic device, and step S160 is performed; if not in the normal operation state, the wafer 130 is detached from the motherboard 120. The new wafer 130 is replaced and returned to step S120 for re-inspection.

Step S160: Generate a corresponding prompt message according to the judgment result.

In summary, the present invention should have the following advantages:

1. The present invention can perform integration on a motherboard (MB) after patching. Circuit (IC) testing to determine the availability of integrated circuits (ICs). By the invention, the test result can be quickly tested and obtained with high accuracy, so that the manufacturer of the integrated circuit (IC) can confirm the early use of the integrated circuit (IC) on the motherboard (MB) after the patch is found. The problem is in line with the principle of “the lower the cost of failure to pay for the discovery of NG (NG) products”.

2. The test program is automatically tested in the present invention, and the host board (MB) is automatically determined. The integrated circuit (IC) uses efficiency, the control device can be connected to the Statistical Process Control (SPC), or the integrated circuit (IC) on the motherboard (MB) can be tested separately without the statistical process control (SPC). Bad to match various production process applications.

3. The invention can effectively save the hardware testing instrument in the production process Cost, through machine testing, can avoid the negligence of manual operation and effectively intercept the output of defective products, so as to improve the quality of the products shipped, and realize the immediate control of production, saving test time.

Although the present invention is disclosed above in the foregoing embodiments, it is not used The invention is not limited by the spirit and scope of the present invention, and the equivalent replacement of the modification and retouching is still the scope of patent protection of the present invention. Inside.

S110~S160‧‧‧Step procedure

Claims (10)

A chip package testing method includes the steps of: mounting a chip on a motherboard; providing a working power through a power supply unit to cause the motherboard to operate; establishing a communication channel between the motherboard and a control device Using the control device to send a test signal to the motherboard for testing the chip; and verifying whether the wafer is functioning properly according to the test result of the chip. The chip package test method of claim 1, wherein the step of mounting a chip on a motherboard further comprises: establishing a board including a plurality of motherboards; and each of the boards A chip is mounted on each of the motherboards. The chip package test method of claim 1, wherein the step of mounting a wafer on a motherboard further comprises: placing the motherboard on which the wafer is mounted into a device to be inspected. The method of claim 3, wherein the step of establishing the communication pipeline comprises: connecting a wireless communication unit of the device to be detected to a wireless communication unit of the control device to establish a wireless communication manner The control device and the communication pipe of the device to be detected. The chip package test method of claim 3, wherein the step of establishing the communication pipe comprises: connecting a communication unit of one of the control devices and one of the devices to be detected through a cable to electrically The connection mode establishes the communication device and the communication pipe of the device to be detected. A chip package test system comprising: a motherboard, which is provided with a wafer; and a power supply device that provides an operating power to render the motherboard in an operational state; A control device establishes a communication pipe with the motherboard through a communication unit to send a test signal to the motherboard, perform the test of the chip, and check whether the wafer is in normal operation according to the test result of the chip. The chip package test system of claim 6, wherein the plurality of motherboards are connected into a single board to place the board in a tool for testing the wafer. The chip package test system of claim 6, further comprising a device to be inspected for placing the motherboard on which the wafer is mounted, the device to be detected being provided with a communication port. The chip package test system of claim 8, wherein the communication port and the communication unit are one of a Bluetooth device and an infrared device. The chip package test system of claim 8, wherein the communication port and the communication unit are respectively a universal serial bus port, and are connected to the communication port and the communication unit through a cable. The universal sequence bus is connected to enable the communication port and the communication unit to establish the communication pipe.