TW201347100A - A method of manufacturing silicon-on-insulator wafers - Google Patents

Abstract

A method is provided for preparing multilayer semiconductor structures, such as silicon-on-insulator wafers, having reduced warp and bow. Reduced warp multilayer semiconductor structures are prepared by forming a dielectric structure on the exterior surfaces of a bonded pair of a semiconductor device substrate and a semiconductor handle substrate having an intervening dielectric layer therein. Forming a dielectric layer on the exterior surfaces of the bonded pair offsets stresses that may occur within the bulk of the semiconductor handle substrate due to thermal mismatch between the semiconductor material and the intervening dielectric layer as the structure cools from process temperatures to room temperatures.

Description

Method of manufacturing a wafer on an insulator

The field of the invention relates generally to a method of fabricating a multilayer semiconductor structure (e.g., a wafer on insulator) having reduced warpage and curvature.

A semiconductor wafer is typically prepared from a single crystal ingot (e.g., tantalum ingot) that has been trimmed and ground to have one or more planes or notches for proper orientation of the wafer in subsequent processes. The ingot is then cut into individual wafers. Although reference will be made herein to semiconductor wafers constructed from tantalum, other materials such as tantalum, tantalum carbide, tantalum telluride or gallium arsenide may be used to prepare semiconductor wafers.

Semiconductor wafers, such as germanium wafers, can be used to fabricate composite layer structures. A composite layer structure (e.g., a structure of a germanium on insulator (SOI)) generally includes a handle wafer or handle layer, a device layer, and an insulating (i.e., dielectric) film between the handle layer and the device layer (usually an oxide layer). The thickness of the device layer is typically between 0.05 microns and 20 microns. In general, a composite layer structure such as on-insulator (SOI), sapphire upper (SOS), and quartz ruthenium is produced by intimately contacting two wafers and then performing a heat treatment.

After thermal annealing, the bonded structure is subjected to further processing to remove a substantial portion of the donor wafer to effect layer transfer. For example, wafer thinning techniques (such as etching or grinding), commonly referred to as etch back SOI (ie, BESOI), can be used, where a wafer is bonded to the processing wafer and then slowly etched until processing Only one thin layer of germanium remains on the wafer. (example See, for example, U.S. Patent No. 5,189,500, the disclosure of which is incorporated herein by reference. One of the particular challenges in the preparation of SOI structures is the presence of warpage or tortuosity, especially when buried oxide (BOX) is facilitated by the bonding surface of the device wafer. If the BOX thickness is different (usually greater than) the thickness of the oxide on the back side of the support wafer, the SOI wafer will have a high degree of warpage or curvature that exceeds an acceptable limit. High warpage or curvature can cause various problems, such as the processing of SOI wafer lines and manufacturing lines.

Thus, in short, the present invention is directed to a method of making a multilayer semiconductor structure. The method sequentially includes the steps of: (a) forming a dielectric layer on a front surface of one of the semiconductor device substrates, the semiconductor device substrate including two substantially parallel major surfaces (one of which is the semiconductor device a front surface of the substrate and the other of the substrate is a rear surface of the semiconductor device substrate, a circumferential edge of the front surface of the semiconductor device substrate and the rear surface, and the front surface of the semiconductor device substrate And a central plane between the rear surface; (b) bonding the front surface of the semiconductor device substrate having the dielectric layer to a front surface of a processing substrate to thereby form a bonding structure, wherein the processing substrate Having two substantially parallel major surfaces (one of which is the front surface of the processing substrate and the other of which is the back surface of the processing substrate), the front surface of the processing substrate and the a rear surface is bonded to a circumferential edge and a central plane between the front surface and the rear surface of the processing substrate; and (c) a dielectric layer is formed on the rear surface of the processing substrate.

1 is a graph depicting a measured warpage (○) in an SOI structure prepared according to a conventional procedure and a measured warpage (□) in an SOI structure prepared according to the method of the present invention. The SOI structures were prepared according to the method described in Example 1.

The present invention is directed to a method for fabricating a multilayer semiconductor structure (eg, an insulator) A method of multilayer structure of germanium (SOI) wherein there is an overall reduced warpage and curvature in the final semiconductor composite multilayer structure. The multilayer semiconductor structure includes a device substrate, a processing substrate, and an intervening dielectric layer. In some embodiments, the method of the present invention is directed to the fabrication of a structure on an insulator that includes an oxide layer between an active layer of a device substrate and a handle substrate. This oxide layer is often referred to as a buried oxide (or "BOX"). In accordance with the method of the present invention, the BOX can be fabricated on the device substrate, the processing substrate, or both substrates prior to substrate bonding.

During the fabrication of a multilayer structure on an insulator, a dielectric layer (e.g., an oxide layer) can be formed on the surface prior to processing the substrate. Forming a dielectric layer on the surface of a semiconductor substrate (ie, the surface of either or both of the device substrate and the processing substrate) may result in stress in the substrate of the substrate that may or may not be sufficiently offset in the substrate of the substrate. . Thus, the dielectric layer can initiate stresses that can cause warpage and tortuosity in a final SOI. When the wafer is cooled from the temperature at which the dielectric is formed to room temperature, stress can be formed in a device and/or a processing substrate.

A dielectric layer (typically an oxide layer) can be formed on one or both of the device substrate and the front surface of the handle substrate at elevated temperatures. As used herein, the front surface of the substrate means the major surface of the substrate that forms the inner surface of the bonded structure when joined. Therefore, the rear surface means the main surface that becomes the outer surface of the joint structure. The temperature of the deposition generally exceeds 500 ° C and may even exceed 1000 ° C. In some embodiments, a dielectric layer (eg, (s) oxide layer) having substantially equal thickness and density may be deposited on both front surfaces of the device substrate and the processing substrate. When a substrate having a dielectric deposited on the front surface is moved to a room temperature environment, both the substrate (e.g., germanium) and the dielectric layer (e.g., hafnium dioxide) shrink at different rates. The different shrinkage rates are attributed to the different coefficients of thermal expansion of the autogenous substrate material and the deposited dielectric layer. For example, helium has a coefficient of thermal expansion of 2.6 ppm/°C. Cerium oxide has a thermal expansion coefficient of 0.5 ppm/°C. In view of these different coefficients, 矽 expands or contracts more than cerium oxide in response to temperature changes. When the substrate having the dielectric deposited thereon is cooled from the deposition temperature At room temperature, differential shrinkage causes stress to be input into the substrate.

In some processes, a substrate (device substrate or processing substrate or both) may be provided with a dielectric layer (eg, an oxide layer) on both the front and back surfaces. In such embodiments, the stress induced by the differential shrinkage in the front surface dielectric layer can be counteracted by the stress from the back dielectric layer. Therefore, the total stress on the substrate can be minimized. However, when the dielectric layer is removed from one side of the substrate and the opposite surface of the substrate has a dielectric layer, the difference in shrinkage between the autogenous substrate structure and the remaining dielectric on the surface having the dielectric The stress can be input to the substrate during subsequent high temperature program steps.

In other processes, stress can be input into a substrate after the device wafer is bonded to the processing wafer and during the thinning process. In this context, the oxide layer on the back side of the device wafer is removed, and the buried oxide (BOX) partially contributed by the device wafer is thicker than the oxide layer on the back side of the handle wafer. In this case, the stress from the backside oxide of the processing wafer does not completely offset the stress from the BOX. Unbalanced stresses on both surfaces can cause warping or bending in the substrate.

According to the method of the present invention, the stress induced by the intervening dielectric layer of one of the bonding structures can be counteracted by oxidizing the outer surface of the substrate after the processing substrate is bonded to the device substrate to form a bonding structure. Stresses caused by thermal expansion mismatch between the autogenous tantalum substrate and the dielectric layer are counteracted by depositing a dielectric on both the front and back surfaces of the bond pair, which results in a final SOI structure exhibiting and supporting prior to oxidation The warpage or curvature of the substrate is close to the minimum amount of warpage or curvature. Thus, in some embodiments, the method of the present invention is directed to counteracting the stresses induced by the dielectric layer (e.g., the BOX layer), thereby enabling the fabrication of semiconductor multilayer structures having low warpage or tortuosity.

In some embodiments in which a multilayer structure of an insulator is fabricated, a dielectric layer (e.g., an oxide layer) can be formed on both the front surface of the substrate and the front surface of the device substrate. Accordingly, the BOX layer can include a combination of one of the oxide layers from the processing substrate and the device substrate. In some processes, a BOX can be preferably prepared by combining two oxide layers. The layer, due to, for example, the desire to provide space between the active ruthenium layer and the bonding interface, as the bonding interface can be contaminated by metals and/or particles that can diffuse into the active ruthenium layer, thereby compromising the electrical properties of the device. Also due to certain applications, a BOX layer can be prepared by combining oxide layers from the processing substrate with the device substrate, wherein the device surface is roughened or uneven due to processing or patterning prior to bonding. To cover the uneven or rough front surface on the device wafer, an oxide such as a chemical vapor deposited oxide (CVD oxide) can be deposited on the device wafer prior to bonding. In embodiments in which the BOX is formed by an oxide layer deposited on the surface of both the device substrate and the processing substrate, the resulting multilayer SOI structure can have one of the stresses BOX contributing to the structure, processing the substrate and/or the device substrate (several The dielectric on the back surface does not adequately counteract these stresses because the BOX layer can be significantly thicker than the oxide layer on the back surface of the substrate and/or device substrate. The dielectric on the back surface of the device substrate and/or the processing substrate cannot counteract the stress induced by the BOX, which can result in an SOI multilayer structure having warpage or curvature exceeding an acceptable limit, and the structure can be employed A dome warped shape. SOI structures with high warpage or curvature cause serious problems in SOI wafer lines and manufacturing lines, such as processing. For example, a wafer manufacturer's maximum tolerance may allow warpage to be no greater than about 60 microns, while some processes may allow warpage to be no greater than 30 microns. The method of the present invention enables the fabrication of SOI structures having warpage within such wafer process tolerances. In other words, a multilayer semiconductor structure (such as an SOI structure) prepared in accordance with the methods of the present invention has a warpage of no greater than about 35 microns, no greater than about 30 microns, no greater than about 28 microns, or even no greater than about 25 microns.

In some embodiments, the present invention is directed to a method of fabricating a semiconductor multilayer structure comprising a dielectric layer having low warpage and curvature. The dielectric layer between a processing substrate and a device substrate is substantially one of the stressors that contribute to the warpage and curvature of the final multilayer structure. According to the method of the present invention, a dielectric layer (for example, a dielectric layer) can be offset by depositing a dielectric layer (eg, an oxide layer) on the surface of the device substrate, the processing substrate, or both the device substrate and the processing substrate. Relatively thick BOX layer Into the stress. The device substrate and/or the oxide layer deposited on the surface after the processing substrate can be deposited after bonding and prior to thinning the bonding device wafer. In a preferred embodiment, an oxide is deposited on the rear side surface of both the device substrate and the processing substrate. Through the method of the present invention, the backside oxide on the handle substrate can be adjusted to counter the stresses induced by the BOX. Therefore, the warpage or curvature of the final SOI structure can be maintained within an allowable level. As an additional advantage, this may be enhanced during furnace cycling of the thermal oxide grown on the bonded pairs of wafers or during thickening of the chemical vapor deposited oxide (CVD oxide) on the bonded pairs of wafers. Bonding between the substrates. The reinforced bond can facilitate thinning processes on the wafer during SOI waferization to, for example, reduce active delamination.

The substrate used in the present invention comprises a single crystal donor substrate and a single crystal processing substrate. In general, the single crystal substrates include: two substantially parallel major surfaces, one of which is a front surface of one of the substrates and the other of which is a back surface of one of the substrates; a circumferential edge Bonding the front surface and the rear surface; and a central plane between the front surface and the rear surface. The front surface and the back surface of the substrate may be substantially identical prior to any of the operations as described herein. A surface is referred to as a "front surface" or a "back surface" merely for convenience and generally to distinguish the surface on which the operation of the method of the present invention is performed. In the context of the present invention, "front surface" means the major surface of the substrate which becomes the inner surface of one of the joined structures. "Back surface" means a major surface that becomes an outer surface of one of the joined structures.

The single crystal donor substrate and the single crystal processed substrate may be semiconductor wafers. In a preferred embodiment, the semiconductor wafers are selected from the group consisting of germanium, tantalum carbide, tantalum telluride, tantalum nitride, hafnium oxide, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide, germanium. And one of the groups of the combination of the above. In a preferred embodiment, the semiconductor wafers comprise a wafer cut from a single crystal germanium wafer that has been cut from a single crystal ingot grown according to conventional Czochralski crystal growth methods. For example, F. Shimura's "Semiconductor Silicon Crystal Technology" (Academic Press, 1989) and "Silicon Chemical Etching" (J. Grabmaier et al.) (Springer-Verlag, N.Y., 1982) These methods, as well as standard enthalpy cutting, polishing, etching, and polishing techniques, are disclosed in the accompanying drawings, which are incorporated herein by reference. Preferably, both the device wafer and the support wafer have a mirror-polished front surface coating free of surface defects such as scratches, large particles, and the like. The wafer thickness generally varies from about 250 microns to about 1500 microns, and a thickness in the range of from about 500 microns to about 1000 microns, such as about 725 microns, is preferred.

According to the method of the present invention, a dielectric layer (for example, an oxide layer or a nitride layer) may be formed on a front surface of a device substrate, a front surface of a processing substrate, or a surface of a device substrate and a processing substrate. . A dielectric layer prepared by oxidation deposits substantially a layer of cerium oxide (SiO ₂ ) on the surface of the wafer, and a dielectric layer prepared by nitriding deposits a layer of tantalum nitride on the surface of the wafer. Si ₃ N ₄ ). In general, an oxide layer can be substantially formed on a germanium substrate by thermal oxidation or chemical vapor deposition.

In some embodiments, the dielectric layer is formed on a front surface of a device substrate, a front surface of a processing substrate, or a device substrate by thermally growing an oxide on the surface of the germanium wafer in a high temperature furnace. A layer of cerium oxide (SiO ₂ ) on the surface of the front side of both substrates is treated. Typically performing a device substrate in a vertical furnace having steam (H ₂ O or a mixture of hydrogen and oxygen) and/or oxygen at temperatures above about 700 ° C (typically between 800 ° C and about 1200 ° C) Thermal oxidation of a front surface, a front surface of a processing substrate, or a front surface of both a device substrate and a processing substrate. This thermal oxidation is typically performed in a vertical furnace, such as the commercially available AMS 400. The oxidizing environment may also contain a certain percentage of hydrochloric acid (HCl). Chlorine removes metal ions that can occur in the oxide. Thermal oxidation of the surface of a front surface of a device substrate, a front substrate of a processing substrate, or a device substrate and a processing substrate generally continues until a formation of between about 50 nm and about 5,000 nm is formed. Preferably, the thickness of the cerium oxide layer is between about 100 nm and about 2000 nm.

In some embodiments, the dielectric layer comprises a oxidization formed on a front surface of a device substrate by chemical vapor deposition, a front surface of a processing substrate, or a surface of a device substrate and a processing substrate.矽 (SiO ₂ ) layer. The deposition of the CVD oxide on the surface of the device substrate, the processing substrate, or both the device substrate and the processing substrate can be performed in a furnace having an environment including one of a helium containing gas and an oxidizing agent. In some embodiments, the ambient atmosphere comprises decane (SiH ₄ ) and oxygen (O ₂ ). In some embodiments, the ambient atmosphere comprises dichlorodecane (SiCl ₂ H ₂ ) and nitrous oxide (N ₂ O). In some embodiments, the ambient atmosphere comprises tetraethyl phthalate (Si(OC ₂ H ₅ ) ₄ ). The CVD oxide can be deposited on the wafer in a CVD tool such as the commercially available Walker Johnson. Chemical vapor deposition of the oxide layer typically occurs at temperatures between about 300 ° C and about 900 ° C. The temperature can vary depending on the particular formulation selected for the CVD oxide. For example, decane (SiH ₄ ) and oxygen (O ₂ ) typically deposit cerium oxide at a temperature between about 300 ° C and about 500 ° C. Dichlorodecane (SiCl ₂ H ₂ ) and nitrous oxide (N ₂ O) typically deposit cerium oxide at temperatures between about 700 ° C and about 900 ° C. Tetraethyl phthalate (Si(OC ₂ H ₅ ) ₄ ) typically deposits cerium oxide at a temperature between about 600 ° C and about 800 ° C. The chemical vapor deposition on the surface of the front surface of one of the device substrates, the front surface of one of the processing substrates, or the surface of a device substrate and a processing substrate generally continues until the formation has a thickness of from about 50 nm to about 5,000. A layer of cerium oxide having a thickness between one nanometer (preferably between about 300 nm and about 2000 nm). The chemical vapor deposited oxide layer is substantially thickened by annealing the substrate in an oven to increase the strength of the oxide layer. Thickening typically occurs at temperatures between about 1000 ° C and about 1200 ° C for hours (typically 2 hours).

The front surface of the substrate can be oxidized by thermal oxidation or thickening of the CVD oxide. Suitable oxidation techniques can depend, at least in part, on the requirements of the SOI device process. For example, if the device is highly sensitive to electrical properties and/or metal between the device layer and the ceria interface, thermal oxidation is typically applied. In some embodiments in which an oxide layer of high uniformity (e.g., <100 angstroms) is desired, the surface of the device substrate and/or the surface of the substrate can be thermally oxidized.

According to the method of the present invention, the front surface of the device substrate and the front surface of the substrate are processed. Herein, the front surface of the device substrate, the front surface of the processing substrate, or the front surface of both the device substrate and the processing substrate may be deposited by thermal oxidation and/or chemical vapor deposition. A dielectric layer, such as a layer of ruthenium dioxide. The ruthenium dioxide layer can have a thickness that is generally between about 50 nanometers to about 5000 nanometers, such as between about 100 nanometers and about 2000 nanometers. Bonding is accomplished by intimately contacting the front surface of the device substrate and the processing substrate to thereby form a joint structure. The bonding is by means of a bonding tool such as a commercially available EV850 (manufactured by Electronic Vision) in which a device substrate and a supporting substrate are joined together. Since the mechanical bond is relatively weak, the bond structure is further annealed to cure the bond between the donor wafer and the handle wafer. The post-join heat treatment can be performed in an electric oven such as a commercially available Blue M. The joined structure can be heat treated at a temperature between about 200 ° C and about 1000 ° C, preferably at a temperature of about 500 ° C. The heat treatment can have a duration of between about 1 hour and about 12 hours, preferably up to about 6 hours.

In some embodiments, the bonded multilayer structure is subjected to a post-bonding anneal. Since the annealing temperature is significantly higher than the temperature of the post-bonding heat treatment, a post-joint annealing further increases the joint strength. The post-bonding anneal may occur at a temperature between about 800 ° C and about 1200 ° C, preferably at a temperature of about 1150 ° C. The post-bonding anneal may have a duration of between about 1 hour and about 10 hours, preferably up to about 4 hours.

After the device substrate has been bonded and the front surface of the substrate is processed, a dielectric layer (eg, an oxide layer) is formed on the surface of the device substrate, the surface after the processing surface, or both the device substrate and the processing substrate. The surface of the device substrate, the substrate or the device substrate, and the substrate can be oxidized by thermal oxidation or chemical vapor deposition. The same thermal oxidation and CVD oxidation procedures, which are used to oxidize the substrate, the device substrate, or the front surface of both the substrate and the device substrate, can be used to oxidize the back surface of the substrate in the multilayer structure. In general, the thickness of the oxide layer on the surface of the device substrate rear surface, the processing surface rear surface, or both the device substrate and the processing substrate may be between about 50 nm and about 5000 nm, preferably about 500 nm to about 2000 nm. The thickness of the or the oxide layer deposited on one or both of the back surfaces depends in part on the thickness of the BOX layer that bonds the device substrate to the front surface of the handle substrate. The thickness of the BOX layer and the cumulative thickness of the (s) back ruthenium dioxide layer Preferably, the thickness is comparable to substantially offset the stress induced by the different coefficients of thermal expansion of the strontium and the cerium oxide. In embodiments in which the BOX layer is made of a thickened CVD oxide, the cumulative thickness of the back ceria layer can be empirically determined by a calibration method to optimize the offset by the BOX layer of the thickened CVD oxide. The cumulative thickness required for stress.

In some embodiments, the device substrate, the substrate or device substrate, and the substrate can be oxidized by thermal oxidation. In the embodiment in which the surface of the intervening dielectric layer (for example, a BOX layer) and the device substrate, the processing substrate or the device substrate, and the processing substrate are oxidized by thermal oxidation, the thickness of the thermal oxide to be grown on the bonding pair It is substantially equal to the thickness of the thermal oxide used to form the BOX layer between the front surfaces of the joint. In short, the formulation of the thermal oxidation of the bonding pair is substantially the same as the formulation of the program for growing the thermal oxide on the device wafer prior to bonding.

In some embodiments in which a dielectric layer (eg, a BOX layer) is prepared by thickening chemical vapor deposition oxidation, since the thickened CVD oxide has less stress than the thermal oxide, it should be empirically determined to be formed on the device substrate. The appropriate thickness of the thermal oxide on the surface of the substrate or device substrate and the treated substrate to counter the stress of the CVD oxide layer. The appropriate thickness of the thermal oxide required to counterbalance the thickened CVD oxide is determined empirically. For example, if the thickness of the thickened CVD oxide layer is about 1 micron, a series of calibrated surface oxide thicknesses (e.g., 0.3 microns, 0.5 microns, 0.7 microns, etc.) can be grown on the surface of the test substrate. The warpage/bending is measured to determine which thermal oxide thickness gives the lowest warpage/bend. The minimum warpage/bending is converted to a suitable back oxide thickness to properly offset the stress induced by the CVD oxide layer. In general, the thickness of the thermal oxide to be grown on the bonded pair is slightly less than the thickness of the thickened oxide on the bonding surface of the device wafer.

After forming a dielectric layer (for example, a ruthenium dioxide layer) on the surface of the device substrate, the surface after the processing surface, or the surface of both the device substrate and the processing substrate, thin by any combination of grinding, polishing, etching, or surface treatment. The surface of the device substrate. Generally, the device substrate is thinned until the device substrate has between about 1 micron and about 300 microns (the One thickness (such as about 7 microns), such as between about 3 microns and about 300 microns or between about 3 microns and 70 microns. The thickness of the thinning device substrate depends on the end use of the SOI structure and customer specifications. Surface grinding typically uses a single-sided grinder such as the Disco bed DFG-830 manufactured by Disco. In surface grinding, most of the material of the device wafer is removed from the backside of the device wafer after bonding. Edge processing can include several steps, such as edge grinding and device wafer edge etching. Edge grinding typically uses an edge profile milling machine such as the STC EP-5800RHO.

In the embodiment in which the surface after etching the substrate of the semiconductor device is used, an alkaline etchant or an acidic etchant is suitable. An alkaline etchant is preferred. The acidic etchant comprises, for example, a mixture of hydrochloric acid, nitric acid, phosphoric acid, and hydrofluoric acid. The alkaline etchant contains KOH and NaOH. Etching procedures are generally known in the art.

In an embodiment in which the surface of the substrate of the semiconductor device is polished, one-side polishing, double-side polishing, or single-side polishing and double-side polishing may be applied to polish the rear surface. One-sided polishing can be accomplished using a commercially available tool (such as Strasbaugh Mark 9-K), while double-sided polishing uses a commercially available tool such as one of Peter Wolters AC2000-P.

After completing all of the program steps, all required parameters of the SOI wafer, such as flatness, particles, etc., are inspected prior to final packaging for the customer. In general, multilayer semiconductor structures (such as SOI structures) prepared in accordance with the methods of the present invention have a warpage of no greater than 35 microns, no greater than 30 microns, no greater than about 29 microns, or even no greater than about 28 microns. In some embodiments, the degree of warpage can be less than about 26 microns, less than about 25 microns, or even less than about 24 microns.

Although the present invention has been described in detail, it is understood that modifications and variations can be made without departing from the scope of the invention as defined in the appended claims.

The following non-limiting examples are provided to further illustrate the invention.

Example 1. Preparation of SOI Structure with Reduced Warpage/Flexibility

Join multiple device wafers and process wafers. The bonded structure was heat treated in a Blue M oven having a temperature of 500 ° C for 6 hours. The two outer major surfaces of the bonded structure are heat treated with a CVD oxide. More specifically, the bonded device wafer and the two back surfaces of the wafer are oxidized by CVD oxidation. CVD oxidation is carried out by decomposing tetraethyl orthosilicate (Si(OC ₂ H ₅ ) ₄ ) in a CVD tool (AMAT Precision 5000, SVG hot vertical furnace) having a temperature of about 700 ° C. The CVD oxide thickness is about 1 micron. The joint structure was annealed in an annealing furnace (AMS 400, SVG hot vertical furnace) having a temperature of one of 1000 ° C for about 2 hours. The total thickness of the oxide layer on the surface of the device wafer and after processing the wafer is substantially the same as the thickness of the BOX layer. The thinning (which includes grinding, etching, polishing, and cleaning) device layers to achieve top layer thickness, uniformity, and surface quality according to customer specifications. Referring to Figure 1, there is depicted the measured warpage in a number of joint structures prepared according to conventional procedures (wherein the major surface outside the joint structure is not subjected to an additional oxidation procedure) (○) and the above procedure according to the present invention. A graph of one of the measured warpages (□) in several joint structures. The measured warpage in conventionally prepared joint structures averaged about 69 microns, with some structures exhibiting warpage exceeding 70 microns. In comparison, the measured warpage in the joint structure prepared according to the method of Example 1 averaged about 29 microns, with some structures exhibiting a warpage of less than 27 microns or even less than 25 microns.

This description uses examples to disclose the invention, including the best mode, and the embodiments of the invention may be used to enable the skilled artisan to practice the invention (which includes the manufacture and use of any device or system and any incorporation method). The patentable scope of the invention is defined by the scope of the claims, and may include other examples that are apparent to those skilled in the art. These other examples are intended to fall within the scope of the patent application, as long as they have structural elements that are not different from the written terms of the patent application, or as long as they contain an equivalent structure that is not substantially different from the written language of the patent application. element.

Claims (17)

A method of fabricating a multilayer semiconductor structure, the method comprising the steps of: (a) forming a dielectric layer on a front surface of a substrate of a semiconductor device, the semiconductor device substrate comprising: two substantially parallel mains a surface, one of which is the front surface of the substrate of the semiconductor device and the other of which is a back surface of the substrate of the semiconductor device; a circumferential edge that is bonded to the front surface of the semiconductor device substrate and thereafter a surface; and a central plane interposed between the front surface and the rear surface of the semiconductor device substrate; (b) bonding the front surface of the semiconductor device substrate having the dielectric layer to one of the processing substrates The front surface thereby forming a bonding structure, wherein the processing substrate comprises: two substantially parallel major surfaces, one of which is the front surface of the processing substrate and the other of which is the processing substrate a rear surface; a circumferential edge that joins the front surface and the back surface of the processing substrate; and a central plane between the front surface and the back surface of the processing substrate; and (c) Substrate processing on the rear surface of the dielectric layer is formed. The method of claim 1, wherein the semiconductor device substrate comprises a substrate selected from the group consisting of germanium, tantalum carbide, tantalum telluride, tantalum nitride, hafnium oxide, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide, germanium. And one of the groups of the combination of the above. The method of claim 1 or 2, wherein the semiconductor device substrate comprises a wafer etched from one of the single crystal germanium ingots grown by the Czochralski method. The method of claim 3, wherein the dielectric layer formed on the front surface of the semiconductor device substrate comprises ruthenium dioxide. The method of claim 4, wherein the dielectric layer comprising cerium oxide has a thickness of between about 50 nanometers and about 5000 nanometers. The method of claim 1 or 2, wherein the processing substrate is a wafer. The method of claim 6, wherein the processing substrate further comprises a dielectric layer on the front surface thereof. The method of claim 7, wherein the dielectric layer comprises cerium oxide and has a thickness of between about 50 nanometers and about 5,000 nanometers. The method of claim 6, wherein the dielectric layer formed on the back surface of the handle substrate during the step (c) comprises ruthenium dioxide. The method of claim 9, wherein the dielectric layer comprising cerium oxide has a thickness of between about 50 nanometers and about 5000 nanometers. The method of claim 1 or 2, wherein the step (c) further comprises simultaneously forming a dielectric layer on the rear surface of the semiconductor device substrate. The method of claim 11, wherein the dielectric layers formed on the back surfaces of both the handle substrate and the semiconductor substrate comprise ruthenium dioxide. The method of claim 12, wherein the dielectric layers comprising cerium oxide have a thickness of between about 50 nanometers and about 5,000 nanometers. The method of claim 1 or 2, further comprising the step (d) of thinning the substrate of the semiconductor device. The method of claim 14, wherein the thinning is performed by grinding the back surface of the semiconductor device substrate, etching the back surface of the semiconductor device substrate, polishing the back surface of the semiconductor device substrate, or any combination of the technologies Semiconductor device substrate. The method of claim 15, wherein after the step (d), the thinned semiconductor device substrate has a thickness between about 3 microns and about 70 microns. The method of claim 1 or 2, wherein the multilayered semiconductor structure has a warpage of no greater than 30 microns.