KR20080020389A - Method for manufacturing soi wafer - Google Patents

Method for manufacturing soi wafer Download PDF

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KR20080020389A
KR20080020389A KR1020060083811A KR20060083811A KR20080020389A KR 20080020389 A KR20080020389 A KR 20080020389A KR 1020060083811 A KR1020060083811 A KR 1020060083811A KR 20060083811 A KR20060083811 A KR 20060083811A KR 20080020389 A KR20080020389 A KR 20080020389A
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silicon wafer
silicon
thickness
wafer
polishing
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KR1020060083811A
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Korean (ko)
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문병삼
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Element Separation (AREA)

Abstract

A method for manufacturing an SOI(Silicon On Insulator) wafer is provided to form uniformly a thickness of silicon layer by performing a polishing process using a thickness difference. A second silicon wafer(32) is attached on a first silicon wafer(31) on which a burial insulating layer(33) is formed. A rear surface of the second silicon wafer is polished in a thickness thicker than the thickness of the desired silicon layer. A part of the rear surface of the second silicon wafer is polished to remove a defect. An oxide layer is formed on the rear surface of the second silicon wafer. A second polishing process is performed to polish the rear surface of the second silicon wafer including the oxide layer. The residual oxide layer is removed. A third polishing process is performed to form the silicon layer of the desired thickness.

Description

ＳＯＩ 웨이퍼 제조방법{METHOD FOR MANUFACTURING SOI WAFER}SOI wafer manufacturing method {METHOD FOR MANUFACTURING SOI WAFER}

도 1은 종래 기술에 따른 SOI 웨이퍼의 제조방법을 설명하기 위한 모식도.1 is a schematic diagram for explaining a method for manufacturing a SOI wafer according to the prior art.

도 2는 종래 기술의 문제점을 설명하기 위한 SOI 웨이퍼의 단면도.2 is a cross-sectional view of an SOI wafer for explaining the problems of the prior art.

도 3a 내지 도 3e는 본 발명의 실시예에 따른 SOI 웨이퍼의 제조방법을 설명하기 위한 공정별 단면도.3A to 3E are cross-sectional views of processes for explaining a method of manufacturing an SOI wafer according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 * Explanation of symbols on the main parts of the drawings

31 : 제1실리콘웨이퍼 32 : 제2실리콘웨이퍼31: first silicon wafer 32: second silicon wafer

33 : 매몰절연막 34 : 산화막33: investment insulating film 34: oxide film

A : 가장 두꺼운 부분 B : 가장 얇은 부분A: the thickest part B: the thinnest part

본 발명은 SOI(Silicon On Insulator) 웨이퍼의 제조방법에 관한 것으로, 보다 상세하게는, 실리콘층의 두께 균일도를 향상시킬 수 있는 SOI 웨이퍼의 제조방법에 관한 것이다. The present invention relates to a method for manufacturing a silicon on insulator (SOI) wafer, and more particularly, to a method for manufacturing a silicon on insulator (SOI) wafer capable of improving thickness uniformity of a silicon layer.

반도체 소자의 고집적화 및 고성능화가 진행됨에 따라, 벌크 실리콘으로 이루어진 실리콘 웨이퍼을 대신하여 SOI(Silicon On Insulator) 웨이퍼를 이용한 반 도체 집적 기술이 주목되고 있다. 상기 SOI 웨이퍼는 지지 수단인 실리콘웨이퍼와 소자가 형성될 실리콘층 사이에 매몰절연막이 개재된 구조로서, 이러한 SOI 웨이퍼 상에 형성된 반도체 소자는 완전한 소자 분리와 기생 용량의 감소로 인하여, 고속 동작이 가능한 장점을 갖는다. As the integration and performance of semiconductor devices have increased, semiconductor integration techniques using silicon on insulator (SOI) wafers have been attracting attention instead of silicon wafers made of bulk silicon. The SOI wafer has a structure in which a buried insulating film is interposed between a silicon wafer, which is a support means, and a silicon layer, on which the device is to be formed. Has an advantage.

종래에는, 상기 SOI 웨이퍼를 제조하기 위한 방법으로서 산소 이온주입을 이용하는 SIMOX(Seperation by Implanted Oxygen)법과 두 장의 실리콘웨이퍼를 매몰절연막의 개재하에 본딩시키는 접합(Bonding)법을 이용하고 있다. 그런데, SIMOX법을 이용한 SOI 웨이퍼 제조방법은 제조 시간이 길다는 단점이 있기 때문에, 최근에는 본딩법을 이용한 SOI 웨이퍼 제조방법이 주로 이용되고 있다. Conventionally, as a method for producing the SOI wafer, a SIMOX (Seperation by Implanted Oxygen) method using oxygen ion implantation and a bonding method in which two silicon wafers are bonded under the buried insulating film are used. However, the SOI wafer manufacturing method using the SIMOX method has a disadvantage in that the manufacturing time is long. Recently, the SOI wafer manufacturing method using the bonding method is mainly used.

상기 본딩법을 이용한 SOI 웨이퍼 제조방법을 간략하게 설명하면, 우선 지지 수단인 실리콘웨이퍼와 실리콘층을 얻기 위한 실리콘웨이퍼 중에서 어느 하나의 웨이퍼에 매몰절연막을 형성하고, 이어서, 매몰절연막의 개재하에 두 장의 실리콘웨이퍼를 본딩시킨다. 그런 다음, 실리콘웨이퍼 후면의 일부 두께를 공지된 기술인 연삭(grinding) 공정과, 화학적기계연마(Chemical Mechanical Polishing : 이하, CMP) 공정으로 제거하여, 소자가 형성될 실리콘층을 얻는다. The SOI wafer manufacturing method using the above bonding method will be briefly described. First, a buried insulating film is formed on one of the wafers, a silicon wafer serving as a support means and a silicon wafer for obtaining a silicon layer, and then two sheets are formed under the buried insulating film. Bond the silicon wafer. Then, part of the thickness of the back surface of the silicon wafer is removed by a known grinding process and a chemical mechanical polishing (CMP) process to obtain a silicon layer on which the device is to be formed.

자세하게, 도 1은 종래 기술에 따른 본딩법을 이용한 SOI 웨이퍼의 제조방법을 설명하기 위한 모식도로서, 이를 설명하면 다음과 같다. In detail, Figure 1 is a schematic diagram for explaining a manufacturing method of the SOI wafer using the bonding method according to the prior art, which will be described as follows.

먼저, 제2실리콘웨이퍼(12)와 표면에 산화막(13)이 형성된 제1실리콘웨이퍼(11)를 마련한 후, 상기 산화막(13)의 개재하에 제1실리콘웨이퍼(11)와 제2실리콘웨이퍼(12)를 경면이 마주보도록 합착시킨다. 그런 다음, 상기 합착된 웨이퍼 들(11,12)간 접합력을 강화시키기 위하여 열처리를 수행한다. 이때, 상기 열처리는 질소(N2) 가스 또는 아르곤(Ar) 가스를 사용하여 수행한다. First, the first silicon wafer 11 having the second silicon wafer 12 and the oxide film 13 formed on the surface thereof is provided, and then the first silicon wafer 11 and the second silicon wafer 11 are disposed under the oxide film 13. 12) and attach them so that the mirror faces each other. Then, heat treatment is performed to strengthen the bonding force between the bonded wafers 11 and 12. In this case, the heat treatment is performed using nitrogen (N 2 ) gas or argon (Ar) gas.

이어서, 상기 제2실리콘웨이퍼(12)의 후면을 소망하는 실리콘층 두께가 얻어질 때까지 연삭(Grinding)한 후, 산화막과 실리콘막 간의 선택비가 없는 슬러리를 이용한 연마 공정을 수행하여 SOI 웨이퍼(14)를 제조한다. Subsequently, after grinding the back surface of the second silicon wafer 12 until the desired silicon layer thickness is obtained, a polishing process using a slurry having no selectivity between the oxide film and the silicon film is performed to perform the SOI wafer 14. ).

한편, SOI 웨이퍼(14) 상에 형성되는 소자의 특성은 소자가 형성될 실리콘층의 두께 균일도에 크게 의존한다. 따라서, SOI 웨이퍼(14)의 제조시에는 실리콘층의 두께 균일도를 확보하는 것이 무엇보다 중요하다. On the other hand, the characteristics of the device formed on the SOI wafer 14 largely depend on the thickness uniformity of the silicon layer on which the device is to be formed. Therefore, in manufacturing the SOI wafer 14, it is most important to secure the thickness uniformity of the silicon layer.

그러나, 전술한 종래 기술의 경우에는, 도 2에 도시된 바와 같이, 제1실리콘웨이퍼(11) 두께의 평탄도, 즉, 전체 두께 변동(Total Thickness Variation)이 존재하기 때문에, 상기 제2실리콘웨이퍼(12) 두께의 균일성이 열악해져 균일한 두께의 실리콘층을 얻을 수 없다는 문제점이 있다. 예컨데, 제1실리콘웨이퍼(11)에 ±1.0㎛ 정도의 두께 변동이 존재한다면, 상기 제2실리콘웨이퍼(12)의 경우에는 제1실리콘웨이퍼(11) 두께 변동 폭의 1/2 정도인 ±0.5㎛ 정도의 두께 변동이 존재하게 되며, 상기 두께 변동은 소자 분리 공정 중 트렌치 깊이의 변동을 야기하므로 반도체 소자의 절연 불량이 유발된다.However, in the above-described prior art, as shown in FIG. 2, since the flatness of the thickness of the first silicon wafer 11, that is, the total thickness variation, exists, the second silicon wafer (12) There is a problem in that the uniformity of the thickness is poor and a silicon layer having a uniform thickness cannot be obtained. For example, if there is a thickness variation of about 1.0 μm in the first silicon wafer 11, in the case of the second silicon wafer 12, ± 0.5 which is about 1/2 of the thickness variation of the first silicon wafer 11. There is a thickness variation of about μm, and the thickness variation causes variations in trench depth during the device isolation process, resulting in poor insulation of the semiconductor device.

이를 방지하기 위해 상기 제1실리콘웨이퍼(11)로서 전체 두께 변동이 양호한 웨이퍼를 사용하고 있기는 하지만, 연마 공정이 수행되는 웨이퍼의 특성상 두께 변동은 존재할 수 밖에 없는 실정이다.In order to prevent this, the first silicon wafer 11 is used as a wafer having good overall variation in thickness, but the variation in thickness is inevitable due to the characteristics of the wafer on which the polishing process is performed.

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, 실리콘층의 두께 균일도를 향상시킬 수 있는 SOI 웨이퍼의 제조방법을 제공함에 그 목적이 있다. Accordingly, an object of the present invention is to provide a method for manufacturing an SOI wafer capable of improving the thickness uniformity of a silicon layer, which is devised to solve the above problems.

상기와 같은 목적을 달성하기 위한 본 발명의 SOI 웨이퍼의 제조방법은, 실리콘웨이퍼와 매몰절연막 및 실리콘층의 적층 구조로 이루어진 SOI 웨이퍼의 제조방법으로서, 매몰절연막이 형성된 제1실리콘웨이퍼 상에 제2실리콘웨이퍼를 합착시키는 단계; 상기 제2실리콘웨이퍼의 후면을 소망하는 실리콘층 두께 보다 두껍도록 연삭하는 단계; 상기 연삭시 발생된 결함이 제거되도록 제2실리콘웨이퍼 후면의 일부 두께를 1차 연마하는 단계; 상기 1차 연마된 제2실리콘웨이퍼의 후면 상에 산화막을 형성하는 단계; 상기 제2실리콘웨이퍼의 두께 균일도가 개선되도록 상기 산화막을 포함한 제2실리콘웨이퍼의 후면을 2차 연마하는 단계; 상기 2차 연마시 제거되지 않고 잔류된 산화막을 제거하는 단계; 및 상기 2차 연마된 제2실리콘웨이퍼의 후면을 3차 연마하여 소망하는 두께의 실리콘층을 형성하는 단계;를 포함하며, 상기 산화막을 포함한 제2실리콘웨이퍼의 2차 연마는 거친 연마의 조건으로 수행하면서 상기 산화막이 우선 연마되다가 가장 두꺼운 제2실리콘웨이퍼 부분이 노출되는 시점부터 잔류 제2실리콘웨이퍼의 두께 변동이 최소화되는 시점까지 수행하는 것을 특징으로 한다.A method of manufacturing an SOI wafer of the present invention for achieving the above object is a method of manufacturing an SOI wafer having a laminated structure of a silicon wafer, an investment insulating film, and a silicon layer, the second silicon on the first silicon wafer formed with an investment insulating film Bonding the silicon wafer; Grinding the back surface of the second silicon wafer to be thicker than the desired silicon layer thickness; First grinding a part of the thickness of the rear surface of the second silicon wafer to remove defects generated during the grinding; Forming an oxide film on a rear surface of the first polished second silicon wafer; Secondly polishing a rear surface of the second silicon wafer including the oxide layer to improve thickness uniformity of the second silicon wafer; Removing the oxide film remaining without being removed during the second polishing; And forming a silicon layer having a desired thickness by tertiary polishing the rear surface of the second polished second silicon wafer, wherein the second polishing of the second silicon wafer including the oxide film is performed under rough polishing conditions. While the oxide film is polished first, the thickness of the second silicon wafer is exposed to the point when the thickness variation of the remaining second silicon wafer is minimized.

여기서, 상기 잔류 제2실리콘웨이퍼의 두께 변동이 최소화되는 시점은 ±0.2 ㎛ 이하인 것을 특징으로 한다.Here, the time point when the variation in the thickness of the remaining second silicon wafer is minimized is characterized in that less than ± 0.2 ㎛.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3a 내지 도 3e는 본 발명의 실시예에 따른 SOI 웨이퍼의 제조방법을 설명하기 위한 공정별 단면도로서, 이를 설명하면 다음과 같다.3A to 3E are cross-sectional views illustrating processes for manufacturing a SOI wafer according to an exemplary embodiment of the present invention.

도 3a를 참조하면, 두 장의 실리콘웨이퍼(31,32), 즉, 가공되지 않은 제1실리콘웨이퍼(31)와 제2실리콘웨이퍼(32)를 마련한 상태에서, 예컨데, 상기 제2실리콘웨이퍼(32) 상에 산화 공정을 통해 매몰절연막(33)을 형성한다. 그런 다음, 상기 매몰절연막(33)의 개재하에 경면이 서로 마주보도록 상기 제1실리콘웨이퍼(31)와 제2실리콘웨이퍼(32)를 합착시킨다.Referring to FIG. 3A, two silicon wafers 31 and 32, that is, an unprocessed first silicon wafer 31 and a second silicon wafer 32 are provided, for example, the second silicon wafer 32. The buried insulating film 33 is formed through the oxidation process. Then, the first silicon wafer 31 and the second silicon wafer 32 are bonded to each other so that mirror surfaces thereof face each other under the buried insulating film 33.

이어서, 상기 합착된 웨이퍼들(31,32)간 접합력을 강화시키기 위하여 결과물에 대해 질소(N2) 또는 아르곤(Ar)과 같은 불활성 가스를 사용하여 고온 열처리 공정을 수행한다.Subsequently, a high temperature heat treatment process is performed using an inert gas such as nitrogen (N 2 ) or argon (Ar) on the resultant to strengthen the bonding force between the bonded wafers 31 and 32.

도 3b를 참조하면, 상기 제2실리콘웨이퍼(32)의 후면을 소망하는 실리콘층 두께보다 두껍도록, 바람직하게, 20㎛ 정도만큼 두껍도록 연삭(Grinding)한다. 이때, 연삭 공정이 수행된 제2실리콘웨이퍼(32)의 후면은 그 표면 균일도가 매우 불량하다. 계속해서, 상기 연삭시 발생된 결함이 제거되도록 제2실리콘웨이퍼(32) 후 면의 일부 두께를 1차 연마한다. 상기 1차 연마는 거친 연마(Rough Polishing)로, 소망하는 실리콘층 두께보다 5㎛ 만큼 두껍도록 수행한다.Referring to FIG. 3B, the back surface of the second silicon wafer 32 is ground to a thickness thicker than a desired silicon layer thickness, and preferably thicker by about 20 μm. At this time, the back surface of the second silicon wafer 32 on which the grinding process is performed has very poor surface uniformity. Subsequently, a part of the thickness of the rear surface of the second silicon wafer 32 is first polished so that defects generated during the grinding are removed. The primary polishing is rough polishing, which is performed by 5 mu m thicker than the desired thickness of the silicon layer.

도 3c를 참조하면, 상기 1차 연마된 제2실리콘웨이퍼(32)의 후면 상에 산화막(34)을 형성한다. 여기서, 상기 산화막(34)은 건식 산화 공정을 통해 형성되며, 제2실리콘웨이퍼(32) 후면의 프로파일을 따라 균일한 두께로 형성된다.Referring to FIG. 3C, an oxide film 34 is formed on the rear surface of the first polished second silicon wafer 32. Here, the oxide film 34 is formed through a dry oxidation process, and is formed to have a uniform thickness along the profile of the back surface of the second silicon wafer 32.

도 3d를 참조하면, 상기 제2실리콘웨이퍼(32)의 두께 균일도가 개선되도록 상기 산화막(34)을 포함한 제2실리콘웨이퍼(32)의 후면을 2차 연마한다. 이때, 상기 2차 연마는 거친 연마의 조건으로 수행하면서, 상기 산화막(34)이 우선 연마되다가 제2실리콘웨이퍼(32)의 가장 두꺼운 부분(A)이 노출되는 시점부터 잔류 제2실리콘웨이퍼(32)의 두께 변동이 최소화되는 시점까지 수행하며, 이를 통해, 소자가 형성될 실리콘층의 두께 균일도를 향상시킬 수 있다.Referring to FIG. 3D, the back surface of the second silicon wafer 32 including the oxide film 34 is secondarily polished to improve thickness uniformity of the second silicon wafer 32. In this case, while performing the secondary polishing under the conditions of rough polishing, the oxide film 34 is first polished and then the remaining second silicon wafer 32 is exposed from the point where the thickest portion A of the second silicon wafer 32 is exposed. ) To a point where the variation in thickness is minimized, thereby improving thickness uniformity of the silicon layer on which the device is to be formed.

자세하게, 제2실리콘웨이퍼(32)의 가장 두꺼운 부분(A)을 가장 얇은 부분(B)보다 높은 압력을 사용해서 연마하여 가장 가까운 부분(A)에 형성된 산화막(34) 부분을 제거한 다음, 산화막(34)의 제거로 인해 노출된 제2실리콘웨이퍼(32) 부분을 포함한 나머지 산화막(34)에 대해 2차 연마를 연속적으로 수행한다. 그런데, 상기 산화막(34)은 실리콘보다 연마 속도가 현저히 느리므로 두꺼운 부분의 제2실리콘웨이퍼(32)가 산화막(34)보다 더 많이 연마되며, 따라서, 제2실리콘웨이퍼(32)의 가장 두꺼운 부분(A)과 가장 얇은 부분(B)의 두께 변동이 최소화되는 시점, 바람직하게는, 상기 두께 변동 폭이 ±0.2㎛ 이하인 시점까지 2차 연마를 연속적으로 수행함으로써 실리콘층의 두께 균일도를 향상시킬 수 있다.In detail, the thickest portion A of the second silicon wafer 32 is polished using a pressure higher than the thinnest portion B to remove the portion of the oxide film 34 formed in the nearest portion A, and then the oxide film ( Secondary polishing is continuously performed on the remaining oxide film 34 including the portion of the second silicon wafer 32 exposed due to the removal of 34). However, since the oxide film 34 has a significantly slower polishing rate than silicon, the thickened second silicon wafer 32 is more polished than the oxide film 34, and thus, the thickest portion of the second silicon wafer 32 The thickness uniformity of the silicon layer can be improved by performing secondary polishing continuously until the thickness fluctuation of (A) and the thinnest part (B) is minimized, preferably until the thickness fluctuation range is ± 0.2 µm or less. have.

도 3e를 참조하면, 상기 2차 연마시 제거되지 않고 잔류된 산화막을 제거한다음, 2차 연마된 제2실리콘웨이퍼(32)의 후면을 3차 연마하여 소망하는 두께의 실리콘층을 형성한다. 이때, 상기 3차 연마는 최종 연마(Final Polishing)로 수행한다.Referring to FIG. 3E, after removing the oxide film remaining without being removed during the second polishing, the back surface of the second polished silicon wafer 32 is third polished to form a silicon layer having a desired thickness. In this case, the tertiary polishing is performed by final polishing.

이후, 도시하지는 않았지만, 공지된 일련의 후속 공정을 차례로 수행하여 본 발명의 SOI 웨이퍼를 제조한다.Then, although not shown, a series of subsequent known processes are sequentially performed to produce the SOI wafer of the present invention.

여기서, 본 발명은 실리콘과 연마 속도 차이를 갖는 산화막을 형성한 상태에서 실리콘웨이퍼가 가장 두꺼운 부분과 가장 얇은 부분에 서로 다른 압력을 사용해서 연마 공정을 수행함으로써, 상기 실리콘웨이퍼의 두께 변동 폭을 종래의 ±0.5㎛에서 60% 정도 개선된 ±0.2㎛(-0.2㎛∼+0.2㎛) 정도로 개선할 수 있으며, 이를 통해, 소자가 형성될 실리콘층의 두께 균일도를 향상시킬 수 있다. 따라서, 상기 SOI 웨이퍼를 이용한 반도체 소자의 제조시 아이솔레이션(Isolation) 공정의 공정 마진을 확보함에 따라 절연 불량으로 인한 제조 수율 저하를 방지할 수 있다.Herein, the present invention performs a polishing process using different pressures on the thickest and the thinnest portions of the silicon wafer in a state in which an oxide film having a difference in polishing rate with the silicon is formed, thereby adjusting the thickness variation of the silicon wafer. It can be improved to about ± 0.2㎛ (-0.2㎛ ~ + 0.2㎛) improved by about 60% at ± 0.5㎛ of the through, thereby improving the thickness uniformity of the silicon layer on which the device is to be formed. Accordingly, as the process margin of the isolation process is secured during the manufacturing of the semiconductor device using the SOI wafer, a decrease in the manufacturing yield due to insulation failure can be prevented.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

이상에서와 같이, 본 발명은 접합법을 이용한 SOI 웨이퍼의 제조시 산화막이 형성된 상태에서 실리콘웨이퍼의 가장 두꺼운 부분에 가장 얇은 부분보다 높은 압 력을 사용해서 연마 공정을 수행함으로써, 실리콘층의 두께 균일도를 향상시킬 수 있다.As described above, the present invention provides a uniform thickness of the silicon layer by performing a polishing process using a pressure higher than the thinnest portion of the thickest portion of the silicon wafer while the oxide film is formed during the fabrication of the SOI wafer using the bonding method. Can be improved.

Claims (2)

실리콘웨이퍼와 매몰절연막 및 실리콘층의 적층 구조로 이루어진 SOI 웨이퍼의 제조방법으로서, A method of manufacturing an SOI wafer comprising a stacked structure of a silicon wafer, an investment insulating film, and a silicon layer, 매몰절연막이 형성된 제1실리콘웨이퍼 상에 제2실리콘웨이퍼를 합착시키는 단계;Bonding a second silicon wafer on the first silicon wafer on which the buried insulating film is formed; 상기 제2실리콘웨이퍼의 후면을 소망하는 실리콘층 두께보다 두껍도록 연삭하는 단계;Grinding the back surface of the second silicon wafer to be thicker than the desired silicon layer thickness; 상기 연삭시 발생된 결함이 제거되도록 제2실리콘웨이퍼 후면의 일부 두께를 1차 연마하는 단계;First grinding a part of the thickness of the rear surface of the second silicon wafer to remove defects generated during the grinding; 상기 1차 연마된 제2실리콘웨이퍼의 후면 상에 산화막을 형성하는 단계;Forming an oxide film on a rear surface of the first polished second silicon wafer; 상기 제2실리콘웨이퍼의 두께 균일도가 개선되도록 상기 산화막을 포함한 제2실리콘웨이퍼의 후면을 2차 연마하는 단계;Secondly polishing a rear surface of the second silicon wafer including the oxide layer to improve thickness uniformity of the second silicon wafer; 상기 2차 연마시 제거되지 않고 잔류된 산화막을 제거하는 단계; 및Removing the oxide film remaining without being removed during the second polishing; And 상기 2차 연마된 제2실리콘웨이퍼의 후면을 3차 연마하여 소망하는 두께의 실리콘층을 형성하는 단계;를 포함하며,Tertiary polishing the back surface of the second polished second silicon wafer to form a silicon layer of a desired thickness; 상기 산화막을 포함한 제2실리콘웨이퍼의 2차 연마는 거친 연마의 조건으로, 상기 제2실리콘웨이퍼의 가장 두꺼운 부분을 가장 얇은 부분보다 높은 압력을 사용해서 수행하면서, 가장 두꺼운 제2실리콘웨이퍼 부분이 노출되는 시점부터 잔류 제2실리콘웨이퍼의 두께 변동이 최소화되는 시점까지 수행하는 것을 특징으로 하는 SOI 웨이퍼의 제조방법.Secondary polishing of the second silicon wafer including the oxide film is performed under conditions of rough polishing, and the thickest second silicon wafer portion is exposed while the thickest portion of the second silicon wafer is performed using a pressure higher than the thinnest portion. SOI wafer manufacturing method characterized in that it is carried out from the point of time until the variation in the thickness of the remaining second silicon wafer is minimized. 제 1 항에 있어서,The method of claim 1, 상기 잔류 제2실리콘웨이퍼의 두께 변동이 최소화되는 시점은 ±0.2㎛ 이하인 것을 특징으로 하는 SOI 웨이퍼의 제조방법.The time point at which the variation in thickness of the remaining second silicon wafer is minimized is ± 0.2㎛ or less manufacturing method of the SOI wafer.
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