JPH0215628A - Manufacture of semiconductor wafer - Google Patents

Abstract

PURPOSE:To contrive the improvement of smoothness of the whole surfaces of the chamfering parts of semiconductor wafers by a method wherein a plurality of sheets of the semiconductor wafers performed mechanically a chamfering processing are pinchingly laminated interposing corrosion-resistant spacers between them and the laminated material is dipped into an etching liquid to etch the chamfering parts only. CONSTITUTION:A laminated material X is placed and clamped between a fixed supporting wall 8 and a movable pressing wall 10 of a clamping device Y and is dipped into an etching liquid W in a container H in a state that semiconductor wafers 2 and spacers 6 are completely adhered closely to one another. In this state, as parts of the wafers 2 which are not adhered closely to the spacers 6, that is, chamfering parts 12 only are exposed in the liquid W, the parts 12 only result in being etched as shown by dotted lines, for example. Parts of the wafers 2 which are adhered closely to the spacers 6 are never subjected to etching as never coming into contact with the liquid W. In such a way, the parts 12 only of the wafers 2 are etched.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention is a method for chamfering a plurality of semiconductor wafers that have been mechanically chamfered by sandwiching and stacking them with corrosion-resistant spacers interposed and immersing them in an etching solution. The present invention relates to a method for manufacturing a semiconductor wafer in which a chamfered portion etching process is performed in which only the chamfered portion is etched.

(Prior Art) As shown in FIG. 1, the conventional method for manufacturing semiconductor wafers includes a slicing step A in which a single crystal semiconductor ingot is sliced into thin plate shapes using a diamond cutter or the like to obtain semiconductor wafers, and a semiconductor wafer is obtained by slicing. a mechanical chamfering step B for mechanically removing the peripheral corner of the semiconductor wafer; a lapping step C for polishing both sides of the mechanically chamfered semiconductor wafer; A full-surface etching process in which the entire surface is etched by immersing it in an etching solution.
This process consists of a polishing step E in which one or both sides of the semiconductor wafer, which has been etched on its entire surface, is polished to a mirror surface.

The surface of the chamfered portion of the semiconductor wafer manufactured by this conventional manufacturing method has surface roughness formed by cutting with a diamond cutter or the like. If the surface of the chamfered portion is rough, there are disadvantages in that dirt and thermal distortion occur. One way to eliminate the surface roughness of the chamfered portion is to immerse the entire surface of the semiconductor wafer in an etching solution and dissolve and remove the surface roughness with the etching solution.

However, if the entire surface is etched, even if the chamfer is etched, the entire surface of the semiconductor wafer will be etched, so if etching is continued until the surface roughness of the chamfer is eliminated, crystal loss will increase.
On the other hand, when attempting to reduce crystal loss, there is a problem in that the surface roughness of the chamfered portion cannot be completely removed.

To solve this problem, before etching the entire surface,
A surface treatment method for a semiconductor wafer is disclosed in which only the chamfered portion of the semiconductor wafer is immersed in an etching solution (Japanese Patent Application Laid-open No. 134935/1983).

However, according to this method, when etching the chamfered portion, a plurality of semiconductor wafers are stacked and sandwiched with their main surfaces in close contact with each other. Scratches may occur, or etching liquid may enter between the semiconductor wafers.
Etching is not limited to the chamfered portion, and the main plane of the wafer is etched irregularly from the outer periphery, resulting in a partial reduction of the main plane of the wafer or a reduction in surface precision. These scratches are relatively deep, locally deteriorating the crystal quality of the surface layer of the wafer, and are not removed during the mirror polishing process on one side of the wafer after chamfering. This may cause defects or performance deterioration. In some cases, the presence of relatively large particles may cause cracks in the wafer. In addition, when the main plane is etched irregularly, even if mirror polishing is performed in a later process, the etched portion will not become mirror polished, resulting in deterioration of the performance or failure of the integrated circuit device formed on this portion. result.

(Problems to be Solved by the Invention) The present invention solves the problem that when etching the chamfered portion of a semiconductor wafer, the main surfaces of the semiconductor wafers that are held closely together are damaged, or the main planes are etched irregularly from the outer periphery. It is an object of the present invention to provide a method for manufacturing a semiconductor wafer, which can improve the smoothness of the entire surface of a chamfered portion without causing any chamfering.

(Means for Solving the Problems) In order to achieve the above object, the present invention includes a slicing process in which a single crystal semiconductor ingot is sliced into thin plates with a diamond cutter or the like to obtain a semiconductor wafer, and a semiconductor wafer obtained by the slicing. a mechanical chamfering process for mechanically removing a peripheral corner of the semiconductor wafer;
a lapping process for polishing both sides of the mechanically chamfered semiconductor wafer; a full-face etching process for etching the entire surface by immersing the lapped semiconductor wafer in an etching solution; and a full-face etching process for etching the entire surface of the semiconductor wafer. a polishing step of mirror-polishing one or both sides of the semiconductor wafer, in which a plurality of the mechanically chamfered semiconductor wafers are sandwiched and stacked with a corrosion-resistant spacer interposed therebetween, and then exposed to an etching solution. The chamfer etching process is performed by dipping and etching only the chamfered part.

More specifically, the chamfer etching process is performed before the lapping process, the chamfer etching process is performed after the lapping process, or the chamfer etching process is performed after the entire surface etching process.

The entire surface etching treatment may be performed by either acid etching or alkali etching.

(Function) When etching only the chamfered portion of a semiconductor wafer, the principal surfaces of both surfaces of the semiconductor wafer are not targeted, and it is necessary to prevent the etching solution from coming into contact with them using a suitable cover.

In the above-mentioned Japanese Patent Application Laid-Open No. 62-134935,
Semiconductor wafers are placed directly together (without intervening spacers) as a measure to prevent contact with the etching solution.
Multiple semiconductor wafers are stacked and held together with a chuck, but in such a state, the main surfaces of the stacked semiconductor wafers that are in contact with each other may be scratched, or the etching solution may enter the inside from the outer periphery of the main surfaces. However, even if the surface is irregularly partially etched and the subsequent mirror finishing step is performed, a mirror surface with high surface precision cannot be obtained, and in some cases, some portions remain in a non-mirror state.

In the present invention, the etching solution does not corrode.
That is, by interposing corrosion-resistant spacers, preferably elastic ones, semiconductor wafers are stacked alternately and bonded to each other by pressure, thereby preventing the etching liquid from coming into contact with the main surfaces of the semiconductor wafers. Since the semiconductor wafers do not come into direct contact with each other, they are prevented from being scratched, or the outer periphery of the main plane is prevented from being irregularly etched away due to the intrusion of etching liquid.

The spacer may be of any type as long as it prevents the etching solution from entering the main surface of the semiconductor wafer and effectively etches the chamfered portion, and various shapes are available as described in the examples below. It will be done.

The etching solution for etching the chamfer in the present invention is a known etching solution used for etching semiconductor wafers, such as hydrofluoric acid (50%): nitric acid (70%).
%): A mixed acid prepared by mixing acetic acid in a ratio of 3:5:3 is used.

Further, as the entire surface etching treatment (conventionally referred to simply as etching) in the present invention, any conventionally known acid etching or alkali etching can be applied.

Acid etching improves the smoothness of the microscopic surface of the semiconductor wafer, but there is a problem in that the macroscopic dimensional accuracy deteriorates. On the other hand, when alkaline etching is performed,
Although the macroscopic dimensional accuracy of the semiconductor wafer does not deteriorate, there is a problem in that the microscopic surface becomes rough.

Therefore, by combining alkali etching of the entire surface and chamfer etching, the advantage of alkali etching is that macroscopic dimensional accuracy is not compromised, and the smoothness of the chamfer is increased by etching of the chamfer, so alkali etching can improve the microscopic etching by alkali etching. This has the advantage that the disadvantage of surface roughness is suppressed.

Further, when machining and finishing the chamfered portion with a diamond grindstone, the smaller the grain size of the abrasive grains, the smoother the surface can be obtained even with a smaller amount of etching. Further, by reducing the abrasive grain size to about #3000, it is possible to form a microscopically smooth surface of the chamfered portion while accurately maintaining the dimensional accuracy of the chamfered portion using alkali etching. The smoothness of the chamfer should be approximately the same as that of the mirror polished surface, but the required degree of smoothness of the zero chamfer is made possible by controlling the amount of etching removed and the abrasive grain size of the diamond grinding wheel. In the heat treatment of the integrated circuit device manufacturing process, it is necessary not only to prevent crystalline deterioration of the wafer due to concentration of thermal stress, but also to prevent contaminants from adhering to and remaining in the valleys of the microscopic irregularities of the chamfered portion.

(Example) The method of the present invention will be explained below based on FIGS. 2 to 13 of the accompanying drawings.

FIG. 2 is a flowchart showing an example of the method of the present invention. In the same figure, A and B are respectively a slicing process and a mechanical chamfering process similar to the conventional method shown in FIG. F is a chamfer etching process in which a plurality of mechanically chamfered semiconductor wafers are sandwiched and stacked with corrosion-resistant spacers interposed therebetween, and then immersed in an etching solution to etch only the chamfered parts. C, D, and E are the lapping process, the entire surface etching process, and the polishing process similar to the conventional method, but differ from the conventional method in that they each process the semiconductor wafer that has undergone the chamfer etching process.

FIG. 3 is a flowchart showing another example of the method of the present invention. In the same figure, A, B, and C are respectively a slicing process, a mechanical chamfering process, and a lapping process similar to the conventional method shown in FIG. F is a chamfer etching step in which a plurality of lapped and mechanically chamfered semiconductor wafers are sandwiched and stacked with corrosion-resistant spacers interposed therebetween, and the wafers are soaked in an etching solution to etch only the chamfered portions. D is an entire surface etching step similar to the conventional method, but differs from the conventional method in that the semiconductor wafer, which has been subjected to the chamfer etching process, is immersed in an etching solution to etch the entire surface. E is also a polishing step similar to the conventional method shown in FIG.

FIG. 4 is a block diagram showing another example of the method of the present invention.

In the figure, A, B, C, and D are respectively a slicing process, a mechanical chamfering process, a lapping process, and an entire surface etching process similar to the conventional method shown in FIG. F is a chamfer etching step in which a plurality of mechanically chamfered semiconductor wafers that have been etched on the entire surface are sandwiched and stacked with corrosion-resistant spacers interposed, and then immersed in an etching solution to etch only the chamfered portions. E is a polishing step similar to the conventional method shown in FIG.

In the above steps, the slicing step A, the mechanical chamfering step B, the lapping step C, the entire surface etching step D (conventionally referred to simply as an etching step), and the polishing step E are well known, and detailed explanation thereof will be omitted.

As mentioned above, the entire surface etching process is as follows:
Either acid etching or alkali etching can be applied, but each has its advantages and disadvantages, and which etching to use should be appropriately determined depending on the intended use of the final product.

The chamfer etching process will now be described with reference to FIGS. 5 to 13. FIG. 5 is an explanatory diagram showing the state of implementation of the chamfer etching process. In the figure, 2 is a semiconductor wafer, and a plurality of semiconductor wafers 2 are sandwiched and laminated with corrosion-resistant spacers 6 interposed therebetween to form a laminate X. Note that if both surfaces of the semiconductor wafer 2 are wetted with a non-etching liquid or a viscous liquid, such as water, and then the spacers 6 are interposed, the adhesion between the two becomes extremely good.

The laminate X is a fixed support wall 8 of a tightening device Y to be described later.
The semiconductor wafer 2 and the spacer 6 are placed between the movable pressing wall 10 and the movable pressing wall 10, and are immersed in the etching solution W in the container H in a state where the semiconductor wafer 2 and the spacer 6 are in complete contact with each other. In this state, only the portion of the semiconductor chip 2 that is not in close contact with the spacer 6, that is, the chamfered portion 12, is exposed in the etching solution W. It will be etched as shown in .

On the other hand, the portion of the semiconductor wafer 2 that is in close contact with the spacer 6 does not come into contact with the etching solution W, and therefore is not etched. In this way, only the chamfered portion 12 of the semiconductor wafer 2 is etched.

The shapes of the corrosion-resistant spacer 6 used in the method of the present invention include the following, but it is needless to say that the shape is not limited to these examples. (2) Corrosion-resistant spacers 6a (FIG. 7) having the same side surface shape as the semiconductor wafer are the most common. In this case, when arranging the semiconductor wafers and the spacers, it is necessary to collapse the orientation flat portion, and it is convenient to use a special jig for arranging, which will be described later. (2) A tapered portion U may be provided around the entire circumference of a corrosion-resistant spacer (6b (FIG. 8)). With this shape, the etching solution can easily enter the peripheral edge of the semiconductor wafer, allowing for good etching. (2) A corrosion-resistant spacer 6c (FIG. 9) in which a concave portion V is provided all around the periphery can also be used. This has the same effect as the above item (2). (2) A structure 6d (Fig. 10) in which a step t is provided all around the circumferential side of a corrosion-resistant spacer can also be used. This also has the same effect as the above item (2). (2) 6e (Fig. 11), which has an opening or thinner part formed in the corrosion-resistant central part, is preferable for another purpose. In this case, there is an advantage that when tightened with a tightening jig to be described later, the tightening effect is greater and the intrusion of etching liquid is reduced accordingly. It is also preferable that the spacer 6 has elasticity, since this will increase the tightening effect accordingly.

FIG. 12 is an exploded perspective view showing an alignment jig 14 as an example of an apparatus for creating a laminate X of a semiconductor wafer 2 and a corrosion-resistant spacer 6.

The alignment jig 14 has a semi-cylindrical main body 18 which has a flat portion 16 formed at the bottom corresponding to the orientation flat portion of the semiconductor wafer 2 and has an inner diameter that matches the outer diameter of the semiconductor wafer 2. A pair of support columns 22 and 22 are provided upright at one end of the main body portion 18 with a gap 20 in between. A corrosion-resistant spacer 6 is attached to the semi-cylindrical main body 18 from the support column 22 side.
By aligning and sequentially stacking the semiconductor wafers 2 and 2, the laminate X can be easily formed.

Note that a known etching solution may be used for etching the chamfered portion, but as mentioned above, for example, 3 parts of hydrofluoric acid (50%): nitric acid (70%): acetic acid.
: A mixed acid mixed at a ratio of 5:3 is used. Further, as processing conditions, for example, immersion at 35° C. for about 30 seconds is sufficient. Further, the stacked body X of semiconductor wafers may be left standing in the etching solution, or may be rotated in the etching solution.

As shown in FIG. 13, the device Y for tightening the stacked body X of a plurality of semiconductor wafers 2 includes a connecting portion connecting the lower arm 26 and the upper arm 2, and the proximal ends of the lower arm 26 and the upper arm 28. 30, and has a fixed support wall 8 provided at the tip of the lower arm 26, and a fixed support wall 8 provided at the tip of the upper arm 26, and a fixed support wall 8 provided at the tip of the upper arm 26, which is movable up and down. The stacked body X of the semiconductor wafers 2 is placed between the fixed support wall 8 and the movable pressure wall 10 of the clamping device y, and the clamping device 34 having a movable pressing wall lO is used. It is tightened by lowering the pressing wall IO. Any known means may be used to attach the fastener 34 to the upper arm 28 in a vertically movable manner. What is necessary is to form a groove and screw it in so that it can move up and down. In this case, it goes without saying that the movable pressing wall 10 is movably attached to each other so that the fastener 34 can rotate. Reference numeral 36 is a guide plate, the tip of which is connected to the movable pressing wall 10. 10. Further, a groove portion 38 is provided at the base end of the guide plate 36 and is slidably inserted into the connecting portion 30 of the main body portion 32 . Therefore,
When the movable pressing wall 10 is moved up and down, the guide plate 36 also moves up and down along the connecting portion 30, and the movement of the movable pressing wall 10 is accurately guided in the vertical direction.

(Effects of the Invention) As described above, according to the method of the present invention, when etching a chamfered portion of a semiconductor wafer, the main surfaces of the semiconductor wafers that are tightly sandwiched are not scratched or the main surface of the wafer is damaged. This has the effect that irregular partial etching does not occur on the outer circumferential surface of the chamfer, and the smoothness of the entire surface of the chamfered portion can be improved.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing a conventional method for manufacturing a semiconductor wafer, FIG. 2 is a flowchart showing an example of a method for manufacturing a semiconductor wafer according to the present invention, and FIG. 3 is another example of a method for manufacturing a semiconductor wafer according to the present invention. FIG. 4 is a flowchart showing another example of the method for manufacturing a semiconductor wafer according to the present invention, FIG. 5 is an explanatory diagram showing one embodiment of the method of the present invention, and FIG. An explanatory diagram showing a state in which etching has been performed, FIGS. 7 to 11 are explanatory diagrams showing deformation of the shape of a corrosion-resistant spacer that can be used in the method of the present invention, and FIG. 12 is an illustration of an alignment that can be used in the method of the present invention. FIG. 13 is a perspective view showing an example of a jig and FIG. 13 is a perspective view showing an example of a fastener used in the method of the present invention. 2--Semiconductor wafer, 6--Spacer, 8--Fixed support wall, 10--Movable pressing wall, Work 2--Chamfer, X--Semiconductor wafer stack, Y--Tightening Equipment, W-...etching liquid, H-...container. Patent applicant Shin-Etsu Semiconductor Co., Ltd. Same as above Naoetsu Electronics Co., Ltd. Figure 5

Claims (5)

[Claims] (1) A slicing process in which a single crystal semiconductor ingot is sliced into thin plates using a diamond cutter or the like to form a semiconductor wafer, and a mechanical chamfering process in which the peripheral corners of the semiconductor wafer obtained by slicing are mechanically removed. a lapping process of polishing both sides of the mechanically chamfered semiconductor wafer; a full-face etching process of immersing the lapped semiconductor wafer in an etching solution to etch the entire surface; and a full-face etching process of the semiconductor wafer. A method for manufacturing a semiconductor wafer comprising a polishing step of mirror-polishing one or both sides of the wafer, in which a plurality of mechanically chamfered semiconductor wafers are sandwiched and stacked with a corrosion-resistant spacer interposed therebetween and then etched. A method for manufacturing a semiconductor wafer, characterized in that a chamfer etching process is performed in which the chamfer is immersed in a liquid and only the chamfer is etched. (2) The method for manufacturing a semiconductor wafer according to claim (1), wherein the chamfer etching process is performed before the lapping process. (3) The method for manufacturing a semiconductor wafer according to claim (1), wherein the chamfer etching process is performed after the lapping process. (4) The method for manufacturing a semiconductor wafer according to claim (1), wherein the chamfering etching process is performed after the entire surface etching process. (5) The method for manufacturing a semiconductor wafer according to claim (1), (2), (3) or (4), wherein the entire surface etching treatment is performed by acid etching or alkali etching.