JP2020120128A - Composite substrate - Google Patents

Abstract

To provide a composite substrate capable of maintaining high resistance after processing at 300°C, and a method of manufacturing the composite substrate.SOLUTION: A composite substrate according to the present invention is manufactured by bonding a silicon (Si) wafer as a support substrate having interstitial oxygen concentration of 2 to 10 ppma to a piezoelectric material substrate and thinning the piezoelectric material substrate after bonding. The piezoelectric material substrate is particularly preferably a lithium tantalate wafer (LT) substrate or a lithium niobate (LN) substrate.SELECTED DRAWING: Figure 1

Description

The present invention relates to a composite substrate used for a surface acoustic wave (SAW) device or the like and a method for manufacturing the composite substrate.

In recent years, in the mobile communication market represented by smartphones, the amount of communication has been rapidly increasing. In order to cope with this, it is inevitably important to increase the number of bands required and to miniaturize and improve the performance of various parts.

Common piezoelectric materials such as lithium tantalate (sometimes abbreviated as LT) and lithium niobate (sometimes abbreviated as LN) are used in surface acoustic wave (SAW) devices. Widely used as a material. These materials have a large electromechanical coupling coefficient and can be used for a wide band, but have low temperature stability and have a problem that the frequency that can be handled shifts due to temperature change. This is because lithium tantalate or lithium niobate has a very high coefficient of thermal expansion.

In order to reduce this problem, lithium tantalate or lithium niobate is bonded with a material having a smaller thermal expansion coefficient, specifically sapphire, and a wafer of lithium tantalate or lithium niobate is ground to several μm. A method has been proposed in which thermal expansion is suppressed and temperature characteristics are improved by thinning the thickness to tens of micrometers (for example, see Non-Patent Document 1). FIG. 5 is a graph showing the thermal expansion coefficients of various materials for comparison. Among them, silicon has a small coefficient of thermal expansion, is easy to be cleaved, has high thermal conductivity, and is excellent in workability, and thus seems to be a well-balanced and excellent choice.

However, this method also has problems. Silicon (Si) is not an insulator like the other materials (quartz, sapphire, etc.) shown in FIG. Therefore, when Si is used for the supporting substrate made of a thinned piezoelectric material such as LT, some dielectric loss occurs. This dielectric loss deteriorates characteristics such as Q value (resonance sharpness). In order to suppress the dielectric loss, it is necessary to maximize the resistivity of the Si substrate. In order to increase the resistivity of the Si substrate, it is important to reduce the amount of oxygen mixed in the Si crystal during the manufacturing process as much as possible. Ordinary Si is manufactured by the CZ method (Czochralski method). At this time, a single crystal ingot is pulled up from Si melted in a quartz crucible. At this time, it is difficult to completely prevent mixing of oxygen from the quartz crucible.

From this, it seems that the FZ method (Floating Zone method) that does not use a quartz crucible for growth is desirable for producing high-resistance Si. However, the FZ method has problems that it is difficult to increase the diameter (up to 150 mmΦ at the maximum) and that the productivity is lower than that of the normal CZ method. Further, not only the productivity of the manufacturing process but also the supply problem that polysilicon having a small amount of impurities must be carefully selected as a material has a great influence on the overall productivity of the FZ method.

Several methods have been proposed to solve the productivity problem (see Patent Document 1, for example). What is disclosed in Patent Document 1 is a method that uses the CZ method instead of the FZ method that is a factor of low productivity. That is, by applying a magnetic field (Magnetic Field Applied CZ: MCZ method), convection of the melt is suppressed when growing a single crystal silicon ingot, oxygen contamination from the quartz crucible is prevented as much as possible, and the dissolved contaminants are present. High resistance is achieved by precipitating oxygen by a special heat treatment. However, since it requires a special heat treatment for promoting oxygen precipitation, it is still difficult to fundamentally improve the productivity, though not as much as the FZ method.

In addition to the resistivity at room temperature, another reason why it is difficult to manufacture a high-resistance wafer is that it is necessary to maintain a high resistance even after a normal semiconductor CMOS process (up to about 1050° C.). Is. In particular, the temperature range (400° C. to 600° C.) in which it is said that the dissolved oxygen becomes a donor (thermal donor) to reduce the resistivity can be said to be a dangerous temperature range in which the reduction in the resistivity can be particularly pushed. Therefore, it is not easy to manufacture a wafer that maintains a high resistance after the CMOS process.

There is also a more serious and fundamental problem than the resistivity problem. It is a problem of mechanical strength (or heat resistance) of Si itself. Since the LT/Si bonded wafer has an extremely large difference in expansion coefficient between LT and Si, if a low temperature heat treatment (for example, 300° C.) is performed after bonding, a crystal shift called slip occurs on the Si substrate or the substrate itself is cracked. It may be lost. FIGS. 6 and 7 show optical micrographs of slips produced after heat treatment at 300° C. was applied to a wafer obtained by bonding an LT (20 μm thick) and a high resistance (>1000 Ωcm) FZ wafer (oxygen concentration is less than 1 ppma). .. These photographs are observations of the portion where the LT was peeled off after the occurrence of slip. FIG. 6 is a photograph near the outer circumference of the substrate, and FIG. 7 is a photograph near 5 mm from the outer circumference of the substrate. When the slip occurs, the LT around it may be peeled off and the substrate may be damaged. This is considered to be a big problem because a low oxygen concentration wafer is used.

As an important point regarding the occurrence of slip, the increase in the oxygen concentration dissolved in the Si wafer to be used increases the yield stress and causes the Si crystal to become “sticky” (see, for example, Non-Patent Document 2) and slip (dislocation). It has become clear that is less likely to occur.

That is, in order to suppress the dielectric loss, it is necessary to reduce the amount of dissolved oxygen in order to increase the resistivity, while it is necessary to increase the amount of dissolved oxygen in order to suppress the problem of mechanical strength.

In the present specification, the method for measuring dissolved oxygen was based on JEIDA-61-2000, which is a standard method for measuring the atomic concentration of interstitial oxygen using infrared rays. This method measures 1106 cm ⁻¹ which is an absorption peak peculiar to interstitial oxygen. A JIR-6500 Fourier transform infrared spectroscope (FT-IR) manufactured by JEOL Ltd. was used as a measuring device. The interstitial oxygen concentration (ppma) is obtained by multiplying the absorption coefficient α obtained here by a coefficient of 6.28. In this specification, the interstitial oxygen concentration obtained by this method is simply referred to as "oxygen concentration".

US Pat. No. 6,544,656

Denpa Shimbun High Technology, November 8, 2012, "SAW-Duplexer Temperature Compensation Technology Used for RF Front Ends of Smartphones" UCS Semiconductor Technology Research Group, "Science of Silicon" Realize Science and Technology Center, June 28, 1996, p.576-582

An object of the present invention is to provide a composite substrate and a method for manufacturing the composite substrate that can maintain high resistance after the process at 300°C.

In order to solve the problems of dielectric loss and mechanical strength that occur when Si is used as a supporting substrate, the present inventors focus on the manufacturing process of LT-SAW devices including an LT/Si bonded substrate. did. SAW devices such as LT and LT/Si do not require a high temperature process (such as gate oxidation) unlike the semiconductor CMOS process, and the maximum temperature is about 300° C. at the maximum. If the high resistance is maintained up to this temperature, there will be no problem in characteristics. Therefore, the inventors arrived at the idea that a Si substrate capable of maintaining high resistance up to about 300° C. should be used as a supporting substrate. From this point of view, even if the oxygen concentration is somewhat high, it can be said that this purpose is met. That is, in the application to the LT-SAW device, whether or not the high resistance can be maintained after the process at 300° C. is a very important criterion for judging the adoption.

In order to solve the above-mentioned problems, the composite substrate according to the present invention is configured such that a silicon (Si) wafer having an interstitial oxygen concentration of 2 to 10 ppma is bonded to a piezoelectric material substrate as a supporting substrate, and the piezoelectric material substrate is bonded after bonding. It is characterized by being manufactured by thinning.

In the present invention, the piezoelectric material substrate may be a lithium tantalate wafer (LT) substrate or a lithium niobate (LN) substrate. Further, it is preferable to use a silicon wafer that is cut out from a crystal manufactured by any one of the FZ method, the MCZ method, and the CZ method.

In the present invention, the composite substrate may have an intervening layer between the piezoelectric material substrate and the silicon wafer. The intervening layer may include any one of a silicon oxide film, a silicon nitride film, silicon oxynitride (SiON), and amorphous silicon. Further, the intervening layer may be thermally oxidized silica. The intervening layer may be formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD), or may be formed by applying a silicone-based oil. When the intervening layer is formed by applying a silicone-based oil, the oil preferably contains perhydropolysilazane or methyltrimethoxysilane. By providing such an intervening layer, the bonding strength can be increased and peeling can be suppressed.

In the present invention, one or both of the piezoelectric material substrate and the silicon wafer may be subjected to surface activation treatment before bonding. In this case, the surface activation treatment may be performed using a vacuum ion beam or plasma activation method. Bonding strength can be increased by these surface activation treatments.

In order to solve the above-mentioned problems, the method for manufacturing a composite substrate according to the present invention provides a step of preparing a piezoelectric material substrate and a silicon (Si) wafer having an interstitial oxygen concentration of 2 to 10 ppma as a supporting substrate. A step of bonding the piezoelectric material substrate and the silicon wafer, and a step of thinning the piezoelectric material substrate after the bonding step.

In the present invention, the piezoelectric material substrate may be a lithium tantalate wafer (LT) substrate or a lithium niobate (LN) substrate. Further, it is preferable to use a silicon wafer that is cut out from a crystal manufactured by any one of the FZ method, the MCZ method, and the CZ method.

The present invention may further include a step of providing a surface of one or both of the piezoelectric material substrate and the silicon wafer and an intervening layer before the step of bonding. The intervening layer may include any one of a silicon oxide film, a silicon nitride film, silicon oxynitride (SiON), and amorphous silicon. In addition, the silicon wafer may be thermally oxidized in the step of providing the intervening layer. Further, in the step of providing the intervening layer, the intervening layer may be formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD). Further, in the step of providing the intervening layer, the intervening layer may be formed by applying a silicone-based oil. In this case, the silicone oil preferably contains perhydropolysilazane or methyltrimethoxysilane.

The present invention may further include a step of performing a surface activation treatment on one or both of the piezoelectric material substrate and the silicon wafer before the bonding step. The surface activation treatment may be performed using a vacuum ion beam or plasma activation method. Bonding strength can be increased by these surface activation treatments.

It is a flow chart of a manufacturing process of a compound substrate concerning this embodiment. It is a schematic cross section which illustrates the composite substrate which concerns on this embodiment. 5 is a graph showing the results of Example 2. 9 is a graph showing the results of Example 3. It is a graph which shows in comparison the coefficient of thermal expansion of various materials. It is an optical microscope photograph of a slip generated after applying heat treatment in the vicinity of the outer periphery of the Si substrate. It is an optical microscope photograph of a slip generated after applying a heat treatment in the vicinity of 5 mm from the outer periphery of the Si substrate.

The composite substrate 1 of the present embodiment is manufactured through a process of performing pre-bonding processing on the support substrate 10 and the piezoelectric material substrate 20 as needed, and then bonding both substrates. The manufacturing method will be described below with reference to the flowchart shown in FIG.

[Treatment of supporting substrate]
First, the support substrate 10 is prepared (step S100). As the support substrate 10, a silicon (Si) wafer having an interstitial oxygen concentration of 2 to 10 ppma is used. The Si wafer used as the support substrate 10 is cut out from a Si single crystal ingot manufactured by the FZ method, the MCZ method, or the CZ method.

Then, the intervening layer 31 is formed on the surface of the support substrate 10 as needed (step S120). The material of the intervening layer 31 may include any one of a silicon oxide film, a silicon nitride film, silicon oxynitride (SiON), and amorphous silicon. The intervening layer 31 can be formed, for example, as a film of thermally oxidized silica obtained by thermally oxidizing a Si wafer. Since the thermally oxidized silica is grown at a high temperature, it has a property that it is dense, has few impurities, and can absorb a certain amount of gas. The intervening layer 31 may be formed by another method. For example, the intervening layer 31 may be formed by depositing a suitable material as the intervening layer by chemical vapor deposition (CVD) such as plasma CVD. Further, the intervening layer 31 may be formed by depositing a suitable material as the intervening layer by physical vapor deposition (PVD). Alternatively, the intervening layer 31 may be formed by applying silicone oil. The applied silicone-based oil may contain perhydropolysilazane or methyltrimethoxysilane. The silicone oil may be applied by spin coating.

Then, if necessary, the surface to be bonded to the piezoelectric material substrate 20 is flattened (step S140). As the degree of flattening, it is preferable that the surface roughness Ra (arithmetic mean roughness) is 0.3 nm or less. This flattening may be performed by chemical mechanical polishing. When the intervening layer 31 is not provided on the supporting substrate 10, the supporting substrate 10 itself is flattened. When the intervening layer 31 is provided on the support substrate 10, the surface of the intervening layer 31 is flattened. When the intervening layer 31 is provided, the characteristics of the composite substrate 1 do not depend on the initial surface roughness of the supporting substrate 10 that is the base. For example, the initial surface roughness Ra of the support substrate 10 may be 150 nm or more.

Further, as described as “if necessary”, if a sufficiently flat surface can be obtained without going through the flattening step, the flattening step may be omitted. For example, when the support substrate 10 whose surface is finished as a mirror surface is used and the intervening layer 31 is formed by thermal oxidation, the surface of the intervening layer 31 is also a mirror surface like the base, and thus this flattening step is unnecessary. is there.

Furthermore, in order to increase the bonding strength at the time of bonding, the surface to be bonded (that is, the surface of the supporting substrate 10 when the intervening layer 31 is not provided, the surface of the supporting substrate 10 when the intervening layer 31 is provided, and the intervening layer 31 when the intervening layer 31 is provided). An activation process is applied to the surface (step S160). The surface activation treatment may be, for example, one of ozone water treatment, UV ozone treatment, ion beam treatment, and plasma treatment.

This completes the processing before bonding to the support substrate 10.

[Treatment of piezoelectric material substrate]
First, the piezoelectric material substrate 20 is prepared (step S200). The piezoelectric material substrate 20 is a substrate of a piezoelectric material such as lithium tantalate (LT) or lithium niobate (LN), and is preferably a single crystal substrate of these piezoelectric materials.

Subsequently, if necessary, the intervening layer 32 is formed on the surface of the piezoelectric material substrate 20 (step S220). The material of the intervening layer 32 may include any one of a silicon oxide film, a silicon nitride film, silicon oxynitride (SiON), and amorphous silicon. The intervening layer 32 can be formed by the following method. That is, the intervening layer 32 may be formed by depositing a suitable material as the intervening layer by chemical vapor deposition (CVD) such as plasma CVD. Further, the intervening layer 32 may be formed by depositing a suitable material as the intervening layer by physical vapor deposition (PVD). Alternatively, the intervening layer 32 may be formed by applying silicone oil. The applied silicone-based oil may contain perhydropolysilazane or methyltrimethoxysilane. The silicone oil may be applied by spin coating.

Then, if necessary, the surface to be bonded to the support substrate 10 is flattened (step S240). As the degree of flattening, it is preferable that the surface roughness Ra (arithmetic mean roughness) is 0.3 nm or less. This flattening may be performed by chemical mechanical polishing. When the intervening layer 32 is not provided on the piezoelectric material substrate 20, the piezoelectric material substrate 20 itself is flattened. Further, when the intervening layer 32 is provided on the piezoelectric material substrate 20, the surface of the intervening layer 32 is flattened. When the intervening layer 32 is provided, the characteristics of the composite substrate 1 do not depend on the initial surface roughness of the piezoelectric material substrate 20 as the base. For example, the initial surface roughness Ra of the piezoelectric material substrate 20 may be 150 nm or more.

Further, in order to enhance the bonding strength at the time of bonding, the surface to be bonded (that is, the surface of the piezoelectric material substrate 20 when the intervening layer 32 is not provided, or the intervening layer 32 when the intervening layer 31 is provided, if necessary. The activation process is performed on the surface of the (step S260). The surface activation treatment may be any one of ozone water treatment, UV ozone treatment, ion beam treatment (for example, vacuum ion beam treatment), and plasma treatment.

With the above, the process before bonding to the piezoelectric material substrate 20 is completed.

[Lamination and subsequent processing]
The support substrate 10 processed as described above and the piezoelectric material substrate 20 are attached to each other (step S300). In that case, it is good to heat at low temperature and to raise joining strength. The heating temperature at this low temperature is preferably about 100° C., and the heating time is preferably about 24 hours.

Subsequently, if necessary, the piezoelectric material substrate 20 is ground and polished to be thinned (step S320). For example, the thickness of the piezoelectric material substrate 20 is reduced to about 20 μm. Thereafter, if necessary, additional heat treatment may be performed to strengthen the bonding force (step S340).

By the manufacturing method described above, the composite substrate 1 in which the piezoelectric material substrate 20 and the support substrate 10 are bonded together can be manufactured. FIG. 2 shows a schematic cross-sectional view of the composite substrate 1 according to this embodiment. In the composite substrate 1, the intervening layer 31 provided on the support substrate 10 and/or the intervening layer 32 provided on the piezoelectric material substrate 20 serve as the intervening layer 30 sandwiched between the piezoelectric material substrate 20 and the support substrate 10.

Hereinafter, examples performed to confirm the effects of the present invention will be described. Although an example in which a lithium tantalate (LT) wafer is mainly used as a piezoelectric material substrate will be described, the same effect can be obtained by using a lithium niobate (LN) wafer instead of the LT wafer.

[Example 1]
Ten types of 150 mmΦ Si wafers (thickness 625 μm, P type, resistivity around 1100 Ωcm) were prepared, and 150 mmΦ LT wafers (thickness 250 μm) were bonded. Table 1 shows the method for producing a single crystal ingot and the oxygen concentration for each of the 10 types of prepared Si wafers. The type of wafer is represented by a combination of the method for producing a single crystal ingot and the numerical value of oxygen concentration. For example, a 1 ppma wafer manufactured by the FZ method is described as “FZ1”.

It was confirmed that the surface roughness of the Si wafer and the LT wafer to be bonded together was Ra (arithmetic mean roughness) of 0.3 nm or less. The bonding was performed by a room temperature bonding method using a vacuum ion beam. After bonding, the LT wafer was thinned to 20 μm by grinding and polishing. The composite substrate wafer thus bonded was reciprocated between the hot plate at 300° C. and the cooling stage 10 times, and then the occurrence of slip and the cracking condition of the wafer were observed. The results are shown in Table 2. From this result, it was found that the occurrence of slip and the cracking of the wafer can be prevented if the oxygen concentration of the Si wafer is 2 ppma or more. The same result was obtained when LN was used instead of LT in the same experiment.

[Example 2]
Ten kinds of Si wafers similar to those in Example 1 were prepared, and heat treatments at 250° C., 300° C., 350° C., 400° C., 450° C. and 500° C. were performed in a nitrogen atmosphere for 1 hour. The results of measuring the resistivity before and after the heat treatment are shown in Table 3 and FIG. As a result, if the oxygen concentration of the Si wafer is 10 ppma or less, the resistivity does not change even if heat treatment is performed up to 350° C., which is considered to be the maximum temperature of the LT device manufacturing process, regardless of the Si single crystal ingot manufacturing method. It turned out to be almost nonexistent.

[Example 3]
A resonator was manufactured using the wafers of 10 kinds of composite substrates obtained in Example 1, and the Q value was measured. The maximum temperature of the manufacturing process of the resonator that is the LT device is about 350°C. For a broken wafer, a surviving portion (that is, a portion having a size capable of manufacturing a device) was used, and for a slipped wafer, a device was manufactured in a portion without slipping, and measurement was performed. The results of the Q value are shown in Table 4 and FIG. From these results, it was observed that the characteristics of the Si wafer having an oxygen concentration of 10 ppma or less did not deteriorate, and the characteristics of the Si wafer having an oxygen concentration of more than 10 ppma deteriorated. This result was found to be consistent with the change in resistivity in Example 2.

[Example 4]
Ten types of 150 mmΦ Si wafers (thickness 625 μm) similar to those in Example 1 were prepared, and a 100 nm thermal oxide film was grown. The conditions of thermal oxidation are 700° C. input and 1000° C. dry oxidation. In addition, a 150 mmΦ LT wafer (thickness 250 μm) was prepared. Surface activation was performed by plasma activation on both the Si wafer and the LT wafer on which the thermal oxide film was grown, and both wafers were bonded. After the bonding, heat treatment was performed at 100° C. for 24 hours. It was confirmed that the surface roughness of each wafer before bonding was 0.3 nm or less in Ra.

After bonding and heat treatment, the LT wafer was thinned to 20 μm by grinding and polishing. These wafers were reciprocated between a hot plate at 300° C. and a cooling stage 10 times, and then the occurrence of slip and the cracking state of the wafer were observed. The results are shown in Table 5. From this result, it was found that slip generation and wafer cracking can be prevented if the oxygen concentration of the Si wafer is 2 ppma or more. This result is almost the same as in Example 1, and regardless of the presence or absence of the thermal oxide film, the occurrence of slip and the cracking of the wafer depend on the oxygen concentration of the Si wafer, and it is important that the oxygen concentration is 2 ppma or more. There was found.

[Example 5]
Ten types of Si wafers similar to those in Example 1 were prepared and subjected to thermal oxidation in the same manner as in Example 4. With respect to the Si wafer thus provided with the thermal oxide film, the conditions of the additional heat treatment were changed, and the resistivity before and after the additional heat treatment was measured. The conditions for the additional heat treatment were six without heat treatment, 250° C., 300° C., 350° C., 400° C. and 500° C., and the additional heat treatment was performed in a nitrogen atmosphere for 1 hour. The resistivity was measured before and after that. The results of the measurement were almost the same as in Example 2, and it was found that if the oxygen concentration was 10 ppma or less, there was almost no change in the resistivity even if heat treatment was performed up to 350°C. It was found that even when using a Si wafer provided with a thermal oxide film, by avoiding the treatment in the thermal donor generation temperature range (400 to 600° C.), it can be used without a problem such as a decrease in resistivity.

[Example 6]
Ten kinds of 150 mmΦ Si wafers (thickness: 625 μm) similar to those in Example 1 were prepared, and a 200 nm plasma CVD oxide film was deposited near room temperature. After depositing the oxide film, polishing was performed for mirroring. In addition, a 150 mmΦ LT wafer (thickness 250 μm) was prepared. Surface activation was performed by plasma activation on both the Si wafer and the LT wafer on which the oxide film was deposited, and the both wafers were bonded together. After the bonding, heat treatment was performed at 100° C. for 24 hours. It was confirmed that the surface roughness of both wafers before bonding was Ra of 0.3 nm or less. As a result of the same heat resistance experiment as in Example 1, the same tendency as in Example 1 was shown. From this result, it was found that the effect of the present invention can be obtained regardless of the method of forming the oxide film.

[Example 7]
Similar to Example 1, ten kinds of 150 mmΦ Si wafers (thickness 625 μm) and 150 mmΦ LT wafers (thickness 250 μm) were prepared, and a 200 nm plasma CVD oxide film was deposited on the LT wafer near room temperature. After the deposition, polishing was performed for mirroring. Surface activation was performed by plasma activation on both the Si wafer and the LT wafer on which an oxide film was deposited, and the two wafers were bonded together. After the bonding, heat treatment was performed at 100° C. for 24 hours. It was confirmed that the surface roughness of both wafers before bonding was Ra of 0.3 nm or less. The same heat resistance experiment as in Example 1 was performed, but the results showed exactly the same tendency as in Example 1. From this result, it was found that the effect of the present invention can be obtained irrespective of where the oxide film is formed (that is, which of the Si wafer and the LT wafer is provided with the intervening layer such as the oxide film).

[Example 8]
Similar to Example 1, ten types of 150 mmΦ Si wafers (thickness 625 μm) and a roughened surface (Ra=160 nm) 150 mmΦ LT wafer (thickness 250 μm) were prepared, and a 5 μm plasma CVD oxide film was used as the LT. It was deposited on the wafer near room temperature. After the deposition, polishing was performed for mirroring. Surface activation was performed by plasma activation on both the Si wafer and the LT wafer on which an oxide film was deposited, and the two wafers were bonded together. After the bonding, heat treatment was performed at 100° C. for 24 hours. It was confirmed that the surface roughness of both wafers before bonding was Ra of 0.3 nm or less. The results showed exactly the same tendency as in Example 1. From this result, it was found that the effect of the present invention can be obtained without depending on the initial surface roughness of the LT wafer forming the intervening layer. Similarly, when Si (Ra=175 nm) having a rough surface was used and the same experiment was performed, the same results as in Example 1 were shown. Similar results were also obtained when the intervening layer was provided on the surface where both LT and Si were bonded together. Therefore, when the intervening layer is provided between LT and Si, it has been found that the effect of this method is not affected even if one or both of the LT or Si bonding surfaces is not mirror-finished.

[Example 9]
Ten kinds of 150 mmΦ Si wafers (thickness: 625 μm) similar to those in Example 1 were prepared, and a 200 nm plasma CVD nitride (SiN) film was deposited near room temperature. After the deposition, polishing was performed for mirroring. In addition, a 150 mmΦ LT wafer (thickness 250 μm) was prepared. Surface activation was performed by plasma activation on both the Si wafer and the LT wafer on which the nitride film was deposited, and the both wafers were bonded together. After the bonding, heat treatment was performed at 100° C. for 24 hours. It was confirmed that the surface roughness of both wafers before bonding was Ra of 0.3 nm or less. The results showed exactly the same tendency as in Example 1. It was found that this method does not depend on the method of forming an oxide film. Similarly, when amorphous Si (formed by a physical vapor deposition method (PVD method)), SiON, or the like is deposited on a Si wafer, similar results are obtained. From this result, it was found that the effect of the present invention can be obtained regardless of the type (material) of the intervening layer. Similar results were obtained when the silicon oxide film was formed by spin coating a silicone oil such as perhydropolysilazane or methyltrimethoxysilane.

From the above results, high mechanical strength and heat resistance (slip resistance, substrate crack resistance) can be achieved by using a Si wafer having an interstitial oxygen concentration of 2 to 10 ppma as a supporting substrate, and at the same time, device characteristics (Q It has been found that the deterioration of (value) can also be prevented. It was also found that it does not depend on the presence or type of the intervening layer or the initial surface roughness of the substrate. Since a Si wafer manufactured by the CZ method can also be used as a supporting substrate, it has been found that the problems of mechanical strength and dielectric loss can be solved and at the same time low cost can be achieved.

Although the present embodiment has been described above, the present invention is not limited to these examples. For example, a person skilled in the art appropriately added, deleted, or modified the configuration of each of the above-described embodiments, or a combination of the features of the embodiments is also included in the gist of the present invention. As long as it is included in the scope of the present invention.

DESCRIPTION OF SYMBOLS 1... Composite substrate 10... Support substrate 20... Piezoelectric material substrate 30, 31, 32... Intervening layer

Claims (24)

A composite substrate produced by bonding a silicon (Si) wafer having an interstitial oxygen concentration of 2 to 10 ppma as a supporting substrate to the piezoelectric material substrate, and thinning the piezoelectric material substrate after the bonding. The composite substrate according to claim 1, wherein the piezoelectric material substrate is a lithium tantalate wafer (LT) substrate or a lithium niobate (LN) substrate. The composite substrate according to claim 1 or 2, wherein the silicon wafer is cut out from a crystal manufactured by any one of the FZ method, the MCZ method, and the CZ method. The composite substrate according to any one of claims 1 to 3, further comprising an intervening layer between the piezoelectric material substrate and the silicon wafer. The composite substrate according to claim 4, wherein the intervening layer contains any one of a silicon oxide film, a silicon nitride film, silicon oxynitride (SiON), and amorphous silicon. The composite substrate according to claim 4, wherein the intervening layer is thermally oxidized silica. The composite substrate according to claim 4, wherein the intervening layer is formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD). The composite substrate according to claim 4, wherein the intervening layer is formed by applying a silicone-based oil. The composite substrate according to claim 8, wherein the silicone-based oil contains perhydropolysilazane or methyltrimethoxysilane. The surface of at least one of the piezoelectric material substrate and the silicon wafer is non-mirror surface, and the intervening layer is provided in advance on the surface of the non-mirror surface before bonding. 10. The composite substrate according to any one of items 1 to 9. The composite substrate according to any one of claims 1 to 10, wherein one or both of the piezoelectric material substrate and the silicon wafer are subjected to surface activation treatment before bonding. The composite substrate according to claim 11, wherein the surface activation treatment is performed using a vacuum ion beam or a plasma activation method. A step of preparing a piezoelectric material substrate,
A step of preparing a silicon (Si) wafer having an interstitial oxygen concentration of 2 to 10 ppma as a supporting substrate,
Bonding the piezoelectric material substrate and the silicon wafer,
And a step of thinning the piezoelectric material substrate after the bonding step. 14. The method of manufacturing a composite substrate according to claim 13, wherein the piezoelectric material substrate is a lithium tantalate wafer (LT) substrate or a lithium niobate (LN) substrate. The method of manufacturing a composite substrate according to claim 13 or 14, wherein the silicon wafer is cut out from a crystal manufactured by any one of the FZ method, the MCZ method, and the CZ method. The method according to any one of claims 13 to 15, further comprising a step of providing an intervening layer on a surface of either or both of the piezoelectric material substrate and the silicon wafer before the bonding step. A method for manufacturing a composite substrate. The method of manufacturing a composite substrate according to claim 16, wherein the intervening layer contains any one of a silicon oxide film, a silicon nitride film, silicon oxynitride (SiON), and amorphous silicon. The method of manufacturing a composite substrate according to claim 16, wherein the silicon wafer is thermally oxidized in the step of providing the intervening layer. 18. The method of manufacturing a composite substrate according to claim 16, wherein in the step of providing the intervening layer, the intervening layer is formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD). 18. The method of manufacturing a composite substrate according to claim 16, wherein in the step of providing the intervening layer, the intervening layer is formed by applying a silicone-based oil. The method of manufacturing a composite substrate according to claim 20, wherein the silicone-based oil contains perhydropolysilazane or methyltrimethoxysilane. 22. The surface of at least one of the piezoelectric material substrate and the silicon wafer is a non-mirror surface, and the intervening layer is provided in advance on the surface of the non-mirror surface before bonding. Item 1. A method for manufacturing a composite substrate according to item 1. The method according to any one of claims 13 to 22, further comprising a step of subjecting one or both of the piezoelectric material substrate and the silicon wafer to a surface activation treatment before the bonding step. A method for manufacturing a composite substrate. 23. The method of manufacturing a composite substrate according to claim 22, wherein the surface activation treatment is performed using a vacuum ion beam or a plasma activation method.