TW201344211A - Burn-in tester - Google Patents

Abstract

The present invention relates to burn-in tester, comprising at least one test panel, a panel-receiving chamber for receiving said at least one test panel, at least a test substrate for generating test signals for testing semiconductor elements carried in the at least one test panel, and a substrate receiving chamber. According to the present invention, a technique is disclosed as follows, i.e., the test panel comprises sockets belonging to the same row formed on a transmission wire group, and a leap-type structure is employed to enable the test signals to be applied sequentially to the semiconductor elements, the test substrate generating strobe signals to accurately sample the feedback resulting signals from the semiconductor elements, so as to realize accurate data sampling in high-speed processing.

Description

Aging test equipment

The present invention relates to a test panel of a burn-in tester that tests the reliability of a semiconductor component for thermal stress when a power source is applied to the packaged semiconductor element and is operated.

The semiconductor element undergoes various tests after production, and the burn-in test associated with the present invention is a test for confirming how much thermal stress the semiconductor element can withstand when an electrical signal is applied to the semiconductor element and operated. Moreover, the device that implements such an aging test is an aging test device.

The aging test apparatus is provided with an aging chamber for accommodating a semiconductor component, and the aging chamber is configured to read a result signal fed back after applying a test signal to the semiconductor component housed in the aging chamber Test substrate.

The semiconductor element is mounted on the test board in a matrix form, and is housed in the aging chamber in this state to test a plurality of semiconductor elements at a time, and in order to further increase the processing capacity, the aging chamber has a structure in which a plurality of test boards are simultaneously accommodated. . Moreover, the semiconductor component mounted on the test board passes through the test board The equipped board connector is electrically connected to the test substrate.

In general, as disclosed in Korean Laid-Open Utility Model No. 1999-004919 (Aging Board for Semiconductor Package Testing, hereinafter referred to as "Prior Art"), a test board (named "Aging Board" in the prior art) has a plurality of sockets, The circuit substrate (named "PCB" in the prior art) and the connector (named "connecting portion" in the prior art) and the like. According to the test board having such a structure, the test signal from the test substrate transmitted through the connector is applied to the semiconductor element on each of the sockets loaded with the semiconductor elements through the circuit on the circuit substrate.

However, in the past, as shown in FIG. 1, the test signal from the test substrate transmitted through the connector is applied to the semiconductor element D mounted on each of the sockets through the circuit C of the tree structure, at this time, due to the radiation originating from the tree structure, The test signal becomes weak, which eventually causes the response speed of the semiconductor element to slow down and reduce the processing speed.

Accordingly, it is an object of the present invention to provide a technique that does not generate radiation of a test signal.

The burn-in test apparatus provided by the present invention as described above includes: at least one test board having a socket capable of loading a semiconductor element in a matrix form, and having a transfer line group for applying a test signal to the socket; a board housing chamber for Storing the at least one test board; at least one test substrate electrically connected to at least one test board housed in the board receiving chamber to generate a test signal for testing a semiconductor component loaded on the at least one test board; a substrate receiving chamber for accommodating the at least one test substrate, the On each of the transmission line groups in the circuit of one less test board, at least two of the sockets are arranged together and have a flying structure, the test substrate comprising: a test unit, selecting a test to be tested Generating a test signal and reading a result signal fed back from the starting semiconductor component; and a flash control signal providing unit providing a flash control signal to the test unit to enable the test unit to accurately sample from the resulting signal data of.

The test unit provides position information about the selected semiconductor component to be tested to the flash control signal providing unit, and the flash control signal providing unit provides a flash control signal that conforms to position information about the selected semiconductor component To the test unit.

The flash control signal supply unit has information on the time at which the result signal fed back by the selected semiconductor element after the test signal generated from the test unit is output to the test board side reaches the test unit (hereinafter, referred to as "Delay information" and a memory regarding position information of the semiconductor element, and a flash control signal based on delay information corresponding to position information on the semiconductor element selected by the test unit is supplied to the test unit.

According to the present invention as described above, the test signal is sequentially applied to the semiconductor element by the flying structure in a state where the radiation of the test signal does not occur, so that the response speed of the semiconductor element becomes faster, and the data can be processed at a high speed, and accordingly, based on The flash control signal of the position information of the semiconductor component to be tested accurately samples a signal that is shortened by high-speed processing, and finally can increase the processing speed.

200‧‧‧Aging test equipment

210‧‧‧ test board

211‧‧‧ socket

212‧‧‧ circuit board

Ca to Ch‧‧‧ transmission line group

220‧‧‧Board accommodating chamber

230‧‧‧Test substrate

231‧‧‧Test unit

232‧‧‧Shot control signal (strobe signal) providing unit

232a‧‧‧ memory

240‧‧‧Substrate housing chamber

FIG. 1 is a reference diagram for explaining application of a test signal according to the related art.

2 is a schematic diagram of an aging test apparatus according to an embodiment of the present invention.

3 is a conceptual diagram of a test board suitable for use in the burn-in test apparatus of FIG. 2.

4 is a conceptual diagram of a test substrate suitable for use in the burn-in test apparatus of FIG. 2.

Figure 5 is a reference diagram for extracting a transmission line group in the test board shown in Figure 2.

Fig. 6 is a reference view referred to in the description of the test substrate of Fig. 4;

Hereinafter, preferred embodiments according to the present invention as described above will be described with reference to the accompanying drawings. In order to make the description more concise, the repeated description or the symbols of the same configuration are omitted or compressed as much as possible.

<Description of aging test equipment>

FIG. 2 is a schematic structural diagram of an aging test apparatus 200 according to an embodiment of the present invention.

As shown in FIG. 2, the burn-in test apparatus 200 provided in this embodiment includes nine test boards 210, a board receiving chamber 220, nine test substrates 230, a substrate receiving chamber 240, and the like.

Each of the nine test boards 210 is used to load a semi-conductor that requires testing The body element will be described in more detail later.

The board housing chamber 220 is for housing nine test boards 210.

The nine test substrates 230 can be electrically connected to the nine test boards 210 directly or through dedicated connection substrates for generating test signals and transmitted to the semiconductor components of the nine test boards 210 accommodated in the board housing chamber 220. Thereafter, the result signal of the feedback is read, which will be described in more detail later.

The substrate housing chamber 240 is for housing nine test substrates 230.

<For the description of the test board>

In addition, as shown in FIG. 3, the test board 210 includes a plurality of sockets 211, a circuit board 212, and a connector 213.

The semiconductor element D to be tested is loaded on each of the plurality of sockets 211, and is arranged on the circuit substrate 212 in a matrix form.

The circuit board 212 is provided with a circuit having a test signal (a signal for operating the semiconductor element) from the side of the test substrate 230 applied to the semiconductor element D respectively mounted on the plurality of sockets 211, and is fed back according to the operating state of the semiconductor element D. The resulting signal is transmitted to the eight transmission line groups Ca to Ch on the side of the test substrate 230 (as a reference, one transmission line group includes as many lines as the number of channels for applying signals to the semiconductor elements). Here, on each of the transmission line groups Ca to Ch on the circuit substrate 212, the sockets 211 belonging to the two columns among the plurality of sockets 211 are arranged together. That is, the sockets 211 belonging to the two columns are arranged on one of the transmission line groups Ca to Ch, and a flying structure is adopted, so that the test signals from the test substrate 230 can be sequentially applied to the semiconductor elements mounted on the sockets 211. According to this, the test signals from the test substrate 230 are sequentially applied to the semiconductor elements to be tested, thereby enabling sequential The semiconductor elements respectively mounted in the two columns are operated, so that high-speed processing can be realized.

Of course, depending on the specific implementation, it is possible to have a structure in which only the outlets 211 belonging to one column are arranged on one transmission line group, or a structure in which the outlets 211 belonging to three or more columns are arranged on one transmission line group. Thus, the problem of how many columns of the outlets 211 are arranged on one transmission line group can be arbitrarily designed depending on the number of sockets, the processing speed, and the like. Further, it is also conceivable to arrange a plurality of sockets not belonging to the same row or column in a flying structure on one transmission line group.

Moreover, the end of the transmission line groups Ca to Cp is subjected to termination processing to avoid generation of a carrier. This is because the time length of the resulting signal becomes shorter as the processing is performed at a high speed, thereby preventing generation of a carrier that distorts the signal.

In addition, when the semiconductor element D is loaded to the socket 211, the impedance is lowered. Thus, preferably, in the circuit on the circuit substrate 212, the impedance of the set region B in which the plurality of sockets 211 are provided and the impedance of the unset region A before the test signal transmitted through the connector 213 enters the set region B are mutually Not the same. That is, since the impedance of the semiconductor element D is lowered after being loaded to the socket 211, it is necessary to set the impedance of the set region B to be higher than that of the unset region A. For example, when the impedance of the region A is not set to 40 ohms, the impedance of the set region B is set to be 60 ohms higher than the impedance of the unset region A, whereby the region B is subsequently set when the semiconductor element D is mounted on the socket 211. The impedance is lowered by 20 ohms to become 40 ohms, so that the impedance is the same as that of the unset region A. Therefore, it is preferable that the impedance difference between the two regions A and B is 20 ohms.

The connector 213 is for making an electrical connection with the test substrate 230 side.

<Description of test substrate>

As shown in FIG. 4, the test substrate 230 includes a test unit 231 and a flash control signal supply unit 232.

The test unit 231 selects the semiconductor component to be tested and generates a test signal to operate the selected semiconductor component and read the resulting signal fed back from the active semiconductor component. At this time, the test unit 231 supplies position information on the selected semiconductor element to the flash control signal supply unit 232.

The flash control signal providing unit 232 supplies a flash control (Strobe) signal to the test unit 231 to cause the test unit 231 to accurately perform data sampling from the resultant signal. To this end, the flash control signal supply unit 232 has a memory 232a on which the result signal feedback from the selected semiconductor element is returned after the test signal output from the test unit 231 is output to the test board 210 side. Information on the time of the unit 231 (hereinafter referred to as "delay information") and position information on the semiconductor element. That is, as shown in FIG. 5, the memory 232a stores location information and delay information, which are arranged in a transmission line group (Ca/Cb/Cc/Cd/Ce/Cf/Cg/Ch). Position information of all the sockets 211 (or semiconductor elements mounted on the sockets) which are different from each other in the distance from the test unit 231 (for example, the 0th semiconductor element, the 1st semiconductor element, ... 31st) The semiconductor component or the like) is the delay information of the result signal reaching the test unit 231 after the test signal is output from the test unit 231 when the test of the semiconductor component D based on the relevant position information is performed. According to this, when the flash control signal supply unit 232 receives the position information about the semiconductor element D selected by the test unit 231 from the test unit 231, it will be based on The flash control signal of the location information corresponding to the location information is provided to the test unit 231 to enable the test unit 231 to accurately perform data sampling.

For example, in the past, since the data section is as long as the low-speed operation of the semiconductor element as in Fig. 6(a), the data sampling is relatively easy, but in the present invention, since the high-speed operation of the semiconductor element is realized, the data interval can only be as a graph. 6(b) is as short as it is. According to this, the end of the transmission line group (Ca/Cb/Cc/Cd/Ce/Cf/Cg/Ch) is terminated to prevent the generation of the carrier, and the relevant sampling point (SP) is specified by the flash control signal to The center frequency enables accurate data sampling.

According to the burn-in test apparatus 200 configured as above, the test unit 231 selects the semiconductor element to be tested and transmits the operation signal (test signal) while transmitting the position information on the selected semiconductor element to the flash control signal supply unit 232. Accordingly, the flash control signal supply unit 232 supplies the flash control signal based on the delay information corresponding to the relevant position information in the memory 232a to the test unit 231, and the test unit 231 is based on the flash control signal received from the flash control signal supply unit 232. Data sampling at an accurate point (SP) to interpret the failure of the semiconductor component. Further, this process is performed in the order of the 0th semiconductor element to the 31st semiconductor element of FIG.

As described above, the present invention has been specifically described using the embodiments with reference to the drawings, but the above-described embodiments are merely preferred embodiments of the present invention, and therefore the invention is not limited to the above embodiments, and the scope of the present invention is The scope of the claims and the equivalent concepts thereof are to be understood as the scope of the claims.

200‧‧‧Aging test equipment

210‧‧‧ test board

220‧‧‧Board accommodating chamber

230‧‧‧Test substrate

240‧‧‧Substrate housing chamber

Claims (3)

An aging test apparatus, comprising: at least one test board, a socket capable of loading a semiconductor component in a matrix form, and having a transmission line group for applying a test signal to the socket; and a board receiving chamber for the shelter At least one test board; at least one test substrate electrically connected to at least one test board housed in the board receiving chamber, generating test signals for testing semiconductor components mounted on the at least one test board; and substrate housing a chamber for accommodating the at least one test substrate, each of the transmission line groups in the circuit of the at least one test board, at least two sockets of the socket are arranged together, and have a flying type Structure, the test substrate includes: a test unit that selects a semiconductor component to be tested to generate a test signal, and reads a result signal fed back from the starting semiconductor component; and a flash control signal supply unit that provides a flash to the test cell The signal is controlled to enable the test unit to sample accurate data from the resulting signal. The aging test apparatus according to claim 1, wherein the test unit supplies position information about the selected semiconductor element to be tested to the flash control signal providing unit, and the flash control signal providing unit A flash control signal conforming to the position information about the selected semiconductor component is supplied to the test unit. The aging test apparatus according to claim 2, wherein the flash control signal providing unit has a test signal recorded from the test unit Information obtained by the time when the result signal fed back by the selected semiconductor element reaches the test unit (hereinafter, referred to as "delay information") and the memory of the position information of the semiconductor element is outputted to the side of the test board, and A flash control signal based on delay information corresponding to position information about the semiconductor element selected by the test unit is supplied to the test unit.