TW201338415A - High voltage swing decomposition method and apparatus - Google Patents

Abstract

A voltage swing decomposition circuit includes first and second clamp circuits and a protection circuit. The first clamp circuit is configured to clamp an output node of the first clamp circuit at a first voltage level when an input node of the voltage swing decomposition circuit has a voltage higher than the first voltage level. The second clamp circuit is configured to clamp an output node of the second clamp circuit at a second voltage level, higher than the first level, when the voltage of the input node is lower than the second voltage level. The protection circuit is coupled to the output nodes of the first and second clamp circuits, and is configured to selectively set an output node of the protection circuit to the first or second voltage level, the first and second clamp circuits are coupled together by the output node of the protection circuit.

Description

Voltage swing decomposition circuit and method

The present invention relates to circuits and methods for decomposing voltage swings.

In many circuit applications, the voltage in the signal is used to represent or convey the message. Generally, a digital signal has a first voltage level for representing a first state, and a second voltage level for a signal corresponding to a second state. For example, a voltage such as 0V (or other relatively low voltage value) can be selected as the ground or a logical "low" value or state; a positive voltage such as 5V is selected as a supply voltage to represent a logic " High value or status. The choice of voltage level or voltage swing is typically a design consideration based on a number of factors, including hardware limitations, resource consumption requirements, and manufacturing or process limitations.

In some cases, a signal has a relatively large difference between high and low voltage values. It is quite difficult to use a component that is not designed to handle such a high voltage swing or that cannot withstand such a high voltage for a long time to process this type of signal. . For example, digital circuit components in integrated circuits typically have relatively low safe operating voltages due to the use of components of a single gate oxide layer. If a high voltage signal (such as a 5V digital input signal) is used for a digital circuit with a low safe operating voltage (such as 2.8V), this digital circuit will be damaged.

According to an embodiment of the invention, a voltage swing decomposition circuit is provided, comprising: a first clamp circuit for clamping the above when a voltage swing input circuit has an input node voltage higher than a first voltage level; One of the first clamp circuits outputs a node voltage at the first voltage level; a second clamp circuit is configured to when the input node voltage is lower than a second voltage level and the second voltage level is higher than the first And clamping a voltage of one of the second clamp circuits to the second voltage level; and a protection circuit coupled to the plurality of outputs of the first clamp circuit and the second clamp circuit a node, the protection circuit is configured to selectively set one of the output nodes of the protection circuit to one of the first clamp circuit and the second voltage level; wherein the first clamp circuit and the second clamp circuit pass the foregoing The output nodes of the protection circuit are coupled together.

The specific exemplary embodiments of this description are read in conjunction with the drawings, which are considered as part of the entire description. Unless specifically stated otherwise, terms, attachments, and similar terms (such as connections and inner connections) in the terms are representative of a structure that is either directly or indirectly secured through the media structure or attached to another structure, which may be movable or fixed. Attachment or relationship. Similarly, electrical connections and the like, such as coupled, connected, and interconnected, refer to a structure that is formed directly or indirectly through an intervening structure to form another structure. A firm or adherent relationship, unless otherwise specified, refers to a moveable or stable bond or relationship.

Embodiments of the present specification provide voltage protection for applications involving high voltage signals. A high voltage signal is decomposed into a plurality of different signals having a voltage level lower than the high voltage signal. Advantageously, a high voltage swing _(V swing_high) can be resolved into the swing voltage signal less than the high voltage swing _(V swing_high) of a plurality of signals, without using its own high voltage swing voltage swing (V _{Swing_high} ) A specific voltage protection circuit. Moreover, there is no DC current loss in many embodiments.

According to some embodiments of the present specification, FIG. 1 is a block diagram of a voltage swing decomposition circuit. Voltage swing decomposition circuit 100 (also referred to as a voltage level decomposition circuit) receives one of the inputs of a relatively high voltage swing and produces a complex signal of relatively low voltage swing. For example, in some embodiments, the input signal to input node 101 (labeled _{V3X_IN in} Figure 1) varies between 0V and 3V depending on the 3V swing. In the following discussion, a 3V input swing is used as an embodiment, but embodiments of the present description are applicable to input and output signals having different voltage values and voltage swings. The symbol "V _{3X_IN} " represents a voltage having a triple voltage swing with respect to the voltage V _1X . In some embodiments, the voltage V _1X and V _2X are 1V and 2V, other values may also be used. Circuit 100 decomposes the input signal of the high voltage swing into complex signals V _1A , V _1B , V _1C , V _{2A ,} and V _2B . To perform this voltage swing decomposition, voltages V _1X and V _2X are 1V and 2V, respectively, and are provided to circuit 100.

Circuit 100 includes clamp circuits 110a and 110b and a protection circuit 120. The clamp circuit 110a provides a signal V _1C , and when the voltage value of the input signal V _{3X_IN} is lower than the voltage V _2X , the signal V _1C is clamped to the voltage V _2X . Due to this clamping, when the voltage value of the input signal V _{3X_IN} changes between 0V and 3V, the signal V _1C changes between 2V and 3V. The clamp circuit 110b provides a signal V _1A , and when the voltage value of the input signal V _{3X_IN} is higher than the voltage V _1X , the signal is clamped to the voltage V _1X . Due to this clamping, when the voltage value of the input signal V _{3X_IN} changes between 0V and 3V, the signal V _1A changes between 0V and 1V. When the voltage value of the input signal V _{3X_IN} changes between 0V and 3V, the signals V _1A and V _1C are generated according to the signals V _2A and V _2B , each of which varies between 0V to 2V and 1V to 3V. Protection circuit 120 according to the signal V _2A and V _2B generates signal V _1B, when the voltage value of the change in the input signal _V 3X_IN between 0V and 3V, signal V _1B is changed from 1V to 2V. Therefore, the protection circuit 120 is configured to selectively set an output node to 1V or 2V, and the output node couples the clamp circuits 110a and 110b together.

2A is a schematic diagram of an implementation circuit 100 that uses a latch as a clamp circuit. Clamp circuit 110a includes latches 210b and 210d, and clamp circuit 110b includes latches 210a and 210c. Each latch has a pair of coupled transistors, as shown in Figure 2A. The clamp circuits 110a and 110b each have a plurality of PMOS transistors and a plurality of NMOS transistors. In each latch, at the same time point, the corresponding transistor is in a "on" (conducting current) state. This latch function functions as a voltage comparator to compare which MOS transistor has a stronger driving strength. Each latch has a pair of transistors whose source/drain are respectively coupled to each other. For each latch consisting of an NMOS transistor, the transistor that is turned on in the latch has a higher gate voltage (compared to the source voltage) than the other transistor in the same transistor pair. . For each latch consisting of a PMOS transistor, the transistor that is turned on in the latch has a lower gate voltage (compared to the source voltage).

Protection circuit 120 includes a pair of protection switches. In some embodiments, the switch includes an NMOS transistor M1 and a PMOS transistor M2, and is coupled to the node 220-1b having the signal V _1B . The transistor M2 controlled by the voltage of the node 220-2a (i.e., the signal V _2A ) is used to selectively set the node 220-1b to the voltage V _1X . The transistor M1 controlled by the voltage of the node 220-2b (i.e., the signal V _2B ) is used to selectively set the node 220-1b to the voltage V _2X . Node 220-1b is the output node of protection circuit 120; node 220-2a is the output node of latch 210a; node 220-2b is the output node of latch 210b; node 220-1a is the output node of latch 210c; node 220 -1c is the output node of latch 210d. Nodes 220-1a and 220-1c are output nodes of clamp circuits 110b and 110a, respectively.

The operation of circuit 100 can be understood by reference to Figure 2B-2C. In the 2B-2C diagram, the transistor is not turned on and is indicated by a broken line "X". Figure 2B illustrates an _{embodiment in which} the voltage value of the input signal V _{3X_IN} is its minimum voltage value (0V in this example). Since the gate of the transistor M3 is biased with the input signal V _{3X_IN} =0 V, the transistor M3 has a lower gate voltage than the transistor M4, so that the transistor M3 is not turned on and the transistor M4 is turned on. Those skilled in the art will understand that metal-oxide semiconductor field effect transistors (MOSFETs) are typically symmetrically constructed from source to drain, and the source/drain extremes of the MOSFET are conventionally biased when the transistor is biased. Only marked as source or 汲 extreme. The source or the NMOS terminal of the NMOS transistor has a relatively low potential called the source terminal, and the other end is called the 汲 terminal. The source or the 汲 terminal of the PMOS transistor has a relatively high potential called the source terminal, and the other end is called the 汲 terminal.

Since V _{3X_IN} =0V, node 220-2a (corresponding to signal V _2A ) is pulled down to 0V via transistor M4. The PMOS transistor M2 is turned on via the gate voltage 0V and maintains the node 220-1b (corresponding to the signal V _1B ) at 1V. Since the gate voltages of the PMOS transistors M5 and M6 are 1V and 0V, respectively, the transistor M5 is not turned on and the transistor M6 is turned on, so the voltage of the node 220-2b (signal V _2B ) is 1V.

The transistors M1 and M2 each have a node coupled to the node 220-1b. The source-to-gate voltage of the PMOS transistor M2 is 1V, and the gate-to-source voltage of the NMOS transistor M1 is 0V, so the transistor M1 is not turned on.

Since the gate voltages of the NMOS transistors M7 and M8 are 1V and 0V, respectively, the transistor M7 is turned on and the transistor M8 is not turned on. Node 220-1a (corresponding to signal V _1A ) is pulled to 0V.

Since the gate voltages of the PMOS transistors M9 and M10 are 1V and 0V, respectively, the transistor M9 is turned on and the transistor M10 is not turned on. Node 220-1c (signal V _1C ) is pulled to 2V.

Figure 2C illustrates an _{embodiment in which} the voltage value of the input signal V _{3X_IN} is its maximum voltage value (in this example, 3V). The PMOS transistor M6 is not turned on due to the gate bias at 3V, and the turned-on transistor M5 pulls the voltage of the node 220-2b (signal V _2B ) to 3V. The NMOS transistor M1, which is turned on with a bias of 3V, maintains the voltage of the node 220-1b (signal V _1B ) at 2V.

Since the gate voltages of the NMOS transistors M3 and M4 are 3V and 2V, respectively, the transistor M3 is turned on and the transistor M4 is not turned on. Therefore, the voltage of node 220-2a (signal V _2A ) is 2V.

The gate-to-source voltage of the NMOS transistor M1 is 1V, and the source-to-gate voltage of the PMOS transistor M2 is 0V. Therefore, the transistor M2 is not turned on.

Since the gate voltages of the NMOS transistors M7 and M8 are 1V and 2V, respectively, the transistor M7 is not turned on and the transistor M8 is turned on. Therefore, the voltage of the node 220-1a (signal V _1A ) is 1V.

Since the gate voltages of the PMOS transistors M9 and M10 are 3V and 2V, respectively, the transistor M9 is not turned on and the transistor M10 is turned on. Node 220-1c (corresponding to signal V _1C ) is pulled high to 3V.

Embodiments of the present specification provide different control signals. In the latch 210a, when V _{3X_IN} < V _2X then V _2A = V _{3X_IN} and when V _{3X_IN} > V _2X then V _2A = V _2X . The latch 210a is used to lock the node 220-2a to 0V or voltage V _2X according to the voltage value of the input signal V _{3X_IN} . In the latch 210b, when V _{3X_IN} > V _1X then V _2B = V _{3X_IN} and when V _{3X_IN} < V _1X then V _2B = V _1X . The latch 210b is used to lock the node 220-2b to a voltage V _1X or 3V according to the voltage V _{3X_IN} . In the latch 210c, when V _{3X_IN} <V _1X then V _1A = V _{3X_IN} , and when V _{3X_IN} > V _1X then V _1A = V _1X . The latch 210c is used to lock the node 220-2c to 0V or voltage V _1X according to the signal V _2A . In the latch 210d, when V _{3X_IN} > V _2X then V _1C = V _{3X_IN} and when V _{3X_IN} < V _2X then V _1C = V _2X . The latch signal V _2B 210d for locking the lock 220-2d node voltage at V _2X or 3V. When V _{3X_IN} <V _1X then V _1B =V _1X , when V _1X <V _{3X_IN} <V _2X then V _1B =V _{3X_IN} , and when V _{3X_IN} >V _2X then V _1B =V _2X .

Figure 3 is a diagram showing the signal trace diagram of various signals as described in the embodiments of the present specification. In the 28 nm process with a data transmission rate of 1 Gbps, the following signals are plotted in Figure 3: the voltage value of the input signal V _{3X_IN} (waveform 310); the signal V _1A (waveform 320); the signal V _1B (waveform 330); Signal V _1C (waveform 340); signal V _2A (waveform 350); signal V _2B (waveform 360). The above figure corresponds to a 100fF capacitive load on the corresponding node. The voltage swings of the signals V _1A , V _1B and V _1C are 1V, and the voltage swings of the signals V _2A and V _2B are 2V. Thus, the input input signal V _{3X_IN} has a high voltage swing of 3V which is processed to produce a plurality of control signals having a lower voltage swing. In some embodiments, these control signals are used as overvoltage protection.

Embodiments of the present specification are implemented in a number of processes, including 25 and 28 nanometer processes. Complex simulations have been successful enough to combat many process corners, including boundaries such as FF, SS, and TT. A common skill person will understand that these boundaries refer to the carrier drift of NMOS, PMOS, and components; for example, FF refers to faster than normal NMOS transistors and faster than normal PMOS transistors. Voltage swing decomposition can be performed over a wide range of temperatures, including -40 ° C to 125 ° C, according to various embodiments.

In some embodiments, the voltage decomposition is performed in multiple stages, such as a tree-based processing topology. 4 is a block diagram of a multi-level voltage swing decomposition circuit 400, in accordance with some embodiments. The input signal V _{NX_IN of the} relatively high voltage swing is decomposed into a plurality of signals of a lower voltage swing. In one embodiment, the low voltage level of the input signal V _{NX_IN} is 0V, and the high voltage level is 9V, so V _{3X_IN} can be called V _{9X_IN by the} same nomenclature. The voltage splitting circuits 400-1, 400-2a, 400-2b, and 400-2c are each similar to the circuit 100 except that the fixed voltage value used is different from the voltages V _1X and V _2X provided by the circuit 100. For example, circuits 400 and a fixed voltage value 3V 6V (refer to the voltage V _3X and V _6X) rather than voltage V _1X and V _2X.

In a first processing stage (corresponding to one of the roots of the tree structure in Figure 4), circuit 400-1 decomposes input signal V _{NX_IN in a} similar manner as described above for circuit 100, providing a swing between 0V and 3V. The signal 405a, the signal 405b swinging between 3V and 6V, and the signal 405c swinging between 6V and 9V. Thus, signal 405a, 405b and 405c are similar to signal V _1A, V _1B, and V _1C, which is wider than the addition of the voltage swing.

In a second processing stage (corresponding to one of the sub-roots of the tree structure in FIG. 4), each of the signals 405a, 405b, and 405c is processed by the decomposition circuits 400-2a, 400-2b, and 400-2c, respectively, to generate The signal of the lower voltage swing. Circuit 400-2a produces signals 410a, 410b, and 410c. The signal 410a swings between 0V and 1V, the signal 410b swings between 1V and 2V, and the signal 410c swings between 2V and 3V. Similarly, circuits 400-2b and 400-2c generate signals 420a, 420b, 420c, 430a, 430b, and 430c, which indicate that their individual voltage swings are in the range of 3V to 4V, 4V to 5V, 5V. Between 6V, 6V to 7V, 7V to 8V, and 8V to 9V. The number of levels in the processing stage will be determined according to different embodiments. Although the circuit 400 of the tree structure performs a voltage swing decomposition on the signals 405a, 405b, and 405c outputted for each of the first stages, not all of the signals are subjected to further processing in the second stage in some embodiments.

Thus, in this embodiment, circuit 400-2a includes a clamping circuit similar to the clamping circuit in circuit 100, but connected to a different fixed voltage. The clamping circuit of the circuit 400-2a is used to clamp the signal 410a at 1V when the signal 405a is higher than 1V, and clamp the signal 410c to 2V when the signal 405a is lower than 2V. Similarly, in this embodiment, the circuit 400-2b includes a clamp signal 420a at 4V when the signal 405b is higher than 4V, and a signal When the number 405b is lower than 5V, the clamp signal 420c is clamped to the 5V clamp circuit. Similarly, the circuit 400-2c includes a clamp circuit for clamping the signal 430a at 7V when the signal 405c is higher than 7V, and clamping the signal 430c at 8V when the signal 405c is lower than 8V. Similar circuit 400-1 in the first stage of the tree diagram, each of the circuits 400-2a, 400-2b, and 400-2c in the second stage includes two clamp circuits each latched therein. For ease of drawing, this second stage clamp circuit and latch are not shown in Figure 4; in some embodiments, the arrangement is similar to the clamp circuit and latch in Figure 2 unless they are connected to Figure 2 is similar to the fixed voltage of the different components.

In some embodiments, the plurality of control signals output by the decomposition circuit have voltage swings of different amplitudes. Figure 5 is a block diagram of a voltage swing decomposition circuit 500 similar to circuit 100 except that circuit 500 does not process an input signal to produce a complex output signal having the same voltage swing. The input voltage V _{5X_IN} has a low level of 0V and a high level of 5V. 4V a fixed voltage (this embodiment is designated voltage V _4X) supplied to the circuit 500, instead of providing a fixed voltage V _2X circuit 100 to a voltage 2V. The circuit 500 generates a signal 510a with a swing between 0V and 1V, a signal 510b with a swing between 1V and 4V, and a signal 510c with a swing between 4V and 5V. Signals 510a, 510b, and 510c are similar to signals V _1A , V _{1B ,} and V _{1C in} terms of how they are generated, but they have different voltage swings. In addition, circuit 500 produces a signal 510d that varies from 0V to 4V, and a signal 510e that varies from 1V to 5V. Thus, signals 510d and 510e are similar to signals V _2A and V _2B except for a wider (or higher) swing. In many embodiments, the input signal provided to the voltage decomposition circuit has a variety of different voltage swings, including a plurality of low and high voltage values. In some embodiments, a multi-stage processing configuration is used similar to Figure 4, with some voltage decomposition circuits providing complex output signals of the same voltage swing, while other decomposition circuits provide complex output signals of different voltage swings. Accordingly, many embodiments provide an elastic architecture to decompose a high voltage swing signal to accommodate various circuit applications and limitations.

Figure 6 is a circuit diagram of a circuit 600 employing voltage swing decomposition in accordance with some embodiments. Circuit 600 includes transistors M11, M12, M13, current source 610, resistor 620, and voltage swing decomposition circuit 630. Circuit 630 is similar to circuit 100 except that circuit 600 uses fixed voltages of 1.8V and 3V instead of 1V and 2V provided by voltages V _1X and V _2X in circuit 100, respectively. The signal V _BUS swing is between 0V and 5V. Since the fixed voltage is 1.8V and 3.3V, the signal V _{A is} similar to the signal V _2B in the circuit 100 except that the signal V _A swing is between 1.8V and 5V instead of between 1V and 3V. If V _BUS =0 V, circuit 630 maintains signal V _A at 1.8V. For example, according to a USBOTG (USB on-the-go) dialog request protocol specification, the PMOS transistor M13 is turned on. If V _BUS = 5V, the circuit 630 maintains the signal V _A at 5 V without conducting the crystal M13. Therefore, the 5V swing is reduced to a smaller swing, which improves the reliability of this application.

Figure 7 is a circuit diagram of a circuit 700 employing voltage swing decomposition in accordance with some embodiments. The input/output pad 710 has an input signal V _{3X_IN} that varies from 0V to a voltage V _3X . The pad 710 is coupled to the circuit 720a including one or more P-type components (all represented by a PMOS transistor symbol in FIG. 7), and is also coupled to include one or more N-type components (all in the seventh Circuit 720b, represented by an NMOS transistor symbol, is shown. In order to protect the circuits 720a and 720b against the high voltage swing caused by the pad 710, the input signal V _{3X_IN} provided by the pad 710 generates a lower swing signal v _1A , V _1B via the voltage swing decomposition circuit 100 and V _1C . In Fig. 7, V _3X = 3 ^* V _1X and V _2X = 2 ^* V _1X . The pull-up drive circuit 740a and the pull-down drive circuit 740b are conventional drive circuits. Due to the control signals V _1A , V _1B and V _1C , the circuits 720a and 720b are protected from high voltage swings to ensure reliability. Advantageously, circuit 700 does not consume DC current.

Figure 8 is a process flow diagram in accordance with some embodiments. After the process 800 begins, step 810 provides an input signal (ie, input signal V _{3X_IN} ) whose voltage varies between a first voltage level (ie, 0V) and a second voltage level (ie, voltage V _3X ). The first voltage level is lower than the second voltage level. Step 820 generates a first signal (i.e. the signal V _2A), which changes the voltage level between the first voltage and the third voltage level (i.e., voltage V _2X) between. The third voltage level is higher than the first voltage level and lower than the second voltage level. The first signal is generated according to the input signal. Step 830 is to generate a second signal (ie, signal V _2B ) whose voltage varies between the fourth voltage level (ie, voltage V _1X ) and the second voltage level. The fourth voltage level is higher than the first voltage level and lower than the third voltage level. The second signal is generated according to the input signal. Step 840 is that the third signal (ie, signal V _1B ) is selectively set to one of the third or fourth voltage _levels based on the first and second signals. In some embodiments, the process includes generating a fourth signal (ie, signal V _1A ) having a voltage change between the first voltage level and the fourth voltage level. The fourth signal generated according to the first signal is clamped to the fourth voltage level when the input signal is higher than the fourth voltage level. In some embodiments, the process includes generating a fifth signal (ie, signal V _1C ) at which the voltage changes to a third voltage level and a second voltage level. The fifth signal generated according to the second signal is clamped to the third voltage level when the input voltage is lower than the third voltage level.

In some embodiments, the voltage swing decomposition circuit (ie, circuit 100) includes first and second clamp circuits (ie, clamp circuits 110a and 110b, respectively) and a protection circuit (ie, protection circuit 120). When the input node of the voltage swing decomposition circuit (ie, node 101) has a voltage higher than the first voltage level, the first clamp circuit is configured to clamp the output node of the first clamp circuit (ie, node 220-1a) a first voltage level (i.e., voltage V _1X). When the input node voltage is lower than the second voltage level, the second clamp circuit is configured to clamp the output node of the second clamp circuit (ie, node 220-1c) to the second voltage level (ie, voltage V _2X ). The protection circuit is coupled to the output nodes of the first and second clamping circuits, and is configured to selectively set an output node (ie, node 220-1b) of the protection circuit to a first or second voltage level. The first and second clamping circuits are coupled together via an output node of the protection circuit.

In some embodiments, the circuit includes first and second latches (ie, latches 210a and 210b, respectively) and a protection module (ie, circuit 120), the first latch including first and second NMOS transistors (ie, They are transistors M3 and M4 respectively. The gate of the first NMOS transistor is coupled to the first terminal of the second NMOS transistor; and the gate of the second NMOS transistor is coupled to the first terminal of the first NMOS transistor. The second end of the first NMOS transistor is coupled to the second end of the second NMOS transistor via the output node of the first latch (ie, node 220-2a). The second latch includes first and second PMOS transistors (ie, transistors M5 and M6, respectively). The gate of the first PMOS transistor is coupled to the first terminal of the second PMOS transistor; the gate of the second PMOS transistor is coupled to the first terminal of the first PMOS transistor. First PMOS transistor The second endpoint is coupled to the second endpoint of the second PMOS via a second latched node (ie, 220-2b). The protection module includes a third NMOS transistor (ie, a transistor M1) and a third PMOS transistor (ie, a transistor M2). The gate of the third PMOS transistor is coupled to the output node of the first latch, and the first end of the third PMOS transistor is coupled to the first terminal of the first NMOS transistor. The gate of the third NMOS transistor is coupled to the output node of the second latch. The first end of the third NMOS transistor is coupled to the first end of the second PMOS transistor. The first end of the third NMOS transistor is coupled to the first end of the third PMOS transistor via an output node of the protection module (ie, node 220-1b).

In some embodiments, a given input signal (e.g. input signal _V 3X_IN), the voltage variation of the first voltage level (i.e., 0V) and a second voltage level (i.e., voltage V _3X). The first voltage level is lower than the second voltage level. A first signal (ie, signal V _2A ) is generated, the voltage of which varies between the first voltage level and the third voltage level (ie, voltage V _2X ). The third voltage level is higher than the first voltage level but lower than the second voltage level. The first signal is generated based on the input signal. A signal (ie, signal V _2B ) is generated whose voltage changes to a fourth voltage level (ie, voltage V _1X ) and a second voltage level. The fourth voltage level is higher than the first voltage level but lower than the third voltage level. The second signal is generated based on the input signal. According to the first and second signals, the third signal (ie, the signal V _1B ) is selectively set to one of the third and fourth voltage levels.

While the invention has been shown and described with respect to the embodiments, the embodiments of the invention are not limited by the scope of the invention.

100,500, 630‧‧‧ voltage swing decomposition circuit

101‧‧‧Input node

110a, 110b‧‧‧ clamp circuit

120‧‧‧Protection circuit

210a, 210b, 210c, 210d‧‧‧ latch

220-1a, 220-1b, 220-1c, 220-2a, 220-2b‧‧‧ nodes

310, 320, 330, 340, 350, 360‧‧‧

400‧‧‧Multi-level voltage swing decomposition circuit

400-1, 400-2a, 400-2b, 400-2c‧‧‧ voltage decomposition circuit

405a, 405b, 405c‧‧‧ signals

420a, 420b, 420c‧‧‧ signals

430a, 430b, 430c‧‧‧ signals

510a, 510b, 510c, 510d, 510e‧‧‧ signals

600, 700‧‧‧ Voltage swing decomposition circuit

610‧‧‧current source

620‧‧‧resistance

710‧‧‧ solder pads

720a, 720b‧‧‧ circuits

740a‧‧‧ Pull-up drive circuit

740b‧‧‧ Pull-down drive circuit

800‧‧‧ Process

810, 820, 830, 840 ‧ ‧ steps

The elements in the figures will be described below, and the above elements are used to illustrate their use without measuring their size.

Figure 1 is a block diagram of a voltage swing decomposition circuit in accordance with an embodiment of the present specification.

Figure 2A is a simplified diagram of a circuit 100 using a latch as a clamp circuit.

Figure 2B is a simplified diagram of circuit 100 for an embodiment corresponding to _{V3X_IN} = 0V.

Figure 2C is a simplified diagram of circuit 100 for an embodiment corresponding to V _{3X_IN} = 3V.

Figure 3 is a diagram showing signal traces of different input and output signals in accordance with some embodiments.

Figure 4 is a block diagram of a multi-level voltage swing decomposition circuit in accordance with some embodiments.

Figure 5 is a block diagram of a voltage swing decomposition circuit in accordance with some embodiments.

Figure 6 is a circuit diagram of voltage swing decomposition in accordance with some embodiments.

Figure 7 is a circuit diagram of voltage swing decomposition in accordance with some embodiments.

Figure 8 is a flow chart in accordance with some embodiments.

100‧‧‧Voltage swing decomposition circuit

110a, 110b‧‧‧ clamp circuit

120‧‧‧Protection circuit

210a, 210b, 210c, 210d‧‧‧ latch

220-1a, 220-1b, 220-1c, 220-2a, 220-2b‧‧‧ nodes

Claims (10)

A voltage swing decomposition circuit includes: a first clamp circuit configured to clamp an output of the first clamp circuit when an input node voltage of the voltage swing decomposition circuit is higher than a first voltage level The node voltage is at the first voltage level; a second clamping circuit is configured to when the input node voltage is lower than a second voltage level and the second voltage level is higher than the first voltage level And clamping a voltage of the output node of the second clamping circuit to the second voltage level; and a protection circuit coupled to the plurality of output nodes of the first clamping circuit and the second clamping circuit, the protection circuit The method for selectively setting an output node of the protection circuit to the first clamp circuit and the second voltage level; wherein the first clamp circuit and the second clamp circuit output via the protection circuit The nodes are coupled together. The voltage swing decomposition circuit of claim 1, wherein the protection circuit comprises: a first protection switch for selectively setting the output node of the protection circuit to the first voltage level, The first protection switch is controlled by the first clamping circuit; and a second protection switch is configured to selectively set the output node of the protection circuit to the second voltage level, and the second protection switch is configured by the second Clamping circuit control; wherein: the first protection switch comprises a PMOS transistor, and the gate of the PMOS transistor is coupled to the output node of the first clamping circuit, a first terminal is connected to the first voltage level, and a second terminal is connected to the output node of the protection circuit; and the second protection switch comprises an NMOS transistor, and the NMOS transistor has a gate coupling Connected to the output node of the second clamping circuit, a first terminal is connected to the second voltage level, and a second terminal is coupled to the output node of the protection circuit. The voltage swing decomposition circuit of claim 1, wherein: the first clamping circuit comprises a first latch, and the first latch is configured to lock the first latch based on the input node voltage One of the output nodes is at a reference voltage level and one of the second voltage levels, wherein the reference voltage level is lower than the first voltage level; the first latch includes a pair of NMOS transistors, wherein each a gate of an NMOS transistor is coupled to a first end of another NMOS transistor, and a second end of each of the NMOS transistor pairs is coupled via the output node of the first latch The first clamping circuit further includes a third latch coupled to the output node of the first latch, wherein the third latch is configured to be based on the output node voltage of the first latch Locking one of the output ports of the third latch to the reference voltage level and one of the first voltage levels; the third latch includes a pair of NMOS transistors, wherein the gate of each NMOS transistor Coupling to another NMOS transistor a first end point, wherein the second end of each of the NMOS transistor pairs is coupled together via the output node of the first clamping circuit; the second clamping circuit includes a second latch Lock, the above second latch And latching, according to the input node voltage, one of the first latch output node to one of the first voltage level and a third voltage level, wherein the third voltage level is higher than the second voltage level The second latch includes a pair of PMOS transistors, wherein a gate of each PMOS transistor is coupled to a first end of another PMOS transistor, and a transistor of each of the PMOS transistor pairs The two terminals are coupled together via the output node of the second latch; the second clamping circuit further includes a fourth latch coupled to the output node of the second latch, wherein the fourth latch The lock is configured to lock one of the output terminals of the fourth latch to the second voltage level and the third voltage level based on the output node voltage of the second latch; the fourth latch includes a pair of PMOS transistors, wherein a gate of each PMOS transistor is coupled to a first end of another PMOS transistor, and a second end of each of the PMOS transistor pairs is via the second The above output nodes of the clamp circuit are coupled together And wherein the change in voltage between the input node of said reference voltage level and said third voltage level. The voltage swing decomposition circuit of claim 1, further comprising: a third clamp circuit, when the output node voltage of the first clamp circuit is higher than the third voltage level, And clamping a third node of the third clamp circuit to the third voltage level, wherein the third voltage level is lower than the first voltage level; and a fourth clamp circuit for using the foregoing Clamping the fourth clamp when the output node voltage of a clamp circuit is higher than a fourth voltage level The output node voltage of the circuit is at the fourth voltage level, wherein the fourth voltage level is higher than the third voltage level but lower than the first voltage level. The voltage swing decomposition circuit of claim 1, further comprising: a third clamp circuit, when the output node voltage of the second clamp circuit is higher than a third voltage level, And clamping a third node of the third clamping circuit to the third voltage level, wherein the third voltage level is higher than the second voltage level; and a fourth clamping circuit for using the foregoing When the output node voltage of the second clamp circuit is lower than a fourth voltage level, clamping one of the output voltages of the fourth clamp circuit to the fourth voltage level, wherein the fourth voltage level is higher than the third The voltage level is higher than the second voltage level described above. A voltage swing decomposition circuit includes: a first latch comprising a first NMOS transistor and a second NMOS transistor, wherein a gate of the first NMOS transistor is coupled to the second NMOS transistor a first end, a gate of the second NMOS transistor is coupled to the first end of the first NMOS transistor, and a node is outputted via one of the first latches, and the second end of the first NMOS The second latch is coupled to the second NMOS transistor; the second latch includes a first PMOS transistor and a second PMOS transistor, wherein the gate of the first PMOS transistor is coupled to the a first end of the second PMOS transistor, a gate of the second PMOS transistor is coupled to the first end of the first PMOS, and An output node of the second latch, the second end of the first PMOS transistor is coupled to the second end of the second PMOS transistor; and a protection module includes a third NMOS transistor and a first a PMOS transistor, wherein a gate of the third PMOS transistor is coupled to the output node of the first latch, and a first end of the third PMOS transistor is coupled to the first NMOS transistor An end of the third NMOS transistor is coupled to the output node of the second latch, and a first end of the third NMOS transistor is coupled to the first end of the second PMOS transistor And a first end of the third NMOS transistor is coupled to the first end of the third PMOS transistor via the output node of one of the protection modules. The voltage swing decomposition circuit of claim 6, wherein the second end of the third PMOS transistor is connected to the first voltage level, and the second end of the third NMOS transistor is connected to the high The second voltage level at the first voltage level, and the second end of the first NMOS transistor and the second end of the first PMOS transistor are coupled to an input node of the circuit; The method further includes: a third latch comprising a fourth NMOS transistor and a fifth NMOS transistor, wherein a gate of the fourth NMOS transistor is coupled to a first end of the fifth NMOS transistor, The gate of the fifth NMOS transistor is coupled to the first end of the fourth NMOS transistor, and the second end of the fourth NMOS transistor is coupled to the first end of the fourth NMOS transistor. a second end of the fifth NMOS transistor; a fourth latch comprising a fourth PMOS transistor and a fifth PMOS transistor, wherein the gate of the fourth PMOS transistor is coupled to a first terminal of the fifth PMOS transistor, a gate of the fifth PMOS transistor is coupled to a first end of the fourth PMOS transistor, and an output node is connected to the fourth latch a second end of the PMOS transistor is coupled to the second end of the fifth PMOS transistor; a fifth latch comprising a sixth NMOS transistor and a seventh NMOS transistor, wherein the sixth NMOS a gate of the transistor is coupled to the first end of the seventh NMOS transistor, and a gate of the seventh NMOS transistor is coupled to the first end of the sixth NMOS transistor via the fifth latch An output node, a second end of the sixth NMOS transistor is coupled to the second end of the seventh NMOS transistor; and a sixth latch comprising a sixth PMOS transistor and a seventh PMOS a transistor, wherein a gate of the sixth PMOS transistor is coupled to a first end of the seventh PMOS transistor, and a gate of the seventh PMOS transistor is coupled to a first end of the sixth PMOS transistor Pointing, through one of the sixth latch outputs node, the second end of the sixth PMOS transistor Connecting to the second end of the seventh PMOS transistor; wherein the first end of the seventh NMOS transistor is coupled to the first end of the sixth PMOS transistor to the third latch and the fourth An output node of one of the latches; wherein the input node voltage of the circuit changes between a reference voltage level and the third voltage level, wherein the reference voltage level is lower than the first voltage level, And the third voltage level is higher than the second voltage level. The voltage swing decomposition circuit as described in claim 6 of the patent application scope further includes: a third latch comprising a fourth NMOS transistor and a fifth NMOS transistor, wherein a gate of the fourth NMOS transistor is coupled to a first end of the fifth NMOS transistor, the fifth a gate of the NMOS transistor is coupled to the first end of the fourth NMOS transistor, and a second end of the fourth NMOS transistor is coupled to the fifth terminal via the output node of the third latch a second end of the NMOS transistor; a fourth latch comprising a fourth PMOS transistor and a fifth PMOS transistor, wherein the gate of the fourth PMOS transistor is coupled to the fifth PMOS transistor a first terminal, a gate of the fifth PMOS transistor coupled to the first end of the fourth PMOS transistor, and an output node via the fourth latch, the fourth PMOS transistor The second end is coupled to the second end of the fifth PMOS transistor; a fifth latch comprising a sixth NMOS transistor and a seventh NMOS transistor, wherein the gate of the sixth NMOS transistor Coupling to a first end point of the seventh NMOS transistor, the seventh NMOS transistor is coupled to the upper end a first end of the sixth NMOS transistor, through one of the output ports of the fifth latch, the second end of the sixth NMOS transistor is coupled to the second end of the seventh NMOS transistor; a six-latch, comprising a sixth PMOS transistor and a seventh PMOS transistor, wherein a gate of the sixth PMOS transistor is coupled to a first end of the seventh PMOS transistor, and the seventh PMOS transistor The gate is coupled to the first end of the sixth PMOS, and the output node of the sixth latch, the second end of the sixth PMOS transistor is coupled to the second of the seventh PMOS transistor An end point; wherein the first end point of the seventh NMOS transistor is the sixth end a first end of the PMOS transistor is coupled to the output node of the third latch and the fourth latch; wherein the second end of the third PMOS transistor is connected to the first voltage level a second end of the third NMOS transistor connected to the second voltage level higher than the first voltage level, a second end of the first NMOS transistor and a second end of the first PMOS transistor The endpoints are each connected to an input node of the circuit; wherein a voltage change of the input node of the circuit is between the reference voltage level and the third voltage level, wherein the reference voltage level is lower than the first The voltage level is above, and the third voltage level is higher than the second voltage level. A voltage swing decomposition method includes: providing an input signal, wherein a voltage is changed between the first voltage level and the second voltage level, wherein the first voltage level is lower than the second voltage level; Generating a first signal whose voltage varies between the first voltage level and the third voltage level, wherein the third voltage level is higher than the first voltage level and lower than the second voltage level The first signal is generated based on the input signal; a second signal is generated, and a voltage thereof is changed between the fourth voltage level and the second voltage level, wherein the fourth voltage level is higher than the first The voltage level is lower than the third voltage level, the second voltage level is generated based on the input signal; and the third signal is selectively set to the third voltage level according to the first signal and the second signal One of the fourth voltage levels as described above. The voltage swing decomposition method of claim 9, further comprising: generating a fourth signal according to the first signal, wherein the voltage changes between the first voltage level and the fourth voltage level The fourth signal is clamped to the fourth voltage level when the input signal is higher than the fourth voltage level; and the fifth signal is generated according to the second signal, and the voltage change is between the third The voltage level is between the second voltage level and the second voltage level, wherein the fifth signal is clamped to the third voltage level when the input signal is lower than the third voltage level.