CN101814525B - ESD protecting method for fin field effect transistor(FinFET) - Google Patents
ESD protecting method for fin field effect transistor(FinFET) Download PDFInfo
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- CN101814525B CN101814525B CN 201010106330 CN201010106330A CN101814525B CN 101814525 B CN101814525 B CN 101814525B CN 201010106330 CN201010106330 CN 201010106330 CN 201010106330 A CN201010106330 A CN 201010106330A CN 101814525 B CN101814525 B CN 101814525B
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- 238000000034 method Methods 0.000 title claims abstract description 9
- 230000005669 field effect Effects 0.000 title abstract 4
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 239000013078 crystal Substances 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 abstract description 5
- 230000005540 biological transmission Effects 0.000 abstract 2
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 description 23
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 description 23
- 238000005516 engineering process Methods 0.000 description 9
- 230000008901 benefit Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 2
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- 239000000463 material Substances 0.000 description 2
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- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
This invention discloses a ESD protecting method for fin field effect transistor(FinFET) . One embody of this invention is a semiconductor includes: a receiver circuit including fin field effect transistor(FinFET); a transceiver circuit including fin field effect transistor(FinFET); a transmission bus which is linked between the receiver circuit and the transceiver circuit, where both the receiver circuit and the transceiver circuit further include a protective circuit for electrostatic discharge. Said protective circuit for electrostatic discharge includes planar transistor being electrically linked to the planar transistor of the transmission bus. Other embodies of this invention may further include a power clamping electrically connected between the first power bus and the first grounding bus, a power clamping electrically connected between the second power bus and the second grounding bus, or at least two diodes electrically connected between the first grounding bus and the second grounding bus in crosswise mode. In addtion, both the planar transistors of receiver circuit and the transceiver circuit includes the planar PMOS transistor and planar NMOS transistor.
Description
Technical field
Present invention relates in general to a kind of circuit that is used for Electrostatic Discharge protection, relate in particular to a kind of circuit that is used in cross-domain (cross-domain) protection of the FinFET (FinFET) of charging device pattern (CDM) interdischarge interval semiconductor chip.
Background technology
Along with the reduction of semiconductor technology size, FinFET (FinFET) is used for semiconductor technology more continually.Unfortunately, because the channel width of FinFET is less relatively, FinFET is more prone to stand the equipment fault that caused by the Electrostatic Discharge incident usually.Thereby, need a kind of solution that addresses this problem.
Because its physical structure, FinFET is considered to three-dimensional transistor.The active area of FinFET (drain electrode, raceway groove and source electrode) stretches out the extraordinary image rectangular box from the surface of the Semiconductor substrate at FinFET place.In addition, grid structure usually three sides but sometimes on two sides around raceway groove.
Because FinFET has relative higher drive current and owing to FinFET prevents the general ability of short-channel effect, FinFET has advantage in littler technology when compare with the device of similar size.Because making around raceway groove, grid increased the effective width of raceway groove, so FinFET has the drive current of increase usually.The channel width that increases allows bigger drive current.In addition, center on raceway groove by making grid, grid can more easily suppress the leakage current by raceway groove, reduces short-channel effect thus.
The advantage of FinFET makes it be used to littler technology, especially below the 32nm, but the sensitiveness that the compromise that is used for smaller szie has caused during esd event the fault to FinFET to increase.The active area width of FinFET is far smaller than another device of corresponding technical size.When esd event took place, littler width caused the increase of current density among the FinFET.For example, compare with about 2mA/ μ m of plane body MOSFET or about 1.4mA/ μ m of planar S OI MOSFET, FinFET had the maximum of 0.1mA/ μ m usually before device fault takes place.The increase of current density can cause the dielectric gate oxide to occur puncturing between active area and grid, causes the short circuit between grid and the active area.Thereby FinFET may complete failure.
Esd event is divided into three kinds of different patterns usually: Human Body Model (HBM), machine pattern (MM) and charging device pattern (CDM).Under HBM, usually the people will make charge storage on one's body he and she.Then, the people will touch the pin that semiconductor package is loaded onto, and make stored charge be discharged into semiconductor chip.Ideally, the circuit in the chip with guide current away from the internal components on the chip and make electric current leak to ground.HBM is generally three kinds of minimum voltage amplitudes in the pattern, but the common duration is the longest.Be similar to HBM, under MM, the machine that is considered to the metal machine usually will make charge storage thereon.Machine will contact with the pin of semiconductor packages and discharge charge stored.Once more, internal circuit should guide current away from the assembly in the chip and make it guide to ground.The voltage amplitude of MM and duration are usually between HBM and CDM.Under CDM, electric charge will be accumulated in chip originally on one's body.The internal circuit of chip is attempted making electric current guide to some power buss, makes electric current be directed away from other internal components of chip subsequently and flows out to pin in the encapsulation.CDM has the highest voltage amplitude and the shortest discharge period usually.
During this period, when causing FinFET to be easy to device fault owing to the discharge of the high voltage amplitude during esd event, the CDM discharge.Thereby, need a kind of device of during the CDM esd event, protecting FinFET in the prior art.
Summary of the invention
By embodiments of the invention, solve usually or avoided these and other problems, and realized technological merit usually.
According to one embodiment of present invention, semiconductor device comprises: transceiver circuit comprises the FinFET (FinFET) and first earth bus; Acceptor circuit comprises the FinFET and second earth bus; And transfer bus, be electrically connected acceptor circuit and transceiver circuit.Acceptor circuit and transceiver circuit all further comprise the Electrostatic Discharge protective circuit, and ESD protection circuit comprises the planar transistor that is electrically connected to transfer bus.
According to another embodiment of the present invention, semiconductor device comprises: transfer bus, transceiver and receiver.Transceiver comprises first power bus, first earth bus, comprises the transceiver computing circuit of the FinFET that is electrically connected to transfer bus and the transceiver esd protection circuit that comprises planar transistor; wherein; first planar transistor is electrically connected the transfer bus and first power bus, and second planar transistor is electrically connected the transfer bus electrical connection and first earth bus.Receiver comprises second source bus, second earth bus, comprises the receiver computing circuit of the FinFET that is electrically connected to transfer bus and the receiver esd protection circuit that comprises planar transistor; wherein; the 3rd planar transistor is electrically connected transfer bus and second source bus, and Siping City's faceted crystal pipe is electrically connected the transfer bus and second earth bus.
According to another embodiment of the present invention, the method that is used to form semiconductor device comprises: be electrically connected the transceiver computing circuit between first power bus and first earth bus; Between the second source bus and second earth bus, be electrically connected the receiver computing circuit; Between transceiver computing circuit and receiver computing circuit, be electrically connected transfer bus; The first Electrostatic Discharge protective circuit is provided; Second esd protection circuit is provided; And outside contact is provided, to discharge the electric current that produces by electrostatic discharge event.Outside contact is connected to bus (first power bus, first earth bus, second source bus or second earth bus).Transceiver computing circuit and receiver computing circuit include one or more FinFETs.First esd protection circuit is electrically connected to first power bus, first earth bus and transfer bus.Second esd protection circuit is electrically connected to second source bus, second earth bus and transfer bus.First esd protection circuit and second esd protection circuit include one or more planar transistors.
The advantage of the embodiment of the invention is to compare with the active area of FinFET, and the robustness of the active area of planar transistor makes bigger electric current walk around the FinFET on the semiconductor chip.Thereby, reduce the FinFET that uses in the less technology because esd event and the possibility of fault.
Description of drawings
In order to understand the present invention and advantage thereof better, carry out following description as a reference in conjunction with the accompanying drawings now, wherein:
Fig. 1 is transceiver with cross-domain esd protection and the acceptor circuit according to the embodiment of the invention.
Embodiment
Below will describe manufacturing of the present invention and use in detail.Yet, should expect, but the invention provides the multiple application invention thought that can in multiple specific environment, specialize.Described specific embodiment only is manufacturing and uses ad hoc fashion of the present invention, do not limit the scope of the invention.
Below will describe the present invention, that is, be used for the circuit of the cross-domain protection of CDM esd event FinFET about the embodiment in the specific environment.Yet the present invention can also be applied to other transistor devices and other esd events, and is not limited thereto.
Before use FinFET became generally, cross-domain protection was considered to impossible to the ESD of the transceiver circuit on the semiconductor chip, and this is because the active area of device is enough kept out the electric current that is produced by esd event; Esd protection only is arranged on the acceptor circuit, with the protective transistor gate oxide.Yet as mentioned above, the FinFET active area in the transceiver circuit can not be kept out the electric current that the CDM esd event produces usually.This causes the fault of the FinFET in the transceiver circuit.
Fig. 1 shows according to the transceiver circuit that all has cross-domain esd protection 10 of the embodiment of the invention and acceptor circuit 50.Transceiver circuit 10 comprises the first voltage source V DD1 bus 12 and outside contact 14, first ground connection VSS1 bus 18 and outside contact 20 and is connected in power supply clamper 16 between VDD1 bus 12 and the VSS1 bus 18.Inverter is connected in the transceiver circuit 10 and other computing circuit (not shown) between VDD1 bus 12 and VSS1 bus 18.Inverter comprises PMOS FinFET 22 and NMOS FinFET 24.The source electrode of PMOS FinFET 22 is connected to VDD1 bus 12, and the source electrode of NMOS FinFET 24 is connected to VSS1 bus 18.The grid of PMOSFinFET 22 and NMOS FinFET 24 is connected to other computing circuit (not shown) in the transceiver circuit 10.The drain electrode of PMOS FinFET 22 and NMOS FinFET 24 links together and is connected to transfer bus 40.Transceiver circuit 10 also comprises the CDM protection mechanism, and it comprises plane P MOSFET 26 and plane NMOSFET 28.The source electrode of plane P MOSFET 26 is connected to VDD1 bus 12, and the grid of plane P MOSFET 26 is connected to VDD1 bus 12 by resistor 30.The source electrode of plane N MOSFET 28 is connected to VSS1 bus 18, and the grid of plane N MOSFET28 is connected to VSS1 bus 18 by resistor 32.
Acceptor circuit 50 comprises the second voltage source V DD2 bus 52 and outside contact 54, second ground connection VSS2 bus 58 and outside contact 60 and is connected in power supply clamper (power clamp) between VDD2 bus 52 and the VSS2 bus 58.Inverter is connected in the acceptor circuit 50 and other computing circuit (not shown) between VDD2 bus 52 and VSS2 bus 58.Inverter comprises PMOS FinFET 62 and NMOS FinFET 64.The source electrode of PMOS FinFET 62 is connected to VDD2 bus 52, and the source electrode of NMOS FinFET 64 is connected to VSS2 bus 58.The grid of PMOSFinFET 62 and NMOS FinFET 64 is connected to the resistor 74 that is connected with transfer bus 40.The drain electrode of PMOS FinFET 62 and NMOS FinFET 64 links together and is connected to other computing circuit (not shown) in the acceptor circuit 50.Acceptor circuit 50 also comprises the CDM protection mechanism, and it comprises plane P MOSFET 66 and plane NMOSFET 68.The source electrode of plane P MOSFET 66 is connected to VDD2 bus 52, and the grid of plane P MOSFET 66 is connected to VDD2 bus 52 by resistor 70.The source electrode of plane N MOSFET 58 is connected to VSS2 bus 58, and the grid of plane N MOSFET 58 is connected to VSS2 bus 58 by resistor 72.
VSS1 bus 18 is connected by the interconnection diode with VSS2 bus 58.Diode 42 has the anode that is connected to VSS1 bus 18 and is connected to the negative electrode of VSS2 bus 58.On the contrary, diode 44 has anode that is connected to VSS2 bus 58 and the negative electrode that is connected to VSS1 bus 18.
Those skilled in the art will recognize that the circuit among Fig. 1 is arranged on the semiconductor element that is contained in the encapsulation usually.Outside contact 14,20,54 and 60 can be represented the contact pad of semiconductor element and/or encapsulation, for example, and the wire bond pad in bump pad in the trigger assembly or the wire bond assembly.These outside contacts 14,20,54 are electrically connected to multiple outer enclosure pin in the encapsulation by different interconnection structures usually with 60.
Chip can be designed as and makes and discharge by any pin on the Chip Packaging at the electric charge that discharges during the esd event, but about Fig. 1, the outside contact 14 of VDD1 is connected to the package pins that the ESD electric charge is leaked by hypothesis.In other embodiments, other outside contacts 20,54 and 60 are connected to package pins, so that the ESD electric charge leaks.In these other embodiment, those skilled in the art will recognize that, the difference of the operation of electric current and different assemblies during the esd event below will be described.In addition, though not so restriction is applied to cross-domain protection especially about the esd protection of Fig. 1 discussion.Therefore,, cross-domain protection only is discussed, is made electric charge be supposed from acceptor circuit 50 about Fig. 1.
Suppose that positive CDM esd event comes from the VDD2 bus 52 or near, plane P MOSFET 26 will operate with 66 so that some electric currents that caused by esd event contact 14 and let out with outside by VDD1 bus 12.When high positive voltage discharges on VDD2 bus 52 suddenly, plane P MOSFET 66 will enter rebound (snap-back) pattern, or avalanche breakdown, cause the approximate short circuit by plane P MOSFET 66.Electric current will pass from VDD2 bus 52, by PMOSFET66, by resistor 74, and arrive transfer bus 40.Thereby transfer bus 40 will be in high voltage, make plane P MOSFET 26 operate under saturation mode, with guide current to VDD1 bus 12 and output to the outside contact 14 of VDD1.By plane P MOSFET 26 and 66 and the electric current of resistor 74 cause pressure drop between VDD1 bus 12 and the VDD2 bus 52, the VDD2 bus is in obviously higher voltage place.Because VDD2 bus 52 is in more high voltage, so power supply clamper 56 will be operated electric current is guided to VSS2 bus 58.This electric current is towards diode 44 biasings, electric current is guided to VSS1 bus 18.This will cause VSS1 bus 18 to be in the voltage higher than VDD1 bus 12, and will cause 16 operations of power supply clamper electric current is guided to VDD1 bus 12.Thereby plane P MOSFET 26 and 66 has prevented to flow through any FinFET in acceptor circuit 50 or the transceiver circuit 10 by most of electric currents that esd event causes.
Suppose that negative CDM esd event comes from the VDD2 bus 52 or near, except reverse direction current flow and plane P MOSFET 26 and 66 operator schemes were switched, circuit was similar to positive CDMESD incident and operates.When negative esd event took place, plane P MOSFET 66 was saturated, and plane P MOSFET 26 is in the rebound pattern.Electric current will flow to VDD1 bus 12 from the outside contact 14 of VDD1, to transfer bus 40, arrive VDD2 bus 52 by resistor 74 and plane PMOSFET 66 by plane P MOSFET 26.Once more, pressure drop occurs between VDD1 bus 12 and the VDD2 bus 52, make power supply clamper 16 and 56 operations and guide current diode 42, VSS2 bus 58 and power supply clamper 56, the esd discharge to the VDD2 bus 52 by power supply clamper 16, VSS1 bus 18, forward bias.Once more, prevent that electric current from flowing through FinFET.
Suppose that positive CDM esd event comes from the VSS2 bus 58 or near, plane N MOSFET 68 and plane PMOSFET 26 will operate, so that some electric currents that caused by esd event contact 14 and let out with outside by VDD1 bus 12.When discharging high positive voltage on VSS2 bus 58, plane N MOSFET 68 will operate under saturation mode.Electric current will flow through plane N MOSFET 68 from VSS2 bus 58, flow through resistor 74, and to transfer bus 40.Thereby transfer bus 40 will be in high voltage, make plane P MOSFET 26 operate under saturation mode, electric current guided to VDD1 bus 12 and to guide to VDD 1 outside contact 14.In addition, second current path will produce.Electric current also will flow to VSS1 bus 18 by forward biased diodes connected 44 from the VSS2 bus.Then, VSS1 bus 18 is in the voltage higher than VDD1 bus 12, makes power supply clamper 16 operate electric current guided to VDD1 bus 12 and to be guided out outside contact 14.Once more, prevent that electric current from flowing through FinFET.
Suppose that negative CDM esd event comes from the VSS2 bus 58 or near, remove mobile in the opposite direction and plane P MOSFET 26 of electric current and plane NMOSFET 68 operator schemes are switched, circuit is similar to positive CDM esd event and operates.When negative esd event took place, plane N MOSFET 68 and plane PMOSFET 26 were in the rebound pattern.Electric current flows to VDD1 bus 12 from the outside contact 14 of VDD1, to transfer bus 40, arrives VSS2 bus 58 by resistor 74 and plane NMOSFET 58 by plane P MOSFET26.Once more, second current path will produce.Electric current also flows to the VSS2 bus from VSS1 bus 18 by forward biased diodes connected 42.Then, VSS1 bus 18 is in well below the voltage of VDD1 bus 12, makes power supply clamper 16 operate to contact 14 guide current from VDD1 bus 12 and outside.Once more, prevent that electric current from flowing through FinFET.
The embodiment that represents among Fig. 1 has simplified the FinFET that how to protect on the semiconductor chip.Compare with the active area of FinFET, the robustness of the active area of planar MOSFET allows multiple current more to walk around FinFET on the semiconductor chip.In 32nm technology and littler technology, this embodiment is particularly useful.Thereby, reduced the FinFET that in these technology, uses because esd event and the possibility of fault.
Though described the present invention and advantage thereof in detail, should be understood that under the situation of the spirit and scope of the present invention that do not break away from the claims qualification, can make multiple change, replacement and change.And scope of the present invention is not intended to be limited to the specific embodiment of processing, machine, manufacturing, things, means, method and the step described in the specification.Those skilled in the art expect according to disclosure of the present invention, combination existing or processing, machine, manufacturing and material, device, method or the step of exploitation afterwards, can utilize according to the present invention carry out basic with corresponding embodiment identical functions described herein or realize the result identical substantially with it.Therefore, claims are included in the scope of combination of such processing, machine, manufacturing and material, device, method or step.
Claims (9)
1. semiconductor device comprises:
Transceiver circuit comprises the FinFET (FinFET) and first earth bus;
Acceptor circuit comprises the FinFET and second earth bus; And
Transfer bus, be electrically connected described acceptor circuit and described transceiver circuit, wherein, described acceptor circuit and described transceiver circuit all further comprise ESD protection circuit, and described ESD protection circuit comprises the planar transistor that is electrically connected to described transfer bus;
Wherein, the described planar transistor of described transceiver circuit comprises plane P MOS transistor and plane nmos pass transistor, the described plane P MOS transistor of described transceiver circuit has source electrode and grid that all is electrically connected to first power bus and the drain electrode that is electrically connected to described transfer bus, and the described plane N MOS transistor of described transceiver circuit has source electrode and grid that all is electrically connected to described first earth bus and the drain electrode that is electrically connected to described transfer bus;
The planar transistor of described acceptor circuit comprises plane P MOS transistor and plane nmos pass transistor, the described plane P MOS transistor of described acceptor circuit has source electrode and grid that all is electrically connected to the second source bus and the drain electrode that is electrically connected to described transfer bus, and the described plane N MOS transistor of described acceptor circuit has source electrode and grid that all is electrically connected to described second earth bus and the drain electrode that is electrically connected to described transfer bus.
2. semiconductor device according to claim 1, wherein, first resistor is inserted between the grid of described first power bus and described plane P MOS transistor, and second resistor is inserted between the grid of described first earth bus and described plane N MOS transistor
Wherein, the power supply clamper is electrically connected described first power bus and described first earth bus.
3. semiconductor device according to claim 1, wherein, first resistor is inserted between the grid of described second source bus and described plane P MOS transistor, and second resistor is inserted between the grid of described second earth bus and described plane N MOS transistor
Wherein, the power supply clamper is electrically connected described second source bus and described second earth bus.
4. semiconductor device according to claim 1, wherein, at least two described first earth bus of diode electrically interconnection and described second earth bus.
5. semiconductor device comprises:
Transfer bus;
Transceiver comprises:
First power bus;
First earth bus;
The transceiver computing circuit comprises the FinFET that is electrically connected to described transfer bus;
The transceiver ESD protection circuit comprises planar transistor, and wherein, first planar transistor is electrically connected to described first power bus with described transfer bus, and second planar transistor is electrically connected to described first earth bus with described transfer bus;
Receiver comprises:
The second source bus;
Second earth bus;
The receiver computing circuit comprises the FinFET that is electrically connected to described transfer bus; And
The receiver ESD protection circuit comprises planar transistor, and wherein, the 3rd planar transistor is electrically connected to described second source bus with described transfer bus, and Siping City's faceted crystal pipe is electrically connected to described second earth bus with described transfer bus;
Wherein, described first planar transistor comprises the first plane P MOS transistor, and described second planar transistor comprises the second plane N MOS transistor, and described the 3rd planar transistor comprises the 3rd plane P MOS transistor, and described Siping City faceted crystal pipe comprises Siping City's face nmos pass transistor
Wherein, the grid of the described first plane P MOS transistor and source electrode are electrically connected to described first power bus, the drain electrode of the drain electrode of the described first plane P MOS transistor and the described second plane P MOS transistor is electrically connected to described transfer bus, and the described transistorized grid of the second plane N OMS and source electrode are electrically connected to described first earth bus, and wherein, the grid of described the 3rd plane P MOS transistor and source electrode are electrically connected to described second source bus, the drain electrode of the drain electrode of described the 3rd plane P MOS transistor and described Siping City face nmos pass transistor is electrically connected to described transfer bus, and the grid of described Siping City face nmos pass transistor and source electrode are electrically connected to described second earth bus.
6. semiconductor device according to claim 5 also comprises:
The first power supply clamper is electrically connected to described first earth bus with described first power bus; And
The second source clamper is electrically connected to described second earth bus with described second source bus.
7. semiconductor device according to claim 5, wherein, cross-coupled diode is electrically connected to described second earth bus with described first earth bus.
8. method that is used to form semiconductor device, described method comprises:
Be electrically connected the transceiver computing circuit between first power bus and first earth bus, wherein, described transceiver computing circuit comprises one or more FinFETs;
Be electrically connected receiver between the second source bus and second earth bus, wherein, described receiver computing circuit comprises one or more FinFETs;
Between described transceiver computing circuit and described receiver computing circuit, be electrically connected transfer bus;
First esd protection circuit that is electrically connected to described first power bus, first earth bus and described transfer bus is provided, and wherein, described first esd protection circuit comprises one or more planar transistors;
Second esd protection circuit that is electrically connected to described second source bus, described second earth bus and described transfer bus is provided, and wherein, described second esd protection circuit comprises one or more planar transistors; And
Provide outside contact to discharge the electric current that is produced by electrostatic discharge event, described outside contact is electrically connected to bus, and wherein, described bus is described first power bus, described first earth bus, described second source bus or described second earth bus;
Wherein, described one or more planar transistors of described first esd protection circuit comprise the second plane N MOS transistor that described first power bus is electrically connected to the first plane P MOS transistor of described transfer bus and described transfer bus is electrically connected to described first earth bus; and wherein; described one or more planar transistors of described second esd protection circuit comprise Siping City's face nmos pass transistor that described second source bus is electrically connected to the 3rd plane P MOS transistor of described transfer bus and described transfer bus is electrically connected to described second earth bus
Wherein, the source electrode of the described first plane P MOS transistor and grid are electrically connected to described first power bus, the drain electrode of the drain electrode of the described first plane P MOS transistor and the described second plane P MOS transistor is electrically connected to described transfer bus, and the source electrode of the described second plane N MOS transistor and grid are electrically connected to described first earth bus, and wherein, the source electrode of described the 3rd plane P MOS transistor and grid are electrically connected to described second source bus, the drain electrode of the drain electrode of described the 3rd plane P MOS transistor and described Siping City face nmos pass transistor is electrically connected to described transfer bus, and the source electrode of described Siping City face nmos pass transistor and grid are electrically connected to described second earth bus.
9. method according to claim 8 also comprises:
Between described first power bus and described first earth bus, be electrically connected the first power supply clamper;
Between described second source bus and described second earth bus, be electrically connected the second source clamper; And
Between described first earth bus and described second earth bus, be electrically connected cross-coupled diode.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15376609P | 2009-02-19 | 2009-02-19 | |
| US61/153,766 | 2009-02-19 | ||
| US12/610,960 US8331068B2 (en) | 2009-02-19 | 2009-11-02 | ESD protection for FinFETs |
| US12/610,960 | 2009-11-02 |
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| Publication Number | Publication Date |
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| CN101814525A CN101814525A (en) | 2010-08-25 |
| CN101814525B true CN101814525B (en) | 2011-12-07 |
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| CN 201010106330 Expired - Fee Related CN101814525B (en) | 2009-02-19 | 2010-01-28 | ESD protecting method for fin field effect transistor(FinFET) |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI512943B (en) * | 2012-10-08 | 2015-12-11 | Intel Deutschland Gmbh | Silicon controlled rectifier (scr) device for bulk finfet technology |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8830639B2 (en) * | 2011-01-14 | 2014-09-09 | Fairchild Semiconductor Corporation | ESD protection against charge coupling |
| US8799833B2 (en) * | 2011-04-29 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and methods for converting planar design to FinFET design |
| US8621406B2 (en) * | 2011-04-29 | 2013-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and methods for converting planar design to FinFET design |
| US8873213B2 (en) * | 2012-03-14 | 2014-10-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | High voltage swing decomposition method and apparatus |
| US8692291B2 (en) | 2012-03-27 | 2014-04-08 | International Business Machines Corporation | Passive devices for FinFET integrated circuit technologies |
| CN108695310A (en) * | 2017-04-05 | 2018-10-23 | 中芯国际集成电路制造(上海)有限公司 | A kind of FinFET circuits |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI512943B (en) * | 2012-10-08 | 2015-12-11 | Intel Deutschland Gmbh | Silicon controlled rectifier (scr) device for bulk finfet technology |
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| CN101814525A (en) | 2010-08-25 |
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