CN108695310A - A kind of FinFET circuits - Google Patents
A kind of FinFET circuits Download PDFInfo
- Publication number
- CN108695310A CN108695310A CN201710217778.1A CN201710217778A CN108695310A CN 108695310 A CN108695310 A CN 108695310A CN 201710217778 A CN201710217778 A CN 201710217778A CN 108695310 A CN108695310 A CN 108695310A
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- Prior art keywords
- bus
- voltage domain
- ground level
- circuit
- check unit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The present invention provides a kind of FinFET circuits, and the FinFET circuits include:First voltage domain circuit, including the first power bus and the first ground level bus;Second voltage domain circuit, including second source bus and the second ground level bus;Transfer bus connects second voltage domain circuit and first voltage domain circuit;Second voltage domain circuit further includes the first check unit and the second check unit, and first check unit is electrically connected the transfer bus and the second source bus, to provide the transfer bus to the one-way passage of the second source bus;Second check unit is electrically connected the transfer bus and the second ground level bus, to provide the second ground level bus to the one-way passage of the transfer bus.The electrostatic protection effect of FinFET circuits is more preferable in technical solution provided by the invention.
Description
Technical field
The present invention relates to electronic technology field more particularly to a kind of FinFET circuits.
Background technology
Compared to planar transistor, smaller, but the breakdown voltage of FinFET of fin formula field effect transistor (FinFET)
It is lower, it is more vulnerable to the influence of static discharge (ESD) event and leads to failure.
Especially when FinFET circuits include different voltage domains, for example, when the voltage of transmission circuit receiving circuit
When the difference of domain, FinFET circuits are more easy to breakdown.
The validity of the electrostatic protection of existing FinFET circuits has to be hoisted.
Invention content
Present invention solves the technical problem that being the validity for the electrostatic protection for promoting FinFET circuits.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of FinFET circuits, including:First voltage domain electricity
Road, including the first power bus and the first ground level bus;Second voltage domain circuit, including second source bus and second
Ground level bus;Transfer bus connects second voltage domain circuit and first voltage domain circuit;The second voltage domain
Circuit further includes the first check unit and the second check unit, and first check unit is electrically connected the transfer bus and described
Second source bus, to provide the transfer bus to the one-way passage of the second source bus;Second check unit
It is electrically connected the transfer bus and the second ground level bus, to provide the second ground level bus to the transfer bus
One-way passage.
Optionally, first voltage domain circuit further includes the first power clamp ESD protection sub-circuits, first power supply
Clamper ESD protection sub-circuits are electrically connected first power bus and the first ground level bus;The second voltage domain electricity
Road further includes and second source clamper ESD protection sub-circuits, the second source clamper ESD are protected described in sub-circuit electrical connection
First power bus and the second ground level bus.
Optionally, the first ground level bus is electrically connected with the second ground level bus by bidirectional conduction unit,
The bidirectional conduction unit is for establishing the first ground level bus to the second ground level bus and second ground
Level bus to the first ground level bus access.
Optionally, the bidirectional conduction unit includes:Back-to-back diode.
Optionally, first check unit includes multiple concatenated diodes, wherein the anode of first diode connects
The transfer bus is connect, the cathode of first diode is connected to the anode of neighboring diode, the cathode of the last one diode
Connect the second source bus.
Optionally, first check unit and the second check unit include gate diode.
Optionally, the gate diode is fin diode, the FinFET transistors in the FinFET circuits and institute
The characteristic line breadth for stating gate diode is 14nm.
Optionally, first voltage domain circuit further includes the first phase inverter, first power bus and described first
Ground level bus is electrically connected with first phase inverter, and the output end of first phase inverter is electrically connected with the transfer bus.
Optionally, second voltage domain circuit further includes the second phase inverter, the second source bus and described second
Ground level bus is electrically connected with second phase inverter, and the output end of second phase inverter is electrically connected with the transfer bus.
Optionally, the diode in first check unit is P+/NW diodes, two poles in second check unit
Pipe is N+/PW diodes.
Optionally, first voltage domain circuit further includes first voltage domain operating circuit, second voltage domain circuit
It further include second voltage domain operating circuit;First voltage domain operating circuit is powered by first power bus, and described
Two voltage domain operating circuits are bus-powered by the second source.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that:
First check unit and the second check unit are set, wherein the first check unit connection transfer bus and power bus
And transfer bus is provided to the one-way passage of second source bus, it is total to transmitting that the second check unit provides the second ground level bus
The one-way passage of line, therefore the circuit of release charge can be built by the first check unit and the second check unit.In existing skill
In art, usually utilize rebound (snap-back) pattern of metal-oxide-semiconductor, or discharged in the way of avalanche breakdown, thus speed compared with
Slowly.And one-way passage is established in embodiments of the present invention to build the circuit of release charge, without using rebound (snap-back)
Pattern or avalanche breakdown are discharged, speed.The FinFET circuits in the embodiment of the present invention are utilized as a result, it can be more
Quickly response esd event is to discharge, and then can be damaged to avoid FinFET circuits.
Further, the first check unit uses P+/NW diodes, the second check unit to use N+/PW diodes, can keep away
Exempt from latch-up.
Description of the drawings
Fig. 1 is a kind of structural schematic diagram of FinFET circuits in the embodiment of the present invention;
Fig. 2 is a kind of structural schematic diagram of fin diode in the embodiment of the present invention;
Fig. 3 is side view of the fin diode in Fig. 2 along the directions Aa or the directions aA;
Fig. 4 is side view of the fin diode in Fig. 2 along the directions Bb or the directions bB.
Specific implementation mode
As previously mentioned, compare planar transistor, smaller, but the FinFET of FinFET (FinFET)
Breakdown voltage is lower, is more vulnerable to the influence of static discharge (ESD) event and leads to failure.Especially wrapped when in FinFET circuits
When including different voltage domains, for example, when the voltage domain difference where transmission circuit receiving circuit, FinFET circuits are more easy to be hit
It wears.The validity of the electrostatic protection of existing FinFET circuits has to be hoisted.
In the prior art, usually by using the rebound of metal-oxide-semiconductor (snap-back) pattern, or avalanche breakdown is utilized
Mode is discharged, therefore speed is slower.In embodiments of the present invention, it is built by the way that the first check unit and the second check unit is arranged
Vertical one-way passage, discharges without using rebound (snap-back) pattern or avalanche breakdown, speed.Utilize this as a result,
FinFET circuits in inventive embodiments, can more quickly respond esd event, to discharge, may further avoid
FinFET circuits are damaged.
It is understandable to enable above-mentioned purpose, feature and the advantageous effect of the present invention to become apparent, below in conjunction with the accompanying drawings to this
The specific embodiment of invention is described in detail.
Referring to Fig. 1, the FinFET circuits in the embodiment of the present invention may include:First voltage domain circuit 11, second voltage
Domain circuit 12 and transfer bus T1.Wherein, FinFET circuits can be only based on the circuit of FinFET structures, or be based on
The circuit of FinFET and other types device structure.
Wherein, first voltage domain circuit 11 may include the first power bus VDD1 and the first ground level bus VSS1, and
One power bus VDD1 can receive the first power supply signal, and the first ground level bus VSS1 can receive the first earth signal;Second
Voltage domain circuit 12 may include second source bus VDD2 and the second ground level bus VSS2, and second voltage domain circuit 12 can
To receive second source signal, the second ground level bus VSS2 can receive the second earth signal, second source signal and the first electricity
Source signal can be identical or different, and the second earth signal can be identical or different with the first earth signal;Transfer bus T1 connections first
Voltage domain circuit 11 and second voltage domain circuit 12.
Specifically, first voltage domain circuit 11 can also include the first check unit 13 and the second check unit 14, first
Check unit 13 connects transfer bus T1 and second source bus VDD2, to provide transfer bus T1 to second source bus VDD2
One-way passage.Second check unit 14 connects transfer bus T1 and the second ground level bus VSS2, to provide the second ground level
Bus VSS2 to transfer bus one-way passage.
Further, first voltage domain circuit 11 can also include the first power clamp ESD protection sub-circuits (ESD
Clamp) 18, the first power clamp ESD protection sub-circuits 18 connect the first power bus VDD1 and the first ground level bus VSS1.
Second voltage domain circuit 12 can also include that second source clamper ESD protects sub-circuit 19, second source clamper ESD
Sub-circuit 19 is protected to connect the first power bus VDD1 and the first ground level bus VSS1.
In specific implementation, the first ground level bus VSS1 and the second ground level bus VSS2 can pass through bidirectional conduction list
Member 15 connects, and bidirectional conduction unit 15 is for establishing the first ground level bus VSS1 to the second ground level bus VSS2 and second
The bi-directional path of ground level bus VSS2 to the first ground level bus VSS1.Bidirectional conduction unit 15 may include a pair of back-to-back
Diode.
It is first power bus VDD1, the first power clamp ESD protection sub-circuit 18, the first ground level bus VSS1, two-way
Onunit 15, the second ground level bus VSS2, second source clamper ESD protection sub-circuits 19 and second source bus VDD2
Between can form bleed-off circuit and release charge.
When the first power bus VDD1, the first ground level bus VSS1, the second ground level bus VSS2 and second source
When esd event occurs for one of bus VDD2, it can be released by above-mentioned bleed-off circuit.
It can be released a large amount of charge by above-mentioned bleed-off circuit, pass through the first check unit of setting 13 and second unidirectional single
Member 14, the remaining charge that can release is to avoid charge remnants.
First check unit 13 may include a diode or multiple concatenated diodes, specifically can be as needed
Design.
When the current potential of the first power bus VDD1 is less than the current potential of second source bus VDD2, the first check unit 13 can
To include a diode.
When the current potential of the first power bus VDD1 is higher than the current potential of second source bus VDD2, the first check unit 13 can
With multiple concatenated diodes, to promote the cut-in voltage of the first check unit 13, and then avoid first voltage domain circuit 11 to
The sink current of second voltage domain circuit 12 may further ensure the normal work of second voltage domain circuit 12.
When the first check unit 13 include it is multiple to concatenated diode when, can be connected in the following way:The
The anode of one diode is connected to the transfer bus T1, and the cathode of first diode is connected to the sun of neighboring diode
The cathode of pole, the last one diode is connected to second source bus VDD2.
Second check unit 14 can also include diode, and the quantity of diode can be one.The anode of diode can
To be connected to the second ground level bus VSS2, the cathode of diode can be connected to transfer bus T1.
Diode in first check unit 13 and the second check unit 14 may each be gate diode, more specifically, the
Diode in one check unit 13 and the second check unit 14 may each be fin diode.The fin diode and FinFET
Identical processing procedure may be used in FinFET in circuit, such as the characteristic line breadth of the two all can be 14nm.
In embodiments of the present invention, first voltage domain circuit can also include first voltage domain operating circuit, described second
Voltage domain circuit can also include second voltage domain operating circuit.First voltage domain operating circuit is operate on first voltage domain
Circuit is powered by the first power bus;Second voltage domain operating circuit is operate on the circuit in second voltage domain, by second source
It is bus-powered.
The concrete function of first voltage domain operating circuit and second voltage domain circuit can be various, such as can distinguish
It is the circuit for realizing transmission-receiving function and receive capabilities.
FinFET circuits in the embodiment of the present invention can be with quick response first voltage domain operating circuit and second voltage
The esd event of domain operating circuit, charge of releasing are damaged to avoid first voltage domain operating circuit and second voltage domain operating circuit
It is bad.
It will be appreciated by persons skilled in the art that the FinFET circuits in the embodiment of the present invention can be drawn from functional perspective
It is divided into the electrostatic discharge protective circuit for electrostatic protection function and realizes the operating circuit of other functions.Electrostatic discharge protective circuit is set
The normal work of operating circuit can be ensured by setting.Meanwhile the setting of electrostatic discharge protective circuit can also avoid itself by esd event
It influences and generates failure.Therefore the FinFET circuits in the embodiment of the present invention have better robustness as a whole.
Fig. 2 is a kind of structural schematic diagram of fin diode in the embodiment of the present invention, and Fig. 3 is two pole of fin in Fig. 2
For pipe along the side view in the directions Aa or the directions aA, Fig. 4 is side view of the fin diode in Fig. 2 along the directions Bb or the directions bB.
It is further described below in conjunction with Fig. 2 to Fig. 4.
Diffusion fin 23, the insulated gate 21 that fin diode may include substrate 24, be formed on substrate 24 are also shown in figure
Interconnection metal structure 22.
It can be boundary with insulated gate 21 to spread fin 23, be divided into the first side and the second side, survey and can divide in the first side and second
It carry out not N+ doping and P+ doping.Substrate 24 can be N traps or p-well.
P+/NW diodes can be formed in N traps, and N+/PW diodes can be formed in p-well.
In order to avoid latch-up, the diode in the first check unit can be P+/NW diodes, the second check unit
Middle diode can be N+/PW diodes.
With continued reference to Fig. 1, first voltage domain circuit 11 can also include the first phase inverter 16, the first power bus VDD1 and
First ground level bus VSS1 is connected with the first phase inverter 16, to power for the first phase inverter 16, the first phase inverter 16
Output end is connected with transfer bus T1.It is not seen in fig. 1, first voltage domain circuit 11 can also include other operations electricity
Road, these computing circuits can be connected to the first phase inverter 16.
Second voltage domain circuit 12 can also include the second phase inverter 17, and second source bus VDD2 and the second ground level are total
Line VSS2 is connected with the second phase inverter 17, to power for the second phase inverter 17.The output end of second phase inverter 17 can be with
Transfer bus T1 is connected.It is not seen in fig. 1, second voltage domain circuit 12 can also include other computing circuits, these
Computing circuit can be connected to the second phase inverter 17.
Computing circuit in first voltage domain circuit 11 and second voltage domain circuit 12 may each comprise FinFET transistors.
Transfer bus T1 can also be connected to storage circuit, and storage circuit equally may include FinFET transistors.
FinFET transistors and fin diode in the embodiment of the present invention can be based on identical processing procedure, the spy of the two
Levying line width all can be 14nm.
When the characteristic line breadth of the FinFET transistors in the embodiment of the present invention is 14nm, the volume of FinFET transistors is more
It is small, but pressure resistance is lower simultaneously, and FinFET circuits are more easy to can not work normally because FinFET transistors are breakdown.
The first check unit and the second check unit are formed using the fin diode that characteristic line breadth is 14nm, can be made
The circuit area smaller of first check unit and the second check unit, while processing procedure can be consistent with FinFET transistors.It utilizes
Smaller starting diode, can also faster build the Releasing loop of charge, and then can more quickly respond
Esd event carries out releasing for charge, and FinFET circuits may further be avoided to be damaged.
In embodiments of the present invention, by the way that the first check unit and the second check unit is arranged, wherein the first check unit
Transfer bus and power bus are connected, provides transfer bus to the one-way passage of second source bus, the second check unit provides
Second ground level bus to transfer bus one-way passage.
The circuit of release charge can be built by the first check unit and the second check unit as a result,.In the prior art
In, usually utilize rebound (snap-back) pattern of metal-oxide-semiconductor, or discharged in the way of avalanche breakdown, therefore speed compared with
Slowly.And one-way passage is established in embodiments of the present invention to build the circuit of release charge, without using rebound (snap-back)
Pattern or avalanche breakdown are discharged, speed.The FinFET circuits in the embodiment of the present invention are utilized as a result, it can be more
Quickly response esd event is to discharge, and then can be damaged to avoid FinFET circuits.
Further, P+/NW diodes are used in the first check unit, and bis- poles N+/PW are used in the second check unit
Pipe, can be to avoid latch-up.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (11)
1. a kind of FinFET circuits, which is characterized in that including:
First voltage domain circuit, including the first power bus and the first ground level bus;
Second voltage domain circuit, including second source bus and the second ground level bus;
Transfer bus connects second voltage domain circuit and first voltage domain circuit;
Second voltage domain circuit further includes the first check unit and the second check unit, the first check unit electrical connection
The transfer bus and the second source bus are led to providing the transfer bus to the unidirectional of the second source bus
Road;Second check unit is electrically connected the transfer bus and the second ground level bus, to provide the second ground electricity
Flat bus to the transfer bus one-way passage.
2. FinFET circuits according to claim 1, which is characterized in that first voltage domain circuit further includes the first power supply
Clamper ESD protects sub-circuit, and the first power clamp ESD protections sub-circuit is electrically connected first power bus and described the
One ground level bus;
Second voltage domain circuit further includes and second source clamper ESD protects sub-circuit, the second source clamper ESD
Sub-circuit is protected to be electrically connected first power bus and the second ground level bus.
3. FinFET circuits according to claim 1, which is characterized in that the first ground level bus and second ground
Level bus is electrically connected by bidirectional conduction unit, and the bidirectional conduction unit is for establishing the first ground level bus to institute
The second ground level bus and the second ground level bus are stated to the access of the first ground level bus.
4. FinFET circuits according to claim 3, which is characterized in that the bidirectional conduction unit includes:Back-to-back two
Pole pipe.
5. FinFET circuits according to claim 1, which is characterized in that first check unit includes multiple concatenated
Diode, wherein the anode of first diode connects the transfer bus, the cathode of first diode is connected to adjacent two
The cathode of the anode of pole pipe, the last one diode connects the second source bus.
6. FinFET circuits according to claim 1, which is characterized in that first check unit and the second unidirectional list
Member includes gate diode.
7. FinFET circuits according to claim 6, which is characterized in that the gate diode is fin diode, described
The characteristic line breadth of FinFET transistors and the gate diode in FinFET circuits is 14nm.
8. FinFET circuits according to claim 1, which is characterized in that first voltage domain circuit further includes first anti-
Phase device, first power bus and the first ground level bus are electrically connected with first phase inverter, first reverse phase
The output end of device is electrically connected with the transfer bus.
9. FinFET circuits according to claim 1, which is characterized in that second voltage domain circuit further includes second
Phase inverter, the second source bus and the second ground level bus are electrically connected with second phase inverter, and described second is anti-
The output end of phase device is electrically connected with the transfer bus.
10. FinFET circuits according to claim 1, which is characterized in that the diode in first check unit
For P+/NW diodes, diode is N+/PW diodes in second check unit.
11. FinFET circuits according to claim 1, which is characterized in that first voltage domain circuit further includes first
Voltage domain operating circuit, second voltage domain circuit further include second voltage domain operating circuit;The first voltage domain work
Circuit is powered by first power bus, and second voltage domain operating circuit is bus-powered by the second source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710217778.1A CN108695310A (en) | 2017-04-05 | 2017-04-05 | A kind of FinFET circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710217778.1A CN108695310A (en) | 2017-04-05 | 2017-04-05 | A kind of FinFET circuits |
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| Publication Number | Publication Date |
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| CN108695310A true CN108695310A (en) | 2018-10-23 |
Family
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| CN201710217778.1A Pending CN108695310A (en) | 2017-04-05 | 2017-04-05 | A kind of FinFET circuits |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090020846A1 (en) * | 2007-07-20 | 2009-01-22 | Hynix Semiconductor, Inc. | Diode for adjusting pin resistance of a semiconductor device |
| CN101814525A (en) * | 2009-02-19 | 2010-08-25 | 台湾积体电路制造股份有限公司 | The esd protection that is used for FinFET |
| CN103187414A (en) * | 2011-12-29 | 2013-07-03 | 台湾积体电路制造股份有限公司 | ESD protection circuit cell |
| US20150221632A1 (en) * | 2013-07-15 | 2015-08-06 | United Microelectronics Corp. | Fin diode structure |
-
2017
- 2017-04-05 CN CN201710217778.1A patent/CN108695310A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090020846A1 (en) * | 2007-07-20 | 2009-01-22 | Hynix Semiconductor, Inc. | Diode for adjusting pin resistance of a semiconductor device |
| CN101814525A (en) * | 2009-02-19 | 2010-08-25 | 台湾积体电路制造股份有限公司 | The esd protection that is used for FinFET |
| CN103187414A (en) * | 2011-12-29 | 2013-07-03 | 台湾积体电路制造股份有限公司 | ESD protection circuit cell |
| US20150221632A1 (en) * | 2013-07-15 | 2015-08-06 | United Microelectronics Corp. | Fin diode structure |
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