CN109144925A - Universal serial bus circuit - Google Patents
Universal serial bus circuit Download PDFInfo
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- CN109144925A CN109144925A CN201810840739.1A CN201810840739A CN109144925A CN 109144925 A CN109144925 A CN 109144925A CN 201810840739 A CN201810840739 A CN 201810840739A CN 109144925 A CN109144925 A CN 109144925A
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- serial bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
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- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Dc Digital Transmission (AREA)
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Abstract
The present invention proposes that a kind of universal serial bus circuit includes power circuit and terminating circuit.Power circuit is to provide differential signal.Terminating circuit couples power circuit.Terminating circuit is to receive differential signal via the first signal output end and second signal output end, and terminating circuit includes the first load circuit and the second load circuit.When universal serial bus circuit operation is in handshake mode, terminating circuit receives differential signal by the first load circuit and the second load circuit, and via the first signal output end and second signal output end output pulse signal.When universal serial bus circuit operation is in normal mode, terminating circuit receives differential signal by the first load circuit, and via the first signal output end and second signal output end outputting data signals.
Description
Technical field
The invention relates to a kind of bus circuits, and in particular to a kind of universal serial bus (Universal
Serial Bus, USB) circuit.
Background technique
In general, universal serial bus (Universal Serial Bus, USB) 2.0 supports (Full at full speed
Speed) and the data of high speed (High Speed) are transmitted.Under the specification of 2.0 standard of USB, as the USB for main control end
When the equipment of device and device end couples, the equipment of USB device and device end can first carry out (Handshake) mode of shaking hands, with
Confirm mutual data transmission capabilities.That is, the USB before the transmission work for carrying out data-signal, as main control end
The equipment that device understands alternate transport undersuing and positive pulse signal to device end, so that the equipment of device end can effectively really
Recognize whether USB device supports the data of high speed to transmit.In other words, when the equipment of device end can not be to USB device alternate transport
When undersuing and positive pulse signal respond, equipment that the equipment of device end will confirm that USB device and device end
Between data transmission only can operate full speed data transmission.Conversely, then the equipment of device end will confirm that USB device and dress
The data transfer operation set between the equipment at end is transmitted in the data of high speed.
During executing handshake mode, USB device can generate negative pulse letter via the terminating circuit in USB circuit
Number and positive pulse signal, wherein undersuing be a kind of Chirp K signal, and positive pulse signal be a kind of Chirp J
Signal.However, the terminating circuit of general USB circuit only receives the difference letter of current source offer by two switching transistors
Number, and the equipment for corresponding to output pulse signal and data-signal to device end.In this regard, due to Chirp K signal and Chirp
The voltage value of J signal is higher than the voltage value of data transmission, therefore the switching transistor of general terminating circuit is shaken hands mould in execution
Biggish electric current is subjected to during formula, to cause the switching transistor possible operation of terminating circuit in saturation region
(Saturation region), and inelastic region (Linear region).Therefore, Chirp caused by general USB device
The case where K signal and Chirp J signal might have spread of voltage or voltage drift generation.In view of this, how to design
A kind of USB circuit can steadily export Chirp K signal and Chirp J signal during executing handshake mode, below
It will propose the solution of several embodiments.
Summary of the invention
The present invention provides a kind of universal serial bus (Universal Serial Bus, USB) circuit, can effectively generate arteries and veins
Signal (Chirp K signal and Chirp J signal) and data-signal are rushed, to be suitable for USB2.0 high speed (High Speed)
Transmission.
Universal serial bus circuit of the invention includes power circuit and terminating circuit.Power circuit is to provide difference
Signal.Terminating circuit couples power circuit.Terminating circuit is to via the first signal output end and second signal output termination
Astigmat sub-signal.Terminating circuit includes the first load circuit and the second load circuit.When universal serial bus circuit operation exists
When normal mode, terminating circuit receives differential signal by the first load circuit, and via the first signal output end and the
Binary signal output end outputting data signals.When universal serial bus circuit operation is in handshake mode, terminating circuit is by first
Load circuit and the second load circuit receive differential signal, and via the first signal output end and second signal output end
Output pulse signal.
2.0 high-speed transfer of USB can be supported based on above-mentioned, of the invention universal serial bus circuit, and can be by terminal
Circuit effectively to provide pulse signal (Chirp K signal and Chirp J signal) and data-signal.In addition, of the invention
Universal serial bus circuit also has effects that can effectively reduce the power consumption of USB circuit and reduces circuit area.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make
Carefully it is described as follows.
Detailed description of the invention
Fig. 1 is the schematic diagram according to the universal serial bus circuit of one embodiment of the invention.
Fig. 2 is the circuit diagram according to the universal serial bus circuit of one embodiment of the invention.
Fig. 3 is the signal waveforms according to the pulse signal of Fig. 2 embodiment.
Fig. 4 is the signal waveforms according to the data-signal of Fig. 2 embodiment.
Fig. 5 is the circuit diagram according to the universal serial bus circuit of another embodiment of the present invention.
Fig. 6 is the circuit diagram according to the universal serial bus circuit of another embodiment of the present invention.
Fig. 7 is the signal waveforms according to the pulse signal of Fig. 6 embodiment.
Symbol description:
100,300,500,700: universal serial bus circuit
110,310,510,710: power circuit
120,320,520,720: terminating circuit
121,321,521,721: the first load circuit
122,322,522,722: the second load circuit
200,400,600: device terminal circuit
301,302,701,702: pulse signal
401,402: data-signal
323,324,523,524: diode
330,530,730: pull-down circuit
540,740: protection circuit
M1, M1 ', M2, M2 ', M3, M4, M5, M5 ', M6, M6 ', M7, M8, M9, M10: transistor
R1, R2, R3, R4, R5, R6, Rp, Ra, Rb: resistance
S1, S2, S3: switch
I1, I2: current source
DP, DM: signal output end
Specific embodiment
In order to be illustrated that the contents of the present invention more easily, spy can actually evidence as the present invention for embodiment below
With the example of implementation.In addition, all possible places, use component/component/step of identical label in the drawings and embodiments,
Represent same or like component.
Fig. 1 is the schematic diagram according to the universal serial bus circuit of one embodiment of the invention.With reference to Fig. 1, general serial
Bus (Universal Serial Bus, USB) circuit 100 includes power circuit 110 and terminating circuit 120.Power circuit
110 coupling terminating circuits 120.In the present embodiment, terminating circuit 120 includes the first load circuit 121 and the second load electricity
Road 122.Power circuit 110 couples the first load circuit 121 and the second load circuit 122 via signal output end DP, DM.Electricity
Source circuit 110 is selectively to provide difference (Differential) signal to the first load circuit 121 and the second load
Circuit 122.
In the present embodiment, USB circuit 100 can support 2.0 high speed (High Speed) transmission of USB.Therefore, when USB electricity
Road 100 is via the device end outside signal output end DP, DM coupling, and the operation of USB circuit 100 is in shake hands (Handshake)
When mode, USB circuit 100 is via signal output end DP, DM output pulse signal to external device end.Pulse signal refers to
USB circuit 100 exports multiple undersuings (Chirp K signal) via signal output end DP, DM and multiple positive pulses are believed
Number (Chirp J signal), and these undersuings (Chirp K signal) and these positive pulse signals (Chirp J letters
Number) be alternately arranged.The voltage of positive pulse signal (Chirp J signal) can be between 700~1100 millivolts (mV), and negative pulse
The voltage of signal can be between -900~-500 millivolts.That is, when external device end receives the alternating of USB circuit 100
When the positive pulse signal (Chirp J signal) and undersuing (Chirp K signal) of output, external device end can be effective
Ground confirmation USB circuit 100 can support 2.0 high-speed transfer of USB, so that the number between USB circuit 100 and the device end of outside
It is operable according to transmission under the transmission speed of 480 Gigabits per seconds (Mbps).
In the present embodiment, USB circuit 100 can be received by the first load circuit 121 and the second load circuit 122
The differential signal that power circuit 110 exports, and export corresponding pulse signal and data-signal.Specifically, when USB electricity
Road 100 is operated in handshake mode, and terminating circuit 120 receives difference by the first load circuit 121 and the second load circuit 122
Sub-signal, and positive pulse signal (Chirp J signal) and undersuing are alternately exported via signal output end DP, DM
(Chirp K signal) extremely external device end.However, when USB circuit 100 is operated at normal mode (or data-transmission mode)
When, terminating circuit 120 only receives the differential signal that power circuit 110 exports by the first load circuit 121, and via signal
Output end DP, DM outputting data signals are to external device end.
Fig. 2 is the circuit diagram according to the universal serial bus circuit of one embodiment of the invention.With reference to Fig. 2, USB circuit
300 include power circuit 310, terminating circuit 320 and pull-down circuit 330.Terminating circuit 320 includes the first load circuit 321
And second load circuit 322.USB circuit 300 is coupled to device terminal circuit 200 via signal output end DP, DM.In this implementation
In example, device terminal circuit 200 for example refers to the equivalent circuit of the usb connecting port of computer equipment, but the present invention is not limited to
This.In the present embodiment, device terminal circuit 200 may include pull-up resistor Rp and reference resistance Ra, Rb.Pull-up resistor Rp coupling
Switch S1.One end of reference resistance Ra couples switch S2, and the other end of reference resistance Ra couples ground terminal.Reference resistance Rb
One end couple switch S3, and reference resistance Ra the other end coupling ground terminal.
Power circuit 310 includes current source circuit and transistor M1, M2.Current source circuit includes input and output power supply
(I/O power) I1, and input and output power supply I1 can for example provide the power supply signal of 3.3 volts (V).The first of transistor M1
End coupling input and output power supply I1.The second end of transistor M1 couples signal output end DP.The first end coupling of transistor M2 is defeated
Enter out-put supply I1.The second end of transistor M2 couples signal output end DM.In the present embodiment, the second end of transistor M1 with
And the second end of transistor M2 can be exported alternately via signal output end DP, DM and be believed via the power supply that input and output power supply I1 is provided
Number to form differential signal.
First load circuit 321 includes resistance R1, R2 and transistor M3, M4.The first end coupling signal of resistance R1 is defeated
Outlet DP.In the present embodiment, the second end of the first end coupling resistance R1 of transistor M3, and the second end coupling of transistor M3
Meet ground terminal (Ground).The first end of resistance R2 couples second signal output end DM.The first end coupling resistance of transistor M4
The second end of R2, and the second end of transistor M4 couples ground terminal.
Second load circuit 322 includes resistance R3, R4, diode 323,324 and transistor M5, M6.In this reality
It applies in example, the first end of resistance R3 couples signal output end DP.The second end of 323 coupling resistance R3 of diode.Transistor
The first end of M5 couples diode 323, and the second end of transistor M5 couples ground terminal.The first end of resistance R4 couples
Signal output end DM.The second end of 324 coupling resistance R4 of diode.The first end of transistor M6 couples diode
324, and the second end of transistor M6 couples ground terminal.In the present embodiment, diode 323 may include transistor M7,
And diode 324 may include transistor M8.The first end coupling resistance R3 of transistor M7.The control terminal coupling of transistor M7
Connect the first end of transistor M7.The first end of the second end coupling transistors M5 of transistor M7.The first end of transistor M8 couples
Resistance R4.The first end of the control terminal coupling transistors M8 of transistor M8.The of the second end coupling transistors M6 of transistor M8
One end.However, diode 323,324 is also possible to the diode circuit of other forms, diode of the invention
323,324 it is not limited to Fig. 2.In addition, pull-down circuit 330 includes resistance R5, R6, and resistance R5, R6 can be 15k ohm
(Ohm)。
In the present embodiment, when USB circuit 300 is coupled to device terminal circuit 200 via signal output end DP, DM, USB
Circuit 300 is used as main control end (Host), and exports USB and reset (Reset) signal to device terminal circuit 200.Device terminal circuit
200 support 2.0 high-speed transfer of USB, therefore device terminal circuit 200 then exports undersuing (Chirp K signal) to USB
Circuit 300, so that USB circuit 300 confirms that device terminal circuit 200 supports 2.0 high-speed transfer of USB.Then, USB circuit 300 is handed over
For passback undersuing (Chirp K signal) and positive pulse signal (Chirp J signal) to device terminal circuit 200, so that
Device terminal circuit 200 can effectively confirm that USB circuit 300 supports 2.0 high-speed transfer of USB.Finally, USB circuit 300 can enter
Normal mode, and outputting data signals are to device terminal circuit 200.
Fig. 3 is the signal waveforms according to the pulse signal of Fig. 2 embodiment.With reference to Fig. 2 and Fig. 3, when USB circuit 300
In handshake mode, USB circuit 300, which can export alternate positive pulse as shown in Figure 3 via signal output end DP, DM, to be believed for operation
Numbers 301 and undersuing 302 to device terminal circuit 200.Specifically, when the operation of USB circuit 300 is in handshake mode,
Switch S2, S3 of device terminal circuit 200 are not turned on, so that terminating circuit 320 bears biggish electric current.Therefore, USB circuit 300
Positive pulse signal 301 and undersuing 302 will be exported by signal output end DP, DM to device terminal circuit 200.In this reality
It applies in example, the crest voltage of positive pulse signal 301 can be 900mV, and the crest voltage of undersuing 302 can be -800mV.
That is, transistor M3, M4 are connected, and the first load circuit 321 can receive input and output power supply I1 offer
Electric current.At this point, transistor M7, M8 can be equally switched on since the voltage of signal output end DP, DM are larger, so that the
One load circuit 321 and the second load circuit 322 can share the electric current of input and output power supply I1 offer simultaneously.In other words, when
USB circuit 300 is operated in handshake mode, and the terminating circuit 320 of the present embodiment can effectively avoid the crystalline substance of the first load circuit 321
Body pipe M3, M4 carry excessive electric current, so that transistor M3, M4 enter saturation region by linear zone (Linear region)
(Saturation region), and pulse signal (Chirp K signal and the Chirp J for exporting signal output end DP, DM
Signal) voltage there is a situation where drift about.
Fig. 4 is the signal waveforms according to the data-signal of Fig. 2 embodiment.With reference to Fig. 2 and Fig. 4, when USB circuit 300
In normal mode, switch S2, S3 of device terminal circuit 200 are connected for operation, so that the reference voltage Ra of device terminal circuit 200,
Rb and terminating circuit 320 while share current.USB circuit 300 will alternately be exported such as Fig. 4 institute by signal output end DP, DM
The data-signal 401,402 shown is to device terminal circuit 200.Data-signal 401,402 forms differential signal.Data-signal 401
Voltage peak can be 400mV, and the voltage peak of data-signal 402 can be -400mV.That is, transistor M3, M4 with
And switch S2, S3 conducting, it is provided so that the first load circuit 321 and reference voltage Ra, Rb can receive input and output power supply I1
Electric current.At this point, transistor M7, M8 will not be switched on since the voltage of signal output end DP, DM are smaller.Therefore, when USB electricity
Road 300 is operated in normal mode, and the electric current that input and output power supply I1 is provided does not flow through the second load circuit 322.
Fig. 5 is the circuit diagram according to the universal serial bus circuit of another embodiment of the present invention.With reference to Fig. 5, USB circuit
500 include power circuit 510, terminating circuit 520, pull-down circuit 530 and protection circuit 540.Terminating circuit 520 includes first
Load circuit 521 and the second load circuit 522.USB circuit 500 is coupled to device terminal circuit via signal output end DP, DM
400.In the present embodiment, device terminal circuit 400 for example refers to the equivalent circuit of the usb connecting port of computer equipment, but this
Invention is not limited to this.In the present embodiment, device terminal circuit 400 is for example including pull-up resistor Rp and reference resistance Ra, Rb.
Pull-up resistor Rp couples switch S1.One end of reference resistance Ra couples switch S2, and the other end of reference resistance Ra connects
Ground terminal.One end of reference resistance Rb couples switch S3, and the other end of reference resistance Rb couples ground terminal.
Power circuit 510 includes current source circuit and transistor M1 ', M2 '.Current source circuit includes input and output power supply
I1 and core power (Core power) I2.Input and output power supply I1 can for example provide the power supply signal of 3.3V, and core
Power supply I2 can for example provide the power supply signal of 1.05V.The first end coupling input and output power supply I1 and core electricity of transistor M1 '
Source I2.The second end of transistor M1 ' couples signal output end DP.Transistor M2 ' first end coupling input and output power supply I1 with
And core power I2.The second end of transistor M2 ' couples signal output end DM.In the present embodiment, the second end of transistor M1 '
And the second end of transistor M2 ' can be exported alternately via signal output end DP, DM via input and output power supply I1 or core electricity
The power supply signal that source I2 is provided is to form differential signal.It is worth noting that, compared to the power circuit 310 of Fig. 2 embodiment, this
The power circuit 510 of embodiment includes two power supplys, and the voltage of input and output power supply I1 is greater than core power I2.It inputs defeated
Power supply I1 and core power I2 can via controller (not shown) and selectively out-put supply signal out.
First load circuit 521 includes resistance R1, R2 and transistor M3, M4.The first end coupling signal of resistance R1 is defeated
Outlet DP.In the present embodiment, the second end of the first end coupling resistance R1 of transistor M3, and the second end coupling of transistor M3
Connect ground terminal.The first end of resistance R2 couples second signal output end DM.The second of the first end coupling resistance R2 of transistor M4
End, and the second end of transistor M4 couples ground terminal.
Second load circuit 522 includes resistance R3, R4, diode 523,524 and transistor M5, M6.In this reality
It applies in example, the first end of resistance R3 couples signal output end DP.The second end of 523 coupling resistance R3 of diode.Transistor
The first end of M5 couples diode 523, and the second end of transistor M5 couples ground terminal.The first end of resistance R4 couples
Signal output end DM.The second end of 524 coupling resistance R4 of diode.The first end of transistor M6 couples diode
524, and the second end of transistor M6 couples ground terminal.In the present embodiment, diode 523 may include transistor M7,
And diode 524 may include transistor M8.The first end coupling resistance R3 of transistor M7.The control terminal coupling of transistor M7
Connect the first end of transistor M7.The first end of the second end coupling transistors M5 of transistor M7.The first end of transistor M8 couples
Resistance R4.The first end of the control terminal coupling transistors M8 of transistor M8.The of the second end coupling transistors M6 of transistor M8
One end.However, diode 523 and diode 524 are also possible to the diode circuit of other forms, it is of the invention
Diode 523 and diode 524 are not limited to Fig. 5.In addition, pull-down circuit 530 includes resistance R5, R6, and
Resistance R5, R6 can be 15k ohm.
In the present embodiment, when the operation of USB circuit 500 is in handshake mode, power circuit 510 is by input and output power supply
I1 out-put supply signal is to the first end of transistor M1 ' and the first end of transistor M2 '.When USB circuit 500 is operated normal
When mode, power circuit 510 by core power I2 out-put supply signal to transistor M1 ' first end and transistor M2 '
First end.However, transistor M1 ', M2 ' correspond to the core power I2 of low-voltage and the low pressure components (core that configures
device).In advanced process, in order to avoid transistor M1 ', M2 ' at Full-Speed mode (voltage be 0V~3.3V) by signal
The voltage of output end DP, DM are damaged, therefore the USB circuit 500 of the present embodiment further includes protection circuit 540.
Protection circuit 540 is coupled between power circuit 510 and terminating circuit 520.Protecting circuit 540 includes transistor
M9,M10.The first end of transistor M9 couples power circuit 510, and the second end of transistor M9 couples terminating circuit 520.It is brilliant
The first end of body pipe M10 couples power circuit 510, and the second end of transistor M10 couples terminating circuit 520.Accordingly, work as letter
Number output end DP, DM can be 0V~3.3V between voltage in Full-Speed mode, at this time can protect transistor M9, M10 closing
Transistor M1 ', M2 ' are unlikely to damage.
In the present embodiment, when USB circuit 500 is coupled to device terminal circuit 400 via signal output end DP, DM, USB
Circuit 500 is used as main control end, and exports USB reset signal to device terminal circuit 400.Device terminal circuit 400 supports USB 2.0
High-speed transfer, therefore device terminal circuit 400 then exports undersuing (Chirp K signal) to USB circuit 500, so that USB
Circuit 500 confirms that device terminal circuit 400 supports 2.0 high-speed transfer of USB.Then, USB circuit 500 is according to input and output power supply I1
Alternately passback undersuing (Chirp K signal) and positive pulse signal (Chirp J signal) extremely fill the power supply signal of offer
Terminal circuit 400 is set, so that device terminal circuit 400 can effectively confirm that USB circuit 500 supports 2.0 high-speed transfer of USB.Finally,
USB circuit 500 can enter normal mode, and carry out outputting data signals to device according to the core power I2 power supply signal provided
Terminal circuit 400.
Specifically, switch S2, S3 of device terminal circuit 400 are not turned on when the operation of USB circuit 500 is in handshake mode,
So that terminating circuit 520 bears biggish electric current.USB circuit 500 will export positive pulse signal by signal output end DP, DM
(Chirp J signal) and undersuing (ChirpK signal) are to device terminal circuit 400.That is, transistor M3, M4 are led
It is logical, so that the first load circuit 521 can receive the electric current of input and output power supply I1 offer.At this point, due to signal output end DP, DM
Voltage it is larger, therefore transistor M7, M8 can be equally switched on, so that the first load circuit 521 and the second load circuit 522
The electric current of input and output power supply I1 offer can be provided simultaneously.In other words, when USB circuit 500 operates this implementation in handshake mode
Transistor M3, M4 that the terminating circuit 520 of example can effectively avoid the first load circuit 521 carry excessive electric current, so that crystal
Pipe M3, M4 enter saturation region by linear zone, and make signal output end DP, DM export pulse signal (Chirp K signal and
Chirp J signal) voltage there is a situation where drift about.
When the operation of USB circuit 500 is in normal mode, switch S2, S3 of device terminal circuit 400 are connected, so that device end
Reference voltage Ra, Rb and terminating circuit 520 while share current of circuit 400.USB circuit 500 will pass through signal output end
DP, DM alternately outputting data signals to device terminal circuit 400.That is, transistor M3, M4 and switch S2, S3 conducting,
And the first load circuit 521 can receive the electric current of core power I2 offer.At this point, due to the voltage of signal output end DP, DM
Smaller, transistor M7, M8 will not be switched on.Therefore, when USB circuit 500 operation in normal mode, core power I2 provide
Electric current does not flow through the second load circuit 522.
Accordingly, when the operation of the USB circuit of the present embodiment 500 is in handshake mode, USB circuit 500 can be higher by having
To generate pulse signal, (Chirp K signal and Chirp J believe the power supply signal that the input and output power supply I1 of voltage is supplied
Number) to device terminal circuit 400.Also, when the operation of the USB circuit of the present embodiment 500 is in normal mode, USB circuit 500 can be by
Data-signal is generated to device terminal circuit 400 by power supply signal that the core power I2 with lower voltage is supplied.Therefore,
The USB circuit 500 of the present embodiment can be floated in addition to can effectively avoid the voltage of the pulse signal of signal output end DP, DM output
The case where shifting, and also can effectively reduce power consumption.
Fig. 6 is the circuit diagram according to the universal serial bus circuit of another embodiment of the present invention.With reference to Fig. 6, USB circuit
700 include power circuit 710, terminating circuit 720, pull-down circuit 730 and protection circuit 740.Terminating circuit 720 includes first
Load circuit 721 and the second load circuit 722.USB circuit 700 is coupled to device terminal circuit via signal output end DP, DM
600.In the present embodiment, device terminal circuit 600 for example refers to the equivalent circuit of the usb connecting port of computer equipment, but this
Invention is not limited to this.In the present embodiment, device terminal circuit 600 is for example including pull-up resistor Rp and reference resistance Ra, Rb.
Pull-up resistor Rp couples switch S1.One end of reference resistance Ra couples switch S2, and the other end of reference resistance Ra connects
Ground terminal.One end of reference resistance Rb couples switch S3, and the other end of reference resistance Rb couples ground terminal.
Power circuit 710 includes current source circuit and transistor M1 ', M2 '.Current source circuit includes core power I2,
And core power I2 can for example provide the power supply signal of 1.05V.The first end of transistor M1 ' couples core power I2.Crystal
The second end of pipe M1 ' couples signal output end DP.The first end of transistor M2 ' couples core power I2.The second of transistor M2 '
End coupling signal output end DM.In the present embodiment, the second end of transistor M1 ' and the second end of transistor M2 ' are via letter
Number output end DP, DM can export the power supply signal provided via core power I2 alternately to form differential signal.It is noticeable
It is that, compared to the power circuit 510 of Fig. 5 embodiment, the power circuit 710 of the present embodiment only includes a power supply.
First load circuit 721 includes resistance R1, R2 and transistor M3, M4.The first end coupling signal of resistance R1 is defeated
Outlet DP.In the present embodiment, the second end of the first end coupling resistance R1 of transistor M3, and the second end coupling of transistor M3
Connect ground terminal.The first end of resistance R2 couples second signal output end DM.The second of the first end coupling resistance R2 of transistor M4
End, and the second end of transistor M4 couples ground terminal.The control terminal of transistor M3, M4 be by one control signal (not shown) into
Row control.When being in handshake mode or normal mode, transistor M3, M4 can be all turned on.
Second load circuit 722 includes transistor M5 ', M6 '.In the present embodiment, the first end of transistor M5 ' couples brilliant
The first end of body pipe M3, and the second end of transistor M5 ' couples ground terminal.The first end coupling transistors M4 of transistor M6 ',
And the second end of transistor M6 ' couples ground terminal.In addition, pull-down circuit 730 includes resistance R5, R6, and resistance R5, R6 can
It is 15k ohm.Transistor M5 ', M6 ' control terminal be to be controlled by another control signal (not shown).When in mould of shaking hands
When formula, transistor M5 ', M6 ' can be turned on.When in normal mode, transistor M5 ', M6 ' can be closed.
In the present embodiment, when the operation of USB circuit 700 is in handshake mode, power circuit 710 is defeated by core power I2
Power supply signal is to the first end of transistor M1 ' and the first end of transistor M2 ' out.When USB circuit 700 is operated in normal mode
When, power circuit 710 is equally by the first end and transistor M2 ' of core power I2 out-put supply signal to transistor M1 '
First end.However, transistor M1 ', M2 ' correspond to the core power I2 of low-voltage and the low pressure components that configure
(coredevice).In advanced process, in order to avoid transistor M1 ', M2 ' at Full-Speed mode (voltage be 0V~3.3V) quilt
The voltage of signal output end DP, DM are damaged, therefore the USB circuit 700 of the present embodiment further includes protection circuit 740.
Protection circuit 740 is coupled between power circuit 710 and terminating circuit 720.Protecting circuit 740 includes transistor
M9,M10.The first end of transistor M9 couples power circuit 710, and the second end of transistor M9 couples terminating circuit 720.It is brilliant
The first end of body pipe M10 couples power circuit 710, and the second end of transistor M10 couples terminating circuit 720.Accordingly, work as letter
Number output end DP, DM can be 0V~3.3V between voltage in Full-Speed mode, at this time can protect transistor M9, M10 closing
Transistor M1 ', M2 ' are unlikely to damage.
In the present embodiment, when USB circuit 700 is coupled to device terminal circuit 600 via signal output end DP, DM, USB
Circuit 700 is used as main control end, and exports USB reset signal to device terminal circuit 600.Device terminal circuit 600 supports USB 2.0
High-speed transfer, therefore device terminal circuit 600 then exports undersuing (Chirp K signal) to USB circuit 700, so that USB
Circuit 700 confirms that device terminal circuit 600 supports 2.0 high-speed transfer of USB.Then, USB circuit 700 is provided according to core power I2
Power supply signal alternately passback undersuing (Chirp K signal) and positive pulse signal (Chirp J signal) to device end
Circuit 600, so that device terminal circuit 600 can effectively confirm that USB circuit 700 supports 2.0 high-speed transfer of USB.Finally, USB is electric
Road 700 can enter normal mode, and carry out outputting data signals to device also according to the core power I2 power supply signal provided
Terminal circuit 600.
Fig. 7 is the signal waveforms according to the pulse signal of Fig. 6 embodiment.With reference to Fig. 6 and Fig. 7, when USB circuit 700
In handshake mode, USB circuit 700, which can export alternate positive pulse as shown in Figure 7 via signal output end DP, DM, to be believed for operation
Numbers 701 and undersuing 702 to device terminal circuit 600.Specifically, when the operation of USB circuit 700 is in handshake mode,
Switch S2, S3 of device terminal circuit 600 are not turned on, so that terminating circuit 720 bears biggish electric current.Therefore, USB circuit 700
Positive pulse signal 701 and undersuing 702 will be exported by signal output end DP, DM to device terminal circuit 600.In this reality
It applies in example, the crest voltage of positive pulse signal 701 can be 800mV, and the crest voltage of undersuing 702 can be -700mV.
That is, transistor M3, M4, M5 ', M6 ' conducting, therefore the first load circuit 721 and the second load circuit
The electric current that 722 receivable core power I2 are provided, so that the first load circuit 721 and the second load circuit 722 can the same time-divisions
Carry on a shoulder pole the electric current that core power I2 is provided.In other words, when USB circuit 700 operates the terminating circuit of the present embodiment in handshake mode
720 transistor M3, M4 that can effectively avoid the first load circuit 721 carry excessive electric current, so that transistor M3, M4 are by linear
Area enters saturation region, and the pulse signal (Chirp K signal and Chirp J signal) for exporting signal output end DP, DM
There is a situation where drift about for voltage.
Referring again to Fig. 6, when the operation of USB circuit 700 is in normal mode, switch S2, S3 of device terminal circuit 600 are connected,
So that reference resistance Ra, Rb and terminating circuit 720 of device terminal circuit 600 while share current.USB circuit 600 will pass through
Signal output end DP, DM alternately outputting data signals to device terminal circuit 600.That is, transistor M3, M4 and switch
S2, S3 conducting, and the first load circuit 721 can receive the electric current of core power I2 offer.At this point, transistor M5 ', M6 '
Control terminal is controlled by another control signal (not shown).When being in handshake mode, transistor M5 ', M6 ' can be held
It opens.When in normal mode, transistor M5 ', M6 ' can be closed.Therefore, when USB circuit 700 operation in normal mode,
The electric current that core power I2 is provided does not flow through the second load circuit 722.
Accordingly, when no matter the USB circuit of the present embodiment 700 operates in normal mode or handshake mode, USB circuit 700
Can all be generated by the power supply signal that the core power I2 with lower voltage is supplied pulse signal (Chirp J signal with
And Chirp K signal) and data-signal to device terminal circuit 600.Therefore, the USB circuit 700 of the present embodiment is in addition to can be effective
The voltage for the pulse signal for avoiding signal output end DP, DM from exporting also can effectively reduce power and disappear there is a situation where drifting about
Consumption.Importantly, the terminating circuit 720 of the USB circuit 700 of the present embodiment can compared to the USB circuit 500 of Fig. 5 embodiment
By less transistor, pulse signal (Chirp K signal and Chirp J signal) and data letter can be effectively generated
Number.Therefore, the USB circuit 700 of the present embodiment also has the characteristics that cost is relatively low and transistor processing procedure area is lesser.
In addition, each transistor described in the various embodiments described above can be metal-oxide-semiconductor (MOS) (Metal Oxide
Semiconductor, MOS) transistor or two-carrier connection transistor (Bipolar Junction Transistor, BJT) etc.
Suchlike transistor component, the present invention is not limited thereto.Also, the class of each transistor described in the various embodiments described above
Type can be N-type transistor or P-type transistor, and the present invention is also without restriction.
In conclusion universal serial bus circuit of the invention can steadily export pulse letter when executing handshake mode
Number (Chirp K signal and Chirp J signal) to device terminal circuit so that device terminal circuit can effectively confirm general serial
The data transmission capabilities of bus circuit.Also, universal serial bus circuit of the invention can also pass through power circuit and load
The design of circuit, and the power consumption of universal serial bus circuit can further be effectively reduced, and reduce the crystalline substance of terminating circuit
The effect of body control journey area.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field
In technical staff, without departing from the spirit and scope of the present invention, when can make some changes and embellishment, therefore guarantor of the invention
Range is protected subject to view scope of the appended claims institute defender.
Claims (16)
1. a kind of universal serial bus circuit, comprising:
One power circuit, to provide a differential signal；And
One terminating circuit couples the power circuit, to via one first signal output end and a second signal output end
The differential signal is received, and the terminating circuit includes one first load circuit and one second load circuit,
Wherein when the universal serial bus circuit operation is in a handshake mode, the terminating circuit is by first load
Circuit and second load circuit receive the differential signal, and via first signal output end and described the
Binary signal output end exports a pulse signal,
Wherein when the universal serial bus circuit operation is in a normal mode, the terminating circuit is by first load
Circuit receives the differential signal, and via one number of first signal output end and second signal output end output
It is believed that number.
2. universal serial bus circuit according to claim 1, wherein the power circuit includes:
One current source circuit, to export a power supply signal；
One the first transistor a, wherein first end of the first transistor couples the current source circuit, the first crystal
One second end of pipe couples first signal output end；And
One second transistor a, wherein first end of the second transistor couples the current source circuit, second crystal
One second end of pipe couples the second signal output end,
Wherein the second end of the first transistor and the second end of the second transistor are via described first
Signal output end and the second signal output end alternately export the power supply signal to form the differential signal.
3. universal serial bus circuit according to claim 2, wherein the current source circuit includes input and output electricity
Source, and the first end of the first transistor described in the input and output supply coupling and the second transistor is described
First end.
4. universal serial bus circuit according to claim 2, wherein the current source circuit include a core power with
And an input and output power supply, and the first transistor described in the core power and the input and output supply coupling is described
The first end of first end and the second transistor,
Wherein when the universal serial bus circuit operation is in the handshake mode, the input and output power supply exports one first
Power supply signal to the first end of the first transistor and the first end of the second transistor,
Wherein when the universal serial bus circuit operation is in the normal mode, the core power exports a second source
Signal is to the first end of the first transistor and the first end of the second transistor.
5. universal serial bus circuit according to claim 4, wherein the voltage of first power supply signal is greater than described
Second source signal.
6. universal serial bus circuit according to claim 2, wherein the current source circuit includes a core power, and
And the core power couples the first end of the first transistor and the first end of the second transistor.
7. universal serial bus circuit according to claim 1, wherein first load circuit includes:
One first resistor a, wherein first end of the first resistor couples first signal output end；
One third transistor, wherein a first end of the third transistor couples a second end of the first resistor, it is described
One second end of third transistor couples a ground terminal；
One second resistance a, wherein first end of the second resistance couples the second signal output end；And
One the 4th transistor, wherein a first end of the 4th transistor couples a second end of the second resistance, it is described
One second end of the 4th transistor couples the ground terminal.
8. universal serial bus circuit according to claim 7, wherein second load circuit includes:
One 3rd resistor a, wherein first end of the 3rd resistor couples first signal output end；
One first diode unit couples a second end of the 3rd resistor；
One the 5th transistor, wherein the first end coupling first diode unit of the 5th transistor, the described 5th
One second end of transistor couples the ground terminal；
One the 4th resistance a, wherein first end of the 4th resistance couples the second signal output end；
One second diode couples a second end of the 4th resistance；And
One the 6th transistor, wherein first end coupling second diode of the 6th transistor, the described 6th
One second end of transistor couples the ground terminal.
9. universal serial bus circuit according to claim 8, wherein when the universal serial bus circuit operation is in institute
When stating normal mode, the first diode unit and second diode are not turned on, wherein when the general string
For row bus circuit operation in the handshake mode, the first diode unit and second diode are according to institute
The differential signal of power circuit offer is provided and is connected.
10. universal serial bus circuit according to claim 8, wherein the first diode unit includes one the 7th brilliant
Body pipe a, wherein first end of the 7th transistor couples the 3rd resistor, a control terminal coupling of the 7th transistor
The first end of the 7th transistor is connect, a second end of the 7th transistor couples the described of the 5th transistor
First end.
11. universal serial bus circuit according to claim 8, wherein second diode includes one the 8th brilliant
Body pipe a, wherein first end of the 8th transistor couples the 4th resistance, a control terminal coupling of the 8th transistor
The first end of the 8th transistor is connect, a second end of the 8th transistor couples the described of the 6th transistor
First end.
12. universal serial bus circuit according to claim 7, wherein second load circuit includes:
One the 9th transistor, wherein a first end of the 9th transistor couples the first end of the third transistor,
One second end of the 9th transistor couples the ground terminal；And
The tenth transistor, wherein a first end of the tenth transistor couples the first end of the 4th transistor,
One second end of the tenth transistor couples the ground terminal.
13. universal serial bus circuit according to claim 12, wherein when the universal serial bus circuit operation exists
When the normal mode, the 9th transistor and the tenth transistor are not turned on, wherein when the universal serial bus
Circuit operation is in the handshake mode, the 9th transistor and the tenth transistor turns, to receive the power supply
The differential signal that circuit provides.
14. universal serial bus circuit according to claim 1, further includes:
One protection circuit, is coupled between the power circuit and the terminating circuit, wherein the protection circuit includes:
The 11st transistor, wherein the first end coupling power circuit of the 11st transistor, the described 11st
One second end of transistor couples the terminating circuit；And
The tenth two-transistor, wherein the first end coupling power circuit of the tenth two-transistor, the described 12nd
One second end of transistor couples the terminating circuit.
15. universal serial bus circuit according to claim 1, further includes:
One pull-down circuit couples first signal output end and the second signal output end, wherein the pull-down circuit
Include:
One the 5th resistance a, wherein first end of the 5th resistance couples first signal output end, the 5th resistance
A second end couple a ground terminal；And
One the 6th resistance a, wherein first end of the 6th resistance couples the second signal output end, the 6th resistance
A second end couple the ground terminal.
16. universal serial bus circuit according to claim 1, wherein the pulse signal includes multiple undersuings
And multiple positive pulse signals, and the undersuing and the positive pulse signal are alternately arranged.
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| CN201810840739.1A CN109144925B (en) | 2018-07-27 | 2018-07-27 | Universal serial bus circuit |
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| CN201810840739.1A CN109144925B (en) | 2018-07-27 | 2018-07-27 | Universal serial bus circuit |
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| CN109144925B CN109144925B (en) | 2020-07-28 |
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| CN109144925B (en) | 2020-07-28 |
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