TW201320199A - Method for forming a silicon layer on a substrate, a method for forming a silicon oxide layer, and a metal oxide TFT device having the same - Google Patents

Method for forming a silicon layer on a substrate, a method for forming a silicon oxide layer, and a metal oxide TFT device having the same Download PDF

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TW201320199A
TW201320199A TW101135223A TW101135223A TW201320199A TW 201320199 A TW201320199 A TW 201320199A TW 101135223 A TW101135223 A TW 101135223A TW 101135223 A TW101135223 A TW 101135223A TW 201320199 A TW201320199 A TW 201320199A
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layer
gas
oxide
substrate
flow rate
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TWI550722B (en
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Qun-Hua Wang
wei-jie Wang
Young-Jin Choi
Seon-Mee Cho
Yi Cui
Beom-Soo Park
Soo-Young Choi
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Applied Materials Inc
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Abstract

Embodiments of the disclosure generally provide methods of forming a silicon containing layers in TFT devices. The silicon can be used to form the active channel in a LTPS TFT or be utilized as an element in a gate dielectric layer, a passivation layer or even an etch stop layer. The silicon containing layer is deposited by a vapor deposition process whereby an inert gas, such as argon, is introduced along with the silicon precursor. The inert gas functions to drive out weak, dangling silicon-hydrogen bonds or silicon-silicon bonds so that strong silicon-silicon or silicon-oxygen bonds remain to form a substantially hydrogen free silicon containing layer.

Description

於基板上形成矽層之方法、形成矽氧化物層之方法及具有 其之金屬氧化物薄膜電晶體元件 a method of forming a germanium layer on a substrate, a method of forming a germanium oxide layer, and having Metal oxide thin film transistor element

本發明之實施例大體上是有關於形成含矽層(silicon containing layer)的方法。更準確地說,本發明是關於形成可運用於薄膜電晶體元件(Thin Film Transistor,TFT)之含矽層的方法。 Embodiments of the invention are generally directed to methods of forming a silicon containing layer. More specifically, the present invention relates to a method of forming a germanium-containing layer that can be applied to a thin film transistor (TFT).

電漿顯示器面板及液晶顯示器(Liquid Crystal Display,LCD)普遍地用於平面顯示器上。LCD通常包含兩個玻璃基板及一層夾於其中的液晶材料。玻璃基板可為半導體基板或可為透明基板,透明基板例如像是玻璃、石英、藍寶石或是透明塑膠膜。LCD也可包含發光二極體,用以作為背光源。 Plasma display panels and liquid crystal displays (LCDs) are commonly used on flat panel displays. LCDs typically contain two glass substrates and a layer of liquid crystal material sandwiched therein. The glass substrate may be a semiconductor substrate or may be a transparent substrate such as glass, quartz, sapphire or a transparent plastic film. The LCD can also include a light emitting diode for use as a backlight.

隨著對於LCD之解析度的需求增加,控制大量的液晶胞的個別區域(稱為畫素)已變得相當重要。在現代的顯示面板中,可存在超過一百萬個畫素。至少有同數量的電晶體係形成於玻璃基板上,以使得各個畫素相對於其他設置在基板上的畫素可於開、關狀態(energized and de-energized)間切換。 As the demand for the resolution of LCDs increases, it has become quite important to control individual regions of a large number of liquid crystal cells, called pixels. In modern display panels, there can be more than one million pixels. At least the same number of electro-crystal systems are formed on the glass substrate such that the respective pixels can be switched between energized and de-energized with respect to other pixels disposed on the substrate.

含矽材料已成為大多數薄膜電晶體的基礎材料。含矽材料已被運用於形成通道材料,像是用於低溫多晶矽薄膜電晶體(Low Temperature Polysilicon Thin Film Transistor,LTPS TFT)的多晶矽,及作為用於形成薄膜電晶體中閘極介電層(gate dielectric layer)、介面層(interface layer)、鈍 化層(passivation layer)或甚至蝕刻終止層(etch stop layer)的一種元素。 Bismuth-containing materials have become the basis material for most thin film transistors. Bismuth-containing materials have been used to form channel materials, such as polysilicon for Low Temperature Polysilicon Thin Film Transistors (LTPS TFTs), and as gate dielectric layers for forming thin film transistors (gate Dielectric layer), interface layer, blunt A passivation layer or even an element of an etch stop layer.

因此,在這個技術領域中需要利用含矽材料形成具有穩定性和可靠之效能(performance)的薄膜電晶體的方法。 Therefore, there is a need in the art for a method of forming a thin film transistor having a stable and reliable performance using a germanium-containing material.

本揭露書之實施例大體上提供了形成薄膜電晶體、有機發光二極體(Organic Light-Emitting Diode,OLED)、發光二極體(Light-Emitting Diode,LED)及太陽電池元件中之含矽層的方法。含矽層可用於形成包含低溫多晶矽和金屬氧化物薄膜電晶體元件等等之薄膜電晶體元件中的主動通道,或是做為閘極介電層、介面層、鈍化層或蝕刻終止層中的一種元素。含矽層係藉由氣相沉積製程來沉積,藉著氣相沉積製程而隨著含矽之前驅物(precursor)提供一惰性氣體,例如氬氣。該惰性氣體具有驅除弱的、懸浮的矽-氫鍵或矽-矽鍵的功能,因此保留較強的矽-矽鍵或是矽-氧鍵。 Embodiments of the present disclosure generally provide for the formation of a thin film transistor, an Organic Light-Emitting Diode (OLED), a Light-Emitting Diode (LED), and a yttrium-containing element in a solar cell element. Layer method. The germanium-containing layer can be used to form an active channel in a thin film transistor element including a low temperature polysilicon and a metal oxide thin film transistor element, or as a gate dielectric layer, an interface layer, a passivation layer, or an etch stop layer. An element. The ruthenium-containing layer is deposited by a vapor deposition process, and an inert gas such as argon is supplied along with the precursor of the ruthenium by a vapor deposition process. The inert gas has the function of repelling weak, suspended hydrazine-hydrogen bonds or hydrazone-hydrazine bonds, thus retaining a strong 矽-矽 bond or a 矽-oxygen bond.

在一實施例中,係揭露一種在基板上形成含矽層的方法。該方法包括運送基板至處理腔室中,並提供具有矽基氣體、惰性氣體且實質上不含氫的混合氣體至處理腔室。混合氣體之惰性氣體之每單位基板表面積的體積流率為矽基氣體之每單位基板表面積的體積流率的約1.8至約79倍。該方法另外包括施加一射頻功率至一電極,以將混合氣體激發成一電漿,並形成一非晶矽層於基板上。 In one embodiment, a method of forming a germanium-containing layer on a substrate is disclosed. The method includes transporting a substrate into a processing chamber and providing a mixed gas having a ruthenium based gas, an inert gas, and substantially no hydrogen to the processing chamber. The volumetric flow rate per unit substrate surface area of the inert gas of the mixed gas is from about 1.8 to about 79 times the volume flow rate per unit substrate surface area of the bismuth-based gas. The method additionally includes applying a radio frequency power to an electrode to excite the mixed gas into a plasma and forming an amorphous germanium layer on the substrate.

在另外一實施例中,係揭露一種形成矽氧化物層的方 法。該方法包括提供具有矽基氣體、惰性氣體及含氧氣體的混合氣體至一個處理腔室。混合氣體之惰性氣體之每單位表面積的體積流率為矽基氣體之每單位表面積的體積流率的約11至約80倍。該方法亦包括施加一射頻功率,以將混合氣體激發成一電漿,並形成一矽氧化物層於基板上。 In another embodiment, a method of forming a tantalum oxide layer is disclosed. law. The method includes providing a mixed gas having a ruthenium-based gas, an inert gas, and an oxygen-containing gas to a processing chamber. The volumetric flow rate per unit surface area of the inert gas of the mixed gas is about 11 to about 80 times the volume flow rate per unit surface area of the cerium-based gas. The method also includes applying a radio frequency power to excite the mixed gas into a plasma and forming a tantalum oxide layer on the substrate.

再一實施例中,一金屬氧化物薄膜電晶體元件包括一基板、設置於基板上之一閘極絕緣層、設置於絕緣層上之一主動通道、設置於主動通道上之一源極-汲極電極及設置於源極-汲極電極層上之一鈍化層,其中閘極絕緣層包含一實質上不含氫之矽氧化物層,其中主動通道至少包含銦鎵鋅氧化物(InGaZnO)、銦鎵鋅氮氧化物(InGaZnON)、氧化鋅(ZnO)、氮氧化鋅(ZnON)、鋅錫氧化物(ZnSnO)、鎘錫氧化物(CdSnO)、鎵錫氧化物(GaSnO)、鈦錫氧化物(TiSnO)、銅鋁氧化物(CuAlO)、鍶銅氧化物(SrCuO)、鑭銅氧硫化物(LaCuOS)、氮化鎵(GaN)、銦鎵氮化物(InGaN)、鋁鎵氮化物(AlGaN)或銦鎵鋁氮化物(InGaAlN)其中之一,其中鈍化層包含一實質上不含氫之矽氧化物層。 In another embodiment, a metal oxide thin film transistor device includes a substrate, a gate insulating layer disposed on the substrate, an active channel disposed on the insulating layer, and one source-side disposed on the active channel a pole electrode and a passivation layer disposed on the source-drain electrode layer, wherein the gate insulating layer comprises a germanium oxide layer substantially free of hydrogen, wherein the active channel comprises at least indium gallium zinc oxide (InGaZnO), InGaAs, Zn, ZnO, ZnO, ZnSnO (TiSnO), copper aluminum oxide (CuAlO), beryllium copper oxide (SrCuO), beryllium copper oxysulfide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride ( One of AlGaN) or indium gallium aluminum nitride (InGaAlN), wherein the passivation layer comprises a tantalum oxide layer substantially free of hydrogen.

又一實施例中,一金屬氧化物薄膜電晶體元件包含一基板及一主動通道,主動通道設置於基板上一源極-汲極電極及一閘極絕緣層之間,其中,一介面形成於主動通道及閘極絕緣層之間,介面包含一實質上不含氫之介電表面。 In another embodiment, a metal oxide thin film transistor device includes a substrate and an active channel disposed between a source-drain electrode and a gate insulating layer on the substrate, wherein an interface is formed on the substrate Between the active channel and the gate insulating layer, the interface comprises a dielectric surface substantially free of hydrogen.

為了對本發明之上述特徵有更詳盡的了解,以下將藉 由實施例並配合所附圖式,而對本發明進行更完整之揭露。為求清楚起見,說明書與圖式中係盡可能地使用相同元件符號來表示相同元件。此外,一實施例中之元件與特徵亦可能出現於其他實施例中,以達較佳之實施方式,而相同的描述內容則就此省略。然而須注意,以下的實施例以及所附圖式僅為例示之用,而非用以限定本發明的範圍。 In order to have a more detailed understanding of the above features of the present invention, the following will The invention will be more fully disclosed by the embodiments and the accompanying drawings. For the sake of clarity, the same component symbols are used to denote the same components as much as possible in the specification and drawings. In addition, the elements and features of an embodiment may also be present in other embodiments for the preferred embodiments, and the same description is omitted. It is to be noted, however, that the following embodiments and the accompanying drawings are intended to illustrate

本揭露書之實施例大體上提供了於薄膜電晶體元件中形成一含矽層之方法。該含矽層可用於形成一低溫多晶矽薄膜電晶體或其他合適之金屬氧化物薄膜電晶體(metal oxide TFT)元件中的主動通道,或可作為一閘極介電層、一介面層、一鈍化層或甚至一蝕刻終止層中之一個元件。含矽層係藉由一氣相沉積製程來沉積,藉著氣相沉積製程而隨著矽之前驅物提供一惰性氣體,例如氬氣。該惰性氣體具有驅除弱的、懸浮的矽-氫鍵或矽-矽鍵的功能,因此保留較強的矽-矽鍵或是矽-氧鍵。 Embodiments of the present disclosure generally provide a method of forming a germanium-containing layer in a thin film transistor device. The germanium-containing layer can be used to form an active channel in a low temperature polycrystalline germanium film transistor or other suitable metal oxide TFT element, or can be used as a gate dielectric layer, an interface layer, and a passivation layer. One of the layers or even an etch stop layer. The ruthenium-containing layer is deposited by a vapor deposition process, and an inert gas such as argon is supplied along with the ruthenium precursor by a vapor deposition process. The inert gas has the function of repelling weak, suspended hydrazine-hydrogen bonds or hydrazone-hydrazine bonds, thus retaining a strong 矽-矽 bond or a 矽-oxygen bond.

在一實施例中,係揭露一種形成一非晶矽層之方法,該非晶矽層可於之後轉變成一多晶矽層。該非晶矽層可用於一低溫多晶矽薄膜電晶體元件中,作為通道材料。或者,藉由此處所述之方法形成的非晶矽層、矽氧化物層、矽氮化物層、氮氧化矽層或其他合適之含矽層,也可應用於合適之薄膜電晶體元件中,例如金屬氧化物薄膜電晶體元件。非晶矽層、矽氧化物層、矽氮化物層、氮氧化矽層或其他合適之含矽層等等,亦可用於光二極體(photodiodes)、半導體二極體、發光二極體(LEDs)、有機 發光二極體(OLEDs)或其他顯示器應用上。非晶矽層、矽氧化物層、矽氮化物層、氮氧化矽層以最低之含氫量,提供高的薄膜品質和穩定性及低的薄膜漏電(film leakage),從而有效地強化電晶體元件之電性表現。值得注意的是,除了上述提到的應用,非晶矽層可用於其他合適元件。 In one embodiment, a method of forming an amorphous germanium layer that can be subsequently converted into a polysilicon layer is disclosed. The amorphous germanium layer can be used in a low temperature polycrystalline germanium thin film transistor element as a channel material. Alternatively, the amorphous germanium layer, tantalum oxide layer, tantalum nitride layer, hafnium oxynitride layer or other suitable germanium-containing layer formed by the method described herein can also be applied to a suitable thin film transistor device. For example, a metal oxide thin film transistor element. Amorphous germanium layer, tantalum oxide layer, tantalum nitride layer, niobium oxynitride layer or other suitable germanium-containing layer, etc., can also be used for photodiodes, semiconductor diodes, light-emitting diodes (LEDs) ),organic Light-emitting diodes (OLEDs) or other display applications. The amorphous germanium layer, the tantalum oxide layer, the tantalum nitride layer, and the niobium oxynitride layer provide high film quality and stability and low film leakage with the lowest hydrogen content, thereby effectively strengthening the transistor. The electrical performance of the component. It is worth noting that in addition to the applications mentioned above, the amorphous germanium layer can be used for other suitable components.

一低溫多晶矽薄膜電晶體元件150之一示範性實施例係繪示於第1圖中。低溫多晶矽薄膜電晶體元件為具有源極區109a、通道區109c及汲極區109b形成於一透光基板(light transparent substrate)102上的金屬氧化物半導體元件,透光基板102具有或不具有可選擇性的一光透介電層104設置於其上。源極區109a、通道區109c及汲極區109b普遍地由一初始沉積時為非晶矽(a-Si)層,之後經熱處理處理(例如退火)以形成多晶矽層的層來形成。源極區109a、通道區109c及汲極區109b可藉由圖案化透光基板102上之區域,並對初始沉積之非晶矽層進行離子摻雜來成形,該非晶矽層於之後會經熱處理以形成多晶矽層。一閘極介電層106接著沉積於多晶矽沉積層之上,以阻隔一閘極電極114與通道區109c、源極區109a及汲極區109b。閘極電極114係形成於閘極介電層106之頂部上。一絕緣層112及元件連結部(device connections)110a、110b係接著被形成,通過絕緣層112,以允許薄膜電晶體元件150之控制。 An exemplary embodiment of a low temperature polysilicon thin film transistor element 150 is shown in FIG. The low temperature polycrystalline germanium thin film transistor element is a metal oxide semiconductor device having a source region 109a, a channel region 109c and a drain region 109b formed on a light transparent substrate 102. The transparent substrate 102 has or does not have A selective light transmissive dielectric layer 104 is disposed thereon. The source region 109a, the channel region 109c, and the drain region 109b are generally formed by a layer of amorphous germanium (a-Si) which is initially deposited, and then heat treated (for example, annealed) to form a layer of a polysilicon layer. The source region 109a, the channel region 109c, and the drain region 109b may be formed by patterning a region on the transparent substrate 102 and ion doping the initially deposited amorphous germanium layer. Heat treatment to form a polycrystalline germanium layer. A gate dielectric layer 106 is then deposited over the polysilicon layer to block a gate electrode 114 and the channel region 109c, the source region 109a, and the drain region 109b. A gate electrode 114 is formed on top of the gate dielectric layer 106. An insulating layer 112 and device connections 110a, 110b are then formed through the insulating layer 112 to allow control of the thin film transistor element 150.

低溫多晶矽薄膜電晶體元件150之效能與沉積形成金 屬氧化物半導體結構之薄膜的品質相關。金屬氧化物半導體元件的關鍵效能元素是多晶矽通道層108、閘極介電層106及多晶矽通道層/閘極介電層介面的品質。多晶矽通道層108的品質在近幾年來備受注意。如以上所討論的,多晶矽通道層108係初始地形成為非晶矽層,接著加熱至約攝氏450度或更高溫,以進行脫氫處理(dehydrogenation process),自非晶矽層中除去氫。經過脫氫處理後,可進行一雷射退火處理,以將非晶矽層轉變成多晶矽層。接著,一閘極絕緣層(gate insulator)或其他合適的層可形成於其上,以完成元件結構。 The performance and deposition of low temperature polycrystalline germanium thin film transistor component 150 The quality of the film belonging to the oxide semiconductor structure is related. The key performance elements of the metal oxide semiconductor device are the quality of the polysilicon channel layer 108, the gate dielectric layer 106, and the polysilicon channel layer/gate dielectric layer interface. The quality of the polysilicon channel layer 108 has received much attention in recent years. As discussed above, the polysilicon channel layer 108 is initially formed as an amorphous germanium layer, which is then heated to about 450 degrees Celsius or higher for a dehydrogenation process to remove hydrogen from the amorphous germanium layer. After the dehydrogenation treatment, a laser annealing treatment may be performed to convert the amorphous germanium layer into a polycrystalline germanium layer. Next, a gate insulator or other suitable layer may be formed thereon to complete the device structure.

在形成多晶矽通道層108之前,非晶矽層中過量的氫元素(例如一濃度過高的氫含量)可能穿透進入鄰近的閘極介電層106或其他鄰近層中,而導致漏電流(current leakage)或其他形式的元件失效(device failure)。非晶矽層可藉由合適之氣相沉積製程形成,例如是電漿輔助化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition,PECVD)。 Excess hydrogen elements (eg, an excessively high hydrogen content) in the amorphous germanium layer may penetrate into the adjacent gate dielectric layer 106 or other adjacent layers before the formation of the polysilicon channel layer 108, resulting in leakage current ( Current leakage) or other form of device failure. The amorphous germanium layer can be formed by a suitable vapor deposition process, such as Plasma Enhanced Chemical Vapor Deposition (PECVD).

第2圖為一PECVD腔室200之一實施例的剖面示意圖,非晶矽層或其他含矽層(例如矽氧化物層)可在PECVD腔室200中形成。一合適的PECVD腔室可由位於加州聖塔克拉拉的應用材料公司(Applied Materials,Inc.)取得。可以預期的是,本發明可使用包括自其他製造商處取得之其他的沉積腔室來實施。 2 is a cross-sectional view of one embodiment of a PECVD chamber 200 in which an amorphous germanium layer or other germanium containing layer (eg, a tantalum oxide layer) can be formed in the PECVD chamber 200. A suitable PECVD chamber is available from Applied Materials, Inc., located in Santa Clara, California. It is contemplated that the invention can be practiced using other deposition chambers including those obtained from other manufacturers.

腔室200通常包括腔壁202、腔底204及腔蓋212。氣體分配板210及基板支撐組件230定義出一處理空間206。處理空間206係由穿過腔壁而形成之一開口208與 外界相通,使得一基板102可被運送進入和移出腔室200。 The chamber 200 generally includes a chamber wall 202, a cavity bottom 204, and a chamber cover 212. Gas distribution plate 210 and substrate support assembly 230 define a processing space 206. The processing space 206 is formed by passing through a cavity wall to form an opening 208 with The outside is communicated such that a substrate 102 can be transported into and out of the chamber 200.

該基板支撐組件230包括一基板接收表面232,用以支撐基板102於其上。基板接收表面232的尺寸通常等於或稍大於基板102。一主幹(stem)234將基板支撐組件230耦接至一抬升系統(lift system)236,抬升系統236於基板轉移及處理的位置之間升高和降低基板支撐組件230。當進行處理時,為防止在基板102的邊緣沉積,一遮蔽框(shadow frame)233可以可選擇性地放置在基板102之周圍上。抬銷(lift pin)238係可動式的設置穿過基板支撐組件230,用於在基板102移入與移出的過程中,使基板102自基板接收表面232分離。基板支撐組件230也可包含加熱及/或冷卻元件239,用以將基板支撐組件230維持於一要求的溫度。基板支撐組件230也可包括射頻返回帶(RF return strap)231,環繞基板支撐組件230周圍,以縮短射頻返回路徑(RF return path)。 The substrate support assembly 230 includes a substrate receiving surface 232 for supporting the substrate 102 thereon. The substrate receiving surface 232 is typically equal in size or slightly larger than the substrate 102. A stem 234 couples the substrate support assembly 230 to a lift system 236 that raises and lowers the substrate support assembly 230 between the substrate transfer and processing locations. To prevent deposition on the edge of the substrate 102 when processing is performed, a shadow frame 233 may be selectively placed on the periphery of the substrate 102. A lift pin 238 is movably disposed through the substrate support assembly 230 for separating the substrate 102 from the substrate receiving surface 232 during the movement and removal of the substrate 102. The substrate support assembly 230 can also include heating and/or cooling elements 239 for maintaining the substrate support assembly 230 at a desired temperature. The substrate support assembly 230 can also include an RF return strap 231 around the substrate support assembly 230 to reduce the RF return path.

氣體分配板210係在其周圍藉由一懸吊部214耦接至腔室200之腔蓋212或腔壁202。氣體分配板210亦可藉由一或多個中央支撐件(center support)216耦接至腔蓋212,以幫助防止氣體分配板210之下垂及/或控制該氣體分配板210之直線度(straightness)/曲率(curvature)。在一實施例中,氣體分配板210具有不同尺寸的不同配置。在一示範實施例中,氣體分配板210具有一四邊形之下游表面(downstream surface)250。下游表面250具有多個孔洞(aperture)211形成於其中,該些孔洞211面對著設置在基板支撐組件230上之基板102之一上表面218。孔洞211 橫跨氣體分配板210而可具有不同的形狀、數量、密度、尺寸及分佈。 The gas distribution plate 210 is coupled around it to the chamber cover 212 or chamber wall 202 of the chamber 200 by a suspension portion 214. The gas distribution plate 210 can also be coupled to the chamber cover 212 by one or more center supports 216 to help prevent the gas distribution plate 210 from sagging and/or controlling the straightness of the gas distribution plate 210 (straightness) ) / curvature (curvature). In an embodiment, the gas distribution plate 210 has different configurations of different sizes. In an exemplary embodiment, the gas distribution plate 210 has a quadrature downstream surface 250. The downstream surface 250 has a plurality of apertures 211 formed therein that face an upper surface 218 of the substrate 102 disposed on the substrate support assembly 230. Hole 211 There may be different shapes, numbers, densities, sizes, and distributions across the gas distribution plate 210.

一氣體源(gas source)220耦接至腔蓋212,以通過腔蓋212提供氣體,然後再通過形成於氣體分配板210的孔洞211,到達處理空間206。一真空泵209係耦接至腔室200,以維持處理空間206中的空氣於一要求的壓力。 A gas source 220 is coupled to the chamber cover 212 to provide gas through the chamber cover 212 and then through the aperture 211 formed in the gas distribution plate 210 to the processing space 206. A vacuum pump 209 is coupled to the chamber 200 to maintain the air in the processing space 206 at a desired pressure.

一射頻功率源(RF power source)222係耦接至腔蓋212及/或氣體分配板210,以提供一射頻功率,該射頻功率於氣體分配板210與基板支撐組件230之間產生一電場,使得電漿可由氣體分配板210與基板支撐組件230之間的氣體產生。可以於一或多個射頻頻率施加射頻功率,舉例來說,可施加頻率介於約0.3百萬赫(MHz)與約200 MHz之間的射頻功率。在一實施例中,射頻功率係被提供於13.56 MHz之頻率。 An RF power source 222 is coupled to the chamber cover 212 and/or the gas distribution plate 210 to provide an RF power that generates an electric field between the gas distribution plate 210 and the substrate support assembly 230. The plasma can be generated from a gas between the gas distribution plate 210 and the substrate support assembly 230. RF power can be applied at one or more RF frequencies, for example, RF power having a frequency between about 0.3 megahertz (MHz) and about 200 MHz can be applied. In one embodiment, the RF power is provided at a frequency of 13.56 MHz.

一遠距電漿源224,像是電感耦合式遠距電漿源(inductively coupled remote plasma source),也可耦接於氣體源與背板之間。在處理基板的製程間隔中,一清洗用氣體可用於遠距電漿源224中被激發,以遠距離地提供用來清洗腔室組件的電漿。清洗氣體可更藉由射頻功率源222提供至氣體分配板210的射頻功率來激發。合適的清洗氣體包括但不限於三氟化氮(NF3)、氟氣(F2)及六氟化硫(SF6)。 A remote plasma source 224, such as an inductively coupled remote plasma source, can also be coupled between the gas source and the backplate. During the process interval in which the substrate is processed, a purge gas can be used in the remote plasma source 224 to be excited to provide plasma for cleaning the chamber assembly over long distances. The purge gas can be excited by the RF power supplied to the gas distribution plate 210 by the RF power source 222. Suitable purge gases include, but are not limited to, nitrogen trifluoride (NF 3 ), fluorine (F 2 ), and sulfur hexafluoride (SF 6 ).

在一實施例中,可於腔室200中處理之基板102可具有10,000平方公分(cm2)或更大之表面積,例如40,000 cm2或更大,例如約55,000 cm2或是更大。可以理解的是,經 過處理後的基板可被切臨以形成較小的元件。 In an embodiment, the substrate 102 that can be processed in the chamber 200 can have a surface area of 10,000 square centimeters (cm 2 ) or greater, such as 40,000 cm 2 or greater, such as about 55,000 cm 2 or greater. It will be appreciated that the processed substrate can be cut to form smaller components.

在一實施例中,加熱及/或冷卻元件239可用於在沉積過程中,提供基板支撐組件230約為攝氏400度或是更低之一溫度,舉例來說介於約攝氏100度與約攝氏400度之間,或介於約攝氏150度與約攝氏300度之間,例如約攝氏200度。於沉積過程中,設置於基板接收表面232上之基板102之上表面218及氣體分配板210之間的間隙(spacing),通常可於約400密耳(mils)與約1200密耳之間變化,例如於約400密耳與約800密耳之間,或其他用以提供所要的沉積結果而選擇的基板102及氣體分配板210之間的距離。在使用一凹面之下游表面氣體分配板210之一示範實施例中,氣體分配板210中央部分之邊緣與基板接收表面232之間的間隙介於約400密耳與約1400密耳之間,氣體分配板210的角落與基板接收表面232的間隙介於約300密耳與約1200密耳之間。 In one embodiment, the heating and/or cooling element 239 can be used to provide a substrate support assembly 230 at a temperature of about 400 degrees Celsius or less during deposition, for example, between about 100 degrees Celsius and about Celsius. Between 400 degrees, or between about 150 degrees Celsius and about 300 degrees Celsius, for example about 200 degrees Celsius. During the deposition process, the spacing between the upper surface 218 of the substrate 102 and the gas distribution plate 210 disposed on the substrate receiving surface 232 can typically vary between about 400 mils and about 1200 mils. For example, between about 400 mils and about 800 mils, or other distance between the substrate 102 and the gas distribution plate 210 selected to provide the desired deposition results. In an exemplary embodiment using a concave downstream surface gas distribution plate 210, the gap between the edge of the central portion of the gas distribution plate 210 and the substrate receiving surface 232 is between about 400 mils and about 1400 mils. The gap between the corner of the distribution plate 210 and the substrate receiving surface 232 is between about 300 mils and about 1200 mils.

第3圖繪示一沉積製程300之一實施例的流程圖,製程300可於如第2圖所繪示的腔室200或其他適合的處理腔室中實施。該沉積製程300繪示一種沉積可用於薄膜電晶體元件或二極體元件之非晶矽層或其他適合的含矽層的方法。在一實施例中,含矽層可單獨或與任何其他適合的薄膜結合使用,以提高於薄膜電晶體元件或二極體元件的電性特性及表現。在一特定的實施例中,所述之含矽層為一非晶矽層,可接著在之後經由熱處理形成一多晶矽層。 FIG. 3 illustrates a flow diagram of one embodiment of a deposition process 300 that may be implemented in a chamber 200 or other suitable processing chamber as depicted in FIG. The deposition process 300 illustrates a method of depositing an amorphous germanium layer or other suitable germanium containing layer useful for thin film transistor elements or diode elements. In one embodiment, the ruthenium containing layer can be used alone or in combination with any other suitable film to enhance the electrical properties and performance of the thin film transistor component or the diode component. In a particular embodiment, the germanium-containing layer is an amorphous germanium layer, which can then be subsequently formed into a polysilicon layer via heat treatment.

製程300始於步驟302,運送如第4A圖所繪示之基 板102至一處理腔室中,例如第2圖所繪示之PECVD腔室200。基板102可具有可選擇性之介電層104設置於其上。值得注意的是,該基板102可具有預先形成於其上的薄膜、結構或是層的不同組合,以有助於在基板102上形成不同元件結構。在不存在介電層104的實施例中,非晶矽層可直接成形於基板102上。 Process 300 begins at step 302 by transporting the base as depicted in Figure 4A. The plate 102 is in a processing chamber, such as the PECVD chamber 200 illustrated in FIG. The substrate 102 can have an optional dielectric layer 104 disposed thereon. It is noted that the substrate 102 can have different combinations of films, structures or layers previously formed thereon to facilitate the formation of different component structures on the substrate 102. In embodiments where dielectric layer 104 is absent, the amorphous germanium layer can be formed directly onto substrate 102.

在一實施例中,基板102可為玻璃基板、塑膠基板、聚合物基板、金屬基板、單片基板(singled substrate)、連續式基板(roll-to-roll substrate)或其他適合讓薄膜電晶體形成於其上之透明基板的任何一種。 In an embodiment, the substrate 102 can be a glass substrate, a plastic substrate, a polymer substrate, a metal substrate, a single-sided substrate, a roll-to-roll substrate, or other suitable for forming a thin film transistor. Any of the transparent substrates thereon.

在步驟304,一混合氣體係通過氣體分配板210被提供至處理腔室中,以沉積一非晶矽層402於基板102上,如第4B圖所繪示。當提供混合氣體至處理腔室中以沉積非晶矽層402時,該混合氣體可包括一矽基氣體(silicon-based gas)、一惰性氣體,且實質上不含氫氣(H2)。「實質上不含氫氣」一詞係用以指示不會使用氫氣作為直接來源以形成該混合氣體。在惰性氣體及/或矽基氣體中可存在著極微量的氫氣(trace amount of hydrogen)。合適的矽基氣體包括但不限定於矽烷(SiH4)、二矽烷(Si2H6)、四氯化矽(SiF4)、四乙氧基矽烷(TEOS)、四氯化矽(SiCl4)、二氯矽烷(SiH2Cl2)及其組合。適合的惰性氣體的例子包括氦、氬、氖或氪等等。在一實施例中,矽基氣體為矽烷(SiH4),惰性氣體為氬氣。 At step 304, a gas mixture system is supplied to the processing chamber through a gas distribution plate 210 to deposit an amorphous germanium layer 402 on the substrate 102, as depicted in FIG. 4B. When a mixed gas is supplied into the processing chamber to deposit the amorphous germanium layer 402, the mixed gas may include a silicon-based gas, an inert gas, and substantially free of hydrogen (H2). The term "substantially free of hydrogen" is used to indicate that hydrogen is not used as a direct source to form the mixed gas. A trace amount of hydrogen may be present in the inert gas and/or the ruthenium-based gas. Suitable sulfhydryl gases include, but are not limited to, decane (SiH 4 ), dioxane (Si 2 H 6 ), ruthenium tetrachloride (SiF 4 ), tetraethoxy decane (TEOS), ruthenium tetrachloride (SiCl 4 ) ), dichlorodecane (SiH 2 Cl 2 ), and combinations thereof. Examples of suitable inert gases include helium, argon, neon or xenon, and the like. In one embodiment, the silicon based gas Silane (SiH 4), the inert gas is argon.

矽基氣體及惰性氣體係以一預定氣體流率(gas flow ratio)來提供。惰性氣體與矽基氣體之預定氣體流率比例可 有助於使非晶矽層之沉積中,包含於薄膜中的氫原子數量為最小。在一實施例中,係以一預定比例提供矽基氣體及惰性氣體至處理腔室中,該預定比例例如超過1:20。在一實施例中,惰性氣體(例如氬氣)比矽基氣體(例如矽烷)之比例(R)係控制在大約高於20(氬氣/矽烷),舉例來說超過50,例如介於約60與200之間,在另一個例子中,介於約70與約100之間,例如約75。或者,提供至處理腔室的矽基氣體及惰性氣體可依據每單位基板表面積(或大約等值的基板支撐表面)之體積流率來提供。在一實施例中,可提供介於約0.042單位時間標準毫升/平方公分(sccm/cm2)與約0.31 sccm/cm2之間的矽烷氣體(SiH4)至處理腔室中,同時,可提供流率介於約0.55 sccm/cm2與約3.29 sccm/cm2之間的惰性氣體至處理腔室中。因此,惰性氣體對矽基氣體的每單位基板表面之體積流率比例介於約1.8:1與約79:1之間。換句話說,混合氣體之惰性氣體的每單位基板表面積之體積流率為矽基氣體的每單位基板表面積之體積流率的約1.8倍至約79倍。在一實施例中,該矽基氣體為矽烷,該惰性氣體為氬氣。 The ruthenium based gas and inert gas system are provided at a predetermined gas flow ratio. The predetermined gas flow rate ratio of the inert gas to the ruthenium based gas can help minimize the amount of hydrogen atoms contained in the film during deposition of the amorphous ruthenium layer. In one embodiment, the ruthenium-based gas and the inert gas are supplied to the processing chamber at a predetermined ratio, for example, in excess of 1:20. In one embodiment, the ratio (R) of the inert gas (eg, argon) to the sulfhydryl-based gas (eg, decane) is controlled to be greater than about 20 (argon/decane), for example, greater than 50, such as between about Between 60 and 200, in another example, between about 70 and about 100, such as about 75. Alternatively, the sulfhydryl gas and inert gas provided to the processing chamber may be provided in accordance with the volumetric flow rate per unit substrate surface area (or approximately equivalent substrate support surface). In one embodiment, decane gas (SiH 4 ) between about 0.042 unit time standard cc/cm 2 (sccm/cm 2 ) and about 0.31 sccm/cm 2 may be provided into the processing chamber, and An inert gas having a flow rate between about 0.55 sccm/cm 2 and about 3.29 sccm/cm 2 is supplied to the processing chamber. Therefore, the volumetric flow rate ratio of the inert gas to the ruthenium-based gas per unit substrate surface is between about 1.8:1 and about 79:1. In other words, the volumetric flow rate per unit substrate surface area of the inert gas of the mixed gas is about 1.8 times to about 79 times the volume flow rate per unit substrate surface area of the cerium-based gas. In one embodiment, the sulfhydryl gas is decane and the inert gas is argon.

提供於混合氣體中之惰性氣體(例如氬氣)被認為是相較於提供於矽基氣體(例如矽烷氣體)中之矽原子及氫原子具有相對較大的分子量。當於製程中提供混合氣體時,混合氣體中之該氬原子可幫助除去矽-氫之弱鍵結及懸浮鍵及/或矽層中弱的矽-矽鍵,據此,可允許矽層中之矽原子形成強的矽-矽鍵,而非形成自矽烷氣體的矽-氫鍵。如上所敘述,強的矽-矽鍵提升了薄膜純度及矽的鍵能,進而改 善形成於非晶矽層402的薄膜品質及純度。此外,隨著氬原子幫助形成強的和健全的矽鍵並除去雜質,不只是矽層中的缺陷減少,非矽晶層亦可獲得良好的均勻性,因而可減少不理想的隨機晶界(random grain boundary)及晶界缺陷。此外,藉由使用氬氣稀釋而不使用傳統氫氣稀釋,於沉積製程中可最小化或消除氫原子的提供,進而減少在所產生的非晶矽層402中形成氫元素的可能性。氬氣稀釋沉積製程亦被認為也可提供一良好的沉積速率,例如每分鐘超過300埃(Å),從而提升製造的產量(throughput of manufacture)。 The inert gas (e.g., argon) supplied to the mixed gas is considered to have a relatively large molecular weight compared to the helium atom and the hydrogen atom supplied to the sulfhydryl-based gas (e.g., decane gas). When a mixed gas is supplied in the process, the argon atoms in the mixed gas can help remove the weak bond of the hydrazine-hydrogen and the weak 矽-矽 bond in the enthalpy layer and/or the ruthenium layer, thereby allowing the ruthenium layer to be The helium atom forms a strong 矽-矽 bond instead of a 矽-hydrogen bond formed from a decane gas. As described above, the strong 矽-矽 bond enhances the purity of the film and the bond energy of the ruthenium. Good film quality and purity formed in the amorphous germanium layer 402. In addition, as the argon atoms help to form strong and robust ruthenium bonds and remove impurities, not only the defects in the ruthenium layer are reduced, but also the non-crystal layer can obtain good uniformity, thereby reducing undesirable random grain boundaries ( Random grain boundary) and grain boundary defects. In addition, by using argon dilution without conventional hydrogen dilution, the supply of hydrogen atoms can be minimized or eliminated during the deposition process, thereby reducing the likelihood of hydrogen formation in the resulting amorphous germanium layer 402. The argon dilution deposition process is also believed to provide a good deposition rate, such as more than 300 angstroms per minute (Å), thereby increasing the throughput of manufacture.

於沉積製程中可控制數種製程參數。沉積過程中,可施加一射頻電源功率(RF source power)以維持電漿。在一實施例中,射頻電源功率密度(RF source power density)可被提供在介於約10毫瓦/平方公分(mWatt/cm2)與約200毫瓦/平方公分之間。或者,一超高頻能量(VHF power)可用於提供高達約27 MHz及約200 MHz之間的頻率。處理壓力係維持在約0.1托耳(Torr)與約10托耳之間,例如介於約0.5托耳與約5托耳之間,例如介於約0.8托耳與約2托耳之間。基板至氣體分佈板組件的間隙可依據基板尺寸來控制。在一實施例中,對於大於1平方公尺之一基板,處理間隙係被控制在約400密耳與約1200密耳之間,例如介於約400密耳與約850密耳之間,例如580密耳。基板溫度可被控制在約攝氏150度與約攝氏500度之間,例如約攝氏370度。 Several process parameters can be controlled during the deposition process. During the deposition process, an RF source power can be applied to maintain the plasma. In one embodiment, the RF source power density can be provided between about 10 milliwatts per square centimeter (mWatt/cm 2 ) and about 200 milliwatts per square centimeter. Alternatively, a VHF power can be used to provide frequencies up to about 27 MHz and about 200 MHz. The process pressure is maintained between about 0.1 Torr and about 10 Torr, such as between about 0.5 Torr and about 5 Torr, such as between about 0.8 Torr and about 2 Torr. The gap of the substrate to the gas distribution plate assembly can be controlled depending on the substrate size. In one embodiment, for a substrate greater than one square meter, the processing gap is controlled between about 400 mils and about 1200 mils, such as between about 400 mils and about 850 mils, such as 580 mils. The substrate temperature can be controlled between about 150 degrees Celsius and about 500 degrees Celsius, such as about 370 degrees Celsius.

在一實施例中,可使用一相對低之射頻功率,例如低 於1500瓦(Watts)或少於100毫瓦/平方公分。在沉積過程中使用較低的射頻功率,相信這有助於形成具有良好之均勻性控制的非晶矽層402。並且,使用相對較低之射頻功率相信可減少可能由惰性氣體產生之濺鍍效應(sputtering effect),從而幫助於一相對溫和的電漿環境中沉積非晶矽層402,而形成具有良好的均勻性及表面粗糙度控制的非晶矽層402。 In an embodiment, a relatively low RF power can be used, such as low At 1500 watts (Watts) or less than 100 mW/cm 2 . The use of lower RF power during deposition is believed to help form an amorphous germanium layer 402 with good uniformity control. Moreover, the use of relatively low RF power is believed to reduce the sputtering effect that may be generated by the inert gas, thereby helping to deposit the amorphous germanium layer 402 in a relatively mild plasma environment, resulting in good uniformity. Amorphous and surface roughness controlled amorphous germanium layer 402.

步驟306中,在非晶矽層402形成於基板102上之後,可進行一後期脫氫烘烤處理(post dehydrogenation bake process),以自非晶矽層402除去氫氣,如第4C圖所繪示。經過後期脫氫烘烤處理後,存在於非晶矽層402中的氫含量大多數可被除去,以形成一脫氫非晶矽層(dehydrogenated amorphous silicon layer)404,如第4C圖所繪示。如以上所討論的,當藉由使用例如氬氣之一惰性氣體,取代氫氣做為稀釋氣體之一實質上不含氫的混合氣體以形成脫氫非晶矽層404時,後期脫氫烘烤處理可以相對短的時間進行,例如少於5分鐘或是可選擇性地取消。 In step 306, after the amorphous germanium layer 402 is formed on the substrate 102, a post dehydrogenation bake process may be performed to remove hydrogen from the amorphous germanium layer 402, as shown in FIG. 4C. . After the late dehydrogenation baking treatment, the hydrogen content present in the amorphous germanium layer 402 can be mostly removed to form a dehydrogenated amorphous silicon layer 404, as shown in FIG. 4C. . As discussed above, when dehydrogenated amorphous germanium layer 404 is formed by using a gas such as an inert gas such as argon instead of hydrogen as a diluent gas which is substantially free of hydrogen, late dehydrogenation baking Processing can be performed in relatively short periods of time, such as less than 5 minutes or can be selectively cancelled.

在一實施例中,後期脫氫烘烤處理可於非晶矽層402沉積之處理腔室原處(in-situ)進行處理。後期脫氫烘烤處理可加熱基板102至超過攝氏400度的溫度,例如介於約攝氏450度與約攝氏550度之間,以幫助蒸發氫元素,形成脫氫非晶矽層404。 In one embodiment, the post-dehydrogenation bake process can be processed in the in-situ of the processing chamber where the amorphous germanium layer 402 is deposited. The late dehydrogenation bake process can heat the substrate 102 to a temperature in excess of 400 degrees Celsius, such as between about 450 degrees Celsius and about 550 degrees Celsius to help vaporize the hydrogen element to form the dehydrogenated amorphous germanium layer 404.

在非晶矽層402的氫含量不高的實施例中,如有需要,可刪去於步驟306進行之後期脫氫烘烤處理。 In the embodiment where the hydrogen content of the amorphous germanium layer 402 is not high, the subsequent dehydrogenation baking treatment may be omitted in step 306 if necessary.

步驟308中,在經過後期脫氫烘烤處理後,係進行一 雷射退火處理,以將脫氫非晶矽層404轉變成多晶矽層406,如第4D圖所繪示。雷射處理幫助脫氫非晶矽層404結晶形成多晶矽層406。在雷射退火處理過程中提供之熱能幫助非晶矽層402之晶粒成長成大尺寸的結晶晶粒,形成多晶矽層406。在一實施例中,用於結晶非晶矽層404之雷射退火處理為一準分子雷射退火處理。準分子雷射退火處理可熱處理基板至約攝氏100度與約攝氏1500度之間的溫度。 In step 308, after the post-dehydrogenation baking treatment, the system performs one A laser annealing treatment is performed to convert the dehydrogenated amorphous germanium layer 404 into a polycrystalline germanium layer 406, as depicted in FIG. 4D. The laser treatment assists in decrystallization of the dehydrogenated amorphous germanium layer 404 to form a polycrystalline germanium layer 406. The thermal energy provided during the laser annealing process helps the grains of the amorphous germanium layer 402 to grow into large-sized crystalline grains, forming a polycrystalline germanium layer 406. In one embodiment, the laser annealing process for crystallizing the amorphous germanium layer 404 is a quasi-molecular laser annealing process. The excimer laser annealing treatment heat treats the substrate to a temperature between about 100 degrees Celsius and about 1500 degrees Celsius.

經過雷射退火處理後,脫氫非晶矽層404轉變成多晶矽層406,多晶矽層406大部分之結晶方向在於(111)面,少部分的方向在於(220)面。當多晶矽層406形成要求的結晶,可獲得一高的光/暗導導電度比值(photo/dark conductivity ratio),並改善多晶矽層406之整體電性性質。 After the laser annealing treatment, the dehydrogenated amorphous germanium layer 404 is transformed into a polycrystalline germanium layer 406. The majority of the crystalline germanium layer 406 has a crystal orientation of the (111) plane and a small portion of the (220) plane. When the polysilicon layer 406 forms the desired crystal, a high photo/dark conductivity ratio can be obtained and the overall electrical properties of the polysilicon layer 406 can be improved.

在脫氫非晶矽層404轉變成多晶矽層406後,可進行圖案化製程、離子植入或其他沉積製程以形成源極區和汲極區、閘極介電層及源極和汲極電極層,進而完成薄膜電晶體元件結構,如第1圖所示及以上配合第1圖討論之內容。 After the dehydrogenation amorphous germanium layer 404 is converted into the poly germanium layer 406, a patterning process, ion implantation or other deposition process may be performed to form the source and drain regions, the gate dielectric layer, and the source and drain electrodes. The layer, and thus the structure of the thin film transistor element, is as shown in Fig. 1 and discussed above in conjunction with Fig. 1.

如上所敘述,含矽層可用於製造薄膜電晶體元件中的其他層。第5A圖為根據本發明另一實施例之一薄膜電晶體元件500的剖面示意圖。薄膜電晶體元件500包括一基板502,基板502具有一閘極電極層504形成於其上。基板502可包括玻璃,但可考慮其他基板材料,例如聚合物系的基板(polymer based substrate)及軟性基板(flexible substrate)。在一實施例中,閘極電極層504可由任何合適 的金屬材料製造而成,例如銦錫氧化物(ITO)、銦鋅氧化物(IZO)、銦錫鋅氧化物(ITZO)、鋁(Al)、鎢(W)、鉻(Cr)、鉭(Ta)、鉬(Mo)、銅(Cu)、鈦(Ti)、其合金或其組合。 As described above, the ruthenium containing layer can be used to make other layers in the thin film transistor element. Figure 5A is a cross-sectional view of a thin film transistor device 500 in accordance with another embodiment of the present invention. The thin film transistor element 500 includes a substrate 502 having a gate electrode layer 504 formed thereon. The substrate 502 may include glass, but other substrate materials such as a polymer based substrate and a flexible substrate may be considered. In an embodiment, the gate electrode layer 504 can be any suitable Made of metal materials such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum (Al), tungsten (W), chromium (Cr), tantalum ( Ta), molybdenum (Mo), copper (Cu), titanium (Ti), alloys thereof, or combinations thereof.

在基板502及閘極電極層504之上,係形成一閘極絕緣層506。適合於閘極絕緣層506之材料可為矽氧化物(SiO2)、氮氧化矽(SiON)、矽氮化物(SiN)或其組合等等。閘極絕緣層506可為單層、複合層、雙層、多層或前述之其他種組合的形式,視需求而定。在一實施例中,閘極絕緣層506可具有矽氮化物層沉積於矽氧化物上(或者顛倒過來),作為基板502上一雙層結構(dual layer),如虛線520所示。或者,閘極絕緣層506可為一矽氧化物單層或一矽氮化物單層,視需求而定。該矽氧化物層及矽氮化物層(或一氮氧化矽層)可由如上所述之製程300製造而成。矽氧化物及/或矽氮化物層可藉由提供具有矽基氣體及例如氬氣之惰性氣體,且不具氫之一混合氣體來製造。 A gate insulating layer 506 is formed over the substrate 502 and the gate electrode layer 504. Materials suitable for the gate insulating layer 506 may be tantalum oxide (SiO 2 ), bismuth oxynitride (SiON), tantalum nitride (SiN), combinations thereof, and the like. The gate insulating layer 506 can be in the form of a single layer, a composite layer, a double layer, multiple layers, or other combinations of the foregoing, as desired. In an embodiment, the gate insulating layer 506 may have a tantalum nitride layer deposited on the tantalum oxide (or reversed) as a dual layer on the substrate 502, as indicated by the dashed line 520. Alternatively, the gate insulating layer 506 can be a tantalum oxide monolayer or a tantalum nitride monolayer, as desired. The tantalum oxide layer and the tantalum nitride layer (or a niobium oxynitride layer) may be fabricated by the process 300 as described above. The ruthenium oxide and/or ruthenium nitride layer can be produced by providing an inert gas having a ruthenium-based gas and, for example, argon, and not having a mixed gas of hydrogen.

在形成矽氧化物層的實施例中,混合氣體包含矽基氣體、含氧氣體及惰性氣體。矽基氣體之合適的例子包括但不限於矽烷(SiH4)、二矽烷(Si2H6)、四乙氧基矽烷(TEOS)、四氟化矽(SiF4)、四氯化矽(SiCl4)、二氯矽烷(SiH2Cl2)及其組合。含氧氣體合適的例子包括氧氣(O2)、一氧化二氮(N2O)、二氧化氮(NO2)、水氣(H2O)、過氧化氫(H2O2)及臭氧(O3)等等。惰性氣體合適的例子包含氦、氬、氖或氪等等。在一特定的實施例中,用於形成矽氧化物之混合氣體包含矽烷(SiH4)、氧氣(O2)及氬氣,或矽烷(SiH4)、一氧化二氮或二氧化氮(N2O或NO2)及氬氣(Ar)。然而值得注意的是, 若四乙氧基矽烷(TEOS)被用來當作矽基前驅物,則因為腔室中的總含氧量高,氧氣(O2)不被使用為佳。 In the embodiment in which the tantalum oxide layer is formed, the mixed gas contains a sulfur-based gas, an oxygen-containing gas, and an inert gas. Suitable examples of sulfhydryl gases include, but are not limited to, decane (SiH 4 ), dioxane (Si 2 H 6 ), tetraethoxydecane (TEOS), antimony tetrafluoride (SiF 4 ), antimony tetrachloride (SiCl). 4 ), dichlorodecane (SiH 2 Cl 2 ) and combinations thereof. Suitable examples of oxygen-containing gases include oxygen (O 2 ), nitrous oxide (N 2 O), nitrogen dioxide (NO 2 ), water vapor (H 2 O), hydrogen peroxide (H 2 O 2 ), and ozone. (O 3 ) and so on. Suitable examples of inert gases include helium, argon, neon or xenon, and the like. In a specific embodiment, the mixed gas used to form the cerium oxide comprises decane (SiH 4 ), oxygen (O 2 ), and argon, or decane (SiH 4 ), nitrous oxide, or nitrogen dioxide (N). 2 O or NO 2 ) and argon (Ar). It is worth noting, however, that if tetraethoxy decane (TEOS) is used as the sulfhydryl precursor, oxygen (O 2 ) is not preferred because of the high total oxygen content in the chamber.

在形成矽氮化物層之實施例中,混合氣體包括矽基氣體、含氮氣體及惰性氣體。可使用之矽基氣體及惰性氣體之種類係如上所述。含氮氣體合適的例子包括氮(N2)、一氧化二氮(N2O)、二氧化氮(NO2)、一氧化氮(NO)或氨氣(NH3)及等等。在一特定的實施例中,用於形成矽氮化物層之混合氣體包括矽烷、氮氣或氨氣、及氬氣。 In the embodiment in which the tantalum nitride layer is formed, the mixed gas includes a sulfur-based gas, a nitrogen-containing gas, and an inert gas. The types of sulfhydryl gas and inert gas that can be used are as described above. Suitable examples of the nitrogen-containing gas include nitrogen (N 2 ), nitrous oxide (N 2 O), nitrogen dioxide (NO 2 ), nitrogen monoxide (NO) or ammonia (NH 3 ), and the like. In a particular embodiment, the mixed gas used to form the tantalum nitride layer comprises decane, nitrogen or ammonia, and argon.

因為使用惰性氣體,需要的射頻功率相較於沒有使用惰性氣體時低。特別是射頻功率有可能減少達約20%。因為惰性氣體原子很重,因而增強製程中的離子轟擊(ion bombardment),所以使得射頻功率的降低成為可能。可施加之合適的射頻功率係介於約1200毫瓦/平方公分(mW/cm2)至約1300毫瓦/平方公分之間。再者,當以一特定比例提供矽基氣體及惰性氣體至腔室中時,不只是降低射頻功率需要的量,亦改善了薄膜沉積厚度的均勻性。因此,惰性氣體的添加製造出具有可重複性、可靠度且高品質的矽氧化物薄膜。在一實施例中,惰性氣體(例如氬氣)之每單位基板表面積的體積流率介於約1.05 sccm/cm2與約1.828 sccm/cm2之間,例如約1.65 sccm/cm2。含矽前驅物可以介由約0.023 sccm/cm2至約0.095 sccm/cm2之間的每單位基板表面積之體積流率提供,例如約0.025 sccm/cm2。含氧前驅物可以介於約1.05 sccm/cm2至約1.66 sccm/cm2之間的每單位基板表面積之體積流率被提供,例如約1.16 sccm/cm2。因此,惰性氣體的量為所供之矽基前 驅物的量的約11至約80倍。惰性氣體的量為所提供之含氧氣體(oxygen based gas)的量的約0.6至約1.70倍。含氧氣體的量為所提供之矽基前驅物的量的約11倍與約82倍之間,特別是約11倍與約72倍之間。 Because of the inert gas, the required RF power is lower than when no inert gas is used. In particular, RF power is likely to be reduced by up to about 20%. Since the inert gas atoms are heavy, the ion bombardment in the process is enhanced, so that the radio frequency power reduction is made possible. Suitable RF power levels that can be applied range from about 1200 milliwatts per square centimeter (mW/cm 2 ) to about 1300 milliwatts per square centimeter. Furthermore, when a bismuth-based gas and an inert gas are supplied to the chamber in a specific ratio, not only the amount required for reducing the radio frequency power but also the uniformity of the thickness of the film deposition is improved. Therefore, the addition of an inert gas produces a tantalum oxide film having reproducibility, reliability, and high quality. In one embodiment, the volumetric flow rate per unit substrate surface area of the inert gas (e.g., argon) is between about 1.05 sccm/cm 2 and about 1.828 sccm/cm 2 , such as about 1.65 sccm/cm 2 . The ruthenium containing precursor may be provided at a volumetric flow rate per unit substrate surface area between about 0.023 sccm/cm 2 to about 0.095 sccm/cm 2 , such as about 0.025 sccm/cm 2 . The oxygen-containing precursor can be provided at a volumetric flow rate per unit substrate surface area between about 1.05 sccm/cm 2 to about 1.66 sccm/cm 2 , for example about 1.16 sccm/cm 2 . Thus, the amount of inert gas is from about 11 to about 80 times the amount of sulfhydryl precursor supplied. The amount of inert gas is from about 0.6 to about 1.70 times the amount of oxygen based gas provided. The amount of oxygen-containing gas is between about 11 times and about 82 times, particularly between about 11 times and about 72 times, the amount of the sulfhydryl precursor provided.

再者,值得注意的是,依照所需,製程參數的控制可相似於上述配合製程300之步驟304所敘述之形成非矽層之製程參數來控制。 Moreover, it is worth noting that, as desired, the control of the process parameters can be controlled similarly to the process parameters of the non-layered layer described in step 304 of the above-described compounding process 300.

接著,一主動通道508可設置於閘極絕緣層506上。主動通道508可為以上述配合第3圖所敘述之製程製造而成的低溫多晶矽層(Lower Temperature Poly-Silicon layer,LTPS)。合適的摻雜物例如是N型或P型摻雜物,可依需求添加至低溫多晶矽層中,以形成主動通道508。在主動通道508之上,可選擇性的一蝕刻終止部(etch stop)514可被形成,以於源極電極510和汲極電極512形成的過程中保護主動通道508。可用於蝕刻終止部514的適合材料包括矽氧化物、矽氮化物及氮氧化矽。蝕刻終止部514可藉由相似於以上所述用於形成閘極絕緣層506的製程來形成。在一些實施例中,其他主動層511、513可先於源極和汲極電極510、512形成。主動層511、513可為P型主動層或N型主動層,例如N型含矽層或P型含矽層。 Next, an active channel 508 can be disposed on the gate insulating layer 506. The active channel 508 can be a low temperature poly-Silicon layer (LTPS) fabricated as described above in conjunction with the process described in FIG. Suitable dopants are, for example, N-type or P-type dopants that can be added to the low temperature polysilicon layer as needed to form active channels 508. Above the active channel 508, an optional etch stop 514 can be formed to protect the active channel 508 during formation of the source electrode 510 and the drain electrode 512. Suitable materials that can be used for the etch stop 514 include tantalum oxide, tantalum nitride, and hafnium oxynitride. The etch stop 514 can be formed by a process similar to that described above for forming the gate insulating layer 506. In some embodiments, other active layers 511, 513 can be formed prior to the source and drain electrodes 510, 512. The active layers 511, 513 may be a P-type active layer or an N-type active layer, such as an N-type germanium-containing layer or a P-type germanium-containing layer.

在源極和汲極電極510、512以及可選擇性的蝕刻終止部514(如果存在)之上,可形成一鈍化層518。可用於鈍化層518之合適材料包括矽氧化物、矽氮化物及氮氧化矽。在一實施例中,相似於上述之閘極絕緣層506,鈍化層518可為單層、複合層、雙層、多層或前述其他組合之 形式,視需求而定。請參照虛線516所繪示,在一實施例中,鈍化層518可具有矽氮化物層設置於矽氧化物上,或者顛倒過來,作為源極和汲極電極510、512上之一雙層結構,如虛線516所示。該矽氧化物層及矽氮化物層(或一氮氧化矽層)可由如上所述之製程300製造而成,或者,矽氧化物層及矽氮化物層也可由如上所述用於形成閘極絕緣層506的製程形成。矽氧化物及/或矽氮化物層可藉由提供一混合氣體來製造,該混合氣體具有矽基氣體及例如氬氣之惰性氣體,且不具有氫氣氣體。或者,鈍化層可為矽氧化物單層或矽氮化物單層。 A passivation layer 518 can be formed over the source and drain electrodes 510, 512 and the optional etch stop 514, if present. Suitable materials that can be used for the passivation layer 518 include tantalum oxide, tantalum nitride, and hafnium oxynitride. In one embodiment, similar to the gate insulating layer 506 described above, the passivation layer 518 can be a single layer, a composite layer, a double layer, multiple layers, or other combinations thereof. Form, depending on the needs. Referring to the dashed line 516, in an embodiment, the passivation layer 518 may have a tantalum nitride layer disposed on the tantalum oxide or reversed as a two-layer structure on the source and drain electrodes 510, 512. As indicated by the dotted line 516. The tantalum oxide layer and the tantalum nitride layer (or a niobium oxynitride layer) may be fabricated by the process 300 as described above, or the tantalum oxide layer and the tantalum nitride layer may also be used to form a gate as described above. The process of insulating layer 506 is formed. The tantalum oxide and/or tantalum nitride layer can be produced by providing a mixed gas having a sulfur-based gas and an inert gas such as argon, and having no hydrogen gas. Alternatively, the passivation layer may be a tantalum oxide single layer or a tantalum nitride single layer.

第5B圖繪示可根據本發明一實施例使用的金屬氧化物薄膜電晶體元件550的一實施例。除了主動通道508的材料不同之外,金屬氧化物薄膜電晶體元件550可具有一相似於以上配合第5A圖所述之低溫多晶矽薄膜電晶體元件500之結構。金屬氧化物薄膜電晶體元件550包含由一含金屬的層(metal containing layer)製造而成的一主動通道530。形成於金屬氧化物薄膜電晶體元件550之主動通道530的合適例子特別是包括銦鎵鋅氧化物(InGaZnO)、銦鎵鋅氮氧化物(InGaZnON)、氧化鋅(ZnO)、氮氧化鋅(ZnON)、鋅錫氧化物(ZnSnO)、鎘錫氧化物(CdSnO)、鎵錫氧化物(GaSnO)、鈦錫氧化物(TiSnO)、銅鋁氧化物(CuAlO)、鍶銅氧化物(SrCuO)、鑭銅硫氧化物(LaCuOS)、氮化鎵(GaN)、銦鎵氮化物(InGaN)、鋁鎵氮化物(AlGaN)或銦鎵鋁氮化物(InGaAlN)。在特定的一實施例中,主動通道530為一銦鎵鋅氧化物(IGZO)層。類似地,閘極絕緣層506及 鈍化層518亦可為單層、複合層、雙層、多層或前述之其他組合的形式,視需求而定。在一例中,鈍化層518及閘極絕緣層506可為一雙層結構,該雙層結構具有矽氮化物層設置於矽氧化物上。 FIG. 5B illustrates an embodiment of a metal oxide thin film transistor element 550 that can be used in accordance with an embodiment of the present invention. The metal oxide thin film transistor element 550 may have a structure similar to that of the low temperature polysilicon thin film transistor element 500 described above in connection with FIG. 5A, except that the material of the active via 508 is different. Metal oxide thin film transistor element 550 includes an active channel 530 fabricated from a metal containing layer. Suitable examples of the active channel 530 formed on the metal oxide thin film transistor element 550 include, inter alia, indium gallium zinc oxide (InGaZnO), indium gallium zinc oxide (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON). ), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), beryllium copper oxide (SrCuO), Beryllium copper oxide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN) or indium gallium aluminum nitride (InGaAlN). In a particular embodiment, active channel 530 is an indium gallium zinc oxide (IGZO) layer. Similarly, the gate insulating layer 506 and Passivation layer 518 can also be in the form of a single layer, a composite layer, a double layer, multiple layers, or other combinations of the foregoing, as desired. In one example, the passivation layer 518 and the gate insulating layer 506 can be a two-layer structure having a tantalum nitride layer disposed on the tantalum oxide.

當由氬稀釋氣體製造之實質上不含氫之矽氧化物層用於金屬氧化物薄膜電晶體元件中時,金屬氧化物薄膜電晶體元件可具有改善的電性表現。舉例來說,啟動電壓Von(turn on voltage)及次臨界電壓擺幅(Sub-threshold voltage swing value,S值)兩者均顯著地降低。在一例中,Von從約-5.5 V降低至約-0.25V。S值從約0.7 V/decade降低至約0.4 V/decade。開啟電流(Ion)從約3.3×10-4安培(A)降低至約1.4×10-4 A。關閉電流(Ioff)從約4.8×10-12 A降低至約1.4×10-13 A。載子移動率(Mo)從約9.8 cm2/(V.s)增加至約9.9 cm2/(V.s)。 When a substantially hydrogen-free tantalum oxide layer made of an argon dilution gas is used in a metal oxide thin film transistor element, the metal oxide thin film transistor element can have improved electrical performance. For example, both the startup voltage V on (turn on voltage) and the sub-threshold voltage swing value (S value) are significantly reduced. In one example, V on is reduced from about -5.5 V to about -0.25 V. The S value is reduced from approximately 0.7 V/decade to approximately 0.4 V/decade. On-current (I on) decreased from about 3.3 × 10 -4 amperes (A) to about 1.4 × 10 -4 A. The shutdown current (I off ) is reduced from about 4.8 x 10 -12 A to about 1.4 x 10 -13 A. The carrier mobility (Mo) increased from about 9.8 cm 2 /(V.s) to about 9.9 cm 2 /(V.s).

第6圖繪示可依據本發明一實施例使用之金屬氧化物薄膜電晶體元件600的一實施例。金屬氧化物薄膜電晶體元件600可具有相似於以上配合第5B圖所述之金屬氧化物薄膜電晶體元件550之結構。金屬氧化物薄膜電晶體元件600亦包括由一含金屬的層製造而成的一主動通道530。形成於金屬氧化物薄膜電晶體元件600之主動通道530的合適例子特別是包括銦鎵鋅氧化物(InGaZnO)、銦鎵鋅氮氧化物(InGaZnON)、氧化鋅(ZnO)、氮氧化鋅(ZnON)、鋅錫氧化物(ZnSnO)、鎘錫氧化物(CdSnO)、鎵錫氧化物(GaSnO)、鈦錫氧化物(TiSnO)、銅鋁氧化物(CuAlO)、鍶銅氧化物(SrCuO)、鑭銅硫氧化物(LaCuOS)、氮化鎵 (GaN)、銦鎵氮化物(InGaN)、鋁鎵氮化物(AlGaN)或銦鎵鋁氮化物(InGaAlN)。此外,一上層介面(upper interface)540及一下層介面(lower interface)542與主動通道530接觸,並具有實質上不含氫之薄膜特性。上層介面540及下層介面542由不含氫之材料製成。舉例來說,下層介面542係形成於主動通道530及閘極絕緣層506之間。在這個情況下,閘極絕緣層506可選擇由實質上不含氫之矽氧化物層形成,如以上配合第5A-5B圖所示之薄膜電晶體元件所作的敘述。在閘極絕緣層506被設置成一雙層結構的實施例中,閘極絕緣層506可具有設置於基板502上的矽氮化物層,以及設置於矽氮化物層上實質上不含氫之矽氧化物層,該矽氧化物層與主動通道530接觸。類似地,上層介面540形成於主動通道530及鈍化層518之間,由源極-汲極通道532之開口所定義。上層介面540也可選擇由一實質上不含氫之矽氧化物層形成,如以上配合第5A-5B圖所示之薄膜電晶體元件所作的敘述。在鈍化層518配置為一雙層結構的實施例中,鈍化層518可具有實質上不含氫之矽氧化物層,設置於主動通道530上與主動通道530接觸,以及設置於實質上不含氫之矽氧化物層上的一矽氮化物層。 FIG. 6 illustrates an embodiment of a metal oxide thin film transistor element 600 that can be used in accordance with an embodiment of the present invention. The metal oxide thin film transistor element 600 may have a structure similar to that of the metal oxide thin film transistor element 550 described above in connection with FIG. 5B. The metal oxide thin film transistor element 600 also includes an active channel 530 fabricated from a metal-containing layer. Suitable examples of the active channel 530 formed on the metal oxide thin film transistor element 600 include indium gallium zinc oxide (InGaZnO), indium gallium zinc oxide (InGaZnON), zinc oxide (ZnO), and zinc oxynitride (ZnON). ), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), beryllium copper oxide (SrCuO), Beryllium copper oxide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), or indium gallium aluminum nitride (InGaAlN). In addition, an upper interface 540 and a lower interface 542 are in contact with the active channel 530 and have film properties that are substantially free of hydrogen. The upper interface 540 and the lower interface 542 are made of a material that does not contain hydrogen. For example, the lower interface 542 is formed between the active channel 530 and the gate insulating layer 506. In this case, the gate insulating layer 506 may be formed of a tantalum oxide layer substantially free of hydrogen, as described above in connection with the thin film transistor element shown in Figures 5A-5B. In an embodiment in which the gate insulating layer 506 is disposed in a two-layer structure, the gate insulating layer 506 may have a tantalum nitride layer disposed on the substrate 502, and is substantially free of hydrogen disposed on the tantalum nitride layer. An oxide layer that is in contact with the active channel 530. Similarly, an upper interface 540 is formed between the active channel 530 and the passivation layer 518, defined by the opening of the source-drain channel 532. The upper interface 540 can also optionally be formed from a layer of germanium oxide that is substantially free of hydrogen, as described above in connection with the thin film transistor elements illustrated in Figures 5A-5B. In the embodiment in which the passivation layer 518 is configured as a two-layer structure, the passivation layer 518 may have a germanium oxide layer substantially free of hydrogen, disposed on the active channel 530 in contact with the active channel 530, and disposed substantially free of A tantalum nitride layer on the hydrogen oxide layer.

或者,額外的層也可形成於介面542、540,作為介面保護層。在一實施例中,一蝕刻終止層也可被使用,以作為形成於介面542、540之介面保護層,以維持介面實質上不含氫。類似地,在一例中,介面保護層為實質上不含氫之矽氧化物層,如以上配合第5A-5B圖所示之薄膜電晶 體元件所作的敘述。在另外一個例子中,介面保護層為含金屬的介電層,例如氮化鉭(TaN)、氮化鈦(TiN)、氮化鎢(WN)、氮化銅(CuN)及任何其他實質上不含氫(例如具有最低氫含量)之適合材料。 Alternatively, additional layers may be formed on the interfaces 542, 540 as an interface protective layer. In one embodiment, an etch stop layer can also be used as an interface protection layer formed on interfaces 542, 540 to maintain the interface substantially free of hydrogen. Similarly, in one example, the interface protective layer is a germanium oxide layer substantially free of hydrogen, such as the above-described thin film electrowinning shown in FIG. 5A-5B. A description of the body components. In another example, the interface protective layer is a metal-containing dielectric layer such as tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), copper nitride (CuN), and any other substantially Suitable materials that do not contain hydrogen (eg, have the lowest hydrogen content).

維持實質上不含氫之介面540、542與主動通道530的接觸,被認為可降低氫氣攻擊主動通道的可能性,進而獲得一高品質之介面,以改善金屬氧化物薄膜電晶體元件600之電性表現。 Maintaining the contact of the substantially hydrogen free interface 540, 542 with the active channel 530 is believed to reduce the likelihood of hydrogen attacking the active channel, thereby obtaining a high quality interface to improve the electrical conductivity of the metal oxide thin film transistor component 600. Sexual performance.

值得注意的是,用於本申請案之矽氮化物層亦可藉由其他所屬技術領域中合適之製程或技術來獲得。 It is to be noted that the tantalum nitride layer used in the present application can also be obtained by other processes or techniques suitable in the art.

因此,這裡描述的方法,藉由最小化一含矽層之氫含量以改善元件表現,係有利於改善電子元件之電子移動率、穩定度及一致性。 Thus, the methods described herein improve the electronic mobility, stability, and uniformity of electronic components by minimizing the hydrogen content of a germanium containing layer to improve component performance.

綜上所述,雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

102、502‧‧‧基板 102, 502‧‧‧ substrate

104‧‧‧介電層 104‧‧‧ dielectric layer

106‧‧‧閘極介電層 106‧‧‧gate dielectric layer

108‧‧‧多晶矽通道層 108‧‧‧Polysilicon channel layer

109a‧‧‧源極區 109a‧‧‧ source area

109b‧‧‧汲極區 109b‧‧‧Bungee Area

109c‧‧‧通道區 109c‧‧‧Channel area

110a、110b‧‧‧元件連結部 110a, 110b‧‧‧ Component connection

112‧‧‧絕緣層 112‧‧‧Insulation

114‧‧‧閘極電極 114‧‧‧gate electrode

150‧‧‧薄膜電晶體元件 150‧‧‧Thin-film transistor components

200‧‧‧腔室 200‧‧‧ chamber

202‧‧‧腔壁 202‧‧‧ cavity wall

204‧‧‧腔底 204‧‧‧ cavity bottom

206‧‧‧處理空間 206‧‧‧Processing space

208‧‧‧開口 208‧‧‧ openings

209‧‧‧真空泵 209‧‧‧vacuum pump

210‧‧‧氣體分配板 210‧‧‧ gas distribution board

211‧‧‧孔洞 211‧‧‧ hole

212‧‧‧腔蓋 212‧‧‧ cavity cover

214‧‧‧懸吊部 214‧‧‧suspension

216‧‧‧中央支撐件 216‧‧‧Central support

218‧‧‧上表面 218‧‧‧ upper surface

220‧‧‧氣體源 220‧‧‧ gas source

222‧‧‧射頻功率源 222‧‧‧RF power source

224‧‧‧遠距電漿源 224‧‧‧Remote plasma source

230‧‧‧基板支撐組件 230‧‧‧Substrate support assembly

231‧‧‧射頻返回帶 231‧‧‧RF return belt

232‧‧‧基板接收表面 232‧‧‧Substrate receiving surface

233‧‧‧遮蔽框 233‧‧‧ shadow frame

234‧‧‧主幹 234‧‧‧Main trunk

236‧‧‧抬升系統 236‧‧‧lifting system

238‧‧‧抬銷 238‧‧‧Sale

239‧‧‧加熱及/或冷卻元件 239‧‧‧ Heating and / or cooling elements

250‧‧‧下游表面 250‧‧‧ downstream surface

300‧‧‧沉積製程 300‧‧‧Sedimentation process

302、304、306、308‧‧‧步驟 302, 304, 306, 308‧ ‧ steps

402‧‧‧非晶矽層 402‧‧‧Amorphous layer

404‧‧‧脫氫非晶矽層 404‧‧‧Dehydrogenated amorphous layer

406‧‧‧多晶矽層 406‧‧‧ Polycrystalline layer

500‧‧‧薄膜電晶體元件 500‧‧‧Thin-film transistor components

504‧‧‧閘極電極層 504‧‧‧gate electrode layer

506‧‧‧閘極絕緣層 506‧‧‧ gate insulation

508、530‧‧‧主動通道 508, 530‧‧‧ active channel

510‧‧‧源極電極 510‧‧‧Source electrode

511、513‧‧‧主動層 511, 513‧‧ ‧ active layer

512‧‧‧汲極電極 512‧‧‧汲electrode

514‧‧‧蝕刻終止部 514‧‧‧etching termination

516、520‧‧‧虛線 516, 520‧‧‧ dotted line

518‧‧‧鈍化層 518‧‧‧ Passivation layer

532‧‧‧源極-汲極通道 532‧‧‧Source-bungee channel

540‧‧‧上層介面 540‧‧‧Upper interface

542‧‧‧下層介面 542‧‧‧lower interface

550、600‧‧‧金屬氧化物薄膜電晶體元件 550, 600‧‧‧Metal oxide thin film transistor components

第1圖為一薄膜電晶體元件結構之剖面圖。 Figure 1 is a cross-sectional view showing the structure of a thin film transistor element.

第2圖為繪示可用於沉積根據本發明一實施例之一非晶矽層的處理腔室的剖面圖。 2 is a cross-sectional view showing a processing chamber that can be used to deposit an amorphous germanium layer in accordance with an embodiment of the present invention.

第3圖為繪示一種形成可用於元件結構中之接著被轉變成多晶矽層的非晶矽層的方法之一實施例的製造流程 圖。 3 is a manufacturing flow diagram showing an embodiment of a method of forming an amorphous germanium layer that can be used in an element structure to be subsequently converted into a polysilicon layer. Figure.

第4A-4D圖為繪示具有一非晶矽層之元件結構之一實施例於根據本發明之一實施例將非晶矽層轉變成一多晶矽層的各步驟的示意圖。 4A-4D are schematic views showing the steps of an embodiment of an element structure having an amorphous germanium layer for converting an amorphous germanium layer into a poly germanium layer according to an embodiment of the present invention.

第5A-5B圖為根據一實施例之薄膜電晶體元件的剖面示意圖。 5A-5B are schematic cross-sectional views of a thin film transistor element in accordance with an embodiment.

第6圖為根據一實施例之薄膜電晶體的剖面示意圖。 Figure 6 is a schematic cross-sectional view of a thin film transistor according to an embodiment.

500‧‧‧薄膜電晶體元件 500‧‧‧Thin-film transistor components

502‧‧‧基板 502‧‧‧Substrate

504‧‧‧閘極電極層 504‧‧‧gate electrode layer

506‧‧‧閘極絕緣層 506‧‧‧ gate insulation

508‧‧‧主動通道 508‧‧‧ active channel

510‧‧‧源極電極 510‧‧‧Source electrode

511、513‧‧‧主動層 511, 513‧‧ ‧ active layer

512‧‧‧汲極電極 512‧‧‧汲electrode

514‧‧‧蝕刻終止層 514‧‧‧etch stop layer

516、520‧‧‧虛線 516, 520‧‧‧ dotted line

518‧‧‧鈍化層 518‧‧‧ Passivation layer

Claims (20)

一種於基板上形成矽層之方法,包括:運送一基板至一處理腔室中;提供一混合氣體至該處理腔室中,該混合氣體具有一矽基氣體、一惰性氣體且實質上不含氫,該混合氣體之該惰性氣體的每單位基板表面積之體積流率為該矽基氣體的每單位基板表面積之體積流率的約1.8倍至約79倍;施加一射頻功率,以將該混合氣體激發成一電漿;以及在該電漿存在的情況下形成一非晶矽層於該基板上。 A method of forming a germanium layer on a substrate, comprising: transporting a substrate into a processing chamber; providing a mixed gas to the processing chamber, the mixed gas having a germanium-based gas, an inert gas, and substantially free Hydrogen, the volumetric flow rate per unit substrate surface area of the inert gas of the mixed gas is about 1.8 times to about 79 times the volume flow rate per unit substrate surface area of the bismuth-based gas; applying a radio frequency power to mix the mixture The gas is excited into a plasma; and an amorphous layer is formed on the substrate in the presence of the plasma. 如申請專利範圍第1項所述之方法,更包括:於該處理腔室中,在原處熱處理該基板,至介於約攝氏450度至約攝氏550度之間之溫度。 The method of claim 1, further comprising: heat treating the substrate in situ in the processing chamber to a temperature between about 450 degrees Celsius and about 550 degrees Celsius. 如申請專利範圍第2項所述之方法,更包括:雷射退火該非晶矽層,以形成一多晶矽層。 The method of claim 2, further comprising: laser annealing the amorphous germanium layer to form a poly germanium layer. 如申請專利範圍第3項所述之方法,其中雷射退火之步驟更包括:加熱該基板至介於約攝氏100度至約攝氏1500度之間之溫度。 The method of claim 3, wherein the step of laser annealing further comprises: heating the substrate to a temperature between about 100 degrees Celsius and about 1500 degrees Celsius. 如申請專利範圍第1項所述之方法,其中施加該射頻功率之步驟更包括:提供低於1500瓦之一射頻功率。 The method of claim 1, wherein the step of applying the RF power further comprises: providing one of the RF powers less than 1500 watts. 如申請專利範圍第1項所述之方法,其中提供該混合氣體之步驟更包括:維持處理壓力於約0.5托耳至約5托耳之間。 The method of claim 1, wherein the step of providing the mixed gas further comprises maintaining a process pressure between about 0.5 Torr and about 5 Torr. 一種形成矽氧化物層之方法,包括:提供一混合氣體至一處理腔室中,該混合氣體具有一矽基氣體、一惰性氣體及一含氧氣體,該混合氣體之該惰性氣體的每單位基板表面積之體積流率為該矽基氣體的每單位基板表面積之體積流率的約11倍至約80倍;施加一射頻功率,以將該混合氣體激發成一電漿;以及形成一矽氧化物層於該基板上。 A method of forming a tantalum oxide layer, comprising: providing a mixed gas to a processing chamber, the mixed gas having a germanium-based gas, an inert gas, and an oxygen-containing gas, the mixed gas of the inert gas per unit The volumetric flow rate of the substrate surface area is about 11 times to about 80 times the volume flow rate per unit substrate surface area of the cerium-based gas; applying a radio frequency power to excite the mixed gas into a plasma; and forming a cerium oxide Layered on the substrate. 如申請專利範圍第7項所述之方法,其中該矽基氣體包括矽烷。 The method of claim 7, wherein the sulfhydryl gas comprises decane. 如申請專利範圍第8項所述之方法,其中該含氧氣體包括氧氣。 The method of claim 8, wherein the oxygen-containing gas comprises oxygen. 如申請專利範圍第8項所述之方法,其中該含氧氣體包括一氧化二氮。 The method of claim 8, wherein the oxygen-containing gas comprises nitrous oxide. 如申請專利範圍第7項所述之方法,其中該矽基氣體包括四乙氧基矽烷。 The method of claim 7, wherein the sulfhydryl gas comprises tetraethoxy decane. 如申請專利範圍第11項所述之方法,其中該含氧氣體包括一氧化二氮。 The method of claim 11, wherein the oxygen-containing gas comprises nitrous oxide. 如申請專利範圍第7項所述之方法,其中該混合氣體之該惰性氣體的每單位基板表面積之體積流率為該含氧氣體的每單位基板表面積之體積流率的約0.6倍至約1.7倍。 The method of claim 7, wherein the volume flow rate per unit substrate surface area of the inert gas of the mixed gas is about 0.6 times to about 1.7 of the volume flow rate per unit substrate surface area of the oxygen-containing gas. Times. 如申請專利範圍第13項所述之方法,其中該矽基氣體包括矽烷。 The method of claim 13, wherein the sulfhydryl gas comprises decane. 如申請專利範圍第14項所述之方法,其中該含氧 氣體包括氧氣或一氧化二氮。 The method of claim 14, wherein the oxygen is contained The gas includes oxygen or nitrous oxide. 如申請專利範圍第13項所述之方法,其中該混合氣體之該含氧氣體的每單位基板表面積之體積流率為該矽基氣體的每單位基板表面積之體積流率的約11倍至約82倍。 The method of claim 13, wherein the volume flow rate per unit substrate surface area of the oxygen-containing gas of the mixed gas is about 11 times to about the volume flow rate per unit substrate surface area of the sulfonium-based gas. 82 times. 如申請專利範圍第7項所述之方法,其中該混合氣體之該含氧氣體的每單位基板表面積之體積流率為該矽基氣體的每單位基板表面積之體積流率的約11倍至約82倍。 The method of claim 7, wherein a volume flow rate per unit substrate surface area of the oxygen-containing gas of the mixed gas is about 11 times to about a volume flow rate per unit substrate surface area of the sulfhydryl gas. 82 times. 一種金屬氧化物薄膜電晶體元件,包括:一基板;一閘極絕緣層,設置於該基板上,其中該閘極絕緣層包括一實質上不含氫之矽氧化物層;一主動通道,設置於該閘極絕緣層上,其中該主動通道包括銦鎵鋅氧化物(InGaZnO)、銦鎵鋅氮氧化物(InGaZnON)、氧化鋅(ZnO)、氮氧化鋅(ZnON)、鋅錫氧化物(ZnSnO)、鎘錫氧化物(CdSnO)、鎵錫氧化物(GaSnO)、鈦錫氧化物(TiSnO)、銅鋁氧化物(CuAlO)、鍶銅氧化物(SrCuO)、鑭銅硫氧化物(LaCuOS)、氮化鎵(GaN)、銦鎵氮化物(InGaN)、鋁鎵氮化物(AlGaN)或銦鎵鋁氮化物(InGaAlN)之其中至少一者;一源極-汲極電極,設置於該主動通道上;以及一鈍化層,設置於該源極-汲極電極層上,其中該鈍化層包括一實質上不含氫之矽氧化物層。 A metal oxide thin film transistor component, comprising: a substrate; a gate insulating layer disposed on the substrate, wherein the gate insulating layer comprises a germanium oxide layer substantially free of hydrogen; an active channel is disposed On the gate insulating layer, wherein the active channel comprises indium gallium zinc oxide (InGaZnO), indium gallium zinc oxide (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide ( ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), beryllium copper oxide (SrCuO), beryllium copper sulfur oxide (LaCuOS) And at least one of gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), or indium gallium aluminum nitride (InGaAlN); a source-drain electrode disposed at the And a passivation layer disposed on the source-drain electrode layer, wherein the passivation layer comprises a germanium oxide layer substantially free of hydrogen. 如申請專利範圍第18項所述之金屬氧化物薄膜電 晶體元件,其中該閘極絕緣層之該實質上不含氫之矽氧化物層或該鈍化層之該實質上不含氫之矽氧化物層係由以下步驟形成:提供一混合氣體至一處理腔室中,該混合氣體具有一矽基氣體、一惰性氣體及一含氧氣體,該混合氣體之該惰性氣體的每單位基板表面積之體積流率為該矽基氣體的每單位基板表面積之體積流率的約11倍至約80倍;以及施加一射頻功率,以將該混合氣體激發成一電漿;以及形成該實質上不含氫之矽氧化物層於該基板上。 Metal oxide film electric as described in claim 18 a crystal element, wherein the substantially hydrogen-free germanium oxide layer of the gate insulating layer or the substantially hydrogen-free germanium oxide layer of the passivation layer is formed by: providing a mixed gas to a process In the chamber, the mixed gas has a ruthenium-based gas, an inert gas and an oxygen-containing gas, and the volume flow rate per unit substrate surface area of the inert gas of the mixed gas is the volume per unit substrate surface area of the ruthenium-based gas. The flow rate is from about 11 times to about 80 times; and a radio frequency power is applied to excite the mixed gas into a plasma; and the substantially hydrogen-free tantalum oxide layer is formed on the substrate. 一種金屬氧化物薄膜電晶體元件,包括:一基板;以及一主動通道,設置於該基板上一源極-汲極電極及一閘極絕緣層之間,其中一介面形成於該主動通道及該閘極絕緣層之間,該介面包括一實質上不含氫之介電表面。 A metal oxide thin film transistor device includes: a substrate; and an active channel disposed between the source-drain electrode and a gate insulating layer on the substrate, wherein an interface is formed on the active channel and the Between the gate insulating layers, the interface includes a dielectric surface that is substantially free of hydrogen.
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