JP2005004183A - Light emission type display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a light emission type display apparatus which can improve luminance or service life. <P>SOLUTION: The light emission type display apparatus has an organic light emitting diode element OLED and an EL drive transistor Qq arranged in each of a plurality of pixel areas defined by two adjacent scanning signal wirings Gm and neighboring video signal wiring Dn and current supply wiring An. A current supplied to the organic light emitting diode element connected to a drain electrode of the EL drive transistor is controlled by a voltage between a gate electrode and a source electrode of the EL drive transistor, and a body electrode BD provided to the EL drive transistor as a fourth electrode is earthed in such a manner that excessive carriers generated in a channel area are caused to escape from the drive transistor through the body electrode. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a light-emitting display device that can be used as a display device for images, character information, and the like of portable terminals, personal computers, TVs, and the like.

  A color image display device using an organic light emitting diode (hereinafter referred to as OLED) has recently attracted attention. In particular, an active matrix OLED display in which a large number of OLED elements arranged in a matrix are driven by respective thin film transistors is considered promising as a method suitable for high definition and large size.

  Conventionally, a pixel circuit of an active matrix type OLED display controls a sampling transistor for sampling an analog image signal, a memory capacity for holding the image signal, and a current supplied to the OLED according to an image signal voltage stored in the memory capacity. A circuit composed of two transistors and one capacitive element constituting a drive transistor is most commonly used. An example of such a circuit configuration is disclosed in Patent Document 1.

  In the above prior art, the magnitude of the current supplied to the OLED is such that the analog voltage held in the memory capacity is applied between the gate and source of the drive transistor, and the drive transistor is in the saturation region, that is, the drain-source voltage is between the gate and source. It is controlled by driving in a region where the voltage is larger than the voltage. Thus, by operating the drive transistor in the saturation region, the voltage drop between the terminals of the OLED element changes due to the change in the current value, and the drive current value is kept constant even if the source-drain voltage of the drive transistor changes. Can keep. Therefore, the drive transistor needs to have good saturation characteristics. Here, good saturation characteristics mean that the voltage range in which the drain current is constant regardless of the source-drain voltage is wide.

Due to the demand for the performance of the drive transistor, a long channel transistor having a channel length as long as 10 μm to 20 μm is usually used for the drive transistor. This is because in a normal MOS transistor, when the channel length is shortened, saturation characteristics such that the drain current has a constant value with respect to the source-drain voltage cannot be obtained due to the channel length modulation effect or the parasitic bipolar effect. Because. Another reason is that the breakdown voltage between the source and the drain decreases as a result of the increase in the electric field in the vicinity of the drain junction due to the shortening of the channel.
JP 2002-156923 A

  However, when a long channel transistor having a channel length of 10 μm to 20 μm is formed in a pixel, the area occupied by the transistor increases, so that the area where an OLED element can be formed decreases and the aperture ratio decreases. For this reason, in order to ensure a certain brightness | luminance, the current density supplied to an OLED element must be enlarged, and there exists a problem which accelerates deterioration of an OLED element and shortens a product life.

  The present invention solves such a problem and includes a transistor having good saturation characteristics and high source-drain breakdown voltage without increasing the channel length to 10 μm to 20 μm. An object is to provide a light-emitting display device that can be improved.

  In order to solve the above problems, a light-emitting display device according to one embodiment of the present invention includes a substrate having an electrically insulating surface, a plurality of scanning signal wirings provided on the surface of the substrate, and the scanning signals. A plurality of video signal wirings provided on the one surface of the substrate so as to cross the wiring, a plurality of current supply wirings provided on the one surface of the substrate so as to cross the scanning signal wiring, and the two adjacent scannings A driving transistor for driving the light emitting element, the light emitting element being disposed in each of the plurality of pixel regions defined by the video signal wiring adjacent to the signal wiring and the current supply wiring; Includes a channel region, a gate electrode, a drain electrode provided in the drain region, a source electrode provided in the source region, and a body electrode, and the driving transistor The current supplied to the light emitting element connected to the drain region of the driving transistor is controlled by the voltage between the gate electrode and the source electrode, and surplus carriers generated in the channel region are formed in the body electrode of the driving transistor. It is grounded so as to escape from the driving transistor through an electrode.

The body electrode of the driving transistor is preferably grounded by being connected to the current supply wiring, or a ground wire is provided on the one surface (insulator surface) of the substrate and connected to these ground wires. To be grounded.

  The biggest reason why so-called SOI-MOS transistors on the insulator surface do not show good saturation characteristics is that the potential of the channel fluctuates as described below due to excess carriers generated by a strong electric field near the drain junction. There is to do. For example, taking an N-channel transistor as an example, holes generated by impact ionization in a strong electric field near the drain junction drift in the back channel toward the source electrode, but are blocked by a potential barrier present at the source junction. It stops and stops near the back channel, and the channel potential shifts in the positive direction. In order to neutralize this, electrons flow from the source and flow into the drain as it is, so that the drain current increases. As the drain voltage increases, the drain junction electric field increases, so the above-described series of processes become more prominent, and the drain current increases rapidly.

  As in the above aspect of the present invention, a drive transistor is provided with a body electrode, and this is connected to, for example, a current supply terminal, so that surplus carriers generated in the transistor are sucked out and into the channel. Since it does not stop, electrons do not flow from the source, and good current saturation characteristics are achieved.

  Embodiments of the present invention will be described below with reference to the accompanying drawings.

(First embodiment)
FIG. 1 shows an equivalent circuit of a pixel of a light emitting display device according to a first embodiment of the present invention. FIG. 2 is a plan view of a pixel of the light emitting display device according to the first embodiment.

  On the electrically insulating substrate (insulator surface) 10, there are a large number of scanning signal lines Gm extending in parallel to each other in the column direction, a large number of video signal lines Dn and an anode current supply wiring An extending in parallel to each other in the row direction. It is arranged. Each of a large number of pixels positioned in a matrix is defined by a region surrounded by two adjacent scanning signal lines Gm, one video signal line Dn, and one anode current supply line An. . Inside each pixel, a sampling transistor Qs, an EL driving transistor Qd, a charge storage capacitor Cs, and an organic light emitting diode OLED are formed. A terminal of one electrode (anode electrode) of the organic light emitting diode OLED is preferably connected to the drain region of the EL driving transistor Qd via the drain electrode thereof. In addition, a charge storage capacitor Cs is connected between the gate terminal node N1 of the EL driving transistor Qd and the anode current supply wiring An, so that the voltage of the gate terminal node N1 can be held for a certain period. ing. The other terminals of the organic light emitting diodes OLED of all the pixels are connected to a common cathode electrode CA that covers almost the entire display area.

  The sampling transistor Qs is composed of a double gate NMOS (N-type TFT) having a gate length of 1 μm + 1 μm. The EL driving transistor Qd is composed of a PMOS (P-type TFT) having a gate length of 2 μm. The EL driving transistor Qd is provided with a body electrode BD made of an n-type semiconductor film, and the body electrode BD is connected to the anode current supply wiring An.

  A vertical scanning circuit VDRV, a horizontal drive circuit HDRV, and an anode power supply circuit PAN are further disposed on the electrical insulating substrate 10. The scanning signal wiring Gm, video signal wiring Dn, and anode current supply wiring An are connected to the vertical scanning circuit VDRV, horizontal driving circuit HDRV, and anode power supply circuit PAN, respectively. Further, all the anode current supply wirings An are grounded as is known by being connected to the anode power supply circuit PAN.

  In the display device configured as described above, the video analog signal is supplied from the horizontal drive circuit HDRV to the pixels for one row selected by the pulse voltage from the vertical scanning circuit VDRV. This signal is held in the charge storage capacitor Cs via the sampling transistor Qs of each pixel. At this time, the voltage between the terminals of the charge storage capacitor Cs becomes the gate-source voltage of the EL driving transistor Qd, and a constant current corresponding to this voltage is supplied from the anode power supply circuit PAN to the anode current supply wiring An and the EL driving transistor Qd. To the organic light emitting diode OLED. As a result, the organic light emitting diode OLED emits light and a multi-tone image can be displayed.

  Hereinafter, the configuration of each pixel element of the active matrix AMX (FIG. 6) will be described in detail with reference to FIGS.

  3 is a sectional view taken along line 3-3 in FIG. 2, FIG. 4 is a sectional view taken along line 4-4 in FIG. 2, and FIG. 5 is taken along line 5-5 in FIG. FIG.

The electrical insulating substrate 10 is configured by forming a buffer insulating film made of a SiON film 12 having a thickness of 200 nm on an alkali-free glass substrate 11 having a strain point of about 670 ° C. This buffer insulating film has a role of preventing diffusion of impurities such as Na from the glass substrate 11 to the element. On the SiON film 12, a single-crystal Si film 13 having a film thickness of 200 nm, which constitutes the sampling transistor Qs, is formed. Since each single crystal Si film 13 is integrally formed with a scanning wiring electrode (scanning signal wiring Gm) made of tungsten (W) via a gate insulating film 14 made of SiO _{2 with} a film thickness of 30 nm, The same symbol Gm is attached).

The sampling transistor Qs is an NMOS having a double gate structure, and has a configuration in which two channel regions 13a are connected in series in one single crystal Si film 13. On both sides of each channel region 13a, n ⁺ -type regions 13b constituting source and drain regions are formed.

  A first connection electrode 15 is formed on a portion of the gate insulating film 14 constituting the charge storage capacitor Cs by using the same W as the scanning wiring electrode Gm.

An interlayer insulating film 16 made of SiO ₂ is formed on these members so as to cover all the members. On the interlayer insulating film 16, signal wiring electrodes (integrated with the video signal wiring Dn are respectively formed of a three-layer metal film of Mo / Al / Mo or Ti / Al—Cu alloy / Ti. A second connection electrode 17 and an anode electrode (which is formed integrally with the anode current supply electrode An, and therefore has the same symbol An). It has been. The signal wiring electrode Dn is electrically connected to one n ⁺ -type region 13b through a contact through hole formed in the interlayer insulating film 16 and the gate insulating film 14. The second connection electrode 17 is electrically connected to the other n ⁺ -type region 13b through a contact through hole formed in the interlayer insulating film 16 and the gate insulating film 14. One end of the second connection electrode 17 is electrically connected to the first connection electrode 15 through a contact through hole formed in the interlayer insulating film 16 and the gate insulating film 14. The first connection electrode 15, the anode current supply electrode An, and the portion of the interlayer insulating film 16 sandwiched therebetween constitute a charge storage capacitor Cs (FIG. 3).

  On the other hand, the EL driving transistor Qd is a PMOS, and is formed in the single crystal Si film 13 (separated from the single crystal Si film 13 constituting the sampling transistor Qs) as shown in FIG. A p + type first region 13d constituting a source / drain region is formed on both sides of one channel region 13c. The gate electrode 15 a of the EL driving transistor Qd is formed integrally with the first connection electrode 15. The anode current supply electrode An is connected to the p + -type first region 13d on the drain side of the EL driving transistor Qd through a contact through hole formed in the interlayer insulating film 16 and the gate insulating film 14. The p + type l region 13d on the source side of the EL driving transistor Qd is further provided on the interlayer insulating film 16, and is formed of a three-layer metal film of Mo / Al / Mo or Ti / Al-Cu alloy / Ti. The third connection electrode 20 is electrically connected to one end side of the third connection electrode 20 through a contact through hole formed in the interlayer insulating film 16 and the gate insulating film 14.

A protective insulating film 18 is provided on the interlayer insulating film 16 including the various electrodes Dn, An, 17 and 20. On this protective insulating film 18, an ITO electrode 19 that also serves as an anode electrode of the organic light emitting diode OLED is provided. The ITO electrode 19 is electrically connected to the other end of the third connection electrode 20 through a contact-hole formed in the protective insulating film 18. A bank insulating film 21 is provided on the ITO electrode 19. In the bank insulating film 21, an opening 21a is formed so as to expose a part of the ITO electrode 19, and an organic film is laminated in a region where the opening 21a is formed to form a light emitting diode element OLED. .

The organic film is formed of a low molecular organic material. Specifically, these organic films are sequentially stacked on the bank insulating film 21 and the anode electrode (ITO electrode) 19 exposed from the opening 21a of the bank insulating film 21, and the hole transport layer HTL, EL light emission. The layer EM and the electron transport layer ETL. The organic light emitting diode OLED covers the entire display unit including the organic film, and has a cathode electrode CA made of aluminum (Al). The hole transport layer HTL is made of, for example, triphenyldiamine (TPD). The EL light emitting layer EM is preferably configured to perform color display with a red light emitting layer, a blue light emitting layer, and a green light emitting layer. The red light emitting layer is made of, for example, DCJTB and rubrene-doped tris (8-hydroxyquinoline) aluminum (Alq ₃ ). The blue light emitting layer is formed of, for example, DPVBi doped with BC _Z VBi. The green light emitting layer is made of, for example, Alq ₃ doped with coumarin 540. The electron transport layer ETL is made of, for example, Alq ₃ . The material for forming the light emitting layer and the transport layer is an example, and various materials can be selected depending on the application. The exposed surface of the organic light emitting diode is covered with a final protective film PV made of a 200 nm thick SiON film.

An n ⁺ -type region 22 is formed in the portion of the single crystal Si film 13 constituting the EL driving transistor Qd (FIG. 5). The n ⁺ -type region 22 is connected to the channel region 13c and is separated from the p ⁺ -type first region 13d constituting the source and drain regions. The n ⁺ -type region 22 functions as a body electrode BD that is a fourth terminal. The n ⁺ -type region 22 constituting the body electrode BD is connected to the anode current supply electrode An through a contact through hole formed in the interlayer insulating film 16 and the gate insulating film 14.

  In the light emitting display device having the EL driving transistor Qd configured as described above, the EL driving transistor Qd is provided with the body electrode BD, which is connected to the anode current supply electrode. As a result, surplus carriers generated by the EL driving transistor Qd are not sucked out by the anode current supply electrode and do not stay in the channel region 13c. Therefore, electrons do not flow from the source region due to the parasitic bipolar effect, and good current saturation characteristics are achieved even in a short channel transistor having a gate length of about 2 μm. Since the body electrode BD of the EL driving transistor Qd of each pixel is provided only to absorb excess carriers, all the body electrodes BD may be shared. In particular, by connecting the body electrode BD to the anode current supply terminal, it becomes unnecessary to separately provide a wiring for the body electrode, which contributes to improvement of the aperture ratio of the pixel. In addition, the use of a short channel transistor having a gate length of about 2 μm for the EL driving transistor also contributes to improvement of the aperture ratio of the pixel.

  Next, an example of a manufacturing method of the active matrix having the above configuration will be described.

A non-alkali glass substrate 11 having a thickness of 500 μm, a width of 750 mm, and a length of 950 mm and a strain point of about 670 ° C. is prepared. After the glass substrate 11 is washed, a 200 nm thick SiON film 12 is formed on the upper surface by plasma CVD using a mixed gas of SiH ₄ , NH ₃ and O ₂ . On this SiON film 12, a substantially intrinsic hydrogenated amorphous silicon film 13 is formed to a thickness of 200 nm by plasma CVD using a mixed gas of SiH ₄ and Ar gas. For example, by setting the film formation temperature at this time to 400 ° C., the hydrogen content immediately after film formation can be set to about 5 at%. Next, the hydrogen in the hydrogenated amorphous silicon film 13 is released by annealing the substrate at 450 ° C. for about 30 minutes. Then, a 200 nm-thickness SiON film is formed on the amorphous silicon film 13 in the annealing process using the next laser beam by a plasma CVD method using a mixed gas of SiH ₄ , NH ₃ and O ₂ . It is formed as a cap layer for preventing ablation. These plasma CVD and annealing processes are performed in a vacuum without exposing the glass substrate 11 to the atmosphere.

  Next, by irradiating the amorphous silicon film 13 with a pulsed excimer laser beam having a wavelength of 308 nm, the silicon is melted and recrystallized to partially monocrystallize the single crystal Si film 13. To do. At this time, in order to obtain a single crystallized region having as large an area as possible, the excimer laser light is laterally distributed by giving a spatial distribution to the laser beam intensity on the substrate surface using a phase shift mask having an appropriate pattern. It is preferable to employ a method for providing a temperature gradient in the direction. As a result, lateral crystal growth was stimulated, and an array of substantially rectangular single crystal regions each having a side of about 4 μm could be obtained. A specific example of the annealing method using such a phase shift mask will be described in detail later.

  Next, the SiON film as the cap layer is removed with buffered hydrofluoric acid, and the single crystal Si film 13 is processed into a predetermined pattern by a normal photolithography method.

Next, an oxide film having a thickness of 4 nm is formed on the surface of the single-crystal Si film 13 by plasma oxidation in a mixed gas of Kr gas and O _2. Subsequently, tetraethoxysilane and A SiO ₂ film having a film thickness of 24 nm is formed by a plasma CVD method using a mixed gas with O ₂ to form a two-layer stacked gate insulating film 14.

Next, boron (B ⁺ ) is implanted into the single crystal Si film 13 at an acceleration voltage of 20 KeV and a dose of 2E11 (cm ⁻² ) by ion implantation. This boron is for adjusting the threshold voltage of the TFT.

Next, a Mo film having a thickness of 250 nm is formed on the gate insulating film 14 by a sputtering method, and then a predetermined resist pattern is formed on the Mo film by an ordinary photolithography method, and reactive using CF ₄ is performed. The Mo film is processed into a predetermined shape by ion etching to obtain the scanning wiring electrode (scanning signal wiring) Gm, the first connection electrode 15 and the gate electrode 15a.

Next, phosphorus (P) ions are implanted into the single crystal Si film 13 at an acceleration voltage of 40 KV and a dose of 1E15 (cm ⁻² ) by an ion implantation method while leaving the resist pattern used for etching, and N-type sampling is performed. The source and drain regions 13b of the transistor Qs and the body region of the P-type EL driving transistor (P-type TFT) Qd are formed.

Next, the substrate is treated with a mixed acid while leaving the resist pattern, the processed Mo electrode is side-etched to slim the pattern, and the resist is removed. Thereafter, phosphorus (P) ions are implanted into the exposed portion of the single crystal Si film 13 at an acceleration voltage of 40 KV and a dose of 1E13 (cm ⁻² ) by an ion implantation method, and the LDD of the sampling transistor (N-type TFT) Qs. Form a region. As in the previous example, the length of this LDD region is controlled by the side etching time with the mixed acid.

Next, a predetermined resist pattern is formed to protect the sampling transistor Qs, and using the gate electrode 15a of the EL driving transistor Qd as a mask, boron ions are accelerated at a voltage of 20 kV and a dose amount is 2E15 (cm ⁻² ). Implantation is performed to form p-type source / drain regions 13d. At this time, by making the boron ion implantation amount larger than the phosphorus ion implantation amount, the source and drain regions 13d of the P-type TFT are inverted from n-type to p-type, and a P-type MOS is obtained.

  Next, after removing the photoresist, the impurities implanted in the single crystal Si film 13 are activated by a rapid thermal annealing (RAT) method using light UV irradiation of an excimer lamp or a metal halide lamp.

Next, an SIO ₂ film having a thickness of 500 nm is formed as an interlayer insulating film 16 on the entire upper surface by plasma CVD using a mixed gas of tetraethoxysilane and oxygen. After forming a predetermined resist pattern on the interlayer insulating film 16, by a dry etching method using a CHF _3, contact to the interlayer insulating film 16 - for opening the hole. Then, a Ti film having a thickness of 50 nm, an Al—Cu alloy film having a thickness of 500 nm, and a Ti film having a thickness of 50 nm are sequentially stacked on the interlayer insulating film 16 by sputtering. Thereafter, after a predetermined resist pattern is formed on the Ti film, batch etching is performed by a reactive ion etching method using a mixed gas of BCl ₃ and Cl ₂ to obtain a signal wiring electrode (video signal wiring) Dn, Second and third connection electrodes 17 and 20 and an anode electrode An are formed.

A SiN ₄ film having a thickness of 400 nm is formed on the interlayer insulating film 16 including the electrodes Dn, 17, 20, and An by a plasma CVD method using a mixed gas of SiH ₄ , NH _3, and N _2. The protective insulating film 18 is formed. On the protective insulating film 18, after forming a predetermined photoresist resist pattern by dry etching method using SF _6, contact to the insulation layer 18 - for opening the hole.

  Subsequently, an ITO film having a thickness of 70 nm is formed on the protective insulating film 18 by sputtering, and this is processed into a predetermined shape by wet etching using a mixed acid, thereby producing an organic light emitting diode (LED). An anode electrode 19 of the OLED is obtained.

Finally, a Si ₃ N ₄ film having a thickness of 100 nm is formed on the protective insulating film 18 including the anode electrode 19 by plasma CVD using a mixed gas of SiH ₄ , NH ₃ and N ₂ . Then, after forming a predetermined photoresist resist pattern to the _{the Si} 3 _{N 4} film on by a dry etching method using SF _6, the _{the Si} 3 _{N 4} film of LED forming portion on the anode electrode 19 is removed by etching The bank insulating film 21 is obtained (by forming the opening 21a). The bank insulating film 21 covers the end portion of the anode electrode 19 so that when an ultra-thin organic film constituting the LED is formed on the anode electrode 19, electric field concentration at the end portion of the ITO electrode is formed. It is formed in order to prevent the element from being destroyed by.

  Next, the process of forming an organic LED element on the TFT active matrix substrate produced by the above process will be described below.

The substrate is set in a vacuum vapor deposition apparatus, and is first introduced into a preheating chamber and baked in vacuum at 200 ° C. for 1 hour to remove moisture adsorbed on the substrate surface. Then, ultraviolet light is irradiated in an atmosphere containing oxygen to remove organic substances on the anode electrode surface. Next, the work function of the anode electrode surface is adjusted by moving the substrate to the pretreatment chamber and performing O ₂ plasma treatment. By this treatment, the work function of ITO forming the anode electrode is adjusted, the height of the barrier when holes are injected into the hole transport material can be lowered, and the injection efficiency can be improved.

  Next, the substrate is moved to the first vapor deposition chamber, and mask vapor deposition is performed using a mask in which a hole transport layer is formed on the entire surface of the display portion. As a material for the hole transport layer, triphenyldiamine (TPD) is used. In addition, for example, α-NPD can be used. Next, the substrate is moved to the second vapor deposition chamber, and RGB light emitting materials are vapor deposited by mask. In forming each light emitting material, first, after aligning the dot to display blue with the opening of the vapor deposition mask, the blue material is vapor-deposited, and then the vapor deposition mask is placed in the vapor deposition chamber by the pitch of one dot. The green material is vapor-deposited, and the vapor deposition mask is moved in the same manner to vapor-deposit the red material. As a result, a predetermined material is formed at each of the RGB dot positions.

Next, the substrate is moved to the third vapor deposition chamber to form a cathode electrode. In order for the cathode electrode to improve the electron injection efficiency with respect to the organic layer, after forming LiF with a film thickness of about 0.8 nm, an Al film is formed with a thickness of 150 nm. Finally, the substrate is moved to the CVD chamber, and a 300 nm thick SiON film 12 is formed by a plasma CVD method using a mixed gas of SiH ₄ , NH ₃ and O ₂ . At this time, in order not to damage the organic LED element, it is desirable that the formation temperature is 100 ° C. or lower and the discharge power is as small as possible.

  Finally, the substrate is cut out to a predetermined size, and a driver LSI is mounted to complete the panel.

  Next, a specific example of the annealing process using the phase shift mask will be described with reference to FIGS. 6 (A) to 6 (D).

  A phase shift mask 100 shown in FIG. 6A is a laser that is incident on a transparent medium, for example, a quartz base material, in which adjacent regions having different thicknesses are adjacent to each other and a step (phase shift portion) between these regions is incident. The light beam is diffracted and interfered to give a periodic spatial distribution to the intensity of the incident laser beam. The phase shift mask 100 includes first strip regions (phase regions) 100b that are alternately arranged in phase so that adjacent patterns have an opposite phase (180 ° shift), and a first phase that has a phase of 0. 2 strip regions (phase regions) 100c. These strip regions (phase shift line regions) have a width of 10 μm. Specifically, the phase shift mask 100 is manufactured by pattern-etching a rectangular quartz substrate having a refractive index of 1.5 to a depth corresponding to π with respect to 248 nm light, that is, a depth of 248 nm. . The region formed thin by this etching is the first strip region 100b, and the region that is not etched is the second strip region 100c.

  In the phase shift mask 100 having such a configuration, the laser beam that has passed through the thick second phase region 100c is delayed by 180 ° compared to the laser beam that has passed through the thin first phase region 100b. As a result, interference and diffraction occur between the laser beams, and an intensity distribution of the laser beams as shown in FIG. 6D is obtained. In other words, the light that has passed through the phase shift unit has a light intensity that is minimum, for example, 0, at a position corresponding to the area between the adjacent transmitted lights, since the adjacent transmitted lights have opposite phases. This minimum region or a region in the vicinity thereof serves as a nucleus for crystallizing the semiconductor. In the specific example, the phase shift mask 100 is used in which the phase shift portions are formed in a plurality of straight lines parallel to each other as shown in FIG. 6A, but the present invention is not limited to this. Absent.

  For example, the phase shift lines can be orthogonal and the phases 0 and π can be arranged in a checkered lattice pattern. In this case, a lattice-like region having a light intensity of 0 is formed along the phase shift line. For this reason, crystal nuclei are generated at arbitrary positions on this line, which makes it difficult to control the position and shape of the crystal grains. For this reason, in order to control the generation of crystal nuclei, the zero intensity region is preferably point-like. For this reason, the phase shift amount of the orthogonal phase shift lines is set to less than 180 °, so that the intensity is not completely zero (although it decreases) at the corresponding position of the phase shift lines, and at the same time, By setting the sum of complex transmittances to zero, the intensity at the position corresponding to the intersection can be zero.

  An example of this will be described with reference to FIGS. 6B and 6C. As shown in FIG. 6B, the mask 100 has a plurality of sets each formed of a square pattern, each set including four square regions 100e, 100f, 100g, and 100h having different thicknesses. . In each set, as shown in FIG. 6C, the first region 100e is the thinnest and the phase is zero. The fourth region 100h is the thickest, and the phase is shifted by 3π / 2 from the first region 100e. The second and third regions 100f and 100g having a thickness between these regions 100e and 100h are out of phase with respect to the first region by π / 2 and π, respectively.

  In such a mask, a portion where the first to fourth regions are adjacent to each other, for example, a center point of a square pattern is a region having zero intensity. Therefore, since this point becomes the nucleus of the crystal, the position and shape of the crystal grain can be easily controlled. The technology using such a phase shift mask is described in the specification of an international application filed on March 19, 2003 by the same applicant as the basic application based on the Japanese application (Japanese Patent Application No. 2002-120312). ing.

  Next, an entire light emitting display device including the active matrix AMX having the above-described configuration will be described with reference to FIG.

  On the rectangular glass substrate 11, the active matrix AMX having the above configuration, the vertical scanning circuit VDRV, and the horizontal driving circuit HDRV are formed. The cathode electrode CA of the organic light emitting diode OLED of each pixel of the active matrix AMX is connected to the external connection terminal PAD through the contact area CACONT by the lead-out wiring WL formed on the substrate 11. In addition, the anode current supply electrodes An provided in each column in the pixel are connected outside the pixel region, and are connected to the external connection terminal PAD by the extraction electrode. On the cathode electrode CA provided over almost the entire pixel region, a final protective film PV is formed on almost the entire surface excluding the external connection terminal PAD so that the organic light emitting diode element is not exposed to the outside air. .

(Second Embodiment)
FIG. 8 shows an equivalent circuit of a pixel of the light emitting display device according to the second embodiment of the present invention. The configuration of the second embodiment is almost the same as that of the first embodiment except that an NMOS is used for the EL drive transistor Qd. Further, the cathode terminal of the organic light emitting diode OLED is connected to the drain terminal of the EL driving transistor Qd, and the anode electrode of the organic light emitting diode OLED is configured as a common electrode. Even in such a configuration, by providing the body electrode BD to the EL driving transistor Qd and connecting it to the anode current supply electrode An, surplus carriers generated in the EL driving transistor Qd are supplied with the anode current. It is not sucked out by the electrode An and stopped in the channel region. For this reason, electrons do not flow from the source due to the parasitic bipolar effect, and good current saturation characteristics are achieved even in a short channel transistor having a gate length of about 2 μm. In particular, NNOS is effective because non-saturation characteristics due to the parasitic bipolar effect are likely to occur.

  In the light-emitting display device including the active matrix AMX configured as described above, in FIG. 7, the anode electrode replaces the cathode electrode PV and the lead-out wiring WL formed on the substrate 11 via the contact area CACONT. To the external connection terminal PAD.

  FIG. 9 and FIG. 10 respectively show the output characteristics when the conventional three-terminal NMOS transistor is used as the EL driving transistor and when the four-terminal NMOS transistor of the second embodiment is used. Indicates.

  In the case of the conventional three-terminal NMOS transistor shown in FIG. 9, there is almost no saturation region where the drain current is constant with respect to the drain voltage due to the manifestation of the parasitic bipolar effect, and there is also a breakdown in the high drain voltage region. It can be seen. On the other hand, in the case of the four-terminal transistor of this embodiment shown in FIG. 10, good saturation characteristics are observed over a wide drain voltage, and breakdown does not occur. Such characteristics are particularly desirable for a transistor used in a constant current drive type light emitting display device.

  In the first and second embodiments, surplus carriers in the channel region are discharged from this transistor by connecting the fourth terminal of the EL driving transistor, that is, the body electrode BD to the anode current supply wiring An. However, for example, the present invention is not limited to the connection with the wiring as in the third embodiment described below.

(Third embodiment)
In the active matrix shown in FIG. 11, the same members as those shown in FIG.

  The EL driving transistor Qd is a PMOS, and its body electrode BD is not connected to the anode current supply wiring An. Instead, the ground line AL is provided on the insulating substrate 10 in parallel with the scanning signal wiring Gm, and the body electrode BD is connected to the ground line AL. These ground lines AL extend outside the pixel region and are held at the power supply potential. These ground lines AL can be formed of the same material together with the scanning signal wiring Gm, for example.

  The ground line AL may be formed in parallel with the video signal wiring Dn, or may not necessarily be formed in parallel with the wiring.

  Excess carriers generated in the channel region of the EL driving transistor having such a structure are discharged from the transistor, that is, escaped through the body electrode BD and the ground line AL. As a result, the effect as shown in FIG. 10 is obtained.

  Needless to say, the technical idea of this embodiment can be applied to the case where an NMOS is used as the EL driving transistor Qd as in the second embodiment.

  As described above, according to the present invention, a light-emitting display device having a uniform and high image quality and a long lifetime can be realized.

1 is a pixel circuit diagram of a light-emitting display device according to a first embodiment of the present invention. 1 is an enlarged plan view showing a pixel portion of a light emitting display device according to a first embodiment of the present invention. FIG. 3 is a cross-sectional view taken along line 3-3 in FIG. 2. FIG. 4 is a cross-sectional view taken along line 4-4 of FIG. FIG. 5 is a cross-sectional view taken along line 5-5 in FIG. (A) thru | or (D) is a figure for demonstrating the annealing process using the phase shift mac used with the method of forming the transistor of 1st Embodiment. It is a disassembled perspective view which shows the whole light emitting display device provided with the active matrix concerning 1st Embodiment. FIG. 6 is a pixel circuit diagram of a light emitting display device according to a second embodiment of the present invention. It is a figure which shows the output characteristic of the conventional EL drive transistor. It is a figure which shows the output characteristic of the transistor for EL drive used for the light emission type display apparatus concerning the 2nd Embodiment of this invention. FIG. 6 is a pixel circuit diagram of a light emitting display device according to a third embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Electrical insulation board | substrate, Gm ... Scanning signal wiring (scanning wiring electrode), Dn ... Video signal wiring (signal wiring electrode), 15 ... 1st connection electrode, 19 ... ITO electrode (anode electrode), 17 ... 2nd Connection electrode, 20 ... third connection electrode, An ... anode current supply electrode, OLED ... organic light emitting diode element, BD ... body electrode, Qs ... sampling transistor Qd ... EL drive transistor, Cs ... charge storage capacitor, 12 ... SiNO Film (buffer film), 14 ... gate insulating film, 16 ... interlayer insulating film, 18 ... protective insulating film, 21 ... bank insulating film, PV ... final protective film, 13a ... channel region, 13b ... n ⁺ type region, 13d ... p ⁺ type first region, HTL ... hole transport layer, EM ... EL light emitting layer, ETL ... electron transport layer, CA ... cathode electrode.

Claims (8)

A substrate having an electrically insulating surface;
A plurality of scanning signal wirings provided on the one surface of the substrate;
A plurality of video signal wirings provided on the one surface of the substrate so as to intersect the scanning signal wirings;
A plurality of current supply wirings provided on the one surface of the substrate so as to intersect the scanning signal wirings;
A light emitting element defined by two adjacent scanning signal lines, an adjacent video signal line and a current supply line, and disposed in each of a plurality of pixel regions;
A driving transistor for driving the light emitting element,
The driving transistor has a channel region, a gate electrode, a drain electrode provided in the drain region, a source electrode provided in the source region, and a body electrode,
The current supplied to the light emitting element connected to the drain region of the driving transistor is controlled by the voltage between the gate electrode and the source electrode of the driving transistor,
The light emitting display device, wherein the body electrode of the driving transistor is grounded so that excess carriers generated in the channel region escape from the driving transistor through the body electrode.   The light emitting display device according to claim 1, wherein the light emitting element includes an EL light emitting diode.   3. The light emitting display device according to claim 1, wherein the body electrode is grounded by being connected to the current supply wiring.   4. The light emitting type according to claim 1, further comprising a ground wire provided on the one surface of the substrate, wherein the body electrode is grounded by being connected to the ground wire. Display device.   3. The light emitting display device according to claim 2, wherein the driving transistor is a P-channel MOS TFT, and the drain region is connected to an anode electrode of the EL light emitting diode through a drain electrode thereof.   3. The light emitting display device according to claim 2, wherein the driving transistor is an N-channel MOS TFT, and the drain region is connected to a cathode electrode of the EL light emitting diode through a drain electrode thereof.   The channel region, the drain region, the source region, and the body electrode are formed of the same semiconductor, and the channel region and the body electrode have different conductivity types from the drain region and the source region. Item 7. The light emitting display device according to any one of Items 1 to 6. A substrate having an electrically insulating surface;
A plurality of scanning signal wirings provided on the one surface of the substrate;
A plurality of video signal wirings provided on the one surface of the substrate so as to intersect the scanning signal wirings;
A plurality of current supply wirings provided on the one surface of the substrate so as to intersect the scanning signal wirings;
A sampling transistor for sampling an image signal and a capacitor for holding the image signal, which are defined by the two adjacent scanning signal lines, the adjacent video signal line and the current supply line, and are arranged in each of the plurality of pixel regions. An element, a light emitting diode element, and a driving transistor for driving the light emitting element,
The driving transistor has a channel region, a gate electrode, a drain electrode, a source electrode, and a body electrode,
The current supplied to the light emitting element connected to the drain region of the driving transistor is controlled by the voltage between the gate electrode and the source electrode of the driving transistor,
A light emitting display device in which a body electrode of the driving transistor is grounded so that excess carriers generated in a channel region escape from the driving transistor through the body electrode.

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