JP2009198990A - Method for manufacturing thin film transistor array substrate and method for correcting threshold, method for correcting luminance of display device, thin film transistor array substrate, and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a thin film transistor array substrate capable of eliminating characteristic irregularity of a print type TFT. <P>SOLUTION: In the method for manufacturing the thin film transistor array substrate 100, semiconductor layers constituting a plurality of thin film transistors 10 are formed by printing with the semiconductor layers of all the thin film transistors connected to respective specified wiring, that constitute a source line group 111 or a gate line group 112 (hereinafter referred to as specified wiring group), as one print unit in transistor processing, and include threshold correction lines provided corresponding to the plurality of specified wiring constituting the specified wiring group and forming a plurality of threshold correction lines on the substrate to be connected to the body terminals 14 of all the thin film transistors connected to the corresponding specified wiring. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a thin film transistor array substrate, and more particularly to a method for manufacturing an array substrate including a printing type thin film transistor typified by an organic thin film transistor.

  In recent years, interest in FPD (Flat Pan Display) has been increased in place of conventional CRT (Cathode Ray Tube). As typical FPDs, LCD (Liquid Crystal Display) and PDP (Plasma Display Panel) have already been realized, but it is known to have the following problems.

  That is, a general large LCD requires active matrix driving having a thin film transistor (hereinafter referred to as a TFT (Thin Film Transistor)) for each pixel. As a result, millions of TFTs are defective in the entire LCD display screen. Must be formed without. In order to form a TFT, a semiconductor process such as formation and patterning of a plurality of thin film layers is necessary, and the manufacturing cost tends to increase. On the other hand, since the PDP can be formed by a simple process that does not require a TFT, the manufacturing cost can be reduced as compared with the LCD. On the other hand, since the voltage for driving the LCD is about several volts to several tens of volts, the size of the external drive circuit for driving the LCD panel is small. Therefore, it is possible to reduce the cost of the drive circuit. On the other hand, since the driving voltage of the PDP is several hundred volts, the size of the driving circuit is large. Therefore, the PDP has a problem that the cost of the drive circuit becomes high. As a result, the current situation is that there is no significant difference between the two in terms of cost.

  Here, the TFT manufacturing process that increases the LCD manufacturing cost will be briefly described. In general, amorphous silicon TFTs are used in large LCDs, and polysilicon TFTs are used in medium and small LCDs. The manufacturing processes are different from each other, but there is no difference in the sense that the semiconductor thin film process is the base. . Here, an amorphous silicon TFT process will be described. First, a gate electrode is formed on a glass substrate. Generally, a low-resistance metal such as Mo, Ti, Ta, Al, or Cu is selected as the material for the gate electrode. More generally, barrier metal layers are disposed above and below the metal layer in consideration of heat resistance.

  First, a gate metal film made of these metals is formed over the entire surface of a glass substrate in a vacuum by a sputtering method. The thickness is about 100 nm to 500 nm. Thereafter, a photoresist is applied, and the resist is patterned by exposure and development in a photo process. Thereafter, using the resist pattern as a mask, the gate metal film in a portion where the resist is not placed is etched by dry etching or wet etching. Thereafter, the resist pattern is peeled off, and patterning of the gate metal film is completed (a gate electrode is formed). Dry etching is also performed in vacuum. Thereafter, a gate insulating film and an amorphous silicon layer are sequentially formed by a CVD method. CVD is also a process under vacuum. These layers are formed to a thickness of about 100 nm to 300 nm. Thereafter, patterning is performed in the same manner as the gate metal film. Subsequently, film formation and patterning are repeated in the order of the source (and drain) metal film, the passivation film, and the ITO film to complete the TFT.

  As described above, the formation of TFTs requires a large number of vacuum processes, and there is a problem that the manufacturing cost increases. The vacuum process also becomes a problem when a flexible substrate using a material typified by plastic is used as the substrate.

Therefore, in order to solve these problems, research and development has been energetically performed to realize a printing type TFT in which a vacuum process is reduced as much as possible and a TFT is formed by a cheaper printing process (for example, Patent Document 1). reference).
JP 2003-258256 A

  However, when a thin film transistor array substrate for a display device is configured by arranging a plurality of conventional print TFTs, there are the following problems. That is, when trying to produce a thin film transistor array substrate as shown in Patent Document 1 using a printing method commonly used at present, such as inkjet printing, roll printing, letterpress printing, intaglio printing, screen printing, dispenser drawing, Unevenness of film thickness due to printing tools is likely to occur. For example, when an ink jet method is taken as an example, film thickness unevenness reflecting the variation in the hole of each nozzle that ejects ink occurs, and as a result, characteristic unevenness occurs in the TFT formed by printing. In the display device using the display, display unevenness due to this occurs.

  The present invention has been made to solve such a problem, and an object of the present invention is to provide a method of manufacturing a thin film transistor array substrate that can eliminate unevenness in characteristics of a printing TFT.

  In order to solve the above-described problems, a method of manufacturing a thin film transistor array substrate according to the present invention includes: source line processing for forming a source line group including a plurality of source lines arranged on a substrate; A plurality of thin film transistors each having a gate terminal, a source terminal, a drain terminal, and a body terminal, and a plurality of thin film transistors each having a gate terminal, a source terminal, a drain terminal, and a body terminal. Corresponding to a three-dimensional intersection of a line and the plurality of gate lines, and any one of the gate terminal, the source terminal, and the drain terminal is connected to the corresponding source line. A semiconductor layer comprising the plurality of thin film transistors in the transistor processing The semiconductor layer of all thin film transistors connected to each specific wiring constituting the source line group or the gate line group (hereinafter referred to as a specific wiring group) is formed by printing as one printing unit, and the specific wiring Threshold value for forming a plurality of threshold correction lines on the substrate so as to be connected to the body terminals of all the thin film transistors connected to the corresponding specific wires and corresponding to the specific wires constituting the group Further includes correction line machining. Here, in the present invention, the source line processing or threshold correction line processing may be performed in an arbitrary order, and a part or all of any of the processing may be performed in parallel with other processing. . Further, “a plurality of lines are arranged” means that other lines are arranged at intervals in the horizontal direction of a certain line.

  In addition, the threshold value correction method for a thin film transistor array substrate according to the present invention is connected to each threshold correction line by applying a voltage to each threshold correction line in the thin film transistor array substrate manufactured by the method for manufacturing a thin film transistor array substrate. The threshold value of the thin film transistor is corrected.

  The thin film transistor array manufacturing method according to the present invention includes a source line processing for forming a source line group composed of a plurality of source lines arranged on a substrate on a substrate, and a gate line group composed of a plurality of gate lines arranged in parallel to the source. A plurality of thin film transistors each having a gate terminal, a source terminal, a drain terminal, and a body terminal formed on a substrate so as to three-dimensionally intersect a line group; and the plurality of source lines and the plurality of gate lines Transistor processing formed on the substrate so that any one of the gate terminal, the source terminal, and the drain terminal is connected to the corresponding source line. A plurality of display elements each having an electrode correspond to the plurality of thin film transistors and each electrode corresponds to a corresponding thin film transistor. Display element processing formed on the substrate so as to be connected to the drain terminal or the source terminal of a transistor, and in the transistor processing and the display element processing, a semiconductor layer constituting the plurality of thin film transistors; The plurality of display elements are formed by printing using all thin film transistors connected to each specific wiring and all display elements connected to all the thin film transistors as one printing unit, and constitute the specific wiring group Threshold correction line processing for forming a plurality of threshold correction lines on the substrate so as to be connected to the body terminals of all the thin film transistors connected to each of the corresponding specific wirings Further included. Here, in the present invention, the source line processing or the display element processing may be performed in an arbitrary order, and a part or all of any of the processing may be performed in parallel with other processing.

  Further, the brightness correction method of the display device according to the present invention is a display device using the thin film transistor array substrate manufactured by the method of manufacturing a thin film transistor array substrate, wherein each threshold value is applied by applying a voltage to each threshold correction line. The threshold value of the thin film transistor connected to the correction line is corrected, and thereby the luminance of the display element connected to each threshold value correction line via the thin film transistor is corrected.

  The thin film transistor array substrate according to the present invention includes a substrate, a source line group formed on the substrate, the source line group including a plurality of source lines arranged side by side, and the substrate line so as to intersect the source line group three-dimensionally. A three-dimensional intersection of the plurality of source lines and the plurality of gate lines each having a gate line group formed of a plurality of gate lines arranged in parallel to each other, a gate terminal, a source terminal, a drain terminal, and a body terminal. And a plurality of thin film transistors formed on the substrate so that any one of the gate terminal, the source terminal, and the drain terminal is connected to the corresponding source line. The semiconductor layers constituting the plurality of thin film transistors are connected to specific wirings constituting the source line group or the gate line group (hereinafter referred to as specific wiring group). The semiconductor layers of all the thin film transistors are formed by printing as one printing unit, and correspond to a plurality of specific wirings constituting the specific wiring group and are connected to the corresponding specific wirings. A plurality of threshold correction lines formed on the substrate to be connected to the body terminals of all the thin film transistors.

  In addition, a display device according to the present invention includes the thin film transistor array substrate, and corrects the threshold value of the thin film transistor connected to each threshold value correction line by applying a voltage to each threshold value correction line.

  The thin film transistor array substrate according to the present invention includes a substrate, a source line group formed on the substrate, the source line group including a plurality of source lines arranged side by side, and the substrate line so as to intersect the source line group three-dimensionally. A three-dimensional intersection of the plurality of source lines and the plurality of gate lines each having a gate line group formed of a plurality of gate lines arranged in parallel to each other, a gate terminal, a source terminal, a drain terminal, and a body terminal. A plurality of thin film transistors formed on the substrate so that each of the gate terminals is connected to at least one of the corresponding gate line and the source line, and an electrode, Each of the gate terminal, the source terminal, and the drain terminal corresponding to the plurality of thin film transistors corresponds to the corresponding source. A plurality of display elements formed on the substrate so as to be connected to a scan line, and a semiconductor layer constituting the plurality of thin film transistors and the plurality of display elements connected to each specific wiring All thin film transistors and all display elements connected to all the thin film transistors are each formed by printing as one printing unit, and correspond to a plurality of specific wirings constituting the specific wiring group and each And a plurality of threshold correction lines formed on the substrate so as to be connected to the body terminals of all the thin film transistors connected to the corresponding specific wiring.

  The display device according to the present invention corrects the threshold value of the thin film transistor connected to each threshold correction line by applying a voltage to each threshold correction line in the display device using the thin film transistor array substrate. Thus, the luminance of the display element connected to each threshold correction line via the thin film transistor is corrected.

  The present invention is configured as described above, and has an effect that it is possible to provide a method of manufacturing a thin film transistor array substrate that can eliminate unevenness in characteristics of a printing TFT.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the following description, the same or corresponding elements are denoted by the same reference symbols throughout the drawings, and redundant description thereof is omitted.

(Embodiment 1)
FIG. 1 is a circuit diagram showing an outline of the electrical configuration of the thin film transistor array substrate according to Embodiment 1 of the present invention. FIG. 2 is a plan view schematically showing the structure of the main part of the thin film transistor array substrate of FIG. 1 as a semiconductor device. 3 is a cross-sectional view schematically showing the structure of the main part of the thin film transistor array substrate of FIG. 1 as a semiconductor device, and FIG. 3A is a cross-sectional view taken along the line IIIA-IIIA of FIG. (B) is sectional drawing along the IIIB-IIIB line | wire of FIG.

  The thin film transistor array substrate 100 of this embodiment is used as a substrate constituting a display panel in a display device. Therefore, in practical use, a display element is formed on the thin film transistor array substrate 100. However, in the present embodiment, the use of the thin film transistor array substrate 100 is not more specifically limited than that for a display panel, and thus the display element is not shown.

[Constitution]
As shown in FIG. 1, the thin film transistor array substrate 100 includes a substrate 31 (see FIGS. 2 and 3). The substrate 31 is made of a material selected according to the type of display device. For example, a glass substrate, a flexible substrate, or the like is used as the substrate 31. Further, as the substrate 31, a transparent substrate and an opaque substrate are selectively used depending on the type of the display device.

  On the substrate 31, a plurality of source lines 102 are formed so as to be aligned with each other (here, in parallel), and these constitute a source line group 111. Further, a plurality of gate lines 101 are formed on the substrate 31 so as to be aligned with each other (here, in parallel), and these constitute a gate line group 112. The source line group 111 and the gate line group 112 are formed so as to three-dimensionally intersect with each other (here, orthogonal). A region defined by the plurality of source lines 102 and the plurality of gate lines 101 as viewed in the thickness direction of the substrate 31 constitutes a pixel. Therefore, the pixels are formed in a matrix, and a display screen is constituted by all the pixels. Here, the plurality of source lines 102 and the plurality of gate lines 101 are formed so as to extend in the column direction and the row direction of the display screen (in other words, the transistor array substrate 100), respectively. A display element (not shown) is formed in each pixel. In the present invention, a source line refers to a wiring that transmits a source signal (an image signal for each line), and a gate line refers to a control signal (hereinafter referred to as a pixel) for selecting a display element (in other words, a pixel) to which the source signal is to be written. (Referred to as a gate signal). A TFT (thin film transistor) 10 is formed so as to correspond to a three-dimensional intersection of the plurality of source lines 102 and the plurality of gate lines 101 (in other words, each pixel). The TFT 10 has four terminals including a gate terminal 11, a source terminal 12, a drain terminal 13, and a body terminal 14. The gate terminal 11 is connected to the corresponding gate line 101 of each TFT 10. The source terminal 12 is connected to the corresponding source line 102 of each TFT 10. The drain terminal 13 is connected to an electrode of a display element (not shown) corresponding to each TFT 10. Here, the source terminal (source) 12 and the drain terminal (drain) 13 of the TFT 10 are not substantially different in structure, and there is no significance in distinguishing these in terms of function. The names of the source terminal and the drain terminal are used to specify each of the pair of terminals of the source terminal and the drain terminal. When a transistor is used in an electronic circuit, the source terminal and the drain terminal of the transistor are reversed depending on whether the transistor is an N-channel type or a P-channel type.

  Further, a plurality of threshold correction lines 105 characterizing the present invention are formed on the substrate 31. In the present embodiment, each threshold correction line 105 is formed in parallel to the source line 102 corresponding to the source line 102. The reason why the threshold correction line 105 is formed corresponding to the source line 102 will be described later. Each threshold correction line 105 is connected to the body terminals 14 of all TFTs 10 whose source terminals 12 are connected to the corresponding source lines 102.

Next, the configuration of the TFT 10 will be described in detail. As shown in FIGS. 2 and 3, in the thin film transistor array substrate 100, the gate electrode 20 (the gate terminal 11 in FIG. 1) of the TFT 10 is formed immediately above the substrate 31. The gate electrode 20 is connected to a gate line 101 (not shown in FIGS. 2 and 3) that is also formed immediately above the substrate 31. The gate electrode 20 and the gate line 101 are, for example, a 50 nm thick Mo layer formed immediately above the substrate 31, a 200 nm thick Al layer formed thereon, and a 50 nm thick Mo layer formed thereon. It consists of and. A gate insulating film 21 is formed so as to cover the gate electrode 20 and the gate line 101 and the surface of the substrate 31 on which these are not formed. The gate insulating film 21 is made of, for example, PVP (polyvinylphenol). A source electrode 22A (source terminal 12 in FIG. 1) and a drain electrode 22B (drain terminal 13 in FIG. 1) are formed on the gate insulating film 21. The source electrode 22A and the drain electrode 22B are formed above the gate electrode 2 so as to face each other with a predetermined interval (see particularly FIG. 3). The source electrode 22A is connected to a source line 102 (not shown in FIGS. 2 and 3) formed on the gate insulating film 21. The drain electrode 22B is connected to one electrode of a display element (not shown in FIGS. 2 and 3) through a wiring 33 formed immediately above the substrate 31. On the gate insulating film 21, a body electrode 32 (the body terminal 14 in FIG. 1) is formed apart from the source electrode 22A and the drain electrode 22B. The body electrode 32 is connected to a threshold correction line 105 (not shown in FIGS. 2 and 3) that is also formed on the gate insulating film 21. As described above, since the body electrode 32 is formed of the same layer as the source electrode 22A and the drain electrode 22B, a new process does not increase in order to form a four-terminal TFT. The source electrode 22A, the drain electrode 22B, the body electrode 32, the source line 102, and the threshold correction line 105 are composed of, for example, a Cr layer formed immediately above the gate insulating film 21 and an Au layer formed thereon. ing. A partition film 23 is formed so as to cover the surface of the gate insulating film where the source electrode 22A, the drain electrode 22B, the body electrode 32, the source line 102, the threshold correction line 105, and these are not formed. The partition film 23 is made of an insulating film made of, for example, a photosensitive resin material having a thickness of about 1 μm. An opening 23 a that defines (defines) the position of the semiconductor layer 24 is formed in the partition film 23. The opening 23 a is located above the gate electrode 20 and is formed so as to straddle the source electrode 22 A, the drain electrode 22 B, and the body electrode 32. A semiconductor layer 24 is formed to fill the opening 23a. Accordingly, the semiconductor layer 24 is in contact with the source electrode 22A, the drain electrode 22B, and the body electrode 32. A portion of the semiconductor layer 24 located between the source electrode 22A and the drain electrode 22B constitutes a channel region, and the remaining portion forms a body region. The semiconductor layer 24 is composed of, for example, a bentacene layer having a thickness of 200 nm. In other words, the semiconductor layer 24 here is composed of an organic semiconductor layer. The material of the semiconductor layer 24 may be any material that can form a semiconductor layer by printing, and may be an organic semiconductor other than pentacene. Further, for example, an oxide semiconductor such as InGaZnO, an inorganic substance such as liquid silicon, silicon nanowire, or carbon nanotube may be used. Then, a passivation film 25 is formed so as to cover the partition film 23 and the semiconductor layer 24 in the opening 23a. The passivation film 25 is composed of, for example, a BCB (benzocyclobutene) film having a thickness of 300 nm. Then, an electrode of a display element (not shown) (for example, a pixel electrode made of ITO in the case of a liquid crystal display element) is formed on the passivation film 25. The electrode of this display element is connected to the wiring 33 by a contact hole (not shown). Although a bottom gate TFT is shown in FIGS. 2 and 3, a top gate TFT may be used. Even in this case, there is no increase in the number of new processes for producing the 4-terminal TFT.

[Production method]
Next, a method for manufacturing the thin film transistor array substrate 100 will be described.

  4 (a) to 4 (e) are cross-sectional views showing a method for manufacturing a main part of the transistor array substrate.

  In the step of FIG. 4A, a gate metal film is formed on the entire surface of the substrate 31. Specifically, as the gate metal film, a 50 nm thick Mo layer, a 200 nm thick Al layer, and a 50 nm thick Mo layer are sequentially formed on the substrate 31 by a sputtering method. Thereafter, the gate metal film is patterned using photolithography. Specifically, a photoresist is applied to a thickness of about 2 μm, and thereafter, exposure and development are performed so that the resist remains only in a portion where the gate metal film is to be left. Next, using this resist as a mask, the gate metal film is etched by wet etching, and then the resist is peeled off to complete the patterning. Thus, the gate electrode 20, the wiring 33, and the gate line 101 (not shown in FIG. 4A) are formed on the substrate 31.

  Next, in the process of FIG. 4B, the gate insulating film 21 is formed to a thickness of 400 nm on the entire surface of the substrate 31 on which the gate electrode 20, the wiring 33, and the gate line 101 are formed. The gate insulating film 21 is formed by applying PVP. Next, the gate insulating film is patterned using photolithography.

  Next, in the step of FIG. 4C, a source / drain electrode film is formed on the gate insulating film 21. The source / drain film is formed by sequentially depositing a Cr layer and an Au layer on the gate insulating film 21 to a total thickness of 200 nm by sputtering. Thereafter, the source / drain electrode film is patterned using photolithography, whereby the source electrode 22A, the drain electrode 22B, the source line 102, the body electrode 32 (see FIG. 2), and the threshold correction line 105 are formed at predetermined positions. The

  Next, in the step of FIG. 4D, a partition film 23 made of an insulating film is formed on the entire surface of the substrate 31 on which the step of FIG. 4C has been performed. The partition wall layer 23 is formed by applying a photosensitive resin material or the like to a thickness of about 1 μm. Next, an opening 23a is formed in the region of the partition film 23 where the semiconductor layer 24 is to be formed using photolithography.

  Next, a 200 nm-thick semiconductor layer 24 is formed in the opening 23a of the partition wall film 23 by ejecting an ink containing bentacene by an ink jet method.

  Next, in the step shown in FIG. 4E, a passivation film 25 is formed on the entire surface of the substrate 31 on which the step of FIG. The passivation film 25 is formed by applying BCB to a thickness of about 300 nm.

  Thereafter, an electrode of a display element (not shown) (for example, a pixel electrode made of ITO in the case of a liquid crystal display element) is formed on the passivation film 25.

  Thus, the thin film transistor array substrate 100 is completed.

  Next, the configuration of the method for manufacturing the thin film transistor array substrate will be described.

  FIG. 5 is a schematic diagram showing a configuration of a method for manufacturing a thin film transistor array substrate. As shown in FIG. 5, the thin film transistor array substrate manufacturing method includes source line processing for forming the source line group 111, gate line processing for forming the gate line group 112, and threshold correction line processing for forming the threshold correction line 105. And transistor processing for forming the thin film transistor 10 (including display element processing when applied to a specific application). In the present embodiment, these processes are performed in the order shown in FIG. Then, as illustrated in the step of FIG. 4C, some or all of these processes are performed in parallel with each other. Of course, the manufacturing method of the thin film transistor array substrate of the present invention is not limited to this, and these processes are performed in an arbitrary order and part or all of them in parallel with each other unless restricted by the manufacturing process. be able to.

[Function and effect]
Next, the effect of the thin film transistor array substrate will be described.

  FIG. 6 is a plan view schematically showing the configuration of the head of the ink jet apparatus which is a cause of the problem of the present invention.

  As shown in FIG. 6, the ink jet apparatus includes a linear head 120. In the head 120, a plurality (hereinafter, a predetermined number) of nozzles (ink ejection holes) 121 are formed in a line at a constant pitch in the major axis direction. Since the head 120 is commonly used for thin film transistor array substrates of various specifications, the pitch of the nozzles 121 is in principle the row direction of the thin film transistor array substrate 100 (the extending direction of the gate lines 101, hereinafter simply referred to as the row direction). ) Or the pitch of the openings 23a (see FIG. 3) of the partition wall film 23 in the column direction (the extending direction of the source line 102, hereinafter may be simply referred to as the column direction). Therefore, the head 120 is arranged so that the projection length (component of the pitch in the row direction or column direction) of the pitch of the nozzle 121 matches the pitch in the row direction or column direction of the openings 23a. The major axis is used with the direction inclined with respect to the row direction or the column direction of the openings 23a. Each nozzle 121 is positioned above the opening 23a, and the ink containing the material of the semiconductor layer 24 (here, bentacene) is ejected from each nozzle 121 to each opening 23a, whereby the semiconductor layer 24 is formed in each opening 23a. It is formed. Thus, since one semiconductor layer 24 is formed by one nozzle 121, the head 120 can form the semiconductor layers 24 for a predetermined number of pixels (a number equal to the number of nozzles 121) at a time.

  In order to form the semiconductor layer 24 over the entire surface of the substrate 31, for example, the head 120 is thin film transistor in a state where the direction of the major axis is inclined in the row direction of the thin film transistor array substrate 100 (more precisely, the substrate 31). Stopping for each row in the column direction of the array substrate 100 and moving the semiconductor layer 24 of a predetermined number of pixels (more precisely, TFTs 10) belonging to that row while forming them at once. When the formation of the semiconductor layer 24 of the predetermined number of pixels is completed for all the rows, one scan of the head 120 is completed, thereby completing one printing of the semiconductor layer 24. When the number of nozzles 121 (predetermined number) is less than the number of pixels belonging to each row, the scanning of the head 120 and the printing of the semiconductor layer 24 are repeated as many times as necessary. Thereby, the semiconductor layer 24 for all pixels can be formed over the entire surface of the substrate 31. In such a printing method of the semiconductor layer 24, printing (formation) of the semiconductors 24 of all the TFTs 10 belonging to each column performed by each nozzle 121 substantially constitutes one printing. Therefore, in the present invention, one printing performed by a substantial printing tool (here, the nozzle 121) is defined as a “printing unit”. In the present embodiment, the semiconductor layers 24 of all the TFTs 10 connected to one source line 102 form one printing unit.

  In general, in such an ink jet printing method, the thickness of the semiconductor layer 24 formed by each nozzle 121 varies depending on the performance of each nozzle 121 (specifically, the diameter of the ink ejection holes). In many cases, the nozzles 121 vary. For example, if printing is performed in the column direction as described above using such a nozzle, as a result, the electrical characteristics (more precisely, the drain current-gate-source voltage characteristics) of the TFT 10 in the thin film transistor array substrate 100 vary from column to column. However, in this embodiment, a threshold correction line 105 is formed in each column, and each threshold correction line 105 is connected to the body terminal 14 of the TFT 10 (pixel) belonging to the corresponding column. When a voltage is applied to the body terminal of the TFT 10, the electrical characteristics of the TFT 10 change as will be described later. Therefore, by applying a voltage that corrects variations in the electrical characteristics of the TFTs 10 between the columns to the body terminals 14 of the TFTs 10 in each column through the threshold correction line 105, the characteristic unevenness of the TFTs 10 can be eliminated. In the present embodiment, the reason why the threshold correction line 105 is formed so as to correspond to the source line 102 is that the semiconductor layer 24 of the TFT 10 is formed by moving the head 120 of the inkjet device in the column direction in this way. is there.

  Next, the principle of correcting the electrical characteristics of the TFT 10 will be described.

  FIG. 7 is a graph schematically showing drain current-gate-source voltage characteristics using the body potential of a four-terminal transistor as a parameter.

  As shown in FIG. 7, the threshold Vt of the gate-source voltage at which the drain current of the four-terminal MIS transistor begins to flow decreases as the body potential with respect to the source potential (hereinafter simply referred to as body potential or body voltage) increases. Substrate bias effect). In other words, in the 4-terminal MIS transistor, when the gate-source voltage is kept constant, the drain current increases as the body potential increases. It has been confirmed that the same effect occurs when the transistor is a TFT. Therefore, by applying an appropriate voltage to the body terminal 14 of the TFT 10, the drain current-gate-source voltage characteristic of the TFT 10 can be changed to a desired characteristic. FIG. 7 shows the characteristics of an N-channel transistor in which electrons are carriers. In a P-channel transistor in which holes serve as carriers, the threshold Vt of the gate-source voltage increases as the body potential increases.

  As described above, in this embodiment, the semiconductor layers 24 of all the TFTs 10 connected to each source line 102 form one printing unit, and correspond to each source line 102 with respect to that. A threshold correction line 105 is formed. Therefore, by applying a voltage that corrects the variation in the electrical characteristics of the TFT 10 between the source lines 105 (between the columns) to the body terminal 14 of the TFT 10 corresponding to each source line 102 through each threshold correction line 105. Unevenness in electrical characteristics of the TFT 10 can be eliminated.

  The printing unit and the threshold correction wiring are not limited to those described above. For example, the semiconductor layers 24 of all the TFTs 10 connected to each gate line 101 form one printing unit and each gate line 101. The threshold correction line 105 may be formed so as to correspond to.

(Embodiment 2)
The second embodiment of the present invention exemplifies a display device incorporating the thin film transistor array substrate of the first embodiment.

  FIG. 8 is a block diagram showing the configuration of the display device according to this embodiment. As shown in FIG. 8, the display device 50 according to the present embodiment includes the thin film transistor array substrate 100 according to the first embodiment. As described in the first embodiment, in practical use, a display element is formed in the drain of the TFT 10 in each pixel of the thin film transistor array substrate 100, and the thin film transistor array substrate 100 functions as a display panel.

  Examples of the display device 50 include a liquid crystal display device, an organic EL display device, an inorganic EL display device, and electronic paper. However, in a display device other than the liquid crystal display device, the configuration of the thin film transistor array substrate is different from that shown in the embodiment. The organic EL display device is exemplified in the fourth embodiment. However, the display devices other than these also have a common configuration in which threshold correction lines are provided corresponding to the printing units and each threshold correction line is connected to the body terminal of the TFT 10 in the corresponding printing unit. Therefore, in the following, only the case where the present invention is applied to a liquid crystal display device and an organic EL display device will be exemplified, but the embodiments in the case where the present invention is applied to other display devices are described in these embodiments. It can be inferred enough from

  A source signal output terminal of the source driver 53 is connected to each source line 102 (see FIG. 1) of the thin film transistor array substrate 100. A source signal is generated from the image signal of the source driver 53 and output to each source line 102. The gate signal output terminal of the gate driver 52 is connected to each gate line 101 (see FIG. 1) of the thin film transistor array substrate 100. The gate driver 52 outputs a gate signal to each gate line 101.

  A control circuit 54 is connected to the source driver 53 and the gate driver 52. The control circuit 54 receives an image signal and outputs it to the source driver 53, and controls the operations of the source driver 53 and the gate driver 52. Specifically, the control circuit 54 outputs a gate signal so that the gate driver 52 sequentially selects rows, and the source driver 43 outputs a source signal to be written to the selected row (pixel) in synchronization with this. The gate driver 52 and the source driver 53 are controlled to output. Thereby, in the pixels belonging to each column, the TFTs 10 are turned on in the order selected by the gate signal, and the corresponding source signals are written to the selected pixels in order. Thereby, an image corresponding to the image signal is displayed on the thin film transistor array substrate (display panel) 100.

  Further, a threshold correction voltage output terminal of the correction circuit 55 is connected to each threshold correction line 105 of the thin film transistor array substrate 100. The correction circuit 55 is connected to the control circuit 54. Under the control of the control circuit 54, the correction circuit 55 outputs a voltage (hereinafter referred to as a correction voltage) that corrects variation in the electrical characteristics of the TFT 10 between the source lines 105 (between columns) to each threshold correction line 105. To do.

  In general, it is necessary to know in advance the electrical characteristics of the thin film transistor array substrate 100 before forming a display element. For this, a known array inspection apparatus may be used (for example, see Japanese Patent No. 3275103). By inspecting the thin film transistor array substrate 100, it is possible to detect characteristic variations of the individual TFTs 10 constituting the substrate. Based on this result, a voltage to be applied to each threshold correction line 105 (voltage that cancels the variation in the electrical characteristics of the TFT 10) is calculated, and the calculated voltage is stored in the memory (in the correction circuit 55 as a correction voltage). (Not shown).

  Thus, when the display device 50 is lit, the correction circuit 55 outputs a correction voltage, and display is performed in that state. Therefore, luminance unevenness due to printing of the semiconductor layer 24 of the TFT 10 is eliminated.

  A method for detecting characteristics of the thin film transistor array substrate 100 other than the above may be used.

  Further, the control circuit 54 may incorporate the correction circuit 55.

(Embodiment 3)
Embodiment 3 of the present invention shows an example in which the display device of Embodiment 2 is a printing type liquid crystal display device.

  FIG. 9 is a circuit diagram showing an outline of the electrical configuration of the thin film transistor array substrate according to the present embodiment. FIG. 10 is a block diagram showing the configuration of the liquid crystal display device according to this embodiment.

  As shown in FIG. 9, in this embodiment, a liquid crystal display element 35 is connected to the drain terminal 13 of the TFT 10 in each pixel of the thin film transistor array substrate 130. Precisely, the pixel electrode of the liquid crystal display element 35 is connected to the drain terminal 13 of the TFT 10. Other configurations of the thin film transistor array substrate 130 are the same as those of the thin film transistor array substrate 100 of the first embodiment. The thin film transistor array substrate 130 constitutes an active matrix substrate of the liquid crystal display panel 21.

  Referring to FIG. 10, a liquid crystal display panel 210 includes a thin film transistor array substrate 130, a color filter substrate (not shown) disposed to face the thin film transistor array substrate 130, a thin film transistor array substrate 130, a color filter substrate, and the like. And a liquid crystal layer (not shown) sealed in a space between them. When the liquid crystal display device is a vertical electric field method, a counter electrode is formed on the color filter substrate, and when the liquid crystal display device is a horizontal electric field method, the counter electrode is formed on the thin film transistor array substrate 130.

  The liquid crystal display device 200 includes the liquid crystal display panel 210, a gate driver 220, a source driver 230, a control circuit 240, a correction circuit 250, a backlight (not shown), and a thin film film such as a polarizing plate. I have. Since the gate driver 220, the source driver 230, the control circuit 240, and the correction circuit 250 are configured in the same manner as in the second embodiment, description thereof is omitted. The liquid crystal display device 200 is configured as is well known except for the configuration relating to the correction of the electrical characteristics of the TFT 10, so detailed description and operation thereof will be omitted.

  According to the present embodiment, it is possible to eliminate luminance unevenness caused by the printing of the semiconductor layer 24 of the TFT 10 in the printing type liquid crystal display device.

(Embodiment 4)
Embodiment 4 of the present invention shows an example in which the display device of Embodiment 2 is a printing type organic EL display device.

  FIG. 11 is a circuit diagram showing an outline of the electrical configuration of the thin film transistor array substrate according to the present embodiment. FIG. 12 is a block diagram showing a configuration of the organic EL display device according to the present embodiment.

  As shown in FIG. 11, the thin film transistor array substrate 140 according to the present embodiment is different from the thin film transistor array substrate 100 according to the first embodiment in the following configuration, and the other configurations are the same.

  That is, in the thin film transistor array substrate 140 of the present embodiment, the light emitting element power supply line 103 is formed. A pixel selection TFT 41 is formed in each pixel, and its source terminal is connected to the source line 102 and its gate terminal is connected to the gate line 101. Each pixel is provided with a light emitting element driving TFT 40, its gate terminal 11 is connected to the drain terminal of the pixel selecting TFT 41, and its drain terminal 13 is connected to the light emitting element power supply line 103. A capacitor 42 is connected between the gate terminal 11 and the drain terminal 13 of the light emitting element driving TFT 40. A light emitting element 36 is connected to the source terminal 12 of the light emitting element driving TFT 40. Here, the light emitting element 36 is composed of an organic EL element. The body terminal 14 of the light emitting element driving TFT 40 is connected to the threshold correction line 105. In the present invention, the display element (the liquid crystal display element in the third embodiment, the light emitting element (organic EL element) in the present embodiment) is substantially driven (the gate of the image signal transmission path to the display element is configured. Alternatively, the electrical characteristics of the TFT (which drives the display element in accordance with the image signal) are to be corrected. This is because correcting the display unevenness is an object of the invention. Therefore, in this embodiment, the TFT whose electric characteristics are to be corrected is not the pixel selection TFT 41 but the light emitting element driving TFT 41. Therefore, in the present invention, a TFT whose electric characteristics are to be corrected has its gate terminal 11 connected to the source line 102 (via the pixel selection TFT 41) (this embodiment), or The source terminal 12 is connected to the source line 101 (the first embodiment), and the source terminal 12 (the present embodiment) or the drain terminal 13 (the first embodiment) is connected to the display element.

  Referring to FIG. 12, an organic EL display device 300 includes an organic EL panel 310 including a thin film transistor array substrate 140 and a printed organic EL layer (not shown) formed thereon, a gate driver 320, and a source. A driver 330, a control circuit 340, a correction circuit 350, and a thin film (not shown) such as a polarizing plate are provided. In the thin film transistor array 140, the printing unit of the semiconductor layer 24 of the light emitting element driving TFT 41 and the printing unit of the printing type organic EL layer are formed for each column. The printable organic EL layer may include a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, and the like in addition to the light emitting layer in order to improve the characteristics of the organic EL. In addition, the gate driver 320, the source driver 330, the control circuit 340, and the correction circuit 350 are configured in the same manner as in the second embodiment, and thus description thereof is omitted.

  In the organic EL display device 300 configured as described above, in the selected pixel, a source signal is input from the source line 102 to the gate terminal of the light emitting element driving TFT 41 through the selection TFT 41 during the writing period. The capacitor 42 is charged to a voltage corresponding to the input source signal. As a result, the light emitting element driving TFT 41 supplies the light emitting element 36 with a drain current corresponding to the voltage of the capacitor 42 as the gate voltage (source-gate voltage). As a result, the light emitting element 36 emits light with a luminance corresponding to the source signal.

  On the other hand, the electrical characteristics of each light emitting element driving TFT 41 are corrected by the correction circuit 350. As a result, luminance unevenness due to printing of the semiconductor layer 24 of the TFT 10 in the printing type organic EL display device is eliminated.

  In the present embodiment, an inorganic EL element may be used as the light emitting element instead of the organic EL element, and the same effect as in the case of the organic EL element can be obtained.

(Embodiment 5)
FIG. 13 is a circuit diagram showing an outline of the electrical configuration of the thin film transistor array substrate according to the fifth embodiment of the present invention.

  In this embodiment, all threshold correction lines 105 are connected to one common wiring 106. Other than this, the third embodiment is the same as the third embodiment. According to such a configuration, by applying a desired voltage to the common wiring 106, the electrical characteristics of all the TFTs 10 constituting the thin film transistor array substrate 150 can be corrected at a time.

  In the first, second and fourth embodiments, similar effects can be obtained by forming the common wiring as in the present embodiment.

(Embodiment 6)
FIG. 14 is a circuit diagram showing an outline of the electrical configuration of the thin film transistor array substrate according to Embodiment 6 of the present invention.

  In the present embodiment, all the semiconductor layers 24 of the thin film transistor substrate 160 are formed by printing a plurality of times (here, m times). As described in the first embodiment, one printing of the semiconductor layer 24 (hereinafter sometimes simply referred to as printing) is performed by one scan of the head 120 (see FIG. 6). Each threshold correction line 105 corresponding to each nozzle 121 of the head 120 is connected to each common wiring 106 in common for all printing. In other words, the thin film transistor substrate 160 corresponds to each printing unit in one printing (here, as described in the first embodiment, all the semiconductor layers 24 of the TFTs 10 connected to each source line 102). Thus, the number (n) of common wires 106-1 to 106-n equal to the number of nozzles 121 (here, n) of the head 120 is formed. In all the printing operations (m times), the threshold correction line 105 corresponding to each printing unit is connected to the common wirings 106-1 to 106-n corresponding to each printing unit. Accordingly, m threshold correction lines 105 are connected to the common wirings 106-1 to 106-n.

  According to such a configuration, the following effects can be obtained. The variation in the electrical characteristics of the TFTs 10 between the columns due to the variation in the performance of the nozzles 121 of the head 120 appears in the same manner for each printing. Therefore, by applying a predetermined correction voltage to each of the common wirings 106-1 to 106-n, the electrical characteristics of all the TFTs 10 constituting the array substrate 150 formed by a plurality of printing operations can be corrected at a time. Can do.

  In the first, second and fourth embodiments, similar effects can be obtained by forming the common wiring as in the present embodiment.

(Embodiment 7)
FIG. 14 is a block diagram showing a configuration of a print-type liquid crystal display device according to Embodiment 7 of the present invention.

  The print type liquid crystal display device 500 of the present embodiment is the same as the print type liquid crystal display device 200 of the third embodiment except for the following differences. Hereinafter, this difference will be described.

  In the print type liquid crystal display device 500 of the present embodiment, a current measurement circuit 520 is inserted between the source driver 230 and the liquid crystal panel 210. The current measurement circuit 520 detects the current flowing through the source line 102 and inputs this to the correction circuit 250. When the current detected by the current measurement circuit 520 falls below a certain reference value, that is, when the electrical characteristics of the TFT 10 deteriorate from the initial state, the correction circuit 250 reduces this deterioration to a voltage that corrects printing variations. A voltage obtained by adding the correction voltage is output to the threshold correction line 105 corresponding to the column (source line 102) in which the deterioration is detected. As a result, the deterioration of the electrical characteristics of the TFT 10 connected to the threshold correction line 105 is corrected. As a result, the luminance deterioration of the liquid crystal display device 500 is corrected.

  In the fourth embodiment, each column is provided with a current line through which the drive current of all the light emitting elements belonging to the column flows, and the above-described current measurement circuit 520 is configured to detect the current of each current line. By configuring the correction circuit 250 as described above, the same effects as those of the present embodiment can be obtained also in the print type organic EL display device.

  Note that the luminance deterioration correction method described above is not limited to the above-described aspect. For example, the deterioration characteristic of the TFT 10 is stored in advance in a memory built in the correction circuit 250, and the correction circuit 250 calculates a deterioration correction voltage based on the deterioration characteristic and uses this to correct printing variations. You may comprise so that it may add to. Further, the correction circuit 250 may be configured to simply calculate a deterioration correction voltage based on the integrated drive time of the display device using a timer.

  In the above embodiment, an inkjet method is used as a printing method. However, the present invention is not limited to this, and roll printing, letterpress printing, intaglio printing, screen printing, dispenser drawing, etc. are generally used at present. Can be used.

  INDUSTRIAL APPLICABILITY The thin film transistor array substrate manufacturing method and threshold value correcting method, display device brightness correcting method, thin film transistor array substrate, and display device of the present invention are useful for various display manufacturing methods and displays for computers and home appliances. It is.

It is a circuit diagram which shows the outline | summary of the electrical constitution of the thin-film transistor array substrate which concerns on Embodiment 1 of this invention. It is a top view which shows typically the structure as a semiconductor device of the principal part of the thin-film transistor array substrate of FIG. FIG. 3 is a cross-sectional view schematically showing a structure of a main part of the thin film transistor array substrate of FIG. 1 as a semiconductor device, in which FIG. 3A is a cross-sectional view taken along line IIIA-IIIA in FIG. 2 and FIG. FIG. 3 is a sectional view taken along line IIIB-IIIB in FIG. 2. 4 (a) to 4 (e) are cross-sectional views showing a method for manufacturing a main part of the transistor array substrate. It is a schematic diagram which shows the structure of the manufacturing method of a thin-film transistor array substrate. It is a top view which shows typically the structure of the head of the inkjet apparatus used as the cause of the subject of this invention. It is a graph which shows typically the drain current-gate-source voltage characteristic which used the body potential of the 4-terminal transistor as a parameter. It is a block diagram which shows the structure of the display apparatus which concerns on Embodiment 2 of this invention. It is a circuit diagram which shows the outline | summary of the electrical constitution of the thin-film transistor array substrate which concerns on Embodiment 3 of this invention. It is a block diagram which shows the structure of the liquid crystal display device which concerns on Embodiment 3 of this invention. It is a circuit diagram which shows the outline | summary of the electrical constitution of the thin-film transistor array substrate which concerns on Embodiment 4 of this invention. It is a block diagram which shows the structure of the organic electroluminescence display which concerns on Embodiment 4 of this invention. It is a circuit diagram which shows the outline | summary of the electrical constitution of the thin-film transistor array substrate concerning Embodiment 5 of this invention. It is a circuit diagram which shows the outline | summary of the electrical structure of the thin-film transistor array substrate which concerns on Embodiment 6 of this invention. It is a block diagram which shows the structure of the printing type liquid crystal display device which concerns on Embodiment 7 of this invention.

Explanation of symbols

10 Thin film transistor (TFT)
DESCRIPTION OF SYMBOLS 11 Gate terminal 12 Source terminal 13 Drain terminal 14 Body terminal 20 Gate electrode 21 Gate insulating film 22A Source electrode 22B Drain electrode 23 Partition 23 Opening 24 Semiconductor layer 25 Passivation film 32 Body electrode 33 Wiring 35 Liquid crystal display element 36 Light emitting element (organic EL) element)
40 Light-emitting element driving TFT
41 Pixel selection TFT
50 Display device 52, 220, 320 Gate driver 53, 230, 330 Source driver 54, 240, 340 Control circuit 55, 250, 350 Correction circuit 100, 130, 140, 150, 160 Thin film transistor array substrate 101 Gate line 102 Source line 103 Power supply line for light emitting element 105 Threshold correction line 106, 106-1 to 106-n Common wiring 111 Source line group 112 Gate line group 120 Head 121 Nozzle 200,500 Print type liquid crystal display device 210 Liquid crystal panel 220 Gate driver 230 Source driver 300 Print-type organic EL display device 310 Organic EL panel 500 LCD display device 520 Current measurement circuit

Claims (8)

Source line processing for forming a source line group consisting of a plurality of source lines arranged on a substrate on a substrate;
Gate line processing that forms a gate line group consisting of a plurality of gate lines arranged on the substrate so as to three-dimensionally intersect the source line group; and
A plurality of thin film transistors each having a gate terminal, a source terminal, a drain terminal, and a body terminal correspond to a three-dimensional intersection of the plurality of source lines and the plurality of gate lines, and each of the gate terminals, the source terminals, and Forming a transistor on the substrate such that any one of the drain terminals is connected to the corresponding source line, and
In the transistor processing, the semiconductor layers constituting the plurality of thin film transistors are the semiconductor layers of all thin film transistors connected to the specific wirings constituting the source line group or the gate line group (hereinafter, specific wiring group). Formed by printing as one printing unit,
In addition, a plurality of threshold correction lines are connected to the body terminals of all the thin film transistors corresponding to the plurality of specific lines constituting the specific line group and connected to the corresponding specific lines, respectively. A method for manufacturing a thin film transistor array substrate, further comprising processing a threshold correction line formed on the thin film transistor array substrate. In the thin film transistor array substrate manufactured by the method of manufacturing a thin film transistor array substrate according to claim 1,
A threshold correction method for a thin film transistor array substrate, wherein a threshold value of a thin film transistor connected to each threshold correction line is corrected by applying a voltage to each threshold correction line. Source line processing for forming a source line group consisting of a plurality of source lines arranged on a substrate on a substrate;
Gate line processing that forms a gate line group consisting of a plurality of gate lines arranged on the substrate so as to three-dimensionally intersect the source line group; and
A plurality of thin film transistors each having a gate terminal, a source terminal, a drain terminal, and a body terminal correspond to a three-dimensional intersection of the plurality of source lines and the plurality of gate lines, and each of the gate terminals, the source terminals, and Transistor processing formed on the substrate such that any one of the drain terminals is connected to each corresponding source line;
A plurality of display elements each having an electrode are formed on the substrate so as to correspond to the plurality of thin film transistors and each electrode is connected to the drain terminal or the source terminal of each corresponding thin film transistor Processing, and
In the transistor processing and the display element processing, the semiconductor layers constituting the plurality of thin film transistors and the plurality of display elements include all thin film transistors connected to each specific wiring and all display elements connected to all the thin film transistors. Are formed by printing each as a printing unit,
In addition, a plurality of threshold correction lines are connected to the body terminals of all the thin film transistors corresponding to the plurality of specific lines constituting the specific line group and connected to the corresponding specific lines, respectively. A method for manufacturing a thin film transistor array substrate, further comprising processing a threshold correction line formed on the thin film transistor array substrate. In the display apparatus using the thin-film transistor array substrate manufactured by the manufacturing method of the thin-film transistor array substrate according to claim 3,
By applying a voltage to each threshold correction line, the threshold value of the thin film transistor connected to each threshold correction line is corrected, thereby correcting the luminance of the display element connected to each threshold correction line via the thin film transistor. , Brightness correction method for display device. A substrate,
A source line group formed of a plurality of source lines arranged on the substrate,
A gate line group comprising a plurality of gate lines arranged on the substrate so as to three-dimensionally intersect the source line group;
Each of the gate terminal, the source terminal, and the drain terminal has a gate terminal, a source terminal, a drain terminal, and a body terminal, and corresponds to a three-dimensional intersection of the plurality of source lines and the plurality of gate lines. A plurality of thin film transistors formed on the substrate so as to be connected to each corresponding source line,
The semiconductor layers constituting the plurality of thin film transistors are configured such that the semiconductor layers of all thin film transistors connected to the specific wirings constituting the source line group or the gate line group (hereinafter, specific wiring group) are used as one printing unit. Formed by printing,
And a plurality of formed on the substrate so as to be connected to the body terminals of all the thin film transistors corresponding to the plurality of specific wirings constituting the specific wiring group and connected to the corresponding specific wirings, respectively. A thin film transistor array substrate further comprising a threshold correction line.   A display device comprising the thin film transistor array substrate according to claim 5, wherein a threshold value of a thin film transistor connected to each threshold correction line is corrected by applying a voltage to each threshold correction line. A substrate,
A source line group formed of a plurality of source lines arranged on the substrate,
A gate line group comprising a plurality of gate lines arranged on the substrate so as to three-dimensionally intersect the source line group;
Each of the gate terminal, the source terminal, and the drain terminal has a gate terminal, a source terminal, a drain terminal, and a body terminal, and corresponds to a three-dimensional intersection of the plurality of source lines and the plurality of gate lines. A plurality of thin film transistors formed on the substrate such that any one of is connected to each corresponding source line;
A plurality of display elements formed on the substrate, each having an electrode, corresponding to the plurality of thin film transistors, and connected to the drain terminal or the source terminal of each corresponding thin film transistor; And comprising
The semiconductor layers constituting the plurality of thin film transistors and the plurality of display elements are formed by printing using all thin film transistors connected to each specific wiring and all display elements connected to all the thin film transistors as one printing unit. It has been
And a plurality of formed on the substrate so as to be connected to the body terminals of all the thin film transistors corresponding to the plurality of specific wirings constituting the specific wiring group and connected to the corresponding specific wirings, respectively. A thin film transistor array substrate further comprising a threshold correction line. In the display device using the thin film transistor array substrate according to claim 7,
By applying a voltage to each threshold correction line, the threshold value of the thin film transistor connected to each threshold correction line is corrected, thereby correcting the luminance of the display element connected to each threshold correction line via the thin film transistor. , Display device.

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