JP2008083171A - Pixel drive circuit and image display apparatus - Google Patents

Pixel drive circuit and image display apparatus Download PDF

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JP2008083171A
JP2008083171A JP2006260632A JP2006260632A JP2008083171A JP 2008083171 A JP2008083171 A JP 2008083171A JP 2006260632 A JP2006260632 A JP 2006260632A JP 2006260632 A JP2006260632 A JP 2006260632A JP 2008083171 A JP2008083171 A JP 2008083171A
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pixel
electrode
light emitting
display
current
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JP4748456B2 (en
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Manabu Takei
学 武居
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Casio Comput Co Ltd
カシオ計算機株式会社
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a pixel drive circuit and an image display apparatus capable of driving the light emitting elements in the brightness matching the display data by suppressing the difference between the write current (specified current) and the light emission drive current (output current) caused by the voltage changes when driving the display pixels (pixel drive circuit). <P>SOLUTION: In the pixel drive circuit DC, double gate transistors Tr13 serving as a light emission drive switch and organic EL elements OLED are connected in series. In the double gate transistor Tr13, its bottom gate terminal BG is connected to the contact N11 to apply the control voltage, its drain terminal D to the power source voltage line VL, and its top gate terminal TG and source terminal S together to the contacts N12 which is connected to the anode terminal of the organic EL element OLED. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a pixel driving circuit and an image display device, and in particular, a pixel driving circuit for causing a current-controlled light emitting element to emit light at a predetermined luminance gradation based on a light emission driving current according to a gradation signal, The present invention also relates to an image display apparatus including a display panel in which display pixels each including the pixel driving circuit and the light emitting element are two-dimensionally arranged.

  Conventionally, an organic electroluminescent device (hereinafter abbreviated as “organic EL device”), a light emitting diode (LED), etc., emits light with a predetermined luminance gradation according to the current value of the supplied drive current. 2. Description of the Related Art A light emitting element type display (image display device) including a display panel in which display pixels each having a current control type light emitting element are two-dimensionally arranged is known.

  In particular, a light-emitting element type display using an active matrix driving method has a higher display response speed than a liquid crystal display (LCD) widely used in various electronic devices including portable devices in recent years. With less viewing angle dependency, high brightness, high contrast, high definition of display image quality, etc. are possible, and unlike the case of liquid crystal display devices, no backlight is required, making it even thinner and lighter It has an extremely advantageous feature that it is possible, and research and development are actively conducted as a next-generation display.

  In such a light emitting element type display, various drive control mechanisms and control methods for controlling light emission of the above-described current control type light emitting element have been proposed. For example, as described in Patent Document 1 and the like, for each display pixel constituting the display panel, in addition to the light-emitting element, a drive circuit including a plurality of switching means for controlling light emission of the light-emitting element ( A pixel drive circuit or a light emission drive circuit) is known.

Hereinafter, a display device including a pixel driving circuit in the prior art will be briefly described.
FIG. 12 is a schematic configuration diagram showing a main part of a light emitting element type display in the prior art, and FIG. 13 is a configuration example of display pixels (pixel driving circuit and light emitting element) applicable to the light emitting element type display in the prior art. FIG.

  As shown in FIG. 12, an active matrix light-emitting element type display described in Patent Document 1 or the like roughly includes a plurality of scanning lines (selection lines) SLp and data lines (signals) arranged in the row and column directions. Line) near each intersection of DLp, a display panel 110P in which a plurality of display pixels EMp are arranged in a matrix, a scanning driver (scanning line driving circuit) 120P connected to each scanning line SLp, and each data line DLp Connected to the data driver (data line driving circuit) 130P, and the data driver 130P generates a gradation signal voltage Vpix corresponding to the display data and supplies it to each display pixel EMp via each data line DLp. It has a configuration.

  Here, for example, as shown in FIG. 13, each display pixel EMp includes a thin film transistor (TFT) Tr111 having a gate terminal connected to the scanning line SLp, a source terminal and a drain terminal connected to the data line DLp and the contact N111, and a gate. A pixel driving circuit DCp including a thin film transistor Tr112 having a terminal connected to the contact N111 and a ground potential Vgnd applied to a source terminal; and an anode terminal connected to a drain terminal of the thin film transistor Tr112 of the pixel driving circuit DCp; An organic EL element (current control type light emitting element) OLED having a low power supply voltage Vss lower than the ground potential Vgnd is applied to the cathode terminal.

  In FIG. 13, Cp is a parasitic capacitance (retention capacitance) formed between the gate and source electrodes of the thin film transistor Tr112. The thin film transistor Tr111 is formed of an n-channel field effect transistor, and the thin film transistor Tr112 is formed of a p-channel field effect transistor.

  In the display device including the display panel 110P including the display pixels EMp having such a configuration, first, a scanning signal Vsel of a selection level (high level) is sequentially applied from the scanning driver 120P to the scanning line SLp of each row. As a result, the thin film transistor Tr111 of the display pixel EMp (pixel drive circuit DCp) for each row is turned on, and the display pixel EMp is set to the selected state.

  In synchronization with this selection timing, a grayscale signal Vpix having a voltage value corresponding to display data is generated by the data driver 130P and applied to the data line DLp of each column, whereby the grayscale signal Vpix is displayed on each display. The voltage is applied to the contact N111 (that is, the gate terminal of the thin film transistor Tr112) via the thin film transistor Tr111 of the pixel EMp (pixel drive circuit DCp). As a result, the thin film transistor Tr112 is turned on in a conductive state corresponding to the gradation signal Vpix, and a predetermined light emission drive current flows from the ground potential Vgnd to the low power supply voltage Vss via the thin film transistor Tr112 and the organic EL element OLED. The EL element OLED emits light at a luminance gradation corresponding to display data.

  Next, by applying a non-selection level (low level) scanning signal Vsel from the scanning driver 120P to the scanning line SLp, the thin film transistor Tr111 of the display pixel EMp in each row is turned off, and the display pixel EMp is turned off. The selected state is set, and the data line DLp and the pixel driving circuit DCp are electrically disconnected. At this time, based on the voltage applied to the gate terminal of the thin film transistor Tr112 and held in the parasitic capacitance Cp, the thin film transistor Tr112 is maintained in an on state, and, similarly to the selected state, a predetermined potential from the ground potential Vgnd. The light emission drive current flows to the organic EL element OLED through the thin film transistor Tr112, and the light emission operation is continued. This light emission operation is controlled so as to continue, for example, for one frame period until the gradation signal voltage Vpix corresponding to the next display data is applied (written) to the display pixel EMp of each row.

  Such a drive control method adjusts the voltage (gradation signal voltage Vpix) applied to each display pixel EMp (the gate terminal of the thin film transistor Tr112 of the pixel drive circuit DCp), thereby causing a light emission drive current to flow through the organic EL element OLED. This is called a voltage designation type (or voltage application type) gradation control method because the light emission operation is performed with a predetermined luminance gradation.

  By the way, in the display pixel EMp provided with the pixel drive circuit DCp corresponding to such a voltage designation type gradation control method, element characteristics (channel resistance and the like) of the thin film transistor Tr111 having a selection function and the thin film transistor Tr112 having a light emission drive function. ) Varies or varies (deteriorates) depending on the external environment (ambient temperature, etc.), usage time, etc., the light emission drive current supplied to the light emitting element (organic EL element OLED) varies. Therefore, there is a problem that it is difficult to stably realize desired light emission characteristics (display with a predetermined luminance gradation) over a long period of time.

  Further, when each display pixel is miniaturized in order to increase the definition of the display panel, variation in operation characteristics (such as a source-drain current) of the thin film transistors Tr111 and Tr112 included in the pixel driving circuit DCp increases. Appropriate gradation control cannot be performed, and there is a problem that the display image quality is deteriorated due to variations in the light emission characteristics of each display pixel.

  Thus, as a configuration for solving such a problem, a configuration of a pixel driving circuit corresponding to a current designation type (or current application type) gradation control method is known. A specific configuration example of the display pixel (pixel drive circuit) corresponding to the current-designated gradation control method will be described in detail in “Best Mode for Carrying Out the Invention” described later. The following configurations and operations (functions) are provided.

  That is, in the pixel drive circuit corresponding to the current designation type gradation control method, for example, at least the display pixel is set to the selected state, and the gradation signal corresponding to the display data is supplied to the display pixel (pixel drive circuit). Selection control means for controlling the writing operation (corresponding to the above-described thin film transistor Tr111), and the current value of the light emission driving current supplied to the light emitting element (organic EL element or the like) based on the written gradation signal and its supply Drive current control means for controlling the state (corresponding to the above-mentioned thin film transistor Tr112 and parasitic capacitance Cp) is provided, and a scanning signal of a selection level is applied to the selection control means, at a timing set to the selection state. By passing a gradation current (gradation signal) with a current value corresponding to the display data, it is converted into a voltage component by the drive current control means and stored. As well as, by supplying a light emission drive current having the current value based on the voltage component in the non-selected state to a light-emitting element, and is configured to continuously emit light emitting element at a predetermined luminance gradation.

  Therefore, in the drive current control means, a function (current / voltage conversion function) for converting the current level of the gradation current corresponding to the display data supplied to each display pixel into a voltage level, and a predetermined value based on the voltage level Since both the function of supplying a light emission drive current having a current value to the light emitting element (light emission drive function) is realized, by configuring the drive current control means with a single active element (thin film transistor), An advantage is that it is possible to suppress the phenomenon that the light emission drive current fluctuates and the display image quality deteriorates due to the variation in operation characteristics between the plurality of thin film transistors in the pixel drive circuit DCp as shown in FIG. Have.

JP 2002-156923 A (pages 3 to 4, FIGS. 1 and 2)

However, the image display device including the display panel in which the display pixels having the pixel driving circuit as described above are two-dimensionally arranged has the following problems.
That is, in the drive control method in which each display pixel emits light at a luminance gradation corresponding to display data by causing the light emission drive current generated by the pixel drive circuit (drive current control means) to flow through the light emitting element. A current path of a thin film transistor serving as a current control means is connected in series to a light emitting element (organic EL element, etc.), and a series circuit including the thin film transistor and the light emitting element is connected to a predetermined voltage source (a certain potential difference). The circuit configuration is adopted.

  In such a circuit configuration, when the thin film transistor serving as the drive current control means is turned on and off (by switching control), a phenomenon in which the voltage applied to the light emitting element relatively fluctuates occurs. Although specifically described later, for example, in the above-described current designation type gradation control method, the control voltage (gate voltage) applied to the thin film transistor changes with the switching control of the drive current control means, and the thin film transistor of the thin film transistor The voltage applied to both ends of the current path changes, so that the output current value of the light emission driving current supplied to the light emitting element is different from the specified current value of the gradation current (write current) in the write operation. Therefore, the light emitting element cannot be operated to emit light with an appropriate luminance gradation according to display data, and there is a problem that the display image quality is deteriorated due to a decrease in contrast or the like.

  Accordingly, in view of the above-described problems, the present invention provides a write current (designated current) and a light emission drive current that are generated due to voltage changes that occur when driving display pixels (pixel drive circuits) that are two-dimensionally arranged on the display panel. A pixel driving circuit capable of causing a light emitting element to emit light with an appropriate luminance gradation according to display data while suppressing a difference in (output current), and an image display device capable of suppressing deterioration in display image quality The purpose is to provide.

  According to a first aspect of the present invention, a light emission driving current having a current value corresponding to a gradation signal is supplied to a current control type light emitting element provided in a display pixel, and a predetermined value based on the gradation signal is supplied. In a pixel driving circuit that performs light emission operation at a luminance gradation, at least a charge holding unit that holds a charge based on the gradation signal as a voltage component, and the light emission driving current based on the voltage component held in the charge holding unit Drive current control means for generating and supplying to the light emitting element, wherein the drive current control means includes a first gate electrode and a second gate electrode provided to face each other across the semiconductor layer. A double-gate thin film transistor structure having a source electrode and a drain electrode provided at both ends of the semiconductor layer, the source electrode being connected to one end of the light emitting element, Wherein the gate electrode is set to be the same as the potential of the source electrode.

According to a second aspect of the present invention, in the pixel drive circuit according to the first aspect, the drive current control means is such that the first gate electrode and the source electrode are electrically connected.
According to a third aspect of the present invention, in the pixel driving circuit according to the first or second aspect, the light emitting element includes a pixel electrode, a light emitting layer provided on the pixel electrode, and the pixel electrode via the light emitting layer. And the drive current control means is characterized in that the first gate electrode and the source electrode are electrically connected to the pixel electrode.

According to a fourth aspect of the present invention, in the pixel drive circuit according to the third aspect, the drive current control means is characterized in that the first gate electrode is formed integrally with the pixel electrode.
According to a fifth aspect of the present invention, in the pixel drive circuit according to the third or fourth aspect, the light emitting element is characterized in that the pixel electrode is formed of an electrode material having light transmission characteristics.

According to a sixth aspect of the present invention, in the pixel drive circuit according to the third or fourth aspect, the light emitting element is characterized in that the pixel electrode is formed of an electrode material having light reflection characteristics.
According to a seventh aspect of the present invention, in the pixel drive circuit according to any one of the first to sixth aspects, the drive current control means is provided so that the source electrode and the drain electrode extend on the semiconductor layer. It is characterized by being.

According to an eighth aspect of the present invention, in the pixel driving circuit according to the seventh aspect, the drive current control means has a block insulating film on the semiconductor layer, and the source electrode and the drain electrode are on the block insulating film. It is provided so that it may extend.
According to a ninth aspect of the present invention, in the pixel driving circuit according to any one of the first to eighth aspects, the pixel driving circuit controls a timing of supplying the grayscale signal to the charge holding unit. Means are provided.

According to a tenth aspect of the present invention, in the pixel driving circuit according to the ninth aspect, the gradation signal control means has a double gate type thin film transistor structure, and the gate electrode provided above the semiconductor layer is light-shielding. It is formed of an electrode material.
According to an eleventh aspect of the present invention, in the pixel drive circuit according to the first or tenth aspect, in the double-gate thin film transistor, the semiconductor layer is made of amorphous silicon.
According to a twelfth aspect of the present invention, in the pixel drive circuit according to any one of the first to eleventh aspects, the gradation signal is a signal current having a current value corresponding to the luminance gradation. .

  According to a thirteenth aspect of the present invention, with respect to a plurality of display pixels arranged near intersections of a plurality of scanning lines and a plurality of signal lines arranged so as to be orthogonal to the display panel, the signal lines are arranged. In the image display device for displaying desired image information on the display panel by supplying a gradation signal according to display data, each display pixel includes a current control type light emitting element and the light emitting element. A pixel driving circuit for controlling the light emission operation of the pixel, the pixel driving circuit holding at least a charge based on the gradation signal as a voltage component, and a voltage component held by the charge holding unit Based on the driving current control means for generating the light emission driving current and supplying the light emitting element to the light emitting element, and the gradation signal control for controlling the timing of supplying the gradation signal to the charge holding means. And the drive current control means includes a first gate electrode and a second gate electrode provided to face each other across the semiconductor layer, source electrodes provided at both ends of the semiconductor layer, and A double gate type thin film transistor structure including a drain electrode, the source electrode is connected to one end of the light emitting element, and the first gate electrode is set to be equal to the potential of the source electrode. It is characterized by.

  According to a fourteenth aspect of the present invention, in the image display device according to the thirteenth aspect, the image display device is provided in at least the display pixel connected to the scan line by applying a selection signal to the scan line. Further, the grayscale signal control means sets a scanning drive means for setting the grayscale signal to the display pixel to be selected, and the display data corresponding to the display pixel set to the selected state. And a signal driving means for generating the gradation signal based on the signal and supplying the gradation signal to the signal line.

According to a fifteenth aspect of the present invention, in the image display device according to the fourteenth aspect, the gradation signal supplied from the signal driving unit is a signal current having a current value corresponding to the display data. To do.
According to a sixteenth aspect of the present invention, in the image display device according to any one of the thirteenth to fifteenth aspects, the driving current control means provided in the pixel driving circuit is configured such that the first gate electrode and the source electrode are electrically connected. It is characterized by being connected.

  According to a seventeenth aspect of the present invention, in the image display device according to the fifteenth or sixteenth aspect, the light emitting element includes a pixel electrode, a light emitting layer provided on the pixel electrode, and the pixel electrode via the light emitting layer. The driving current control means provided in the pixel driving circuit is configured such that the first gate electrode and the source electrode are electrically connected to the pixel electrode. It is characterized by that.

According to an eighteenth aspect of the present invention, in the image display device according to the seventeenth aspect, in the drive current control means provided in the pixel drive circuit, the first gate electrode is formed integrally with the pixel electrode. It is characterized by that.
According to a nineteenth aspect of the present invention, in the image display device according to any one of the thirteenth to eighteenth aspects, the light emitting element is an organic electroluminescent element.

  According to the pixel drive circuit and the image display apparatus according to the present invention, the write current (designated current) and the light emission caused by the voltage change that occurs when driving the display pixels (pixel drive circuit) arranged two-dimensionally on the display panel. A difference in driving current (output current) can be suppressed, and the light emitting element can be operated to emit light at an appropriate luminance gradation according to display data, so that deterioration in display image quality can be suppressed.

Hereinafter, an image display apparatus including a pixel driving circuit according to the present invention and a display panel in which display pixels including the pixel driving circuit are two-dimensionally arranged will be described in detail with reference to embodiments.
<Image display device>
First, a schematic configuration of an image display device according to the present invention will be described with reference to the drawings.
FIG. 1 is a schematic block diagram showing an embodiment of an image display device according to the present invention. Here, an image display apparatus having a configuration corresponding to a current designation type gradation control method will be described.

  As shown in FIG. 1, an image display device 100 according to the present invention generally includes a plurality of scanning lines SL arranged in a row direction (left-right direction in the drawing) and a plurality of scanning lines SL arranged in a column direction (up-down direction in the drawing). A display panel 110 in which a plurality of display pixels EM are arranged in a matrix of n rows × m columns (n and m are arbitrary positive integers) in the vicinity of each intersection with the data line (signal line) DL, A scanning driver (scanning driving means) 120 that sets (scans) the display pixels EM for each row by applying a scanning signal (selection signal) Vsel sequentially to each scanning line SL at a predetermined timing, and a scanning line A power supply driver (power supply driving means) 130 for applying a power supply voltage Vsc at a predetermined voltage level to a plurality of power supply voltage lines VL arranged in the row direction in parallel with SL, and a current value based on display data But A timing signal supplied from a data driver (signal driving means) 140 that generates a specified gradation current (gradation signal, signal current) Ipix and supplies it to each data line DL, and a display signal generation circuit 160 described later. A system controller 150 that generates and outputs a scan control signal, a power supply control signal, and a data control signal for controlling at least the operation state of the scan driver 120, the power supply driver 130, and the data driver 140, and an image display device, for example Display data (brightness gradation data) composed of a digital signal is generated based on a video signal supplied from the outside of 100, supplied to the data driver 140, and given to the display panel 110 based on the display data. Extract timing signals (system clock, etc.) for displaying image information, It generates and includes a display signal generation circuit 160 supplied to the system controller 150.

(Display panel 110)
Each display pixel EM that is two-dimensionally arranged in a matrix on the display panel 110 includes a current control type light emitting element such as an organic EL element, a scanning signal Vsel applied to the scanning line SL from the scanning driver 120, and a power supply driver 130. Write operation for holding a voltage component corresponding to the gradation current Ipix based on the power supply voltage Vsc applied to the power supply voltage line VL and the gradation current Ipix supplied from the data driver 140 to the data line DL And a pixel drive circuit that selectively executes a light emission operation of supplying light emission drive current having a predetermined current value to the light emitting element based on the voltage component to emit light at a predetermined luminance gradation. Have. Note that specific examples of display pixels (a pixel driving circuit and a light-emitting element) applicable to the present invention will be described later.

(Scanning driver 120)
The scan driver 120 sequentially applies a selection level (for example, high level) scan signal Vsel to each scan line SL based on the scan control signal supplied from the system controller 150, thereby causing the display pixels EM for each row to be displayed. The selected state is set, and the gradation current Ipix based on the display data supplied from the data driver 140 via each data line DL is controlled to be written in each display pixel EM (pixel drive circuit).

  Here, the scan driver 120, for example, based on a scan control signal supplied from the system controller 150 described later, a shift register that sequentially outputs a shift signal corresponding to the scan line SL of each row, and the shift signal as a predetermined signal An output circuit unit (output buffer) that converts the voltage level (selection level) and sequentially outputs it as the scanning signal Vsel to the scanning line SL of each row can be applied.

(Power supply driver 130)
The power supply driver 130 applies a low-level power supply voltage Vsc (= Vscw) to each power supply voltage line VL during a write operation period described later based on a power supply control signal supplied from the system controller 150. The gradation current Ipix supplied by the data driver 140 is controlled to be written in the display pixel EM (pixel driving circuit), and a high level power supply voltage Vsc (= Vsce) is applied during the light emitting operation period. Thus, the light emission driving current having a current value corresponding to the display data (gradation current Ipix) is controlled to be supplied to the light emitting element.

  Here, the power driver 130, for example, based on a power control signal supplied from the system controller 150, a shift register that sequentially outputs a shift signal corresponding to the power voltage line VL of each row, and the shift signal to a predetermined voltage An output circuit unit (output buffer) that converts to a level and outputs the power supply voltage Vsc to the power supply voltage line VL of each row can be applied.

(Data driver 140)
Based on the data control signal supplied from the system controller 150, the data driver 140 fetches and holds display data for each display pixel EM supplied from the display signal generation circuit 160 at a predetermined timing, and stores the display data. A gradation current Ipix having a current value corresponding to the gradation value is generated and supplied to each data line DL within a selection period set for each scanning line SL.

  Here, for example, the data driver 140 receives a shift register that sequentially outputs a shift signal based on a data control signal supplied from the system controller 150 and a display signal generation circuit 160 based on the input timing of the shift signal. A data register for sequentially fetching the supplied display data for one row, a data latch circuit for holding the fetched display data for one row, and the stored display data based on a gradation reference voltage. A D / A converter (digital-analog converter) for converting to an analog signal voltage and a gradation current Ipix having a current value corresponding to the analog signal voltage are generated, and each display pixel EM is connected to each display pixel EM via the data line DL. A voltage / current conversion / current supply circuit to be supplied can be applied.

(System controller 150)
For example, based on the timing signal supplied from the display signal generation circuit 160, the system controller 150 scans at least the scanning driver 120, the power supply driver 130, and the data driver 140. By generating and outputting the data control signal, each driver is operated at a predetermined timing to generate the scanning signal Vsel, the power supply voltage Vsc, and the gradation current Ipix, and each scanning line SL, power supply voltage line VL, A series of drive control operations (write operation and light emission operation) in each display pixel (pixel drive circuit and light emitting element) EM are executed by applying to the data line DL, and image information based on the video signal is displayed on the display panel 110. To control.

(Display signal generation circuit 160)
For example, the display signal generation circuit 160 extracts a luminance gradation signal component from a video signal supplied from the outside of the image display apparatus 100, and converts the luminance gradation signal component into a digital signal for each row of the display panel 110. Is supplied to the data driver 140 as display data (luminance gradation data). Here, when the video signal includes a timing signal component that defines the display timing of image information, for example, a television broadcast signal (composite video signal), the display signal generation circuit 160 is as shown in FIG. In addition to the function of extracting the luminance gradation signal component, a function of extracting a timing signal component and supplying it to the system controller 150 may be provided. In this case, the system controller 150 generates control signals to be individually supplied to the scan driver 120, the power supply driver 130, and the data driver 140 based on the timing signal supplied from the display signal generation circuit 160. .

  In addition, when the video signal supplied from the outside of the image display apparatus 100 is formed by a digital signal, and the timing signal is supplied separately from the video signal, the video signal (digital signal) is directly used as display data. In addition, the display signal generation circuit 160 may be omitted by supplying the timing signal directly to the system controller 150 while supplying the data driver 140.

<Display pixel>
Next, specific circuit examples of display pixels that are two-dimensionally arranged on a display panel applied to the above-described image display device will be described in detail with reference to the drawings.
FIG. 2 is a circuit configuration diagram showing a specific circuit example of a display pixel (pixel drive circuit) applicable to the display device according to the present embodiment, and FIG. 3 is applicable to the pixel drive circuit according to the present embodiment. It is a cross-sectional block diagram which shows the example of the element structure of a double gate type transistor.

  As shown in FIG. 2, the display pixel EM according to the present embodiment includes, for example, a gate near each intersection of the scanning line SL and the data line DL arranged so as to be orthogonal to the display panel 110 described above. A transistor (gradation signal control means) Tr11 having a terminal connected to the scanning line SL, a drain terminal connected to the power supply voltage line VL, and a source terminal connected to the contact N11, a gate terminal to the scanning line SL, and a drain terminal to the data line DL, a transistor (grayscale signal control means) Tr12 whose source terminal is connected to the contact N12, a bottom gate terminal BG to the contact N11, a drain terminal D to the power supply voltage line VL, a top gate terminal TG and a source terminal Double gate type transistor (double gate type transistor; drive current control) with S connected to contact N12 Stage) Tr13, and a pixel drive circuit DC comprising a contact N11 and a contact N12 (that is, a capacitor (charge holding means) Cs connected between the bottom gate and the source of the double-gate transistor Tr13), and An organic EL element (current control type light emitting element) OLED having an anode terminal connected to the contact N12 of the pixel driving circuit DC and a cathode terminal connected to a predetermined low voltage (for example, ground potential GND) is provided.

Here, an example of the first element structure of the double gate transistor Tr13 connected in series to the organic EL element OLED and functioning as a switching element for driving light emission is, for example, amorphous silicon as shown in FIG. And n-channel type semiconductor layer (channel region) SMC made of polysilicon, etc., and source electrode Tr13s (at each end of semiconductor layer SMC via n + silicon impurity layer (ohmic contact layer) OHM) ( A source terminal S) and a drain electrode Tr13d (drain terminal D), and a top gate electrode Tr13tg (top gate terminal TG, formed above the semiconductor layer SMC via an insulating film (top gate insulating film) 13 above (in the drawing). Formed integrally with a pixel electrode 14 described later; a first gate electrode), and a semiconductor layer A bottom gate electrode Tr13bg (bottom gate terminal BG; second gate electrode) formed via an insulating film (bottom gate insulating film) 12 below the SMC (downward in the drawing) is configured.

  In addition, an example of the second element structure of the double gate transistor Tr13 is formed on the semiconductor layer SMC in addition to the first element structure (FIG. 3A) described above, for example, as shown in FIG. A block insulating film (etching stopper film) BL is provided, and is formed integrally with a top gate electrode Tr13tg (a pixel electrode 14 described later) via the block insulating film BL and the insulating film 13 above the semiconductor layer SMC (upward in the drawing). Is formed). Here, the block insulating film BL has a function as an etching stopper in an etching process when the source electrode Tr13s and the drain electrode Tr13d provided on the semiconductor layer SMC are formed by patterning, and the etching to the semiconductor layer SMC is performed. It has a function for preventing damage.

  The double-gate transistor Tr13 having such a configuration is formed on an insulating substrate 11 such as a glass substrate, as shown in FIGS. 3 (a) and 3 (b). In addition, an insulating film 15 is formed on the top gate electrode Tr13tg of at least the double gate transistor Tr13.

  In the present invention, in the double gate transistor Tr13 having such a configuration, for example, the top gate electrode Tr13tg (pixel electrode 14) and the source electrode Tr13s are electrically connected (short-circuited) so as to have the same potential. It is configured. As will be described in detail later, in this case, for example, in the element structure shown in FIGS. 3A and 3B, the top layer on the upper layer side is formed through a contact hole formed in the insulating film 13 serving as the top gate insulating film. A configuration in which the gate electrode Tr13tg (pixel electrode 14) and the lower-layer source electrode Tr13s are electrically connected can be applied.

  As the transistors Tr11 and Tr12, well-known field-effect transistors (thin film transistors) can be applied. The capacitor Cs may be a parasitic capacitance formed between the bottom gate and the source of the double gate transistor Tr13, and in addition to the parasitic capacitance, a capacitive element is further connected in parallel between the contact N11 and the contact N12. It may be what you did.

  Note that the transistors Tr11 to Tr13 applied to the pixel drive circuit DC according to the present embodiment are not particularly limited, but in the following description, any transistor has an n-channel semiconductor layer as a channel region. A case where the provided transistor structure is applied will be described.

Next, a specific device structure (planar layout and cross-sectional structure) of the display pixel (pixel driving circuit and light emitting element) having the above-described circuit configuration will be described.
FIG. 4 is a plan layout diagram illustrating an example of a display pixel applicable to the display device (display panel) according to the present embodiment, and FIG. 5 is an AA view of the display pixel having the planar layout illustrated in FIG. It is a schematic sectional drawing which shows a cross section. In FIG. 4, in order to clarify the element structure of the display pixel EM (pixel driving circuit), the layer in which each transistor, wiring layer, and the like of the pixel driving circuit are formed is mainly shown.

  For example, as shown in FIG. 4, the display pixel EM has a display pixel formation region (pixel formation region) Rpx set on one surface side of the insulating substrate 11 in the X direction (in FIG. 4). The scanning line SL and the power supply voltage line VL are respectively arranged so as to extend in the left-right direction (corresponding to the row direction in FIG. 1), and on the left side of the pixel formation region Rpx so as to be orthogonal to them. Data lines DL and are arranged so as to extend in the Y direction of the edge region (vertical direction in FIG. 4: corresponding to the column direction in FIG. 1). Further, the transistor Tr11 and the transistor Tr12 illustrated in FIG. 2 are arranged so as to extend in the Y direction along the data line DL, and the transistor Tr13 extends in the Y direction of the right edge region of the pixel formation region Rpx. It is arranged to exist.

  Here, as described above, the transistors Tr11 and Tr12 have a well-known field effect transistor structure, and only the transistor Tr12 is shown in FIG. 5, but each of the transistors Tr11 and Tr12 is formed on a transparent insulating substrate 11 such as a glass substrate. The formed gate electrodes Tr11g, Tr12g, the semiconductor layer SMC formed in a region corresponding to each gate electrode Tr11g, Tr12g via the gate insulating film 12, and formed so as to extend to both ends of the semiconductor layer SMC. Source electrodes Tr11s and Tr12s and drain electrodes Tr11d and Tr12d.

  The transistor Tr13 has an element structure as shown in FIGS. 3A and 3B. As shown in FIG. 5, the transistor Tr13 has a gate insulation with a bottom gate electrode Tr13bg formed on the insulating substrate 11. The semiconductor layer SMC formed in a region corresponding to the bottom gate electrode Tr13bg via the film 12, the source electrode Tr13s and the drain electrode Tr13d formed so as to extend at both ends of the semiconductor layer SMC, and the insulating film 13 And a top gate electrode Tr13tg formed in a region corresponding to the semiconductor layer SMC.

  Although the illustration is simplified in FIG. 5, etching damage to the semiconductor layer SMC is caused on the semiconductor layer SMC in which the source electrode and the drain electrode of the transistors Tr11 and Tr12 and the double gate transistor Tr13 face each other. A blocking layer such as silicon oxide or silicon nitride is formed for prevention, and an ohmic connection between the semiconductor layer SMC and the source and drain electrodes is realized on the semiconductor layer SMC where the source and drain electrodes are in contact An impurity layer may be formed (corresponding to the element structure shown in FIG. 3B in the double gate transistor Tr13).

  Here, the gate electrodes Tr11g and Tr12g of the transistors Tr11 and Tr12, the bottom gate electrode Tr13bg of the double gate transistor Tr13, and the data line DL are all formed by patterning the same gate metal layer. . The source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d of the transistors Tr11 and Tr12, the source electrode Tr13s and the drain electrode Tr13d of the double gate transistor Tr13, the scanning line SL, and the power supply voltage line VL are all the same source. The drain metal layer is formed by patterning. Further, the top gate electrode Tr13tg of the double gate transistor Tr13 and the pixel electrode (for example, anode electrode) 14 of the organic EL element OLED described later are integrally formed of the same electrode material. Further, as shown in FIGS. 4 and 5, the power supply voltage line VL is formed integrally with the drain electrode Tr13d of the double gate transistor Tr13, and the scanning line SL and the power supply voltage line VL are higher than the data line DL. On the side.

  In order to correspond to the circuit configuration of the pixel drive circuit DC shown in FIG. 2, the transistor Tr11 includes a contact hole HLA in which a gate electrode Tr11g is provided in the gate insulating film 12, as shown in FIGS. The source electrode Tr11s is connected to the electrode ECA on one end side (the contact N11 side) of the capacitor Cs via the contact hole HLB provided in the gate insulating film 12, and the drain electrode Tr11d. Are formed integrally with the power supply voltage line VL.

  For example, as shown in FIGS. 4 and 5, the transistor Tr12 has a gate electrode Tr12g connected to the scanning line SL through a contact hole HLA provided in the gate insulating film 12, and the source electrode Tr12s connected to the capacitor Cs. The drain electrode Tr12d is integrally formed with the electrode ECB on the other end side (contact N12 side), and the drain electrode Tr12d is connected to the data line DL through a contact hole HLC provided in the gate insulating film 12.

  For example, as shown in FIGS. 4 and 5, in the double gate transistor Tr13, the bottom gate electrode Tr13bg is integrally formed with the electrode ECA on one end side (contact N11 side) of the capacitor Cs, and the source electrode Tr13s is formed with the capacitor Cs. Is formed integrally with the electrode ECB on the other end side (contact N12 side), the drain electrode Tr13d is formed integrally with the power supply voltage line VL, and the top gate electrode Tr13tg is integrated with the pixel electrode 14 of the organic EL element OLED. And is connected to the source electrode Tr13s through a contact hole HLD provided in the insulating film 13.

  The capacitor Cs is formed integrally with the bottom gate electrode Tr13bg of the double gate transistor Tr13, and is connected to the one end electrode ECA connected to the source electrode Tr11s of the transistor Tr11 and the source electrode of the double gate transistor Tr13. The other end electrode ECB formed integrally with Tr13s and the source electrode Tr12s of the transistor Tr12 is formed to extend so as to face each other with the gate insulating film 12 therebetween.

  In the pixel formation region Rpx, in the formation region of the organic EL element OLED, the pixel electrode (for example, anode electrode) 14 formed integrally with the top gate electrode Tr13tg of the double gate transistor Tr13 described above, hole transport An organic EL element OLED in which an organic EL layer (light emitting layer) 16 composed of a layer 16a (charge transport layer) and an electron transporting light emitting layer 16b (charge transport layer) and a counter electrode (for example, a cathode electrode) 17 are sequentially stacked is provided. On the other hand, the region other than the region where the organic EL element OLED is formed is covered with the interlayer insulating film 15 on the above-described transistors Tr and Tr12 and the double gate transistor Tr13, the scanning line SL, the power supply voltage line VL, and the data line DL. Formed on the interlayer insulating film 15 so as to extend the counter electrode 17. .

  In other words, the counter electrode 17 is formed by a single planar electrode (solid electrode) so as to be opposed to a plurality of display pixels EM (each pixel electrode 14) two-dimensionally arranged on the insulating substrate 11. ing. Then, as shown in FIG. 5, for example, an insulating sealing layer 18 is formed on the entire area of the insulating substrate 11 on which the pixel driving circuit DC and the organic EL element OLED are formed.

  Here, when the display panel 110 (display pixel EM) has a bottom emission structure, the pixel electrode 14 is transparent, for example, tin-doped indium oxide (ITO) or zinc-doped indium oxide (Indium Zinc Oxide; IZO). An electrode material formed of an electrode material (having light transmission characteristics) and having a light reflection characteristic such that the counter electrode 17 is an alloy of aluminum (Al), chromium (Cr), silver (Ag), palladium silver (AgPd), etc. The light emitted from the organic EL layer 16 is emitted to the other side of the insulating substrate 11 that is the visual field side (downward in FIG. 5) through the insulating substrate 11, while the display panel When 110 (display pixel EM) has a top emission structure, the pixel electrode 14 has a light reflection characteristic, and the counter electrode 17 has a light transmission characteristic. By being formed, the light emitted from the organic EL layer 16 is emitted to one surface side (upper side of FIG. 5) of the insulating substrate 11 through the sealing layer 18.

  In addition, when the organic EL element provided with the organic EL layer formed by applying a polymer organic material is applied as the light emitting element arranged in the display panel 110, the above-described formation of the organic EL element OLED is performed. In order to define a region (that is, a region where the hole transport layer 16a and the electron transporting light emitting layer 16b to be the organic EL layer 16 are applied and formed), on each wiring layer or transistor between the formation regions of the organic EL element OLED The formed interlayer insulating film 15 may be formed in a partition shape or a bank shape so as to protrude from the surface of the insulating substrate 11.

  FIG. 6 is a timing chart showing the basic operation of the display pixel to which the pixel driving circuit according to this embodiment is applied, and FIG. 7 is a conceptual diagram showing the operation state of the pixel driving circuit according to this embodiment. . Here, in FIG. 6, i row and j column and (i + 1) row and j column of display panel 110 (i is a positive integer satisfying 1 ≦ i ≦ n, and j is a positive integer satisfying 1 ≦ j ≦ m. The drive control operation in the display pixel EM of (integer) is shown.

  The light emission drive control (drive control method) of the light emitting element (organic EL element OLED) in the pixel drive circuit DC having such a configuration is, for example, as shown in FIG. 6, with one scan period Tsc as one cycle. A write operation period (selection period) in which a display pixel EM connected to the scan line SL is selected and a gradation current Ipix is supplied according to display data to hold a voltage component according to display data within the scan period Tsc. ) Based on Tse and the voltage component held in the writing operation period Tse, a light emission driving current corresponding to the display data is generated and supplied to the organic EL element OLED to perform a light emission operation at a predetermined luminance gradation. The light emission operation period (non-selection period) Tnse is set to be included (Tsc ≧ Tse + Tnse). Here, the writing operation period Tse set for each scanning line SL of each row is set so that there is no time overlap.

(Write operation period)
In the writing operation period Tse of the display pixel EM, as shown in FIG. 6, first, the high-level scanning signal Vsel is applied from the scanning driver 120 to a specific scanning line (for example, the i-th scanning line) SL. Is applied to set the display pixel EM in the row to a selected state, and a low-level power supply voltage Vsc (= Vscw) is applied from the power supply driver 130 to the power supply voltage line VL of the display pixel EM in the row. Is done. In synchronization with this timing, the data driver 140 draws the grayscale current Ipix having a current value based on the display data corresponding to each display pixel EM in the row from each data line DL.

  As a result, the transistors Tr11 and Tr12 constituting the pixel drive circuit DC are turned on, and the low-level power supply voltage Vsc is applied to the contact N11 (that is, the bottom gate terminal BG of the double gate transistor Tr13 and one end side of the capacitor Cs). In addition, the operation of drawing the gradation current Ipix from the data line DL side by the data driver 140 is performed, so that the voltage level lower than the low-level power supply voltage Vsc becomes the contact N12 (that is, the double gate type transistor). Applied to the source terminal S of Tr13 and the other end of the capacitor Cs).

  As described above, the potential difference is generated between the contacts N11 and N12 (between the bottom gate and the source of the double gate transistor Tr13), so that the double gate transistor Tr13 is turned on, as shown in FIG. A write current (designated current) Ia corresponding to the current value of the gradation current Ipix flows from the power supply voltage line VL to the data driver 140 through the double gate type transistor Tr13, the contact N12, the transistor Tr12, and the data line DL.

  At this time, a charge corresponding to the potential difference generated between the contacts N11 and N12 (between the bottom gate and the source of the double gate transistor Tr13) is accumulated in the capacitor Cs and held (charged) as a voltage component. Further, a low level power supply voltage Vsc (= Vscw) having a voltage level equal to or lower than the ground potential is applied to the power supply voltage line VL, and the write current Ia is controlled to flow in the direction of the data line DL. Therefore, the potential applied to the anode terminal (contact N12) of the organic EL element OLED is lower than the potential of the cathode terminal (ground potential GND), and a reverse bias voltage is applied to the organic EL element OLED. A light emission drive current does not flow through the organic EL element OLED, and no light emission operation is performed.

(Light emission operation period)
Next, in the light emission operation period Tnse after the end of the write operation period Tse, as shown in FIG. 6, the low level scan signal Vsel is applied to the scan line SL on which the write operation is performed from the scan driver 120. As a result, the display pixel EM is set to a non-selected state, and a high level power supply voltage Vsc (= Vsce) is applied to the power supply voltage line VL of the display pixel EM in the row. In synchronism with this timing, the grayscale current Ipix drawing operation by the data driver 140 is stopped.

  Thereby, the transistors Tr11 and Tr12 constituting the pixel drive circuit DC are turned off, and the application of the power supply voltage Vsc to the contact N11 (that is, the bottom gate terminal BG of the double gate transistor Tr13 and one end side of the capacitor Cs) is performed. In addition to being cut off, application of the voltage level due to the drawing operation of the gradation current Ipix by the data driver 140 to the contact N12 (that is, the source terminal S of the double gate transistor Tr13 and the other end of the capacitor Cs) is cut off. Therefore, the capacitor Cs holds the charge accumulated during the above-described write operation period.

  As described above, the capacitor Cs holds the charging voltage at the time of the writing operation, whereby the potential difference between the contacts N11 and N12 (between the bottom gate and the source of the double gate transistor Tr13) is held. The type transistor Tr13 is kept on. Further, since the high level power supply voltage Vsc (= Vsce) having a voltage level higher than the ground potential is applied to the power supply voltage line VL, the potential applied to the anode terminal (contact N12) of the organic EL element OLED. Becomes higher than the potential of the cathode terminal (ground potential).

Therefore, as shown in FIG. 7B, a predetermined light emission drive current (output current) Ib flows in the forward bias direction from the power supply voltage line VL to the organic EL element OLED through the double gate transistor Tr13 and the contact N12. The organic EL element OLED emits light. Here, the potential difference (charging voltage) based on the electric charge accumulated by the capacitor Cs corresponds to the potential difference when the write current Ia corresponding to the gradation current Ipix is caused to flow in the double gate transistor Tr13, and therefore the organic EL element OLED. The light emission drive current Ib supplied to 1 has a current value equivalent to the write current Ia. Thereby, in the non-selection period Tnse after the writing operation period Tse, the voltage component corresponding to the display data (gradation current Ipix) written in the writing operation period Tse is passed through the double gate transistor Tr13. Accordingly, the light emission drive current Ib is continuously supplied, and the organic EL element OLED continues the operation of emitting light at the luminance gradation corresponding to the display data.
Then, the display data for one screen of the display panel is written by sequentially repeating the above-described series of operations for all the rows (scan lines SL) of the display panel 110 from the (i + 1) th row onward. The light emission operation is performed at the luminance gradation, and desired image information is displayed.

  Here, in the pixel drive circuit DC according to the present embodiment, the case where the semiconductor layers (channel layers) of the transistors Tr21 and Tr22 and the double-gate transistor Tr13 are all formed by the n-channel type has been described. In this case, by applying amorphous silicon as the semiconductor layer and applying the already established amorphous silicon manufacturing technique, a pixel driving circuit having stable element characteristics (such as electron mobility) can be manufactured at a relatively low cost.

  In the pixel drive circuit DC according to the present embodiment, as described above (see FIG. 6), it is necessary to apply the power supply voltage Vsc having a predetermined voltage value to the power supply voltage line VL. As shown in FIG. 1, the configuration including the power supply driver 130 is shown. However, the present invention is not limited to this. For example, the power supply voltage Vsc is applied to the power supply voltage line VL at a timing synchronized with the scanning signal Vsel. Therefore, the scanning driver 120 inverts the scanning signal Vsel (or the shift signal for generating the scanning signal), amplifies it to a predetermined voltage level, and applies it to each power supply voltage line VL as the power supply voltage Vsc. You may have the structure made to do.

  In addition, the display pixel EM described above includes three transistors having the same channel polarity as an example of a pixel drive circuit corresponding to the current designation type gradation control method, and the display pixel EM (pixel drive circuit DC). Although the circuit configuration in which the gradation current Ipix corresponding to the display data is drawn in the direction of the data driver 140 from the data line DL to the data driver DL is shown, the present invention is not limited to this. For example, four transistors are provided. It may have a circuit configuration provided, or may further have a circuit configuration in which a gray scale current flows from the data driver in the direction of the display pixel (pixel drive circuit) via the data line. Good.

  In addition, in the display pixel EM described above, the configuration in which the organic EL element is applied as the current control type light emitting element is shown, but the present invention is not limited to this, and the light emission driving current supplied from the pixel driving circuit is not limited thereto. For example, a light emitting diode or other light emitting element may be applied as long as the light emitting element emits light with a predetermined luminance gradation according to the current value.

<Verification of effects in the present invention>
Next, the effect of the image display device including the display pixel (pixel drive circuit) according to the present embodiment and the display panel in which the display pixel is two-dimensionally arranged will be specifically described.
First, the connection state of the capacitance components (retention capacitance and parasitic capacitance) in the pixel drive circuit having the circuit configuration described above will be examined in detail.

  FIG. 8 is a conceptual diagram showing a connection state of capacitance components in a pixel drive circuit (comparison target) to which transistors having the same element structure are applied. Here, in FIG. 8, in the circuit configuration equivalent to the pixel drive circuit DC according to the present invention shown in FIG. 2, instead of the double gate transistor Tr13 which is a switching element for light emission drive, transistors Tr11, Tr12 and A pixel drive circuit DCx in the case where a similar field effect transistor is applied is shown and will be described as a comparison object with respect to the present invention. In the pixel drive circuit shown in FIG. 8, the circuit configuration corresponding to FIG.

  First, as a switching element for driving light emission, a well-known field effect transistor Tr23 is applied in the same manner as the transistors Tr11 and Tr12, instead of the double gate transistor Tr13 in the pixel drive circuit DC shown in FIG. The circuit configuration is shown in FIG. Here, the field effect transistors Tr21 to Tr23 are formed so that the gate electrode and the source electrode, and the gate electrode and the drain electrode are opposed to each other with the gate insulating film interposed therebetween. And parasitic capacitance arises between gate-drain, respectively.

  Therefore, in the display pixel EMx (pixel drive circuit DCx) having the circuit configuration shown in FIG. 8A, as shown in FIG. 8B, the transistor Tr21 includes a gate electrode connected to the scan line SL. A parasitic capacitance Cgs1 is formed between the gate electrode and the source electrode connected to the contact N21, and a parasitic capacitance Cgd1 is formed between the gate electrode and the drain electrode connected to the power supply voltage line VL. In the transistor Tr22, a parasitic capacitance Cgs2 is formed between the gate electrode connected to the scanning line SL and the source electrode connected to the contact N22. The drain electrode connected to the gate electrode and the data line DL In the meantime, a parasitic capacitance Cgd2 is formed. In the transistor Tr23, a parasitic capacitance Cgs3 is formed between the gate electrode connected to the contact N21 and the source electrode connected to the contact N22, and the drain electrode connected to the gate electrode and the power supply voltage line VL. In the meantime, a parasitic capacitance Cgd3 is formed.

  Further, since the organic EL element OLED has a diode junction structure, a parasitic capacitance Coled due to the junction capacitance is formed between the anode electrode and the cathode electrode, and between the data line DL and the scan line SL. The wiring capacitances (parasitic capacitances) Cd-s and Cd-v are also formed between the data line DL and the power supply voltage line VL. In addition, a capacitor Cx as a storage capacitor is connected between the contacts N21 and N22.

The influence of such various capacitance components on the drive control operation of the display pixel EMx (pixel drive circuit DCx) (drive control operation equivalent to the above-described pixel drive circuit DC) is generally described as follows. be able to.
As shown in the timing chart of FIG. 6 as the drive control method of the pixel drive circuit DC described above, the display pixel EMx (pixel drive circuit DCx) shown in FIGS. 8A and 8B is changed from the selected state to the non-selected state. The voltage difference ΔVsel of the scanning signal Vsel when switching to is expressed by the following equation (1).

ΔVsel = Vsel (L) −Vsel (H) (1)
Here, Vsel (L) is the voltage value of the scanning signal Vsel immediately after the selection state is released (non-selected state), and Vsel (H) is the voltage value of the scanning signal Vsel immediately before the selection state is released (selected state).
A displacement current flows between each parasitic capacitor and holding capacitor with this potential fluctuation, but the charge accumulated in the capacitor Cx is held in the selected state and the non-selected state, and the sum of the displacement currents flowing into the respective contacts N21 and N22. Since 0 is 0, the following equations (2) and (3) are obtained.

Here, ΔVn21 and ΔVn22 are potential changes at the contacts N21 and N22, respectively, and ΔVsc is a difference in power supply voltage Vsc when the display pixel EMx (pixel drive circuit DCx) is switched from the selected state to the non-selected state. In addition, when the potential fluctuation occurs gently instead of instantaneously, a current caused by conductance flows in addition to the displacement current. Here, it is assumed that the above-described potential fluctuation occurs instantaneously.
Next, in the above equations (2) and (3), the potential changes ΔVn21 and ΔVn22 at the contacts N21 and N22 are solved, and the difference Δ (Vn21−Vn22) = ΔVn21−ΔVn22 is obtained as shown in equation (4).

Here, the potential variation represented by the difference ΔVn21−ΔVn22 in the equation (4) corresponds to the variation ΔVgs-T3 of the gate voltage (gate-source voltage) in the transistor Tr23, and between the drain and source of the transistor Tr23. Corresponds to current fluctuations.
As described above, the display pixel EMx (pixel drive circuit DCx) is controlled to be switched between the selected state and the non-selected state, whereby the gate voltage (to be applied to the gate electrode of the transistor Tr23 which is a switching element for driving light emission) The gate-source voltage (Vgs) changes.

  On the other hand, in the pixel drive circuit DCx shown in FIG. 8A, the current path (source-drain) of the transistor Tr23 is connected to the anode electrode of the organic EL element OLED via the contact N22. A series circuit composed of EL elements OLED is connected between a power supply voltage line (power supply voltage Vsc) and a ground potential GND). Here, when the drive control operation as shown in FIG. 6 is executed, the power supply voltage Vsc changes in synchronization with the switching timing of the scanning signal Vsel, so that the both ends (between the drain and source) of the current path of the transistor Tr23. The applied voltage Vds will change.

  Therefore, a difference occurs in the light emission drive current (output current) with respect to the write current (designated current) to the display pixel EMx (pixel drive circuit DCx), and the light emitting element emits light at an appropriate luminance gradation according to display data. In other words, there is a problem that the display quality is deteriorated due to a decrease in contrast or the like.

Here, the operation characteristics of the transistor Tr23, which is a switching element for driving light emission, will be examined in detail.
FIG. 9 is a diagram showing operating characteristics of a light emission driving transistor applied to the pixel driving circuit shown as a comparison target. Here, in the cross-sectional structure of the field effect transistor shown in FIG. 9A, the components corresponding to FIGS. 3 and 5 are denoted by the same reference numerals. FIG. 9B shows operating characteristics (voltage-current characteristics) when a transistor having the parameters shown in Table 1 (the relative dielectric constant and film thickness of the insulating film and the element dimensions) is applied. It is shown.

  That is, in the field effect transistor Tr23 having the element structure as shown in FIG. 9A, as shown in Table 1, the gate insulating film 12 formed on the gate electrode Tr23g formed on the insulating substrate 11 is used. (LYR1) is set to have a relative dielectric constant ε = 7.5 and a film thickness d1 = 250 nm (2500 mm), and the semiconductor layer SMC (LYR2) made of amorphous silicon formed on the gate insulating film 12 has a relative dielectric constant. The block insulating film BL (LYR3) formed on the semiconductor layer SMC is set to ε = 12, the film thickness d2 = 50 nm (500 mm), and the relative dielectric constant ε = 7.5, the film thickness d3 = 170 nm (1700 mm). The insulating film 13 (LYR4) formed on the block insulating film BL is set to have a relative dielectric constant ε = 7.5 and a film thickness d4 = 200 nm (2000 mm). .

  In the field effect transistor Tr23, the channel length L corresponding to the overlapping length of the block insulating film BL and the semiconductor layer SMC in the left-right direction (source-drain direction) in FIG. 9A is set to 7 μm. The channel width W corresponding to the overlapping length of the block insulating film BL and the semiconductor layer SMC in the direction perpendicular to the paper surface of FIG. 9A (the direction parallel to the source and drain) is set to 600 μm, and FIG. ) In the left-right direction (source-drain direction), and the overlap length Xs of the source electrode Tr23s and the channel region and the overlap length Xd of the drain electrode Tr23d and the channel region are both set to 2 μm.

  The relationship (voltage-current characteristics) between the drain-source voltage Vds and the drain-source current Ids in such a transistor Tr23 is as shown by the characteristic lines SPx and SPy shown by solid lines in FIG. 9B. In the region where the source-to-source voltage Vds is low, the drain-source current Ids tends to increase sharply as the drain-source voltage Vds increases, and in the region where the drain-source voltage Vds is high, the drain-source It shows a saturation tendency in which the drain-source current Ids gradually converges as the inter-voltage Vds increases.

  Further, in FIG. 9B, a characteristic line SPw indicated by a one-dot chain line sets the display pixel EMx (pixel drive circuit DCx) to a selected state (that is, turns on the transistor Tr21 and turns on the gate of the transistor Tr23). A characteristic line indicating the relationship between the drain-source voltage Vds and the drain-source current Ids during a write operation in which a specified current is drawn according to display data (with the drain connected) As the source-to-source voltage Vds increases, the drain-source current Ids increases nonlinearly.

  Here, the characteristic line SPx shown in FIG. 9B is used when the display pixel EMx (pixel drive circuit DCx) is set to the selected state and the gradation current corresponding to the display data is extracted to execute the writing operation. 2 shows the operating characteristics of the transistor Tr23 (the drain-source current Ids with respect to the drain-source voltage Vds at the gate voltage Vg = 8.1 V), and the characteristic line SPy does not select the display pixel EMx (pixel driving circuit DCx). The operational characteristics (drain-source current Ids with respect to the drain-source voltage Vds at the gate voltage Vg = 8.6 V) of the transistor Tr23 when set to the state are shown.

  When the display pixel EMx (pixel drive circuit DCx) is switched from the selected state to the non-selected state, as described above, the gate voltage (gate-source voltage) Vgs applied to the transistor Tr23 and the transistor Tr23 Since the voltage Vds applied to both ends of the current path (between the drain and source) changes, as shown in FIG. 9B, the write current (display current to the display pixel EMx (pixel drive circuit DCx) ( For example, even when a current value of 3 μA (3.0E-06A) is specified as (gradation current) (indicated by a white circle on the characteristic line SPx in the figure), the transistor Tr23 having the parameters shown in Table 1 In FIG. 5, a voltage change of 0.5V (8.6-8.1V) occurs in the gate voltage Vg.

  As a result, the operating characteristics of the transistor Tr23 change (characteristic line SPx → SPy), and a light emission driving current (output current) having a current value of 5.1 μA (indicated by a black circle on the characteristic line SPy in the figure) is organic. As a result, the light emission driving current with respect to the writing current is different, and the light emitting element cannot be operated to emit light at an appropriate luminance gradation according to display data.

  Therefore, in the present invention, as shown in FIGS. 2 to 5, a double gate type transistor Tr13 is applied as a switching element for light emission driving, and a pair of gate electrodes (above and below the semiconductor layer SMC ( A control voltage (gate voltage) based on selective control is applied to either one of the top gate electrode and the bottom gate electrode), and the other gate electrode is connected to the organic EL element OLED or the double gate Since the circuit configuration is connected to the source electrode of the type transistor Tr13, the voltage change caused by the drive control operation of the display pixel EM (pixel drive circuit DC) affects the gate voltage of the double gate type transistor Tr13. I try to suppress it.

  FIG. 10 is a diagram showing operating characteristics of the light emission driving transistor applied to the pixel driving circuit according to the present embodiment. Here, in the cross-sectional structure of the field effect transistor shown in FIG. 10A, the components corresponding to FIG. 3 and FIG. FIG. 10B shows operating characteristics (voltage-current characteristics) when a transistor having the parameters (relative permittivity and film thickness of insulating film and element dimensions) as shown in Table 2 is applied. It is shown.

  That is, in the double gate transistor Tr13 having an element structure as shown in FIG. 10A, as shown in Table 2, the gate insulating film (on the bottom gate electrode Tr13bg formed on the insulating substrate 11) The bottom gate insulating film) 12 (LYR1) is set to have a relative dielectric constant ε = 7.5 and a film thickness d1 = 250 nm (2500 mm), and is formed on the gate insulating film 12 with a semiconductor layer SMC (LYR2) made of amorphous silicon. ) Is set to a relative dielectric constant ε = 12, and a film thickness d2 = 50 nm (500 Å), and the block insulating film BL (LYR3) formed on the semiconductor layer SMC has a relative dielectric constant ε = 7.5 and a film thickness. The insulating film 13 (LYR4) set to d3 = 170 nm (1700 mm) and formed on the block insulating film BL has a relative dielectric constant ε = 7.5 and a film thickness d4 = 20. It is set to nm (2000Å).

  Note that the channel length L, the channel width W, the overlap length Xs of the source electrode Tr13s and the channel region, and the overlap length Xd of the drain electrode Tr13d and the channel region in the double gate transistor Tr13 are as shown in Table 2. In addition, the size is set to be the same as that of the transistor Tr23 to be compared (see Table 1).

  The relationship (voltage-current characteristics) between the drain-source voltage Vds and the drain-source current Ids in such a double gate type transistor Tr13 is the solid line in FIG. In the region where the drain-source voltage Vds is low as indicated by the characteristic lines SPa and SPb shown in FIG. 5, the drain-source current Ids tends to increase sharply as the drain-source voltage Vds increases. In a region where the source-to-source voltage Vds is high, the drain-source current Ids tends to be gradually converged as the drain-source voltage Vds increases. In particular, in the saturation region, the increase amount of the drain-source current Ids with respect to the drain-source voltage Vds is suppressed to be smaller than in the case of the comparison target shown in FIG.

  Here, the characteristic line SPa shown in FIG. 10B is set when the display pixel EM (pixel drive circuit DC) is set to the selected state, the gradation current corresponding to the display data is extracted, and the writing operation is executed. 2 shows the operating characteristics of the double-gate transistor Tr13 (drain-source current Ids with respect to the drain-source voltage Vds at the gate voltage Vg = 8.3 V), and the characteristic line SPb is the display pixel EM (pixel drive circuit DC). 7 shows the operating characteristics (drain-source current Ids with respect to drain-source voltage Vds at gate voltage Vg = 8.8 V) of when transistor is set to the non-selected state.

  When the display pixel EM (pixel drive circuit DC) is switched from the selected state to the non-selected state, as described above, the gate voltage (gate-source voltage) Vgs applied to the double gate transistor Tr13, and The voltage Vds applied across the current path of the transistor Tr13 (between the drain and the source) changes. As shown in FIG. 10B, however, writing to the display pixel EM (pixel drive circuit DC) is performed. When a current value of, for example, 3 μA (3.0E-06A) is designated as the inrush current (gradation current) (indicated by white circles on the characteristic line SPa in the figure), the double gate type having the parameters shown in Table 2 In the case where the transistor Tr13 is applied to a light emission driving transistor, a voltage change (8.8-8.3 V) of 0.5 V occurs in the gate voltage Vg, and a double gate is generated. Although the operating characteristic of the transistor Tr13 changes (characteristic line SPa → SPb), a light emission driving current having a current value of 4.7 μA (indicated by a black circle on the characteristic line SPb in the figure) is supplied to the organic EL element OLED. It is suppressed to be smaller than the comparison target described above.

  That is, as a switching means for driving light emission, when a double gate type transistor in which a top gate electrode is connected to a source electrode is used, compared to a case in which a field effect transistor is used (comparative object), the write current is reduced. Since the difference in the light emission drive current is suppressed to be small, the light emitting element can be operated to emit light with a luminance gradation relatively corresponding to the display data. The effect peculiar to such a double gate type transistor can be explained as follows.

FIG. 11 is a diagram for explaining a relationship between an element structure and a channel potential in a double gate transistor applied to the pixel driving circuit according to the present embodiment. Here, in FIG. 11A, for convenience of illustration, a part of hatching in the cross-sectional view is omitted.
That is, for example, a thin film transistor structure as shown in FIG. 11A (that is, an element structure in which the top gate electrode Tr13tg of the double gate transistor Tr13 is removed, or a gate independent of the top gate terminal Tr13tg in the double gate transistor Tr13). This is because the source electrode Tr13s and the drain electrode Tr13d extend on the block insulating film BL over the semiconductor layer SMC in a state where no voltage is applied, thereby serving as a pseudo top gate electrode. It can be explained as a thing.

  Specifically, in the transistor having the element structure shown in FIG. 11A, in the region where the source electrode Tr13s and the drain electrode Tr13d overlap with the semiconductor layer SMC via the block insulating film BL, these electrodes are not formed. The channel region is formed in the semiconductor layer SMC by the applied voltage, and the original channel region formed in the region where the source electrode Tr13s and the drain electrode Tr13d are not formed (that is, by the gate voltage applied to the top gate electrode Tr13tg). In addition to the channel region formed in the semiconductor layer SMC), the channel region is also formed in the region corresponding to the source electrode Tr13s and the drain electrode Tr13d, whereby the semiconductor layer SMC in the region extending from the source electrode Tr13s to the drain electrode Tr13d is formed. Channel region Rch is shaped It is. At this time, a potential change according to the bias voltage (source voltage and drain voltage) applied between the source and drain occurs in the channel region Rch.

  As shown in FIG. 11B, a predetermined bias voltage is applied between the source and drain, a low potential voltage Vsl (for example, 0 V) is applied to the source electrode Tr13s, and a high potential voltage Vdh is applied to the drain electrode Tr13d. Then, on the source electrode Tr13s side to which the low potential voltage Vsl is applied (a region where the source electrode Tr13s and the block insulating film BL overlap), the channel potential is lowered (negative direction), that is, the direction converges (approximates) to the voltage Vsl. On the other hand, the on-current (drain-source current Ids) is suppressed, while the channel potential is reduced on the drain electrode Tr13d side (the region where the drain electrode Tr13d and the block insulating film BL overlap) to which the high potential voltage Vdh is applied. The on-current increases by acting in the direction of increasing (positive direction), that is, the direction of convergence (approximation) to the voltage Vdh. In FIG. 11B, a characteristic line SPv indicated by a thin solid line indicates an ideal value of potential change (relative to the channel position) in the channel region.

  In contrast, the double gate transistor Tr13 described above has a configuration in which the top gate electrode Tr13tg is connected to the source electrode Tr13s. As a result, the effect of lowering the channel potential and suppressing the on-current on the source electrode Tr13s side shown in FIG. 11B is further promoted by the top gate electrode Tr13tg, and the drain-source with respect to the drain-source voltage Vds. The increase amount of the inter-current Ids is suppressed.

  Therefore, a double gate type transistor as shown in FIGS. 3 and 5 is applied as a switching element for light emission driving of the pixel driving circuit DC, and a source electrode is connected to the top gate electrode of the double gate type transistor. By applying the same potential, an increase in the drain-source current (output current) Ids with respect to the drain-source voltage Vds in the saturation region of the voltage-current characteristic can be suppressed, and the gate-source voltage can be suppressed. (Gate voltage) An increase in drain-source current Ids with respect to a change in Vgs can be suppressed.

  Accordingly, in the drive control operation of the display pixel EM (pixel drive circuit DC), the voltage applied to the gate electrode of the double gate transistor that is a switching element for light emission drive when switching control from the selected state to the non-selected state is performed. Even when the voltage change is the same, compared to the case where a known field effect transistor is applied as a switching element for driving light emission (comparative object described above), the write current ( Since the difference in the light emission drive current (output current) with respect to the specified current is reduced, the light emitting element can be operated to emit light at a luminance gradation relatively corresponding to the display data.

  In this case, as shown in FIG. 5, as the top gate electrode Tr13tg of the double gate transistor Tr13 serving as a switching element for driving light emission, a pixel electrode (organic EL element OLED) electrically connected to the source electrode Tr13s is used. Can be formed integrally with the pixel electrode 14 by extending to the semiconductor layer SMC of the double-gate transistor Tr13, and only the patterning mask for the pixel electrode 14 is changed. Thus, the conventional manufacturing process can be applied as it is without adding a new process, and the film can be easily formed.

  In the above-described embodiment, a circuit configuration and an element structure in which a top gate electrode and a source electrode are electrically connected in a double gate transistor provided as a switching element for light emission driving in a pixel driving circuit are shown. The present invention is not limited to this, and the top gate electrode and the drain electrode may be connected in accordance with the channel polarity of the semiconductor layer constituting the double gate transistor.

  In addition, for the pixel electrode formed integrally with the top gate electrode of the double gate transistor, the top gate electrode (pixel electrode) is made to have a light reflection characteristic (that is, light) according to the light emission structure of the display panel (display pixel). In this case, the channel region (semiconductor layer) of the double gate transistor is shielded from light, so that the light-induced leakage current caused by the incidence of external light is reduced. While being able to reduce, the influence (for example, the influence by an adjacent electrode and wiring) of an external electric field can be shielded (shield).

  In the above-described embodiment, the circuit configuration and the element structure in which the double gate type transistor is applied only to the switching element for light emission driving in the pixel driving circuit are shown, but the present invention is not limited to this. A double gate transistor may be applied as the other transistors (that is, transistors Tr11 and Tr12) constituting the pixel drive circuit. In this case, by forming the top gate electrode of the double gate transistor applied to the transistors Tr11 and Tr12 using an opaque electrode material, the incidence of external light on the channel region is shielded, and the light-induced leakage current is reduced. In addition, the influence of an external electric field can be shielded.

1 is a schematic block diagram illustrating an embodiment of an image display device according to the present invention. It is a circuit block diagram which shows the specific circuit example of the display pixel (pixel drive circuit) applicable to the display apparatus which concerns on this embodiment. It is a cross-sectional block diagram which shows the example of the element structure of the double gate type transistor applicable to the pixel drive circuit which concerns on this embodiment. It is a plane layout figure which shows an example of the display pixel applicable to the display apparatus (display panel) which concerns on this embodiment. FIG. 5 is a schematic cross-sectional view showing an AA cross section in a display pixel having the planar layout shown in FIG. 4. 6 is a timing chart showing the basic operation of a display pixel to which the pixel driving circuit according to the present embodiment is applied. It is a conceptual diagram which shows the operation state of the pixel drive circuit which concerns on this embodiment. It is a conceptual diagram which shows the connection state of the capacitive component in the pixel drive circuit (comparative object) to which the transistor which has the same element structure is applied. It is a figure which shows the operating characteristic of the transistor for light emission drive applied to the pixel drive circuit shown as a comparison object. It is a figure which shows the operating characteristic of the light emission drive transistor applied to the pixel drive circuit which concerns on this embodiment. It is a figure for demonstrating the relationship between the element structure and channel potential in the double gate type transistor applied to the pixel drive circuit which concerns on this embodiment. It is a schematic block diagram which shows the principal part of the light emitting element type display in a prior art. It is an equivalent circuit diagram which shows the structural example of the display pixel (a pixel drive circuit and a light emitting element) applicable to the light emitting element type display in a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Image display apparatus 110 Display panel 120 Scan driver 130 Power supply driver 140 Data driver EM Display pixel DC Pixel drive circuit OLED Organic EL element SL Scan line VL Power supply voltage line DL Data line Tr11, Tr12 Field effect type transistor Tr13 Double gate type transistor Tr13tg Top gate electrode Tr13bg Bottom gate electrode 14 Pixel electrode (anode electrode)
17 Counter electrode (cathode electrode)

Claims (19)

  1. A pixel that emits light at a predetermined luminance gradation based on the gradation signal by supplying a light emission driving current having a current value corresponding to the gradation signal to a current control type light emitting element provided in the display pixel. In the drive circuit,
    at least,
    Charge holding means for holding charge based on the gradation signal as a voltage component;
    Drive current control means for generating the light emission drive current based on the voltage component held by the charge holding means and supplying the light emission drive current to the light emitting element;
    With
    The drive current control means includes a first gate electrode and a second gate electrode provided to face each other with a semiconductor layer interposed therebetween, and a source electrode and a drain electrode provided at both ends of the semiconductor layer. A double-gate thin film transistor structure,
    A pixel driver circuit, wherein the source electrode is connected to one end of the light emitting element, and the first gate electrode is set to be equal to the potential of the source electrode.
  2. 2. The pixel driving circuit according to claim 1, wherein the driving current control means is configured such that the first gate electrode and the source electrode are electrically connected.
  3. The light emitting element includes a pixel electrode, a light emitting layer provided on the pixel electrode, and a counter electrode provided to face the pixel electrode through the light emitting layer,
    3. The pixel driving circuit according to claim 1, wherein the driving current control unit is configured such that the first gate electrode and the source electrode are electrically connected to the pixel electrode.
  4. 4. The pixel drive circuit according to claim 3, wherein the drive current control means has the first gate electrode formed integrally with the pixel electrode.
  5. 5. The pixel driving circuit according to claim 3, wherein the pixel electrode is formed of an electrode material having light transmission characteristics.
  6. 5. The pixel driving circuit according to claim 3, wherein the pixel electrode is formed of an electrode material having light reflection characteristics.
  7. The pixel drive circuit according to claim 1, wherein the drive current control unit is provided so that the source electrode and the drain electrode extend on the semiconductor layer.
  8. 8. The drive current control unit includes a block insulating film on the semiconductor layer, and the source electrode and the drain electrode are provided so as to extend on the block insulating film. The pixel drive circuit described.
  9. 9. The pixel drive circuit according to claim 1, further comprising a gradation signal control unit that controls a timing at which the gradation signal is supplied to the charge holding unit. .
  10. 10. The pixel according to claim 9, wherein the gradation signal control means has a double gate type thin film transistor structure, and a gate electrode provided above the semiconductor layer is formed of a light shielding electrode material. Driving circuit.
  11. 11. The pixel driving circuit according to claim 1, wherein the semiconductor layer of the double gate type thin film transistor is made of amorphous silicon.
  12. 12. The pixel driving circuit according to claim 1, wherein the gradation signal is a signal current having a current value corresponding to the luminance gradation.
  13. A plurality of display pixels arranged near the intersections of a plurality of scanning lines and a plurality of signal lines arranged so as to be orthogonal to the display panel, according to display data via the signal lines. In an image display device that displays desired image information on the display panel by supplying a gradation signal,
    Each display pixel includes a current control type light emitting element and a pixel driving circuit that controls a light emitting operation of the light emitting element,
    The pixel drive circuit generates charge emission current based on at least charge holding means for holding charge based on the gradation signal as a voltage component, and voltage component held in the charge holding means, and Drive current control means for supplying to the light emitting element, and gradation signal control means for controlling the timing for supplying the gradation signal to the charge holding means,
    The drive current control means includes a first gate electrode and a second gate electrode provided to face each other with a semiconductor layer interposed therebetween, and a source electrode and a drain electrode provided at both ends of the semiconductor layer. A double-gate thin film transistor structure,
    An image display device, wherein the source electrode is connected to one end of the light emitting element, and the first gate electrode is set to be equal to the potential of the source electrode.
  14. The image display device is at least
    A selection state in which a selection signal is applied to the scanning line and the gradation signal control means provided in the display pixel connected to the scanning line can write the gradation signal to the display pixel. Scanning drive means set to
    Signal driving means for generating the gradation signal based on the display data corresponding to the display pixel set in the selected state and supplying the gradation signal to the signal line;
    The image display apparatus according to claim 13, further comprising:
  15. 15. The image display apparatus according to claim 14, wherein the gradation signal supplied from the signal driving means is a signal current having a current value corresponding to the display data.
  16. 16. The image display according to claim 13, wherein the drive current control means provided in the pixel drive circuit has the first gate electrode and the source electrode electrically connected. apparatus.
  17. The light emitting element includes a pixel electrode, a light emitting layer provided on the pixel electrode, and a counter electrode provided to face the pixel electrode through the light emitting layer,
    The image display according to claim 15 or 16, wherein the drive current control means provided in the pixel drive circuit has the first gate electrode and the source electrode electrically connected to the pixel electrode. apparatus.
  18. 18. The image display device according to claim 17, wherein the drive current control means provided in the pixel drive circuit has the first gate electrode formed integrally with the pixel electrode.
  19. The image display apparatus according to claim 13, wherein the light emitting element is an organic electroluminescent element.
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