JP2009063607A - Electro-optical device, method for controlling electro-optical device, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To compensate variations in the threshold voltage of a drive transistor with a simple configuration. <P>SOLUTION: Each of a plurality of unit circuits U includes a drive transistor TDR and an electro-optical element E. The drive transistor TDR includes a gate G which is set to a potential VG according to a data signal D[j], and a back gate B for controlling a channel formed according to the voltage VG of the gate G. Gradation of the electro-optical element E changes according to a drive current IDR flowing through the drive transistor TDR. A potential control circuit 36 supplies a characteristic control potential V[j] to the back gate B of the drive current TDR of each unit circuit U. Each characteristic control potential V[j] is set for each unit circuit U so that the gradation of the electro-optical element E is uniformized over the plurality of unit circuits when the potential VG of each drive transistor TDR is set to a prescribed potential. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technique for controlling an electro-optical element such as a light-emitting element.

In an electro-optical device that controls the drive current supplied to an electro-optical element in accordance with the potential of the gate of a transistor (hereinafter referred to as “drive transistor”), the level of each electro-optical element due to variations in the threshold voltage of the drive transistor. Tone unevenness becomes a problem. In Patent Document 1, the drive transistor of each pixel circuit is diode-connected, the gate is converged to a potential corresponding to its own threshold voltage, and then the gate potential is changed in accordance with data, whereby the threshold voltage of the drive transistor is changed. A technique for compensating for this variation is disclosed.
JP 2006-38965 A

  However, the technique of Patent Document 1 requires a large number of transistors and a large number of wirings for each electro-optical element, which causes a problem that the configuration of the electro-optical element is complicated. Further, in the technique of Patent Document 1, since the procedure for controlling the pixel circuit is complicated, there is a problem that the scale of the peripheral circuit that drives each pixel circuit is enlarged. In view of the above circumstances, an object of the present invention is to solve the problem of compensating for the influence of variations in threshold voltage of a driving transistor with a simple configuration.

  In order to solve the above problems, an electro-optical device according to the invention includes a gate whose potential is set according to a data signal and a characteristic control electrode that controls a channel formed according to the potential of the gate. A plurality of unit circuits each including a drive transistor and an electro-optical element whose gradation changes according to a drive current flowing through the drive transistor, and the gate of each drive transistor is set to a predetermined potential and the characteristics of each drive transistor The characteristic control potential set for each unit circuit is set so that the gradation of the electro-optic element is uniform over a plurality of unit circuits when the characteristic control potential is supplied to the control electrode. And a potential control circuit to be supplied to the control electrode. Note that an electro-optical element is an element whose gradation (brightness and transmittance) changes with the supply of electric energy (application of voltage or supply of current).

  According to the above configuration, since the characteristic control potential supplied to the characteristic control electrode of the driving transistor in each unit circuit is set for each unit circuit, the configuration of each driving transistor is simpler than that in Patent Document 1. It is possible to compensate for variations in threshold voltage (unevenness of gradation of electro-optic element). The characteristic control electrode is a back gate (eg, back gate B in FIG. 3) facing the gate across the semiconductor layer, or a channel electrode (eg, channel electrode 26 in FIG. 10) conducting to the channel contact region of the semiconductor layer. is there.

  In a preferred aspect of the present invention, each of the plurality of unit circuits includes a capacitive element that holds the potential of the characteristic control electrode. According to the above configuration, there is an advantage that the potential control circuit does not need to hold the characteristic control potential during the operation of the drive transistor.

  In a preferred aspect of the present invention, each of the plurality of unit circuits includes a first switching element (for example, in FIGS. 2, 7, and 9) that controls electrical connection between the characteristic control electrode of the driving transistor and the potential supply line. The potential control circuit supplies the characteristic control potential to the potential supply line corresponding to the unit circuit within a period in which the first switching element of each unit circuit is in the ON state. According to the above configuration, whether or not the characteristic control potential can be supplied to the characteristic control electrode of each driving transistor is controlled by the first switching element. For example, the characteristic control is performed in a time division manner for the driving transistors of a plurality of unit circuits. A potential can be supplied.

  In a preferred aspect of the present invention, each of the plurality of unit circuits includes a second switching element that controls electrical connection between the gate of the driving transistor and a signal line to which a data signal is supplied. The 1 switching element and the 2nd switching element are controlled according to the signal supplied to a common control line. According to the above configuration, since a common signal is shared for control of the first switching element and the second switching element, the first switching element and the second switching element are compared with the configuration controlled by separate signals. This has the advantage that the configuration of each unit circuit is simplified.

  In the electro-optical device according to a preferred aspect of the present invention, for each of the plurality of unit circuits, a detection unit that detects a detection current that flows through the driving transistor when the gate is set to a predetermined potential, and the detection unit detects Setting means for setting the characteristic control potential of each unit circuit according to the detected current. According to the above aspect, since each characteristic control potential is set according to the detection current that actually flows through the drive transistor, for example, an apparatus for measuring the gradation of the electro-optic element is not necessary. It is also possible to set each characteristic control potential so that a change with time of the characteristics of the driving transistor is compensated.

  The electro-optical device according to the invention is used in various electronic apparatuses. A typical example of an electronic device is a device that uses an electro-optical device as a display device. Examples of the electronic apparatus according to the present invention include a personal computer and a mobile phone. However, the use of the electro-optical device according to the present invention is not limited to image display. For example, the electro-optical device of the present invention can also be applied as an exposure device (exposure head) for forming a latent image on an image carrier such as a photosensitive drum by irradiation of light.

  The present invention is also specified as a method for controlling an electro-optical device including a plurality of unit circuits according to each of the above aspects. In the electro-optical device driving method according to the present invention, the gate of each driving transistor is set to a predetermined potential, and the gradation of the electro-optical element has a plurality of gradations when the characteristic control potential is supplied to the characteristic control electrode of each driving transistor. The characteristic control potential set for each unit circuit so as to be uniform over the unit circuits is supplied to the characteristic control electrode of the drive transistor of each unit circuit. According to the above method, the same operation and effect as the electro-optical device of the present invention are exhibited. In a more preferable method, for each of the plurality of unit circuits, a detection current flowing through the driving transistor when the gate is set to a predetermined potential is detected, and a characteristic control potential of each unit circuit is set according to the detection current. To do.

<A: First Embodiment>
FIG. 1 is a block diagram showing a configuration of an electro-optical device (display device) according to a first embodiment of the present invention. As shown in the figure, the electro-optical device 100 includes an element array unit 10 in which a plurality of unit circuits (pixel circuits) U are arranged, and peripheral circuits (control line drive circuits 32, 32) for driving each unit circuit U. A signal supply circuit 34, a potential control circuit 36, and a control circuit 40).

  The element array unit 10 includes a pair of m control line groups 12 extending in the X direction, n signal lines 14 extending in the Y direction intersecting the X direction, and pairs of the signal lines 14. N potential supply lines 16 extending in the Y direction are formed (each of m and n is a natural number of 2 or more). Each unit circuit U is arranged corresponding to each intersection of the control line group 12 and the signal line 14. Therefore, in the entire element array unit 10, the unit circuits U are arranged in a matrix of m rows × n columns across the X direction and the Y direction.

  FIG. 2 is a circuit diagram showing a specific configuration of each unit circuit U. In the drawing, only one unit circuit U in the j-th column (j = 1 to n) belonging to the i-th row (i = 1 to m) is representatively shown. As shown in FIG. 2, each control line group 12 in FIG. 1 is composed of three control lines (LSL, LBG, LDR).

  The unit circuit U includes an electro-optic element E. The electro-optical element E of this embodiment is an organic EL element in which a light emitting layer of an organic EL (Electroluminescence) material is interposed between an anode and a cathode that face each other. The electro-optical element E is driven at a gradation (luminance) corresponding to the amount of drive current IDR supplied to the light emitting layer. The cathode of the electro-optic element E is connected to the lower power supply GND.

  An N-channel type drive transistor TDR is arranged on the path of the drive current IDR (between the high-potential power supply VEL and the anode of the electro-optic element E). The drive transistor TDR is means for controlling the amount of drive current IDR according to the potential VG (gate-source voltage) of its gate G. A capacitive element C1 is interposed between the gate G of the driving transistor TDR and the lower power supply GND. The capacitive element C1 may be interposed between the gate G and a constant potential wiring other than the low-potential power supply GND.

  FIG. 3 is a cross-sectional view illustrating a specific structure of the drive transistor TDR. As shown in FIGS. 2 and 3, the driving transistor TDR is a four-terminal thin film transistor having a back gate B in addition to a gate G, a source S, and a drain D. The drive transistor TDR is formed together with each electro-optic element E on the surface of the insulating substrate 20.

  As shown in FIG. 3, the back gate B is formed on the surface of the substrate 20. The back gate B is covered with a gate insulating film 21, and a semiconductor layer (for example, a polysilicon film body) 22 is formed on the surface of the gate insulating film 21. A gate G is formed so as to face the channel region of the semiconductor layer 22 with the gate insulating film 23 on the surface of the semiconductor layer 22 interposed therebetween. That is, the back gate B is formed on the side opposite to the gate G with the semiconductor layer 22 interposed therebetween. A source S is connected to the source region of the semiconductor layer 22 through a through hole in the interlayer insulating layer 24, and a drain D is connected to the drain region of the semiconductor layer 22 through a through hole in the interlayer insulating layer 24.

  FIG. 4 is a graph illustrating the relationship between the gate-source voltage VG (horizontal axis) of the drive transistor TDR and the drive current IDR (vertical axis) flowing between the source and drain. The thickness of the channel formed in the semiconductor layer 22 according to the potential VG of the gate G changes according to the potential VB (voltage between the back gate and the source) of the back gate B. Therefore, the amount of drive current IDR increases or decreases according to the potential VB of the back gate B. That is, as shown in FIG. 4, the threshold voltage VTH of the drive transistor TDR decreases as the potential VB of the back gate B increases, so that the amount of drive current IDR with respect to the potential VG of the gate G increases. Further, the threshold voltage VTH of the drive transistor TDR increases as the potential VB of the back gate B decreases, so that the amount of drive current IDR with respect to the potential VG of the gate G decreases. As described above, the back gate B functions as an electrode (characteristic control electrode) for controlling the electrical characteristics of the drive transistor TDR.

  As shown in FIG. 2, the unit circuit U includes three switching elements SW (SW1, SW2, SW3). Each switching element SW is an N-channel thin film transistor formed on the surface of the substrate 20 together with the driving transistor TDR.

  The switching element SW1 is interposed between the back gate B of the driving transistor TDR and the potential supply line 16 in the j-th column and controls the electrical connection (conduction / non-conduction) between them. The gate of the switching element SW1 in each of the n unit circuits U belonging to the i-th row is commonly connected to the i-th row control line LBG. Further, a capacitive element C2 for holding the potential VB of the back gate B is interposed between the back gate B of the driving transistor TDR and the lower power supply GND. The capacitive element C2 may be interposed between the back gate B and a constant potential wiring other than the lower power supply GND.

  The switching element SW2 is interposed between the gate G of the drive transistor TDR and the signal line 14 in the j-th column and controls the electrical connection between them. The gate of the switching element SW2 in each of the n unit circuits U belonging to the i-th row is commonly connected to the i-th row control line LSL.

  The switching element SW3 is interposed between the source S of the driving transistor TDR and the anode of the electro-optical element E (that is, on the path of the driving current IDR) and controls the electrical connection between them. The gate of the switching element SW3 in each of the n unit circuits U belonging to the i-th row is commonly connected to the i-th row control line LDR. Since the path of the drive current IDR is established by the conduction of the switching element SW3, the switching element SW3 functions as a means for controlling whether or not the drive current IDR can be supplied to the electro-optical element E.

  Next, the function of the peripheral circuit will be described with reference to FIG. The control line drive circuit 32 is a circuit that drives each control line (LSL, LBG, LDR) of each of the m sets of control line groups 12. First, the control line driving circuit 32 generates control signals GSL [1] to GSL [m] for sequentially selecting the unit circuits U in units of rows and outputs the control signals GSL [1] to GSL [m] to the control lines LSL. As shown in FIG. 5, the control signal GSL [i] supplied to the control line LSL in the i-th row is included in m periods (hereinafter referred to as “writing period”) PWR set in the frame period F. It is set to a high level in the i-th writing period PWR and is maintained at a low level in a period other than the writing period PWR.

  Second, the control line drive circuit 32 generates control signals GBG [1] to GBG [m] and outputs them to the control lines LBG. As shown in FIG. 5, the control signal GBG [i] supplied to the i-th row control line LBG has the same waveform as the control signal GSL [i]. Third, the control line drive circuit 32 generates control signals GDR [1] to GDR [m] and outputs them to the control lines LDR. As shown in FIG. 5, the control signal GDR [i] supplied to the control line LDR of the i-th row is the control signal GSL next after the writing period PWR in which the control signal GSL [i] is at the high level. [i] is set to a high level in a predetermined period (hereinafter referred to as “driving period”) PDR before the start of the writing period PWR in which the level becomes high, and a period other than the driving period PDR (including the writing period PWR) ) To maintain the low level. A configuration in which the control signals GSL [1] to GSL [m], the control signals GBG [1] to GBG [m], and the control signals GDR [1] to GDR [m] are generated by separate circuits is also employed. The

  The signal supply circuit 34 in FIG. 1 generates data signals D [1] to D [n] that specify the gradation of each unit circuit U and outputs the data signals to each signal line 14. The data signal D [j] supplied to the signal line 14 in the j-th column is the unit circuit U in the j-th column belonging to the i-th row in the writing period PWR in which the control signal GSL [i] is at the high level. Is set to the potential VDATA corresponding to the gradation specified in.

  The control circuit 40 in FIG. 1 controls the control line drive circuit 32, the signal supply circuit 34, and the potential control circuit 36 by outputting various signals such as a synchronization signal. As shown in FIG. 1, the control circuit 40 includes a memory circuit 42. The storage circuit 42 stores correction data A [1,1] to A [m, n] individually for each unit circuit U (m × n) constituting the element array unit 10. The correction data A [i, j] is data for compensating for variations in the threshold voltage VTH of the drive transistor TDR in the unit circuit U in the j-th column belonging to the i-th row. Details of the correction data A [i, j] will be described later.

  The potential control circuit 36 generates characteristic control potentials V [1] to V [n] and outputs them to each potential supply line 16. The characteristic control potential V [j] supplied to the potential supply line 16 in the j-th column is the correction data A [stored in the storage circuit 42 during the writing period PWR in which the control signal GBG [i] is at the high level. i, j] is set to a potential.

  Next, the operation of the unit circuit U in the j-th column belonging to the i-th row will be described. When the control signal GSL [i] changes to a high level in the writing period PWR (that is, when the i-th row is selected), the switching element SW2 is turned on. Therefore, the potential VDATA of the data signal D [j] is supplied from the signal line 14 in the j-th column to the gate G of the driving transistor TDR via the switching element SW2, and the charge corresponding to the potential VDATA is supplied to the capacitive element C1. Accumulated. That is, the potential VG of the gate G of the drive transistor TDR is set and held at the potential VDATA of the data signal D [j].

  Further, in the writing period PWR, the control signal GBG [i] is set to a high level together with the control signal GSL [i], so that the switching element SW1 is turned on and the back gate B of the driving transistor TDR and the jth column The eye potential supply line 16 is electrically connected. Therefore, the characteristic control potential V [j] corresponding to the correction data A [i, j] is supplied from the potential control circuit 36 to the back gate B of the driving transistor TDR, and also according to the characteristic control potential V [j]. Charge is accumulated in the capacitive element C2. That is, the potential VB of the back gate B of the driving transistor TDR in the unit circuit U in the j-th column belonging to the i-th row is set and held at the characteristic control potential V [j] corresponding to the correction data A [i, j]. The In other words, the electrical characteristics of the drive transistor TDR (the relationship between the potential VG of the gate G and the current amount of the drive current IDR) are corrected according to the characteristic control potential V [j] (correction data A [i, j]). Is done.

  When the control signal GDR [i] transitions to a high level in the driving period PDR after the writing period PWR has elapsed, the switching element SW3 transitions to the on state and the path of the driving current IDR is established. Also in the driving period PDR, the potential VG of the gate G and the potential VB of the back gate B of the driving transistor TDR are maintained at the potential set in the immediately preceding writing period PWR. Therefore, the drive current IDR obtained by correcting the amount of current according to the potential VG of the gate G of the drive transistor TDR according to the characteristic control potential V [j] (correction data A [i, j]) is driven from the high-order power supply VEL. It is supplied to the electro-optical element E through the transistor TDR and the switching element SW3. The electro-optical element E emits light with an intensity corresponding to the amount of the drive current IDR (that is, an intensity corresponding to the potential VDATA and the characteristic control potential V [j] of the data signal D [j]). A desired image is displayed on the element array unit 10 by controlling the gradation of each electro-optical element E by the above procedure.

  The correction data A [1,1] to A [m, n] (characteristic control potential V [1] to V [n]) sets the potential VG of the gate G of the driving transistor TDR in each unit circuit U to a predetermined value. In this case, the gradation of each electro-optical element E is set to be uniform over all the unit circuits U of the element array unit 10. For example, when the data signal D [1] to D [n] of the same potential VDATA is supplied to each unit circuit U to drive the electro-optical element E (that is, when the same gradation is instructed to all the unit circuits U) The element array unit 10) is imaged by an imaging device, and the actual luminance (gradation) of each electro-optical element E is measured. Then, correction data A [1,1] to A [m, n] are selected based on the measured luminance value of each unit circuit U so that the gradation of each electro-optical element E is made uniform.

  As illustrated in FIG. 4, in the N-channel type drive transistor TDR, the amount of drive current IDR (drive capability) with respect to the potential VG of the gate G decreases as the potential VB of the back gate B decreases. Therefore, when the characteristic control potential V [j] of the unit circuit U whose measured luminance value matches the target value is the reference value VREF1, the characteristic control potential supplied to the unit circuit U whose measured luminance value is lower than the target value. Correction is made so that the characteristic control potential V [j] supplied to the unit circuit U where the V [j] is higher than the reference value VREF1 and the measured luminance value is higher than the target value is lower than the reference value VREF1. Data A [1,1] to A [m, n] are set.

  Assuming that the electrical and optical characteristics of each electro-optical element E are the same for each unit circuit U, the correction data A [1,1] to A [m, n] are stored in each drive transistor TDR. It can also be said that the threshold voltage VTH is set to be equalized to a predetermined value. As illustrated in FIG. 4, in the N-channel type drive transistor TDR, the threshold voltage VTH decreases as the potential VB of the back gate B increases. Therefore, if the characteristic control potential V [j] supplied to the drive transistor TDR whose threshold voltage VTH matches the target value is the reference value VREF2, the characteristic control supplied to the drive transistor TDR whose threshold voltage VTH is lower than the target value. Correction is made so that the potential V [j] is lower than the reference value VREF2, and the characteristic control potential V [j] supplied to the drive transistor TDR whose threshold voltage VTH is higher than the target value is higher than the reference value VREF2. Data A [1,1] to A [m, n] are set.

  As described above, in this embodiment, since the characteristic control potential V [j] set for each unit circuit U is supplied to the back gate B of the drive transistor TDR of each unit circuit U, the drive transistor TDR Variations in electrical characteristics (deviations from design values due to differences in characteristics between unit circuits U and deterioration over time) are compensated. Therefore, gradation unevenness in the element array unit 10 can be suppressed. In addition, since a large number of transistors and a large number of wirings as in the technique of Patent Document 1 are not required for each unit circuit U, the present invention can be easily applied to the electro-optical device 100 in which a large number of unit circuits U are arranged with high definition. The Further, since the procedure for driving each unit circuit U is extremely simple, there is an advantage that the enlargement of the scale of the peripheral circuit is suppressed as compared with the configuration of Patent Document 1.

<B: Second Embodiment>
Next, a second embodiment of the present invention will be described. In the first embodiment, the correction data A [1,1] to A [m, n] (characteristic control potential V [] is based on the measured luminance value of each electro-optical element E when each unit circuit U is driven. 1] to V [j]) were selected. In the second embodiment, the function of detecting the electrical characteristics of the drive transistor TDR of each unit circuit U and the function of setting the correction data A [1,1] to A [m, n] based on the detection result Are provided in the electro-optical device 100. In addition, about the element which an effect | action and function are common in 1st Embodiment in each following form, the same code | symbol as above is attached | subjected, and each detailed description is abbreviate | omitted suitably.

  FIG. 6 is a block diagram illustrating a configuration of the electro-optical device 100. As shown in the figure, n detection lines 18 are formed in the element array section 10 of the electro-optical device 100 so as to be paired with the signal lines 14 and extend in the Y direction. A detection current IDT [j] reflecting the electrical characteristics of the drive transistor TDR in each unit circuit U in the j-th column is output to the detection line 18 in the j-th column. The detection circuit 52 in FIG. 6 acquires the detection currents IDT [1] to IDT [n] flowing through the detection lines 18 and sequentially outputs them to the setting circuit 54. The setting circuit 54 generates and updates the correction data A [1,1] to A [m, n] of the storage circuit 42 based on the detection currents IDT [1] to IDT [n].

  FIG. 7 is a circuit diagram showing a configuration of the unit circuit U in the j-th column belonging to the i-th row. As shown in the figure, the control line group 12 includes a control line LDT in addition to the three control lines (LSL, LBG, LDR) of the first embodiment. The control line drive circuit 32 generates control signals GDT [1] to GDT [m] and outputs them to the control lines LDT.

  As shown in FIG. 7, the unit circuit U has a configuration in which a switching element SW4 is added to the unit circuit U of the first embodiment. The switching element SW4 is an N-channel type thin film transistor formed on the surface of the substrate 20 together with the driving transistor TDR. The switching element SW4 is interposed between the path of the drive current IDR (specifically, the source S of the drive transistor TDR) and the detection line 18 in the j-th column and controls the electrical connection between them. The gate of the switching element SW4 in each of the n unit circuits U belonging to the i-th row is commonly connected to the i-th row control line LDT. A configuration in which the switching element SW4 is interposed between the drain D of the driving transistor TDR and the detection line 18 in the j-th column is also employed.

  FIG. 8 is a timing chart showing waveforms of signals supplied to the unit circuit U in the j-th column belonging to the i-th row. As shown in FIG. 8, the control signal GSL [i] is set to the high level in the writing period PWR and the detection period PDT immediately before the writing period PWR. Similar to the control signal GSL [i], the control signal GBG [i] is set to a high level in the detection period PDT and the writing period PWR. The control signal GDR [i] is a driving period from the elapse of the writing period PWR in which the control signal GSL [i] is at the high level to the next start of the detection period PDT in which the control signal GSL [i] is at the high level. High level is set by PDR. Further, the control signal GDT [i] supplied to the control line LDT in the i-th row is set to the high level in the detection period PDT in which the control signal GSL [i] is at the high level, and is a period other than the detection period PDT. The low level is maintained (including the writing period PWR and the driving period PDR).

  The signal supply circuit 34 sets the data signals D [1] to D [n] to a predetermined potential VDT in the detection period PDT in which each of the control signals GDT [1] to GDT [m] is at a high level, and writes In the pull-in period PWR, the data signals D [1] to D [n] are set to the potential VDATA as in the first embodiment. The potential VDT is set so that the drive transistor TDR becomes conductive when supplied to the gate G. In addition, the potential control circuit 36 has a predetermined initialization potential for the n potential supply lines 16 in the detection period PDT during the period in which the control signal GSL [i] and the control signal GBG [i] are at a high level. In addition to supplying VRS, the characteristic control potential V [j] corresponding to the correction data A [i, j] is supplied to the potential supply line 16 in the j-th column in the writing period PWR following the detection period PDT.

  Next, a specific operation of the unit circuit U will be described by focusing on the i-th row and the j-th column. When the control signal GSL [i] changes to a high level during the detection period PDT and the switching element SW2 is turned on, the potential VDT of the data signal D [j] supplied to the signal line 14 in the j-th column. Is supplied to the gate G of the drive transistor TDR via the switching element SW2. In addition, since the switching element SW1 is turned on when the control signal GBG [i] changes to the high level together with the control signal GSL [i], the initialization potential VRS is supplied from the potential supply line 16 in the detection period PDT. It is supplied to the back gate B of the drive transistor TDR via the switching element SW1.

  Further, since the control signal GDT [i] is set to a high level in the detection period PDT, the source S of the driving transistor TDR and the detection line 18 in the j-th column are electrically connected when the switching element SW4 is turned on. Connected. Since the control signal GDR [i] is set to the low level, the switching element SW3 maintains the OFF state. Therefore, in the detection period PDT, the potential VG (VDT) of the gate G of the drive transistor TDR and the potential of the back gate B A detection current IDT [j] corresponding to VB (VRS) is supplied to the detection circuit 52 from the high potential side power supply VEL via the drive transistor TDR, the switching element SW4, and the detection line 18 in the jth column. The detection circuit 52 outputs the detection currents IDT [1] to IDT [n] to the setting circuit 54 in order.

  The setting circuit 54 detects each of the detection currents IDT [1] to IDT [n] so that the gradation of each electro-optical element E in the drive period PDR (current amount of the drive current IDR flowing through each drive transistor TDR) is uniformized. ], The i-th correction data A [i, 1] to A [i, n] are generated and stored in the memory circuit 42. For example, if the characteristic control potential V [j] when the current amount of the detected current IDT [j] matches the target value is the reference value VREF3, the detected current IDT [j] having a current amount lower than the target value is detected. The characteristic control potential V [j] supplied to the unit circuit U is higher than the reference value VREF3, and the characteristic control potential supplied to the unit circuit U in which the detected current IDT [j] having a current amount exceeding the target value is detected. The setting circuit 54 adjusts the correction data A [i, 1] to A [i, n] (in other words, the characteristic control potentials V [1] to V [n] so that V [j] is lower than the reference value VREF3. ) Is set.

  In the writing period PWR, characteristic control potentials V [1] to V [n] corresponding to the correction data A [i, 1] to A [i, n] set by the setting circuit 54 in the immediately preceding detection period PDT. Is output from the potential control circuit 36 to each potential supply line 16, and is supplied to the back gate B of the drive transistor TDR via the switching element SW1 turned on by the high level control signal GBG [i]. The operation in which the potential VDATA of the data signal D [j] is supplied to the gate G of the drive transistor TDR in the writing period PWR and the operation in which the drive current IDR is supplied to the electro-optical element E in the drive period PDR are described in the first embodiment. It is the same.

  As described above, since the characteristic control potential V [j] set for each unit circuit U is supplied to the back gate B of the drive transistor TDR, the electrical characteristics of the drive transistor TDR are the same as in the first embodiment. Variation in various characteristics is compensated. In addition, correction data A [1,1] to A [m, n] (characteristic control potentials V [1] to V [V] are calculated based on the detection currents IDT [1] to IDT [n] that actually flow through the drive transistors TDR. n]) is updated, an imaging device for observing the element array unit 10 is not necessary when setting the correction data A [1,1] to A [m, n]. In addition, since the imaging device is unnecessary, the correction data A [1,1] to A [m, n] can be easily updated at any time after the electro-optical device 100 is shipped. Therefore, even when the electrical characteristics of each driving transistor TDR change over time, the correction data A [1,1] to A [m, n] so as to compensate for the variation in characteristics after the change. There is an advantage that the gradation of each electro-optical element E can be made uniform by updating (characteristic control potentials V [1] to V [n]). Further, the potential VB of the back gate B set to the characteristic control potential V [j] in the writing period PWR is initialized to the initialization potential VRS in the detection period PDT after the driving period PDR has elapsed. Detection currents IDT [1] to IDT [n] that accurately reflect the electrical characteristics of the drive transistor TDR are output. Therefore, it is possible to set correction data A [1,1] to A [m, n] (characteristic control potentials V [1] to V [n]) that can compensate for variations in characteristics of the drive transistor TDR with high accuracy. it can.

<C: Third Embodiment>
FIG. 9 is a circuit diagram showing a configuration of the unit circuit U of the electro-optical device 100 according to the third embodiment of the present invention. As shown in FIG. 9, the control line group 12 of this embodiment is composed of a control line LSL and a control line LDR, and does not include the control line LBG. The gates of both the switching element SW1 and the switching element SW2 are connected to the control line LSL. Therefore, the switching element SW1 and the switching element SW2 are controlled according to a common control signal GSL [i] that the control line drive circuit 32 supplies to the control line LSL. That is, in the write period PWR, the control signal GSL [i] transitions to a high level, whereby the switching element SW1 and the switching element SW2 become conductive. Therefore, as in the first embodiment, the gate G of the drive transistor TDR The potential VG is set to the potential VDATA of the data signal D [j], and the potential VB of the back gate B of the driving transistor TDR is set to the characteristic control potential V [j]. Therefore, the same effect as the first embodiment is achieved.

  According to the present embodiment, since the control signal GSL [i] is used for both the switching element SW1 and the switching element SW2, the element array is compared with the first embodiment in which each is controlled by a separate signal. There are advantages that the number of wirings in the unit 10 is reduced and the configuration of the control line driving circuit 32 is simplified. 9 illustrates the modification of the unit circuit U of the first embodiment, the unit circuit U of the second embodiment is similarly modified. That is, the switching element SW1 and the switching element SW2 in FIG. 7 are connected to the common control line LSL.

<D: Modification>
Various modifications are added to the above embodiments. An example of a specific modification is as follows. Two or more aspects may be arbitrarily selected from the following examples and combined.

(1) Modification 1
In each of the above embodiments, the potential VB of the back gate B of the drive transistor TDR is controlled. As a configuration for adjusting (correcting) the electrical characteristics of the drive transistor TDR, for example, a channel contact (body described below) A contact structure is also preferably employed.

  FIG. 10 is a plan view showing the configuration of an N-channel type drive transistor TDR employing a channel contact structure. The drive transistor TDR has a semiconductor layer 25 formed on the surface of the substrate 20 (not shown in FIG. 10). A gate G is formed so as to face the semiconductor layer 25 with a gate insulating film (not shown) covering the semiconductor layer 25 interposed therebetween. In the semiconductor layer 25, a source region 25s, a drain region 25d, and a channel contact region 25c are formed after the gate G is formed. The source region 25s and the drain region 25d are regions into which N-type impurities are introduced. The channel contact region 25c is a region into which an N-type impurity having the same conductivity type as the channel of the driving transistor TDR is introduced.

  An interlayer insulating layer (not shown) is formed so as to cover the semiconductor layer 25 and the gate G. A plurality of through holes (H1, H2, H3) are formed in the interlayer insulating layer. A source S is connected to the source region 25s of the semiconductor layer 25 through a through hole H1, and a drain D is connected to the drain region 25d through a through hole H2. A channel electrode 26 is connected to the channel contact region 25c of the semiconductor layer 25 through a through hole H3.

  The configuration of the unit circuit U is the same as that of the above embodiments. As shown in FIG. 10, the channel electrode 26 of the drive transistor TDR is connected to the potential supply line 16 via the switching element SW1. Therefore, when the control signal GBG [i] (control signal GSL [i] in the third embodiment) transits to a high level, the characteristic control potential V [j] output from the potential control circuit 36 is changed to the potential supply line 16 and the switching element. The signal is supplied to the channel contact region 25c of the drive transistor TDR via SW1 and the channel electrode 26. The electrical characteristics of the drive transistor TDR (the relationship between the potential VG of the gate G and the amount of current of the drive current IDR) vary depending on the potential of the channel contact region 25c. Therefore, even in the configuration employing the channel contact structure, the correction data A [1,1] to A [m, n] (characteristic control potentials V [1] to V [n]) are appropriately controlled to As in the first embodiment, it is possible to suppress uneven gradation of each electro-optic element E.

  As described above, the characteristic control electrode (back gate B or channel electrode 26) for controlling the channel formed in the semiconductor layer in accordance with the potential VG of the gate G is formed in the drive transistor TDR, and for each unit circuit U. A configuration in which the set characteristic control potential V [j] is supplied to the characteristic control electrode is preferably employed.

(2) Modification 2
In each of the above embodiments, the characteristic control potential V [j] is supplied to the back gate B (the channel electrode 26 in FIG. 10) in the writing period PWR of each frame period F, but the characteristic control potential V [j] is supplied. The timing and number of times of supply to the unit circuit U are arbitrary. For example, the characteristic control potential V [j] is supplied in the writing period PWR only in a predetermined number of frame periods F, or the characteristic control is performed in a period set separately from the writing period PWR and the driving period PDR. A configuration for supplying the potential V [j] is also employed. In addition, the characteristic control potential V [j] is supplied every predetermined time set regardless of the frame period F or the configuration in which the characteristic control potential V [j] is supplied immediately after the electro-optical device 100 is turned on. A configuration for supplying is also suitable. In the configuration in which the characteristic control potential V [j] is held in the capacitive element C2 of the unit circuit U as shown in FIGS. 2 and 7, the characteristic control potential is reduced before the voltage of the capacitive element C2 is significantly reduced due to charge leakage. It is desirable to newly supply V [j] (refresh the voltage of the capacitive element C2).

(3) Modification 3
In the second embodiment, the configuration in which the detection currents IDT [1] to IDT [n] are detected immediately before each writing period PWR is exemplified. However, the detection (correction) of the detection currents IDT [1] to IDT [n] is exemplified. The timing and frequency of data A [i, 1] to A [i, n] are arbitrary. For example, a configuration in which the detection currents IDT [1] to IDT [n] are detected in a predetermined number of frame periods F, or a detection current IDT [1] immediately after the electro-optical device 100 is turned on or every predetermined time. ] To IDT [n] are also employed. Further, the correction data A [i, 1] to A [i, n] set from the detection currents IDT [1] to IDT [n] in the detection period PDT of one frame period F are used as the frame period F for the next and subsequent times. A configuration in which the potential control circuit 36 is used to generate the characteristic control potentials V [1] to V [n] in the writing period PWR is also suitable. According to the above configuration, it is not necessary to reflect the detection currents IDT [1] to IDT [n] in the detection period PDT to the characteristic control potentials V [1] to V [n] in the immediately subsequent write period PWR. There is an advantage that the operation speed required for the detection circuit 52 and the setting circuit 54 is reduced.

(4) Modification 4
The configuration of the unit circuit U is changed as appropriate. For example, the back gate B (channel electrode 26 in FIG. 10) of each driving transistor TDR is individually connected to the potential control circuit 36 for each unit circuit U (the potential control circuit 36 applies the characteristic control potential V [j to the driving transistor TDR). ] Can be omitted, the capacitor C2 and the switching element SW1 can be omitted. Further, in the electro-optical device 100 in which the unit circuits U are arranged in a single column (for example, an exposure apparatus employed in an electrophotographic image forming apparatus), an operation of selecting each unit circuit U in units of rows is unnecessary. The switching element SW2 is omitted, and the gate G of the drive transistor TDR is directly connected to the signal line 14. Further, when the light emission of the electro-optical element E in the writing period PWR is not a particular problem, the switching element SW3 is omitted (the driving current IDR is supplied to the electro-optical element E even in the writing period PWR). ) Is also adopted.

  The conductivity type of each transistor constituting the unit circuit U is arbitrary. For example, a P-channel type thin film transistor is employed as the drive transistor TDR. In the P-channel type drive transistor TDR, the amount of drive current IDR with respect to the potential VG of the gate G decreases as the potential VB of the back gate B (or the channel electrode 26 in FIG. 10) increases. Therefore, the characteristic control potential V [j] of the unit circuit U with the low gradation of the electro-optical element E (the threshold voltage VTH of the driving transistor TDR is low and the amount of the driving current IDR is small) is the gradation of the electro-optical element E. Is set lower than the characteristic control potential V [j] of the unit circuit U (the threshold voltage VTH of the drive transistor TDR is high and the amount of the drive current IDR is large).

(5) Modification 5
The organic EL element is only an example of the electro-optical element E. For example, light-emitting elements such as inorganic EL elements and LED (Light Emitting Diode) elements are also used as the electro-optical element E. The electro-optical element E in each of the above embodiments is an element whose optical characteristics (luminance) are changed by supplying the drive current IDR.

<E: Application example>
Next, electronic equipment using the electro-optical device according to the invention will be described. FIGS. 11 to 13 show a form of an electronic apparatus that employs the electro-optical device 100 according to any one of the forms described above as a display device.

  FIG. 11 is a perspective view illustrating a configuration of a mobile personal computer that employs the electro-optical device 100. The personal computer 2000 includes an electro-optical device 100 that displays various images, and a main body 2010 on which a power switch 2001 and a keyboard 2002 are installed. Since the electro-optical device 100 uses an organic light-emitting diode element as the electro-optical element E, it is possible to display an easy-to-see screen with a wide viewing angle.

  FIG. 12 is a perspective view illustrating a configuration of a mobile phone to which the electro-optical device 100 is applied. The cellular phone 3000 includes a plurality of operation buttons 3001 and scroll buttons 3002, and the electro-optical device 100 that displays various images. By operating the scroll button 3002, the screen displayed on the electro-optical device 100 is scrolled.

  FIG. 13 is a perspective view illustrating a configuration of a personal digital assistant (PDA) to which the electro-optical device 100 is applied. The information portable terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and the electro-optical device 100 that displays various images. When the power switch 4002 is operated, various information such as an address book and a schedule book are displayed on the electro-optical device 100.

  The electronic apparatus to which the electro-optical device according to the present invention is applied includes the digital still camera, the television, the video camera, the car navigation device, the pager, the electronic notebook, and the electronic paper in addition to the apparatuses illustrated in FIGS. Calculators, word processors, workstations, videophones, POS terminals, printers, scanners, copiers, video players, devices with touch panels, and the like. The use of the electro-optical device according to the invention is not limited to image display. For example, the electro-optical device of the present invention is also used as an exposure device that forms a latent image on a photosensitive drum by exposure in an electrophotographic image forming device.

1 is a block diagram illustrating a configuration of an electro-optical device according to a first embodiment of the invention. FIG. It is a circuit diagram which shows the structure of a unit circuit. It is sectional drawing which shows the structure of a drive transistor. It is a graph which shows the electrical property of a drive transistor. 6 is a timing chart for explaining the operation of the electro-optical device. FIG. 6 is a block diagram illustrating a configuration of an electro-optical device according to a second embodiment of the invention. It is a circuit diagram which shows the structure of a unit circuit. 6 is a timing chart for explaining the operation of the electro-optical device. It is a circuit diagram which shows the structure of the unit circuit which concerns on 3rd Embodiment of this invention. It is a top view which shows the structure of the drive transistor of a channel contact structure. It is a perspective view which shows the form (personal computer) of an electronic device. It is a perspective view which shows the form (cellular phone) of an electronic device. It is a perspective view which shows the form (mobile information terminal) of an electronic device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Electro-optical apparatus, U ... Unit circuit, 10 ... Element array part, 12 ... Control line group, LSL, LBG, LDR ... Control line, 14 ... Signal line, 16 ... Potential supply line, 18... Detection line 32... Control line drive circuit 34... Signal supply circuit 36... Potential control circuit 40... Control circuit 42. Circuit, E ... Electro-optic element, TDR ... Drive transistor, SW1-SW4 ... Switching element, C1, C2 ... Capacitance element, GSL [i] (GSL [1] -GSL [m]), GBG [i ] (GBG [1] to GBG [m]), GDR [i] (GDR [1] to GDR [m]), GDT [i] (GDT [1] to GDT [m]) ... Control signal, D [j] (D [1] to D [n]) …… Data signal, V [j] (V [1] to V [n]) …… Characteristic control potential, IDT [j] (IDT [1] to IDT [n]) …… Detected current, A [1,1] to A [m, n] …… Correction data.

Claims (8)

A driving transistor including a gate whose potential is set in accordance with a data signal and a characteristic control electrode for controlling a channel formed in accordance with the potential of the gate, and a gray scale level in accordance with a driving current flowing in the driving transistor A plurality of unit circuits each including a varying electro-optic element;
The gate of each driving transistor is set to a predetermined potential, and the gradation of the electro-optic element when the characteristic control potential is supplied to the characteristic control electrode of each driving transistor is made uniform over the plurality of unit circuits. And an electric potential control circuit for supplying the characteristic control potential set for each unit circuit to the characteristic control electrode of the drive transistor of each unit circuit. The electro-optical device according to claim 1, wherein each of the plurality of unit circuits includes a capacitive element that holds a potential of the characteristic control electrode. Each of the plurality of unit circuits includes a first switching element that controls electrical connection between a characteristic control electrode of the driving transistor and a potential supply line,
3. The potential control circuit supplies the characteristic control potential to a potential supply line corresponding to the unit circuit within a period in which the first switching element of each unit circuit is in an ON state. Electro-optic device. Each of the plurality of unit circuits includes a second switching element that controls electrical connection between a gate of the driving transistor and a signal line to which the data signal is supplied,
The electro-optical device according to claim 3, wherein the first switching element and the second switching element in each unit circuit are controlled according to a signal supplied to a common control line. For each of the plurality of unit circuits, detection means for detecting a detection current flowing through the drive transistor when the gate is set to a predetermined potential;
5. The electro-optical device according to claim 1, further comprising: a setting unit that sets a characteristic control potential of each unit circuit in accordance with a detection current detected by the detection unit.   An electronic apparatus comprising the electro-optical device according to claim 5. A method of controlling an electro-optical device including a plurality of unit circuits each including an electro-optical element whose gradation changes according to a driving current flowing in a driving transistor,
The drive transistor includes a gate whose potential is set according to a data signal, and a characteristic control electrode that controls a channel formed according to the potential of the gate,
The gate of each driving transistor is set to a predetermined potential, and the gradation of the electro-optical element when the characteristic control potential is supplied to the characteristic control electrode of each driving transistor is made uniform over the plurality of unit circuits. A control method for an electro-optical device, wherein the characteristic control potential set for each unit circuit is supplied to a characteristic control electrode of a drive transistor of each unit circuit. For each of the plurality of unit circuits, a detection current flowing through the drive transistor when the gate is set to a predetermined potential is detected,
The method of controlling an electro-optical device according to claim 7, wherein a characteristic control potential of each unit circuit is set according to the detection current.

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