JP2013054161A - Electro-optical device, driving method of the same and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress display unevenness with high accuracy.SOLUTION: An electro-optical device comprises: a pixel circuit; and a driving circuit for driving the pixel circuit. The pixel circuit includes: a transistor 131 and an OLED 140 connected in series between a power source line 116 and an electrode 117; and a capacitive element 136 whose one end is connected to a source node s of the transistor 131 and other end is connected to a signal line 118. In an initialization period, the driving circuit supplies a low side potential Vel_L to the power source line 116 and an initialization potential causing the transistor 131 to be a conduction state to a gate node g of the transistor 131. In a set period, the driving circuit supplies a high side potential Vel_H to the power source line 116 and the initialization potential to the gate node g. In a writing period, the driving circuit supplies a data signal of a potential corresponding to a gradation level to the gate node g. The driving circuit supplies a ramp signal that causes a potential to be Vref from the initialization period to the middle of the set period, raises the potential from Vref to Vx at the middle thereof and, subsequently, linearly lowers the potential to Vref to the signal line 118.

Description

  The present invention relates to an electro-optical device, a driving method of the electro-optical device, and an electronic apparatus.

  In recent years, various electro-optical devices using light emitting elements such as organic light emitting diode (hereinafter referred to as “OLED”) elements have been proposed. In this electro-optical device, a pixel circuit is provided corresponding to a pixel of an image to be displayed. The pixel circuit generally has a circuit configuration including a transistor that supplies current to the light emitting element in addition to the light emitting element. In such a circuit configuration, if the characteristics such as the threshold voltage and mobility of the transistors are different for each pixel circuit, display unevenness that impairs the uniformity of the display screen occurs. For this reason, a technique for compensating characteristics such as a threshold voltage and mobility of a transistor has been proposed (see, for example, Patent Document 1).

JP 2008-122632 A

However, in this technique, the operation for compensating the threshold voltage of the transistor that supplies current to the light-emitting element is repeatedly executed in a plurality of horizontal periods preceding the sampling of the video signal. Becomes shorter. Therefore, there is a problem that it is difficult to ensure a sufficient length of the light emission period.
The present invention has been made in view of such circumstances, and one of its purposes is to shorten the time required to set the target voltage between the gate and the source of the transistor in the period preceding sampling. Therefore, the length of the light emission period is ensured accordingly.

In order to achieve the above object, an electro-optical device according to the present invention includes a pixel circuit and a drive circuit that drives the pixel circuit, and the pixel circuit includes a first power supply line and a second power supply line. A first transistor and a light emitting element connected in series with each other, a capacitor having one end connected to a node on the non-connection side of the first transistor and the first power supply line, and the other end connected to a signal line The driving circuit supplies the second potential of the first potential on the higher side or the second potential on the lower side with respect to the first power supply line in the first period; An initialization potential that makes the first transistor conductive is supplied to the gate of one transistor, and the first potential is supplied to the first power supply line in a second period after the first period. , With respect to the gate of the first transistor After supplying the initializing potential and changing the voltage between the gate and the source of the first transistor in the direction in which the voltage between the gate and source of the first transistor is lowered during the second period, a set current is supplied to the capacitor element. A waveform signal whose potential changes with time is supplied so as to flow, and a data signal having a potential corresponding to a gradation level is supplied to the gate of the first transistor in a third period after the second period. It is characterized by that.
According to the present invention, in the second period, the potential of the waveform signal changes while the voltage necessary for the set current to flow through the first transistor is set between the gate and the source of the first transistor. Due to this potential change, the voltage between the gate and the source varies in the direction of lowering. Therefore, in the present invention, the time length required for setting can be shortened as compared with the case where the threshold voltage is set between the gate and the source.

  In the present invention, the drive circuit linearly changes from the fourth potential to the third potential after changing the waveform signal from the third potential to the fourth potential in the middle of the second period. It is good also as a mode to make it change, and it is good also as a mode made to change toward the said 3rd potential from the said 4th electric potential so that the end point of the said 3rd period may be included, and it is good from the 1st period to the middle of the 2nd period It is good also as an aspect made into the said 3rd electric potential.

In the present invention, the pixel circuit includes a second transistor disposed between a gate of the first transistor and a data line, and the driving circuit includes the second transistor in the first period and the second period. Further, a configuration may be adopted in which the conductive state is set in the third period, the initialization potential is supplied to the data line in the first period and the second period, and the data signal is supplied in the third period.
In this configuration, the semiconductor device further includes a third transistor disposed between the data line and a power supply line to which the initialization potential is supplied, and the third transistor is conductive in the first period and the second period. It is good also as a structure which will be in a state.
In addition to the electro-optical device, the present invention can be conceptualized as a driving method of the electro-optical device or an electronic apparatus having the electro-optical device. The electronic device is typically a display device, and examples of the electronic device include a personal computer and a mobile phone. However, the use of the electro-optical device according to the invention is not limited to the display device. For example, the present invention can also be applied to an exposure apparatus (optical head) for forming a latent image on an image carrier such as a photosensitive drum by irradiation of light.

1 is a block diagram illustrating a configuration of an electro-optical device according to an embodiment. It is a figure which shows the pixel circuit in an electro-optical apparatus. It is a figure which shows the operation | movement in an electro-optical apparatus. It is a figure for demonstrating operation | movement of a pixel circuit. It is a figure for demonstrating operation | movement of a pixel circuit. It is a figure for demonstrating operation | movement of a pixel circuit. It is a figure for demonstrating operation | movement of a pixel circuit. It is a figure for demonstrating operation | movement of a pixel circuit. It is a figure for demonstrating operation | movement of a pixel circuit. FIG. 3 is a diagram illustrating an electronic apparatus (part 1) using the electro-optical device of the embodiment. It is a figure which shows the electronic device (the 2) using the electro-optical apparatus of embodiment. FIG. 6 is a diagram illustrating an electronic apparatus (part 3) using the electro-optical device according to the embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram illustrating a configuration of an electro-optical device according to an embodiment of the invention. As shown in this figure, the electro-optical device 10 is roughly divided into a display unit 100, a scanning line driving circuit 160, a power supply line driving circuit 170, and a demultiplexer 240.
Among these, in the display unit 100, pixel circuits 110 corresponding to pixels of an image to be displayed are arranged in a matrix. Specifically, in the display unit 100, first, m rows of scanning lines 112 are provided so as to extend in the horizontal direction in the drawing, and (3n) columns of data lines 114 are grouped every three columns. The scanning lines 112 are provided so as to extend in the vertical direction and to be electrically insulated from each scanning line 112. Next, the pixel circuit 110 is provided corresponding to the intersection of the m rows of scanning lines 112 and the (3n) columns of data lines 114. For this reason, in the present embodiment, the pixel circuits 110 are arranged in a matrix form of vertical m rows × horizontal (3n) columns.

Here, m and n are both natural numbers. In order to distinguish the row (row) of the matrix of the scanning line 112 and the pixel circuit 110, they may be referred to as 1, 2, 3,... (M−1), m rows in order from the top in the drawing. In order to generalize and describe the group of data lines 114, when an integer j of 1 to n is used, the (3j-2) th column, the (3j-1) th column and the (3j-1) th column counted from the left in FIG. The data lines 114 in the (3j) th column belong to the jth block.
Further, the display unit 100 is provided with individual power supply lines 116 and signal lines 118 for each row, and is shared over the pixel circuits 110 for one row.

The electro-optical device 10 is supplied with the following control signals and data signals from a host control device (not shown). That is, the control signal Ctra for controlling the scanning line driving circuit 160, the control signal Ctrb for controlling the power supply line driving circuit 170, and the control signal Sel (1) for controlling selection of the demultiplexer 240 from the control device. , Sel (2), Sel (3), and the control signal Gini for initialization are supplied.
Also, data signals Vd (1), Vd (2),..., Vd (n) are supplied from the control device corresponding to the first, second,. The maximum potential value Vdata (max) that can be taken by the data signals Vd (1) to Vd (n) corresponds to the white level with the maximum luminance, and the minimum value Vdata (min) corresponds to the black level with the minimum luminance.

  The scanning line driving circuit 160 generates a scanning signal for sequentially scanning the scanning lines 112 for each row over the period of the frame in accordance with the control signal Ctra. Here, the scanning signals supplied to the scanning lines 112 of 1, 2, 3,..., (M−1) and the m-th row are Gwr (1), Gwr (2), Gwr (3),. It is written as Gwr (m-1) and Gwr (m). The term “frame period” refers to a period required for the electro-optical device 10 to display an image for one cut (frame). If the vertical scanning frequency is 60 Hz, 16.67 milliseconds for one cycle. Is the period.

The power supply line driving circuit 170 synchronizes the potentials of the power supply line 116 and the signal line 118 in the 1st, 2nd, 3rd,... Thus, each is controlled. Specifically, the power supply line driving circuit 170 switches and supplies the power supply line 116 to either the high potential Vel_H as the first potential or the low potential Vel_L as the second potential. In FIG. 1, Vel (1), Vel (2) are respectively used in order to distinguish the power supply potentials supplied to the power supply lines 116 of 1, 2, 3,. ), Vel (3),..., Vel (m−1), Vel (m).
On the other hand, the power supply line driving circuit 170 supplies the following ramp signal (waveform signal) to the signal line 118 corresponding to the scanning line 112 that is horizontally scanned. That is, as will be described later, the power supply line driving circuit 170 rises from the potential Vref as the third potential to the potential Vx as the fourth potential in the middle of the set period, and then to the potential Vref at the end of the writing period. A ramp signal that falls linearly is supplied. In order to distinguish the ramp signals supplied to the signal lines 118 in the first, second, third,..., (M−1) and m-th rows, Vrmp (1), Vrmp (2), Vrmp (3),. , Vrmp (m-1), Vrmp (m).
The power supply driving circuit 170 also supplies the initialization potential Vini to the power supply line 124.

The demultiplexer 240 is an aggregate of N-channel type transistors 242 provided for each data line 114, and distributes data signals in order to the three columns of data lines 114 constituting each block.
Here, in the data line 114 located in the leftmost column in each block, and in the j-th block, the transistor 242 provided in the data line 114 in the (3j-2) th column has a control signal Sel (1) of H When it is level, it is turned on (conducted), and the data signal is sampled on the data line 114 in the left end column.
Similarly, in each block, the data line 114 located in the center column and the rightmost column, and in the j-th block, the transistor 242 provided in the data line 114 in the (3j-1) and (3j) columns is controlled. When the signals Sel (2) and Sel (3) are at the H level, they are turned on, and the data signals are sampled on the center and right end data lines 114, respectively.
Although not shown, each column data line 114 has parasitic capacitance. Therefore, when the transistor 242 is turned on and the data signal is sampled on the data line 114, the potential of the data signal is held by the parasitic capacitance even if the transistor 242 is turned off (non-conducting) thereafter. It has a configuration.

  An N-channel transistor 120 is provided for each data line 114. In the transistor 120, the gate node is connected to the control signal line 122 that supplies the control signal Gini, one of the source or drain node is connected to the power supply line 124, and the other of the source or drain node is connected to the data line 114. It is connected. The control signal Gini is a signal that becomes H level during an initialization period and a set period, which will be described later, and becomes L level during other periods in the scanning period of each row.

  In the present embodiment, the scanning line driving circuit 160, the power supply line driving circuit 170, and the demultiplexer 240 are divided for convenience, but these are collectively considered as a driving circuit for driving the pixel circuit 110. Is also possible.

The pixel circuit 110 will be described with reference to FIG. In this figure, the i-th row and the (i + 1) -th scanning line 112 adjacent to the lower side of the i-th row and (3j-2) columns among the three columns belonging to the j-th block The pixel circuit 110 for a total of four pixels of 2 × 2 corresponding to the intersection with the data line 114 of the (3j-1) column adjacent on the right side with respect to the eye and the (3j-2) column is shown. .
As shown in the figure, each pixel circuit 110 includes N-channel transistors 131 and 132, capacitive elements 135 and 136, and an OLED 140. Since each pixel circuit 110 has the same configuration when viewed electrically, the pixel circuit 110 will be described as being representatively located in the i row (3j-2) column.

  In the pixel circuit 110 in the i row (3j-2) column, the gate node of the transistor 132 is connected to the scanning line 112 in the i row. In the transistor 132, one of the drain node and the source node is connected to the data line 114, and the other of the drain node and the source node is connected to one end of the capacitor 135 and the gate node g of the transistor 131.

The other end of the capacitive element 135 is connected to the source node s of the transistor 131, one end of the capacitive element 136, and the anode of the OLED 140. The drain node d of the transistor 131 is connected to the i-th power line 116. The other end of the capacitive element 136 is connected to the i-th signal line 118.
Here, the transistor 131 becomes a first transistor, and the transistor 132 becomes a second transistor. Further, the source node s is a node that is not connected to the power supply line 116 (first power supply line). As the capacitor 135, a capacitor parasitic on the gate node g of the transistor 131 may be used.

  The anode of the OLED 140 is a pixel electrode provided individually for each pixel circuit 110. On the other hand, the cathode of the OLED 140 is a common electrode 117 (second power supply line) throughout the pixel circuit 110, and is kept at the lower potential Vct of the power supply. The OLED 140 is an element in which a light emitting layer made of an organic EL material is sandwiched between an anode facing each other and a cathode having transparency, for example, on a glass substrate. In the OLED 140, when a current flows in the forward direction from the anode toward the cathode in a state where the light emission threshold voltage is exceeded, light is generated at a luminance corresponding to the current and passes through the cathode on the side opposite to the substrate. It is configured to be visually recognized by the observer side.

  In FIG. 2, Gwr (i) and Gwr (i + 1) are scanning signals supplied to the scanning lines 112 in the i and (i + 1) th rows, respectively. Vel (i) and Vel (i + 1) are power supply potentials supplied to the power line 116 in the i and (i + 1) th row, respectively, and Vrmp (i) and Vrmp (i + 1) are i, This is a ramp signal supplied to the signal line 118 in the (i + 1) th row.

  The display unit 100 is generally formed on a transparent insulating substrate such as a glass substrate. For this reason, the transistors 131 and 132 in the pixel circuit 110 of the display unit 100 are, for example, thin film transistors, and are formed of amorphous silicon or low-temperature polysilicon. In the case of using low-temperature polysilicon, the active elements constituting the scanning line driver circuit 160 and the power line driver circuit 170 and the transistors 120 and 242 can be formed on the insulating substrate together with the pixel circuit 110. Further, the entire electro-optical device 10 may be formed on a semiconductor substrate such as a silicon substrate.

The operation of the electro-optical device 10 will be described with reference to FIG. FIG. 3 is a waveform diagram for explaining the operation of each part in the electro-optical device 10, but the vertical scale indicating the potentials of signals other than the logic signal is different between waveforms for convenience of explanation. There is a case.
As shown in this figure, the scanning line driving circuit 160 switches the potentials of the scanning signals Gwr (1) to Gwr (m), so that the scanning lines 112 in the 1st to mth rows perform one horizontal scanning in the period of one frame. Scanning is performed in order for each period (H).
The operation in one horizontal scanning period (H) is common to the pixel circuits 110 in each row. Accordingly, in the following, attention is focused on the pixel circuit 110 of the (3j-2) column belonging to the j-th block in the i-th row in the scanning period in which the i-th scanning line 112 is horizontally scanned. I will explain.

  In this embodiment, the scanning period of the i-th row is roughly divided into an initialization period, a set period, a sampling period, and a writing period in the order of time. The light emission period is from the time when the condition described later is satisfied after the end of the writing period until the initialization period of the next frame starts, and these periods are repeated. Note that the set period is a period in which a target voltage is set in the capacitor 135, and the writing period includes a period in which the mobility μ of the transistor 131 is compensated.

<Light emission period>
For convenience of explanation, a presumed light emission period will be described before the i-th scanning period. As shown in FIG. 3, in the light emission period, the scanning signal Gwr (i) is at the L level. Therefore, in the pixel circuit 110 in the i row (3j-2) column, as shown in FIG. 4, the transistor 132 is off and the gate node g is electrically disconnected from the data line 114. Become.
Since the ramp signal Vrmp (i) is constant at the potential Vref, no current flows through the capacitive element 136.
In addition, a voltage compensated so as to cancel the characteristics of the transistor 131 with respect to a potential corresponding to the gradation level is set between the gate and the source of the transistor 131, as will be described later. Yes. Since the potential Vel (i) is the higher potential Vel_H, the OLED 140 is supplied with a current Idr corresponding to the gate-source voltage Vgs as shown in FIG. For this reason, the OLED 140 emits light in a state in which the characteristics of the transistor 131 are canceled out with luminance according to the gradation level. At this time, the source node s (the anode of the OLED 140 and one end of the capacitor 136) is held at a potential corresponding to the current Idr during the light emission period.

<Initialization period>
Next, the scanning period of the i-th row is reached. The beginning of the scanning period is an initialization period as the first period. As shown in FIG. 3, in the initialization period of the i-th row, the control signal Gini and the scanning signal Gwr (i) are each at the H level. Therefore, as shown in FIG. 5, in the pixel circuit 110 in the i row (3j-2) column, the transistors 120 and 132 are turned on. Accordingly, since the gate node g is electrically connected to the power supply line 124 via the transistor 132, the data line 114, and the transistor 120, the gate node g is set to the initialization potential Vini (see FIG. 3).

On the other hand, the potential Vel (i) in the power supply line 116 is switched to the lower potential Vel_L by the power supply line driving circuit 170. Here, the voltage difference between the potential Vel_L and the initialization potential Vini is set to be sufficiently higher than the threshold voltage Vth of the transistor 131. Therefore, since the transistor 131 is turned on, the source node s is reset to the potential Vel_L of the power supply line 116 as illustrated in FIG. 3 or FIG.
Therefore, in the pixel circuit 110 in the i-th row, the voltage Vgs between the gate and the source of the transistor 131 (the holding voltage of the capacitor 135) is initialized to the voltage (Vini−Vel_L), and is uniformly aligned. Become.

  The source node s is also the anode of the OLED 140. At this time, the potential Vel_L of the anode of the OLED 140 is set so that the voltage difference from the potential Vct of the cathode of the OLED 140 does not exceed the light emission threshold voltage of the OLED 140. For this reason, the OLED 140 that has been in the on state during the light emission period is in the off state (non-light emission state) during the initialization period.

<Set period>
Following the initialization period, a set period as a second period is reached. As shown in FIG. 3, in the set period of the i-th row, the potential Vel (i) in the power line 116 in the i-th row is switched to the higher potential Vel_H compared to the initialization period. Thus, current flows from the power supply line 116 between the drain and source of the transistor 131 that is in the on state, so that the source node s starts to rise from the potential Vel_L (see FIG. 3).

In the middle of the i-th set period, the ramp signal Vrmp (i) rises from the potential Vref to the potential Vx. On the other hand, since the scanning signal Gwr (i) and the control signal Gini are continuously at the H level in the set period, the transistors 131 and 120 are turned on, and the gate node g is fixed to the initialization potential Vini.
Therefore, as shown in FIG. 3 or FIG. 6, the potential of the source node s, which is the connection point of the capacitive elements 135 and 136, is the other of the capacitive element 136 when viewed at the moment when the ramp signal Vrmp (i) rises. The voltage variation (Vx−Vref) of the ramp signal Vrmp (i) supplied to the end rises by the amount divided by the capacitance ratio of the capacitive elements 135 and 135.

After the potential of the ramp signal Vrmp (i) rises during the set period of the i-th row, it decreases at a constant rate of change. Therefore, as shown in FIG. 7, the set current Is flows from the power supply line 116 to the signal line 118 via the transistor 131 and the capacitor 136 in order.
Therefore, during the set period, the voltage between the gate and the source of the transistor 131 converges to a voltage (Vth + Va) necessary for the set current Is to flow through the transistor 131 itself. In other words, in the set period, the source node s is saturated at a potential lower than the initialization potential Vini by the voltage (Vth + Va) as shown in FIG.

  In this embodiment, the difference voltage between the saturation potential (Vini−Vth−Va) of the source node s that is the anode of the OLED 140 and the cathode potential Vct of the OLED 140 is set to be lower than the light emission threshold voltage of the OLED 140. Is done. For this reason, OLED140 maintains an OFF state also in a set period.

<Sampling period>
After the set period, the sampling period is reached. As shown in FIG. 3, in the sampling period of the i-th row, the scanning signal Gwr (i) and the control signal Gini are each at the L level as compared with the set period. Therefore, in the pixel circuit 110 in the i-th row (3j-2) column, as shown in FIG. 8, the transistor 132 is turned off, so that the gate node g of the transistor 131 is the (3j-2) -th column. The data line 114 is electrically disconnected, that is, a high impedance (floating) state.
Since the transistors 120 in each column are also turned off, each data line 114 is electrically disconnected from the power supply line 124. Therefore, each data line 114 is maintained at the initialization potential Vini by the parasitic capacitance until the next data signal is sampled.
Even during the sampling period, the potential of the ramp signal Vrmp (i) decreases at a constant rate of change, so that the set current Is continues to flow. Therefore, the voltage (Vth + Va) at the end of the set period is maintained between the gate and the source of the transistor 131.

In the sampling period of the i-th row, the control device (not shown) outputs the data signals Vd (1) to Vd (n) as the data signals Vd (1) to Vd (n). Data signals having potentials corresponding to the gradation levels of the pixels in the column are sequentially supplied. Therefore, as shown in FIG. 3, the data signal Vd (j) corresponding to the j-th block is a pixel in i row (3j-2) column, a pixel in i row (3j-1) column, i row (3j) The potential changes according to the gradation level of the pixels in the column.
Further, the control signals Sel (1), Sel (2), and Sel (3) are exclusively set to the H level in accordance with the output of the data signal by the control device. As a result, in the demultiplexer 240, the transistors 242 are turned on in the order of the leftmost column, the center column, and the rightmost column in each block, so that each data line 114 has a pixel level of the corresponding column in the i-th row. A data signal having a potential corresponding to the tone level is sampled. In the data line 114 in the (3j-2) th column, as shown in FIG. 8, the potential Vdata corresponding to the gradation level of the pixel in the i-th row (3j-2) column is sampled as a data signal. Note that when the control signals Sel (1), Sel (2), and Sel (3) are at L level, the transistors 242 in each column are turned off. Therefore, the data lines 114 in each column are in a floating state, but the potential of the sampled data signal is held as it is by the parasitic capacitance.

<Writing period>
After the sampling period, the writing period as the third period is reached. As shown in FIG. 3, in the writing period of the i-th row, the scanning signal Gwr (i) becomes H level again as compared with the sampling period. For this reason, in the pixel circuit 110 in the i-th row (3j-2) column, the transistor 131 is turned on again as shown in FIG. 9, so that the data in the (3j-2) -th column is stored in the gate node g. The potential Vdata of the sampled data signal is set to the line 114. For this reason, since the current Ids corresponding to the potential Vdata flows through the transistor 131, the potential of the source node s starts to rise again as shown in FIG.

  In the i-th set period, the potential of the ramp signal Vrmp (i) decreases at the same rate as the sampling period with time, so that the set current Is is supplied from the source node s to the i-th line via the capacitive element 136. It flows in the path to the signal line 118 of the eye. As a result, the current Ids flowing through the transistor 131 branches from the source node s into a set current Is flowing toward the capacitive element 136 and a current flowing toward the capacitive element 135 (Ids−Is).

At this time, the voltage Vgs between the gate and the source of the transistor 131 is subjected to negative feedback control (mobility compensation) by the current Ids flowing through the transistor 131 as follows.
That is, if the mobility μ of the transistor 131 is small, the current flowing from the drain node d to the source node s decreases even if the gate node g is at the same potential Vdata. For this reason, the potential increase amount ΔV of the source node s is reduced (see FIG. 3), and the change amount (negative feedback amount) of the voltage Vgs is increased accordingly, so that the transistor 131 having the small mobility μ is used. The control works in the direction in which a large amount of current flows.
On the other hand, if the mobility μ of the transistor 131 is large, even if the gate node g is at the same potential Vdata, the current flowing from the drain node d to the source node s increases. For this reason, the potential increase amount ΔV of the source node s increases, and the change amount (negative feedback amount) of the voltage Vgs decreases accordingly, so that a small amount of current flows through the transistor 131 having a high mobility μ. Control works in the direction.
Thus, as shown in FIG. 3, the gate-source voltage Vgs of the transistor 131 eventually converges to the voltage (Vdata + Vth + Va−ΔV) by the end of the writing period.

<Light emission period>
When the writing period ends, as shown in FIG. 3, the potential Gwr (i) of the scanning signal becomes L level again. Therefore, as shown in FIG. 4, the transistor 132 is turned off, so that the gate node g is in a floating state. At this time, the gate-source voltage Vgs (the voltage across the capacitor 135) in the transistor 131 is maintained at the voltage at the end of the writing period (Vdata + Vth + Va−ΔV). Current Idr flows.
In the writing period, the decrease in the potential of the ramp signal Vrmp (i) is stopped and becomes constant at the potential Vref. Therefore, the set current Is does not flow through the capacitor 136.

As a result, as shown in FIG. 3, the potential of the source node s, which is one end of the capacitor 136, rises again with time. Since the gate node g is in a floating state, the potential of the gate node g rises in conjunction with the potential rise of the source node s. That is, the gate node g and the source node s rise while maintaining the voltage (Vdata + Vth + Va−ΔV) at the end of the writing period.
In the process of increasing the potential of the source node s, when the voltage across the OLED 140 exceeds the light emission threshold voltage, part of the current Idr begins to flow through the OLED 140 and light emission starts. When the charging of the capacitive element 136 is completed soon, all of the current Ids flows to the OLED 140, so that the OLED 140 continues to emit light with a luminance corresponding to the current Idr.

  Since the gate-source voltage Vgs is (Vdata + Vth + Va−ΔV), the current Idr supplied to the OLED 140 by the transistor 131 is first affected by the threshold voltage Vth when the transistor 131 operates in the saturation region. Is offset. In addition, since the voltage Vgs is negative feedback controlled according to the mobility μ of the transistor 131, even if the mobility μ of the transistor 131 is different for each pixel circuit 110, the influence due to the variation in the current Idr can be suppressed.

Such an operation is executed in parallel in time in the i-th pixel circuit 110 other than the pixel circuit 110 in the (3j-2) th column of interest in the i-th scanning period. Further, such an operation on the i-th row is executed in the order of 1, 2, 3,..., (M−1), m-th row in the period of one frame and is repeated for each frame.
In this operation, the OLED 140 in each pixel circuit 110 is supplied with a current compensated for variations in the threshold voltage Vth and mobility μ of the transistor 131.
Therefore, according to the present embodiment, even if the characteristics of the transistor 131 vary for each pixel circuit 110, luminance unevenness due to the variation is suppressed, so that high-quality display is possible.

By the way, in the conventional technique described in the background art section, the transistor 131 is turned on while being fixed at the initialization potential Vini, whereby the voltage between the gate and the source of the transistor 131 is changed to the threshold voltage of the transistor 131. Asymptotically approaching Vth. However, in this technique, as the voltage between the gate and the source of the transistor 131 approaches the threshold voltage Vth, the current flowing from the drain node d to the source node s becomes very small, and the time change rate of the voltage between the gate and the source is very high. Get smaller. For this reason, it takes a very long time until the voltage between the gate and the source of the transistor 131 reaches the target threshold voltage (until the value of the current flowing through the transistor 131 becomes zero). It will be.
On the other hand, in this embodiment, the set current Is flows from the drain node d of the transistor 131 to the source node s even at the end of the set period, so that the voltage between the gate and source of the transistor 131 is the target. The time required to reach the voltage (Vth + Va) can be shortened, and the length of the light emission period can be ensured accordingly.

In the present embodiment, the ramp signal Vrmp (i) rises from the potential Vref to the potential Vx in the middle of the set period of the i-th row. With this rise, as shown in FIG. 3, the voltage Vgs between the gate and the source of the transistor 131 is lowered at a stretch and becomes close to the target voltage (Vth + Va). Therefore, according to the present embodiment, even if the set period is shortened, the gate-source voltage Vgs of the transistor 131 can sufficiently reach the target voltage (Vth + Va) within the set period. .
In other words, when the voltage is set between the gate and the source only by the current flowing from the drain node d to the source node s, the target voltage (Vth + Va) is not reached within the set period as shown by the broken line in FIG. There is a time. At this time, since the threshold voltage of the transistor 131 is not sufficiently compensated, display unevenness occurs.
In contrast, in the present embodiment, the target voltage (Vth + Va) is reached between the gate and source of the transistor 131 even in a short set period, so that the threshold voltage is compensated more reliably and the occurrence of display unevenness is suppressed. High-quality display is possible.

  Note that in order to make the voltage between the gate and the source of the transistor 131 reach the target voltage by the end of the set period, at first glance, it seems that the potential Vel_L should be increased. However, when the potential Vel_L is increased, the voltage difference from the cathode potential Vct of the OLED 140 tends to exceed the light emission threshold voltage of the OLED 140. If the light emission threshold voltage is exceeded, for example, even when black having the lowest gradation level is designated, the light emission state is entered. For this reason, since the expression characteristic on the low gradation side is deteriorated, the potential Vel_L cannot be increased unnecessarily.

The present invention is not limited to the above-described embodiments, and various modifications and applications are possible.
For example, in the embodiment described above, either the potential Vel_H or the potential Vel_L is supplied to the power supply line 116 for each row in synchronization with the scanning of the scanning line 112. A power supply line and a lower power supply line for supplying the potential Vel_L may be provided, and a switch for selecting one of the power supply lines may be provided in the pixel circuit 110 and supplied to the drain node d of the transistor 131.

  In the embodiment, the data lines 114 are grouped for each of a plurality of lines, and in each group, the data lines 114 in three columns are selected in order, and the data signal is supplied. May be “2” or “4” or more. Further, a configuration may be adopted in which data signals are supplied all at once to the data lines 114 in each column in the writing period without being grouped. In any case, any structure may be employed as long as a data signal having a potential corresponding to the gradation level is supplied to the gate node g when the transistor 131 is turned on in the writing period.

On the other hand, each of the transistors 131 and 132 is an N-channel type, but either one or both may be a P-channel type.
In the embodiment, the OLED 140 is exemplified as the light emitting element. However, an element that emits light with luminance according to current, such as an inorganic EL element or an LED (Light Emitting Diode) element, can be applied.

<Electronic equipment>
Next, some electronic apparatuses to which the electro-optical device according to the invention is applied will be described.
FIG. 10 is a diagram illustrating an appearance of a personal computer as an electronic apparatus (part 1) that employs the electro-optical device 10 according to the above-described embodiment as a display device. The personal computer 2000 includes an electro-optical device 10 as a display device and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002. In the electro-optical device 10, when the OLED 140 is used as a light emitting element, a screen display with a wide viewing angle and easy viewing is possible.

  FIG. 11 is a diagram illustrating an appearance of a mobile phone that is an electronic apparatus (part 2) that employs the electro-optical device 10 according to the embodiment as a display device. The cellular phone 3000 includes the electro-optical device 10 described above together with the earpiece 3003 and the mouthpiece 3004 in addition to the plurality of operation buttons 3001 and the direction key 3002. By operating the direction key 3002, the screen displayed on the electro-optical device 10 is scrolled.

  FIG. 12 is a diagram illustrating an appearance of a personal digital assistant (PDA) as an electronic apparatus (part 3) that employs the electro-optical device 10 according to the embodiment as a display device. The portable information terminal 4000 includes the above-described electro-optical device 10 in addition to a plurality of operation buttons 4001 and direction keys 4002. In the portable information terminal 4000, various kinds of information such as an address book and a schedule book are displayed on the electro-optical device 10 by a predetermined operation, and the displayed information is scrolled according to the operation of the direction key 4002.

  The electronic apparatus to which the electro-optical device according to the invention is applied includes, in addition to the examples shown in FIGS. 10 to 12, a television, a car navigation device, a pager, an electronic notebook, electronic paper, a calculator, a word processor, a work Stations, videophones, POS terminals, printers, scanners, copiers, video players, devices equipped with a touch panel, and the like.

DESCRIPTION OF SYMBOLS 10 ... Electro-optical device, 110 ... Pixel circuit, 112 ... Scan line, 114 ... Data line, 116 ... Power supply line, 117 ... Electrode, 118 ... Signal line, 120 ... Transistor, 131 ... Transistor, 132 ... Transistor, 135 ... Capacitor Element 136 ... Capacitor element 140 ... Light emitting element 160 ... Scanning line driving circuit 170 ... Power line driving circuit 240 ... Demultiplexer 242 ... Transistor 2000 ... Personal computer 3000 ... Mobile phone 4000 ... Mobile information terminal .

Claims (8)

A pixel circuit; and a drive circuit that drives the pixel circuit;
The pixel circuit includes:
A first transistor and a light emitting element connected in series between the first power line and the second power line;
A capacitive element having one end connected to a node on the non-connection side of the first transistor and the first power supply line, and the other end connected to a signal line;
Including
The drive circuit is
Supplying the second potential out of the first potential on the higher side or the second potential on the lower side with respect to the first power supply line in the first period;
Supplying an initialization potential for bringing the first transistor into a conductive state with respect to the gate of the first transistor;
In a second period after the first period, the first potential is supplied to the first power supply line, the initialization potential is supplied to the gate of the first transistor, and the signal line is supplied. Then, after changing the voltage between the gate and the source of the first transistor in the middle of the second period, the waveform signal whose potential changes with time so that a set current flows through the capacitor element. Supply
An electro-optical device, wherein a data signal having a potential corresponding to a gradation level is supplied to a gate of the first transistor in a third period after the second period. The drive circuit changes the waveform signal linearly from the fourth potential to the third potential after changing from the third potential to the fourth potential in the middle of the second period. The electro-optical device according to claim 1. The electro-optical device according to claim 2, wherein the drive circuit changes the waveform signal from the fourth potential toward the third potential so as to include the end point of the third period. The electro-optical device according to claim 3, wherein the driving circuit causes the waveform signal to be the third potential from the first period to the middle of the second period. The pixel circuit includes:
A second transistor disposed between the gate of the first transistor and the data line;
The drive circuit is
The second transistor is turned on in the first period, the second period, and the third period,
5. The electricity according to claim 1, wherein the initialization potential is supplied to the data line during the first period and the second period, and the data signal is supplied during the third period. Optical device. A third transistor disposed between the data line and a power supply line to which the initialization potential is supplied;
The electro-optical device according to claim 5, wherein the third transistor is in a conductive state in the first period and the second period. A first transistor and a light emitting element connected in series between the first power line and the second power line;
A capacitive element having one end connected to a node on the non-connection side of the first transistor and the first power supply line, and the other end connected to a signal line;
An electro-optical device driving method including:
In the first period, the second potential is supplied to the first power supply line from the first potential on the higher side or the second potential on the lower side, and the first transistor is turned on to the gate of the first transistor. Supply initialization potential to
In a second period after the first period, the first potential is supplied to the first power supply line, the initialization potential is supplied to the gate of the first transistor, and the signal line is supplied. Then, after changing the voltage between the gate and the source of the first transistor in the middle of the second period, the waveform signal whose potential changes with time so that a set current flows through the capacitor element. Supply
A method for driving an electro-optical device, wherein a data signal having a potential corresponding to a gradation level is supplied to a gate of the first transistor in a third period after the second period. An electronic apparatus comprising the electro-optical device according to claim 1.

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