TW201305577A - Parallel test method - Google Patents

Abstract

A parallel test method is provided. The parallel test method comprises the steps as follows. A test instrument having driving channels and power channels is provided. The driving channels have a first group and a second group. A under-test chip comprising signal pins and at least one power pin is provided. The signal pins are connected to the driving channels belonging to the first group. Each of the power pins is connected to one of the driver channels belonging to the second group in parallel. The signal pins receive driving signals from the channels belonging to the first group and the power pins receive power signals of different sources from the driver channels belonging to the second group such that the parallel test is performed on the under-test chips.

Description

Parallel test method

The present disclosure is directed to an electronic device testing method, and more particularly to a parallel testing method.

Wafer testing is the last step in the wafer process. However, a large number of wafers often take a lot of time to test, such as the ability to test many wafers simultaneously on a single machine, which will save a lot of test costs and time costs. In order to achieve parallel testing, it has been common to share the power provided by one test machine with several chips to be tested, so as to achieve parallel testing in the case where the power supply of the test machine is not much. However, in such a design, when one of the wafers to be tested is short-circuited, the impact of a large current will cause the wafer to be tested with which the power source is shared to be damaged. Furthermore, in the test procedure of some of the power pins of the test chip, it is also impossible to measure a single wafer due to the power sharing, and it is difficult to distinguish which is caused when an abnormal condition occurs.

Therefore, how to design a new parallel test method to overcome the above problems is an urgent problem to be solved in the industry.

Accordingly, one aspect of the present disclosure is to provide a parallel test method comprising the steps of: providing a test machine, wherein the test machine includes a plurality of driver channels and a plurality of power channels, wherein the drive channels comprise the first group And the second group; the plurality of chips to be tested are provided, wherein each of the chips to be tested includes a plurality of signal pins and at least one power pin; and the signal pins of the chips to be tested are connected to the driving channels located in the first group; The power pins of the chips to be tested are respectively connected in parallel to one of the driving channels of the second group; and the signal pins of the chip to be tested are received from the driving signals of the first group, and the driving signals are received, and The power supply pins of the test chip are respectively received from the parallel connection of the drive channels of the second group to receive power signals of different origins, and the test wafers are tested in parallel.

According to an embodiment of the present disclosure, one of the signal pins of each of the chips to be tested shares one of the driving channels located in the second group.

According to another embodiment of the present disclosure, each of the signal pins of each of the chips to be tested is connected in parallel to one of the driving channels located in the second group.

According to still another embodiment of the present disclosure, the test machine further includes a plurality of input and output channels, and each of the chips to be tested includes at least one input and output pin. The parallel test method further comprises the steps of: connecting each input and output pin of each chip to be tested in parallel to one of the input and output channels; and respectively receiving input and output pins of the chip to be tested from the input and output channels of the parallel connection respectively. The output signal is tested in parallel with the wafer to be tested.

According to still another embodiment of the present disclosure, the signal pin includes a write protection pin, a chip selection pin to be tested, a clock pin, a retention pin, and a program pump voltage pin.

There is further an embodiment in accordance with the present disclosure in which the parallel test includes a standby current test. The standby current test is used to measure the standby current of the power pins of each chip to be tested.

There is yet another embodiment in accordance with the present disclosure in which the parallel test is a circuit probing test. Parallel testing is DC power wafer testing or AC power wafer testing.

The advantage of the application of the present disclosure is that by connecting the power pins in parallel with the driving channels of the test machine, in addition to avoiding that the power channel of the test machine is insufficient to supply a large number of parallel tested wafers to be tested, Increase the accuracy of the test and easily achieve the above objectives.

Please refer to Figure 1. FIG. 1 is a flow chart of a parallel testing method in an embodiment of the disclosure. Please also refer to Figure 2. FIG. 2 is a schematic diagram of the test machine 20 and a plurality of wafers 22 to be tested connected in an embodiment of the disclosure. The parallel test method includes the following steps (it should be understood that the steps mentioned in the present embodiment can be adjusted according to actual needs, and can be performed simultaneously or partially simultaneously, unless otherwise specified.

In step 101, a test machine 20 as shown in FIG. 2 and a plurality of wafers 22 to be tested are provided. The wafer to be tested 22 is a finished product after the wafer is subjected to a process of slicing, grinding, exposing, developing, implanting, etching, and the like. However, the wafer 22 to be tested still needs some testing to ensure its normal operation and complete the manufacturing and inspection process. The chip 22 to be tested is in communication and operation with other electronic components, and includes a plurality of signal pins 220 and a power pin 222. The signal pin 220 may include, for example, a write protection pin, a chip select pin to be tested, a clock pin, a reserved pin, and a program pump voltage pin, etc., to receive signals from external components, or to be tested. The signal within the wafer 22 is transmitted. The power pin 222 is used to receive power to enable the entire wafer 22 to be tested to operate. It should be noted that, in FIG. 2, each of the chips 22 to be tested only shows one signal pin 220 and the power pin 222. In different embodiments, the signal pins 220 of each of the chips 22 to be tested are substantially 220. And the number of power pins 222 may vary according to design requirements, and is not limited by the number shown in FIG.

Test machine 20 includes a plurality of drive channels 200 and a plurality of power channels 202. The drive channel 200 of the test machine 20 includes a first group of drive channels 200 and a second group of drive channels 200. The first group is drawn in solid lines, and the second group is shown in dotted lines. Generally, the driving channel 200 can transmit a driving signal (not shown) to the signal pin 220 when the test program is performed, and the power channel 202 can transmit a power signal (not shown) to the power source of the chip 22 to be tested. Foot 222.

However, a large number of wafers often take a lot of time to test, such as the ability to test many wafers simultaneously on a single machine, which will save a lot of test costs and time costs. In order to achieve parallel testing, it has been common to share the power provided by one test machine 20 by a plurality of wafers 22 to be tested, so as to achieve the purpose of parallel testing in the case where the power supply of the test machine 20 is not much. However, in such a design, when one of the wafers 22 to be tested is short-circuited, the impact of a large current will cause the wafer 22 to be tested with which the power source is shared to be damaged. Moreover, in the test procedure of the power pin 222 of the test chip 22, the single chip cannot be measured due to the power sharing, and it is difficult to distinguish which is caused when an abnormal condition occurs.

Therefore, in step 102, the signal pins 220 of the wafers 22 to be tested are connected to the driving channels 200 (portions drawn by solid lines) located in the first group. Next, in step 103, the power pins 222 of the wafers 22 to be tested are respectively connected in parallel to one of the driving channels 220 located in the second group. That is, the signal pins 220 of the respective chips to be tested 22 are connected to the driving channels 200 of the first group, and the power pins 222 of the respective chips 22 to be tested are respectively connected to different driving channels 220, and Be parallel and independent of each other.

It should be noted that, depending on the signal pin 220, the manner of connecting to the driving channel 200 of the first group may be different. For example, the same signal pin 220 of each of the chips 22 to be tested is the same. For example, the clock pins of each of the chips 22 to be tested may be connected to one of the same driving channels 220 of the first group to achieve sharing for the purpose of saving the number of driving channels. The signal pins 220 of the same portion of each of the wafers 22 to be tested, such as the program pump voltage pins of the respective wafers 22 to be tested, may be connected to a driving channel 200 and become parallel connections due to the use requirements. The way.

Next, in step 104, the signal pin 220 of the chip 22 to be tested receives the driving signal from the connected driving channel 200 of the first group, and the power pin 222 of the wafer to be tested 22 is connected to the second group from the parallel connection. The driving channels 200 of the group respectively receive the power signals of different sources, and perform parallel testing on the wafers 22 to be tested.

That is, when the same signal pins 220 between the respective chips to be tested 22 are shared, for example, the clock pins of the respective wafers 22 to be tested are connected to one of the same driving channels 220 of the first group. Therefore, the device 20 to be tested only needs to transmit the clock signal through the single driving channel 220, and can be transmitted to the signal pin 220 of each of the shared wafers 22 to be tested. When the same signal pins 220 are not shared between the chips 22 to be tested, the signals from different sources are transmitted to the signal pins 220 of the respective chips 22 to be tested through different driving channels 220.

On the other hand, the power pins 222 of each of the chips 22 to be tested are parallel and independent of each other because they are respectively connected to different driving channels 220 or power channels 202. Therefore, the devices 20 to be tested will be respectively driven by the driving channels 220. The power signal is transmitted to the power pin 222 of each of the wafers 22 to be tested. Therefore, the power pin 222 of each of the chips 22 to be tested will receive power signals of different origins.

The purpose of the parallel test is to perform various wafer tests on a large number of wafers to be tested at the same time, such as DC power wafer testing or AC power wafer testing. In one embodiment, the content of the parallel test includes a standby current test. The standby current is a current generated in the case where the wafer 22 to be tested does not perform any operation after receiving the power.

In the present disclosure, the power pin 222 is connected to the mutually different driving channels 220, so that the received power sources are independent of each other, and the standby current can be separately measured, and the current of the single chip to be tested 22 can be excessively large. It is known that there is an abnormal situation, and the defective wafer 22 to be tested is detected. Moreover, the mutually parallel and independent connection manner can also prevent the other wafers 22 to be tested from being damaged and damaged when one of the wafers 22 to be tested is short-circuited.

It should be noted that, in an embodiment, since the power channel 202 can still be used to connect the power pin 222 for power supply, the wafer 22 to be tested can still be in parallel with the power pins 222 of the respective wafers 22 to be tested. Power is supplied through the power channel 202.

In an embodiment, the test machine 20 shown in FIG. 2 may further include an input and output channel 204, and each of the chips 22 to be tested may further include at least one input and output pin 224. The parallel test method may further include connecting the input and output pins 224 of each of the wafers 22 to be tested in parallel to one of the input and output channels 204, and inputting the input and output pins 204 of the wafer to be tested 22 from the parallel connection. The output channel 224 receives the input and output signals (not shown) for parallel testing. In FIG. 2, in order to avoid making the illustration too complicated, the actual connection relationship between the input/output channel 204 and the input/output pin 224 is not shown in detail.

Please refer to Figure 3. FIG. 3 is a schematic diagram showing the connection of various types of pins to the channel of the machine 20 to be tested in an embodiment of the disclosure.

As shown in FIG. 3, the write protection, the chip selection, the clock, and the reserved signal pins in each of the chips to be tested can be shared by a driving channel, respectively, and the program Lei voltage is used due to the use requirements. They are transmitted by different drive channels. The signal output pins are also connected to different input and output channels. In this embodiment, each of the chips to be tested includes two power sources, which are respectively connected and supplied by different driving channels and power channels to achieve the purpose of parallel connection.

The advantage of the application of the present disclosure is that by connecting the power pins in parallel with the driving channels of the test machine, in addition to avoiding that the power channel of the test machine is insufficient to supply a large number of parallel tested wafers to be tested, Increase the accuracy of the test and easily achieve the above objectives. For example, a die to be tested may have one power pin, five signal pins, and one input and output pin, for example, a machine with 32 power channels, 480 drive channels, and 128 input and output channels. Parallel testing of 128 test wafers is performed. Since the drive channels can be used to supply power as described above, even if the four test chips are grouped so that the signal pins share the drive channels, the number of drive channels required is only At (128*5)/4+128=288, it is still within the range that the test machine can accept, so parallel testing of 128 test wafers can be easily achieved. In other embodiments, other numbers of parallel tests can be achieved by adjusting the number of channels of the machine under test and the manner in which they are shared.

The present disclosure has been disclosed in the above embodiments, but it is not intended to limit the disclosure, and any person skilled in the art can make various changes and refinements without departing from the spirit and scope of the disclosure. The scope of protection of the disclosure is subject to the definition of the scope of the patent application.

101-104. . . step

20. . . Test machine

200. . . Drive channel

202. . . Power channel

204. . . Input and output channel

twenty two. . . Chip to be tested

220. . . Signal pin

222. . . Power pin

224. . . Input and output pin

The above and other objects, features, advantages and embodiments of the present disclosure will become more apparent and understood.

1 is a flow chart of a parallel testing method in an embodiment of the disclosure;

2 is a schematic diagram of a test machine and a plurality of wafers to be tested connected in an embodiment of the disclosure;

FIG. 3 is a schematic diagram showing the connection of various types of pins to the channel of the machine to be tested in an embodiment of the disclosure.

101-104. . . step

Claims (10)

A parallel test method comprising the steps of: providing a test machine, wherein the test machine comprises a plurality of driver channels and a plurality of power channels, wherein the drive channels comprise a first group and a second group Providing a plurality of chips to be tested, wherein each of the standby chips includes a plurality of signal pins and at least one power pin; and the signal pins of each of the waiting chips are connected to the driving channels located in the first group The power pins of each of the waiting chips are respectively connected in parallel to one of the driving channels located in the second group; and the signal pins of the standby chip are self-connected at the first The driving channels of the group receive a driving signal, and the power pins of the standby chip are respectively received from the parallel connection of the driving channels of the second group, respectively, to receive a source of different power signals, The waiting wafer is subjected to a parallel test. The parallel test method of claim 1, wherein one of the signal pins of each of the waiting chips shares the one of the driving channels located in the second group. The parallel test method of claim 1, wherein each of the signal pins of each of the waiting chips is connected in parallel to one of the driving channels located in the second group. The parallel test method of claim 1, wherein the test machine further comprises a plurality of input and output channels, and each of the standby chips comprises at least one input and output pin. The parallel testing method of claim 4, further comprising the steps of: connecting each of the input and output pins of each of the waiting chips to one of the input and output channels in parallel; and causing each of the waiting chips to be The input and output pins receive an input and output signal from the input and output channels connected in parallel to perform a parallel test on the waiting chip. The parallel test method of claim 1, wherein the signal pins comprise a write protection pin, a die select pin to be tested, a clock pin, a reserved pin, and a program pump. Voltage pin. The parallel test method of claim 1, wherein the parallel test comprises a standby current test. The parallel test method of claim 7, wherein the standby current test is used to measure a standby current of the power pin of each of the standby chips. The parallel test method of claim 1, wherein the parallel test is a circuit probing test. The parallel test method of claim 1, wherein the parallel test is a DC power supply wafer test or an AC power supply wafer test.