JP2014099630A - Semiconductor integrated circuit wafer and method for testing semiconductor integrated circuit chip and semiconductor integrated circuit wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit wafer capable of reducing bonding failures and improving connection reliability without leaving a scar on a bonding pad.SOLUTION: A semiconductor integrated circuit wafer comprises: a semiconductor integrated circuit region 2a; a scribe region 3; a BIST circuit 4 provided in the scribe region; a connection wiring 9 which connects a semiconductor integrated circuit 2 and the BIST circuit 4; a BIST switching signal input pad 7; and a BIST switching circuit 8 driven by a driving signal from the BIST switching signal input pad 7. The BIST switching circuit 8 further comprises: an input/output pad 6 for a semiconductor integrated circuit; a circuit wiring 11 which connects the input/output pad 6 and the semiconductor integrated circuit 2; and a switch element 10 provided in the middle of the circuit wiring 11 and driven by a driving signal from the BIST switching signal input pad 7.

Description

  The present invention relates to a semiconductor integrated circuit wafer, a semiconductor integrated circuit chip, and a method for testing a semiconductor integrated circuit wafer that are suitable for detecting defects in a semiconductor integrated circuit using a BIST (Built-in Self Test) circuit.

  A test of a semiconductor integrated circuit wafer is performed by bringing a probe pin (probe) into contact with an input / output pad (external electrode) in a semiconductor integrated circuit such as a memory and supplying a test pattern signal supplied from the tester to the pad via the probe pin. Input and measure the electrical characteristics to determine whether it is defective. When the probe pin is brought into contact with the input / output pad, a scar due to the probe pin contact may remain on the input / output pad. If a scar remains on the input / output pad, it will lead to an increase in defects and a decrease in connection reliability during the work of bonding wires to the input / output pad and the bump construction work in a later process. Therefore, it is necessary to improve the input / output pad structure and adjust the probe pin contact pressure so that a stable test can be performed with few scars.

  On the other hand, there is a method of using a BIST (Built in Self Test) circuit as a technique for improving the efficiency of testing of a semiconductor integrated circuit. The chip size of the entire circuit increases and the chip cost increases. Further, there is a problem that power consumption increases due to an unnecessary BIST circuit remaining after the product.

  In order to solve the problem of increase in chip size and power consumption, a structure including a BIST circuit and a test pad in a scribe region has been proposed (Patent Document 1). In Patent Document 1, it is necessary to bring a probe pin into contact with both the test pad of the BIST circuit in the scribe region and the input / output pad of the integrated circuit region, and to electrically connect them through a transmission path via the probe pin. For this reason, (i) the number of probes increases, and inspection jigs (probe cards) become complicated and expensive. (Ii) The electrical characteristics of the inspection tool influence the test of the semiconductor integrated circuit. There are issues such as.

  There is another proposal in which a BIST circuit and a test pad are provided in a scribe region, and an input / output pad in a semiconductor integrated circuit region is electrically connected by wiring (Patent Document 2). In Patent Document 2, the semiconductor chip is cut into pieces one by one, and at the same time, the scribe region and the connection wiring are cut. Depending on the finished state of the cut surface, the connection wiring may cause an electrical failure such as a short circuit. There is sex.

  Furthermore, there is a technique for forming a wiring for connecting a test circuit to a functional circuit and a switching element for electrically cutting the wiring (Patent Document 3). In Patent Document 3, there is no description about the presence / absence of the pads of the test circuit (BIST circuit) and the functional circuit (semiconductor integrated circuit) and the use effect, and the present invention suggests a method for improving the scar of the input / output pad that the problem is to be solved. Not done.

JP 2002-176140 A JP 2003-124275 A JP 2001-085479 A

  The present invention provides a semiconductor integrated circuit that does not leave any scratches on the bonding pads, can reduce bonding defects, improve connection reliability, can reduce the size of a semiconductor chip, and can prevent an increase in power consumption. It is an object to provide a circuit wafer, a semiconductor integrated circuit chip, and a test method for a semiconductor integrated circuit wafer.

In order to achieve the above object, the present invention employs the following configuration.
A semiconductor integrated circuit wafer of the present invention is provided in a plurality of semiconductor integrated circuit regions formed with semiconductor integrated circuits, a scribe region that separates the semiconductor integrated circuit regions adjacent to each other, and the scribe region, A BIST circuit used for testing the semiconductor integrated circuit; a connection wiring formed across the scribe region and the semiconductor integrated circuit region to connect the semiconductor integrated circuit and the BIST circuit; and the semiconductor integrated circuit A BIST switching signal input pad provided in the circuit area; and a BIST switching circuit provided in the semiconductor integrated circuit area and driven by a drive signal from the BIST switching signal input pad. The input / output pad for the semiconductor integrated circuit, and the input / output pad and the semiconductor integrated circuit are connected to each other. A circuit wiring, provided in the middle of the circuit wiring, and characterized by being provided with a switch element driven by a drive signal from the BIST switching signal input pad.

  According to the above configuration, by installing the BIST circuit in the scribe region, the area of the semiconductor integrated circuit region is reduced as compared with the case where the BIST circuit is built in the semiconductor integrated circuit region, thereby reducing the manufacturing cost and the package. It is possible to reduce the mounting size.

  Further, a BIST switching signal input pad and a BIST switching circuit are provided in the semiconductor integrated circuit region, and the BIST switching circuit is provided with a switch element that is driven by a drive signal from the BIST switching signal input pad. With this configuration, the BIST switching circuit can perform a switching operation by a drive signal from the BIST switching signal input pad. The BIST switching circuit performs a switching operation of connecting the semiconductor integrated circuit and the input / output pad or connecting the semiconductor integrated circuit and the BIST circuit through the connection wiring by using a switch element. Accordingly, the probe pin is connected to the BIST circuit and the BIST switching signal input pad to perform the switching operation, thereby connecting the BIST circuit and the semiconductor integrated circuit to execute the test of the semiconductor integrated circuit using the BIST circuit. This makes it possible to reduce bonding defects and improve connection reliability without leaving scars on the input / output pads by the probe pins.

  In addition, the use of the BIST circuit can reduce the number of external terminals in the semiconductor integrated circuit. Furthermore, the number of probe pins can be reduced, and the cost of a jig (probe card) for testing can be suppressed.

  The semiconductor integrated circuit wafer of the present invention is the semiconductor integrated circuit wafer described above, wherein the switch element connects the input / output pad and the semiconductor integrated circuit via the circuit wiring in an off state, The circuit wiring is cut off when turned on by a drive signal, and the BIST circuit and the semiconductor integrated circuit are connected via the connection wiring.

  According to the above configuration, the BIST circuit and the semiconductor integrated circuit are connected via the connection wiring only when the switch element is in the on state, and when the switch element is off, the input / output pad is connected via the circuit wiring. By connecting the semiconductor integrated circuit, the connection wiring is disconnected from the circuit wiring and the semiconductor integrated circuit. Thus, current does not flow through the connection wiring when the switch element is off, so that current consumption can be reduced.

  Next, a semiconductor integrated circuit chip according to the present invention is a semiconductor integrated circuit chip obtained by dividing the semiconductor integrated circuit wafer described above along the scribe region, and includes a semiconductor integrated circuit and a BIST switching signal input pad. And a BIST switching circuit driven by a drive signal from the BIST switching signal input pad, the BIST switching circuit comprising: an input / output pad for the semiconductor integrated circuit; the input / output pad; and the semiconductor integrated circuit; And a switching element provided in the middle of the circuit wiring and driven by a driving signal from the BIST switching signal input pad.

  According to said structure, the scar of the input / output pad by a probe pin decreases, it can reduce the defect of bonding and can improve the reliability of connection.

  Next, a test method for a semiconductor integrated circuit according to the present invention is a test method for a semiconductor integrated circuit using the semiconductor integrated circuit wafer described above, and the probe pin of the probe card is connected to the BIST circuit and the BIST switching signal input pad. Connecting to the BIST switching signal input pad, turning on the switch element in the BIST switching circuit to cut off the circuit wiring and via the connection wiring to the BIST circuit A step of connecting the semiconductor integrated circuit, a test information signal is input from the tester to the BIST circuit via the probe pin, and the input test information signal is further tested via the connection wiring And a step of executing a test of the semiconductor integrated circuit by inputting the information signal. .

  According to the above configuration, the BIST switching circuit uses the switch element to switch between the semiconductor integrated circuit and the input / output pad, or the semiconductor integrated circuit and the BIST circuit are connected via the connection wiring. I do. Accordingly, the probe pin is connected to the BIST circuit and the BIST switching signal input pad to perform the switching operation, thereby connecting the BIST circuit and the semiconductor integrated circuit to execute the test of the semiconductor integrated circuit using the BIST circuit. This makes it possible to reduce bonding defects and improve connection reliability without leaving scars on the input / output pads by the probe pins.

  According to the present invention, no scratches remain on the bonding pad, the bonding defect can be reduced, the connection reliability can be improved, the size of the semiconductor chip can be reduced, and the increase in power consumption can be prevented. A semiconductor integrated circuit wafer, a semiconductor integrated circuit chip, and a test method for a semiconductor integrated circuit wafer can be provided.

FIG. 1 is a schematic plan view showing a semiconductor integrated circuit wafer according to an embodiment of the present invention. FIG. 2 is a partially enlarged view of FIG. 1 and is a schematic plan view showing a main part of a semiconductor integrated circuit wafer according to an embodiment of the present invention. FIG. 3 is a schematic diagram illustrating a circuit configuration of a semiconductor integrated circuit wafer and a test method for the semiconductor integrated circuit according to the embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic plan view showing a semiconductor integrated circuit wafer according to an embodiment of the present invention, and FIG. 2 is a partially enlarged view of FIG. 1, showing the essential parts of the semiconductor integrated circuit wafer according to an embodiment of the present invention. FIG. 3 is a schematic diagram illustrating a circuit configuration of a semiconductor integrated circuit wafer and a test method for the semiconductor integrated circuit according to an embodiment of the present invention.

  As shown in FIGS. 1 to 2, the semiconductor integrated circuit wafer 1 of this embodiment includes a BIST circuit 4 having a BIST circuit pad 5 for testing the semiconductor integrated circuit 2 in a scribe region 3 on the wafer 1. A connection wiring 9 that is provided and electrically connects the BIST circuit 4 and the semiconductor integrated circuit 2 in the scribe region 3 is formed extending from the semiconductor integrated circuit region 2 a to the scribe region 3. A BIST switching signal input pad 7 is provided in the semiconductor integrated circuit 2, and the BIST switching circuit 8 is driven by a drive signal from the BIST switching signal input pad 7 to turn on the electrical connection of the switch element 10. Thereby, the semiconductor integrated circuit 2 and the BIST circuit 4 are connected.

  When testing the semiconductor integrated circuit 2 using the BIST circuit 4, the BIST circuit pad 5 of the BIST circuit 4 in which the probe pin 13 is formed in the scribe region 3 and the BIST switching signal input pad 6 in the semiconductor integrated circuit 2 are used. The semiconductor integrated circuit 2 is electrically connected to the semiconductor measuring device 14 (tester) via the probe card 13 and the BIST circuit 4 is driven by a signal from the tester 14 to test the semiconductor integrated circuit 2. At the time of the test, the probe pin 13 is added to the BIST switching signal input pad 7 and further brought into contact with the power supply pad and the GND pad in the semiconductor integrated circuit 2 and electrically connected to the tester 14 via the probe card 12. The BIST circuit 4 is driven by the test information signal from the semiconductor integrated circuit 2 to test the semiconductor integrated circuit 2.

Hereinafter, it will be described in detail with reference to the drawings.
1 and 2, reference numeral 1 denotes a semiconductor integrated circuit wafer. In the semiconductor integrated circuit wafer 1, a plurality of semiconductor integrated circuit regions 2a are arranged in a matrix. A semiconductor integrated circuit 2 is formed in the semiconductor integrated circuit region 2a. Around each semiconductor integrated circuit region 2a, a scribe region 3 for separating adjacent semiconductor integrated circuit regions 2a one by one is provided. A BIST circuit 4 is provided in the scribe region 3. The BIST circuit 4 is provided with a BIST circuit pad 5 for inputting a test information signal to the BIST circuit 4. Note that there may be a plurality of types of BIST circuit 4 for each function. The semiconductor integrated circuit 2 may be a memory circuit such as a DRAM or SRAM, or a logic circuit. In the present embodiment, an example in which a memory circuit is used as the semiconductor integrated circuit 2 will be described.

  In the vicinity of the semiconductor integrated circuit 2 in the semiconductor integrated circuit region 2a, a VDD (power supply) pad 11, a GND pad 12, a plurality of input / output pads 6 and a BIST switching signal input pad 7 are arranged. Further, as shown in FIG. 3, a BIST switching circuit 8 that is driven by a drive signal from the BIST switching signal input pad 7 and used for testing the semiconductor integrated circuit 2 is provided in the semiconductor integrated circuit region 2a. Yes. The BIST circuit 4 and the BIST switching circuit 8 (see FIG. 3) are connected by a connection wiring 9 formed across the scribe region 3 and the semiconductor integrated circuit region 2a.

  As shown in FIG. 3, the semiconductor integrated circuit 2 is connected to the input / output pads 6 by circuit wiring 11. The BIST switching circuit 8 used for testing the semiconductor integrated circuit 2 includes an input / output pad 6 for the semiconductor integrated circuit 2, a circuit wiring 11 for connecting the input / output pad 6 and the semiconductor integrated circuit 2, and The switch element 10 is provided in the middle of the circuit wiring 11 and is driven by a drive signal from the BIST switching signal input pad 7. The switch element 10 connects the input / output pad 6 and the semiconductor integrated circuit 2 via the circuit wiring 11 in the off state, while blocking the circuit wiring 11 and connecting the connection wiring 9 when turned on by the drive signal. The BIST circuit 4 and the semiconductor integrated circuit 2 are connected to each other. The on / off control of the switch element 10 is performed by a BIST switching signal from the BIST switching signal pad 7. When a drive signal is input to the BIST switching signal input pad 7, the switch element 10 is turned on, and the BIST circuit 4 and the semiconductor integrated circuit 2 are connected.

  For example, when the switch element is active high, the switch element 10 is switched on when the input is High and turned off when the input is Low. As the switch element 10, for example, a transfer MOS formed by pulling down a BIST switching signal can be used. Note that a plurality of input / output pads 6 and switch elements 10 constituting the BIST switching circuit 8 are provided according to the memory array of the semiconductor integrated circuit 2. For connection between the semiconductor integrated circuit 2 and the circuit wiring 11, a fuse or the like can be used instead of the transfer MOS.

Next, a method for testing a semiconductor integrated circuit will be described with reference to FIG.
The probe card 12 used for the test includes a plurality of probe pins 13. The probe pin 13 causes the plurality of BIST circuit pads 5 provided in the BIST circuit 4 and the power supply pads 11, the GND pads 12, and the BIST switching signal input pads 7 in the semiconductor integrated circuit region 2 to be touched. Thus, the semiconductor integrated circuit 2 can be tested by the BIST signal from the BIST circuit 4 via the probe card 12 and the probe pin 13.

  First, at the start of the test, the probe pins 13 are contacted with the plurality of BIST circuit pads 5, the power supply pad 11, the GND pad 12, and the BIST switching signal input pad 7 in the memory chip, respectively.

  Next, a drive signal is input from the tester 14 to the BIST switching signal input pad 7 via the probe pin 13. When a BIST switching signal (driving signal) that is a BIST switching signal is input to the BIST switching signal input pad 7, the switch element 10 is turned on. As a result, the circuit wiring 11 is cut off by the switch element 10, and the BIST circuit 4 and the semiconductor integrated circuit 2 are connected via the connection wiring 9, the switch element 10, and the circuit wiring 11a on the semiconductor integrated circuit side.

  Next, a test information signal for controlling the BIST circuit 4 is input to the BIST circuit pad 5 from the tester 14 via the probe pin 13. Thus, the test information signal is transmitted from the BIST circuit 4 to the semiconductor integrated circuit 2 via the connection wiring 9 and the switch element 10, and the test of the semiconductor integrated circuit 2 is executed.

  After all the tests in the wafer state for the semiconductor integrated circuit 2 are completed, the semiconductor integrated circuit wafer 1 is divided along the scribe region 3. As a result, the semiconductor integrated circuit chip 10 partitioned into the semiconductor integrated circuit region 2a is cut out, and the connection wiring 9 in the scribe region 3 is cut at the same time. Depending on the state of the cut surface, there is a risk that the semiconductor integrated circuit 2 may be adversely affected by a short circuit or the like. However, since the switch element 10 is turned off by the pulled down BIST Enable signal in the semiconductor integrated circuit 2, the connection wiring 9 is electrically cut and does not affect the operation of the memory circuit according to the state of the cut surface. In addition, since no current flows through the connection wiring 9 after the chip is formed, the power consumption of the semiconductor integrated circuit chip 10 can be reduced.

  The formed semiconductor integrated circuit chip 10 includes a semiconductor integrated circuit 2, a BIST switching signal input pad 7, and a BIST switching circuit 8. The BIST switching circuit 8 includes an input / output pad 6, a circuit wiring 11, and the like. The switch element 10 provided in the middle of the circuit wiring 11 and the cut connection wiring 9a are provided.

  As described above, when testing the semiconductor integrated circuit 2, it is not necessary to bring the probe pin 13 into contact with the input / output pad 6 of the semiconductor integrated circuit 2, and the test is executed without leaving any scar on the input / output pad 6. Is possible.

  Further, by installing the BIST circuit 4 in the scribe region 3, the area of the semiconductor integrated circuit region 2a is reduced as compared with the case where the BIST circuit 4 is built in the semiconductor integrated circuit 2, thereby reducing the manufacturing cost and the package mounting. Can be realized. In addition, after the semiconductor integrated circuit chip 10 is formed, the BIST circuit 4 is removed for each scribe region, so that an unnecessary increase in current consumption by the BIST circuit 4 can be prevented.

  In addition, by constructing the connection wiring 9 on the wafer 1, compared with the conventional method of transmitting a signal via a probe card, signal deterioration is reduced and a high-speed test can be performed. Furthermore, the number of BIST circuit pads 5 can be reduced by the configuration of the BIST circuit 4. In addition, the number of probe pins can be reduced, and the cost of a tool (probe card) for testing can be reduced. Furthermore, a short circuit failure at the time of disconnection that occurs in the connection wiring method can be prevented by the switch structure.

  Further, the number of pads that damage the input / output pads 6 of the semiconductor integrated circuit 2 used at the time of assembly by the probe pins 13 is minimized (in the operation explanation example, three pads of the power supply pad 11, the GND pad 12, and the BIST switching signal input pad 7). Therefore, it is possible to reduce bonding defects and improve connection reliability during wire bonding.

  In the above test method, the pads requiring contact with the probe pins 13 in the semiconductor integrated circuit 2 are the BIST switching signal input pad 7, the power supply pad 11, and the GND pad 12. However, the pads need to be limited to these three terminals. There is no increase or decrease in the number of pads requiring contact with the probe pin 13. Further, by installing two three terminals together, it is possible to eliminate the scars on the three terminals without fail, and it is possible to take measures against a small increase in the chip size of the high input.

  1: Semiconductor integrated circuit wafer, 2; Semiconductor integrated circuit, 2a; Semiconductor integrated circuit region, 3; Scribe region, 4; BIST circuit, 5; BIST circuit pad, 6: I / O pad, 7; 8: BIST switching circuit, 9: Connection wiring, 10: Switch element, 11: Circuit wiring, 12: Probe card, 13: Probe pin, 14: Tester.

Claims (1)

A plurality of semiconductor integrated circuit regions in which semiconductor integrated circuits are formed;
A scribe region that separates the semiconductor integrated circuit regions adjacent to each other;
A BIST circuit provided in the scribe region and used for testing the semiconductor integrated circuit;
A connection wiring formed across the scribe region and the semiconductor integrated circuit region to connect the semiconductor integrated circuit and the BIST circuit;
A BIST switching signal input pad provided in the semiconductor integrated circuit region;
A BIST switching circuit provided in the semiconductor integrated circuit region and driven by a drive signal from the BIST switching signal input pad;
The BIST switching circuit includes an input / output pad for the semiconductor integrated circuit, a circuit wiring for connecting the input / output pad and the semiconductor integrated circuit, and a BIST switching signal input pad provided in the middle of the circuit wiring. And a switching element driven by a driving signal from the semiconductor integrated circuit wafer.