TW201301558A - Method of semiconductor manufacturing process - Google Patents
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- TW201301558A TW201301558A TW100122950A TW100122950A TW201301558A TW 201301558 A TW201301558 A TW 201301558A TW 100122950 A TW100122950 A TW 100122950A TW 100122950 A TW100122950 A TW 100122950A TW 201301558 A TW201301558 A TW 201301558A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 94
- 239000000463 material Substances 0.000 claims description 32
- 230000004888 barrier function Effects 0.000 claims description 16
- 238000001039 wet etching Methods 0.000 claims description 12
- 238000003672 processing method Methods 0.000 claims description 11
- 150000004767 nitrides Chemical group 0.000 claims description 9
- 229910052594 sapphire Inorganic materials 0.000 claims description 9
- 239000010980 sapphire Substances 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 7
- 239000000956 alloy Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910000838 Al alloy Inorganic materials 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 3
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910000420 cerium oxide Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910003460 diamond Inorganic materials 0.000 claims description 3
- 239000010432 diamond Substances 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical group [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 2
- 229910052797 bismuth Inorganic materials 0.000 claims 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims 1
- 229910010293 ceramic material Inorganic materials 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 12
- 229910002601 GaN Inorganic materials 0.000 description 5
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02647—Lateral overgrowth
- H01L21/0265—Pendeoepitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
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Abstract
Description
本發明係相關於一種半導體製程方法，尤指關於剝離半導體基板的半導體製程方法。The present invention relates to a semiconductor processing method, and more particularly to a semiconductor processing method for stripping a semiconductor substrate.
在傳統的發光二極體製程(Light-Emitting Diode;LED)中，為了在成長基板上成長出較高品質之氮化物半導體(例如：形成鎵基(GaN－based)磊晶薄膜)，一般會選擇晶體結構與氮化鎵之晶體結構類似的藍寶石(Al2O3)基板作為成長基板，但藍寶石基板在導電性質與導熱性質上是比較差的，因此氮化鎵發光二極體在高電流、高功率、長時間操作下，存在著散熱不佳、影響晶粒之發光效率與發光面積、可靠度不良等問題，因而對氮化鎵發光二極體之製造與發光效率的提昇造成阻礙與限制。In a conventional Light-Emitting Diode (LED), in order to grow a higher quality nitride semiconductor on a grown substrate (for example, forming a GaN-based epitaxial film), A sapphire (Al 2 O 3 ) substrate having a crystal structure similar to that of gallium nitride is selected as a growth substrate, but the sapphire substrate is inferior in conductivity and thermal conductivity, so the gallium nitride light-emitting diode is at a high current. Under high power and long-time operation, there are problems such as poor heat dissipation, affecting the luminous efficiency and light-emitting area of the die, and poor reliability. Therefore, the manufacturing and luminous efficiency of the gallium nitride light-emitting diode are hindered. limit.
為了改善上述缺失，傳統作法是去除藍寶石基板，習知的技術是以晶圓接合技術將氮化物半導體元件從藍寶石成長基板轉移至接合基板，藉以使LED的元件特性提升，也就是將氮化鎵元件磊晶層自藍寶石基板剝離，轉移至具有高導電率、高導熱率的基板。在上述製程中，大部分以雷射剝離(Laser Lift Off)技術來去除藍寶石成長基板，然而雷射剝離法會使LED的元件特性劣化，影響LED元件的良率，而且雷射剝離成本較高。因此，如果能在晶圓接合過程中將氮化物半導體元件從成長基板剝離，避免使用雷射剝離技術，則能大大降低製造成本。In order to improve the above-mentioned defects, the conventional method is to remove the sapphire substrate. The conventional technique is to transfer the nitride semiconductor device from the sapphire growth substrate to the bonding substrate by the wafer bonding technique, thereby improving the component characteristics of the LED, that is, GaN. The element epitaxial layer is peeled off from the sapphire substrate and transferred to a substrate having high conductivity and high thermal conductivity. In the above process, most of the laser lift off (Laser Lift Off) technology is used to remove the sapphire growth substrate. However, the laser stripping method deteriorates the LED component characteristics, affects the yield of the LED component, and the laser peeling cost is high. . Therefore, if the nitride semiconductor element can be peeled off from the growth substrate during the wafer bonding process and the laser lift-off technique is avoided, the manufacturing cost can be greatly reduced.
職是之故，申請人鑑於習知技術中所產生之缺失，經過悉心試驗與研究，並一本鍥而不捨之精神，終構思出本案「半導體製程方法」，能夠克服上述缺點，以下為本案之簡要說明。For the sake of his position, the applicant has been able to overcome the above shortcomings in the light of the lack of knowledge in the prior art, through careful experimentation and research, and the spirit of perseverance. Description.
本發明提出一種新的製程技術，在製程中減少成長基板與氮化物半導體基板間的接觸面積，在晶圓接合步驟因為加熱而產生溫度變化的過程中，因為成長基板與氮化物半導體的膨脹係數不同，產生應力集中，藉此導致氮化物半導體基板與成長基板剝離而製造出氮化物半導體元件。無需使用雷射剝離技術來進行去除成長基板的製程，因而有效降低製程成本。The invention proposes a new process technology, which reduces the contact area between the growth substrate and the nitride semiconductor substrate in the process, and the expansion coefficient of the growth substrate and the nitride semiconductor in the process of temperature change during the wafer bonding step due to heating Unlike the stress concentration, the nitride semiconductor substrate is peeled off from the growth substrate to produce a nitride semiconductor device. There is no need to use a laser lift-off technique to perform the process of removing the grown substrate, thereby effectively reducing the process cost.
根據本發明的第一構想，提供一種半導體之製程方法，包含下列步驟：提供一成長基板；形成一凹凸結構於該成長基板上；形成一半導體元件層於該凹凸結構上；以及改變該成長基板與該半導體元件層的溫度。According to a first aspect of the present invention, a method of fabricating a semiconductor includes the steps of: providing a growth substrate; forming a concavo-convex structure on the growth substrate; forming a semiconductor device layer on the relief structure; and changing the growth substrate The temperature with the layer of the semiconductor element.
較佳地，其中改變該成長基板與該半導體元件層的溫度更包括一步驟：加熱該成長基板與該半導體元件層，並施加一壓力使該半導體元件層接合至一接合基板。Preferably, wherein changing the temperature of the growth substrate and the semiconductor device layer further comprises the steps of: heating the growth substrate and the semiconductor device layer, and applying a pressure to bond the semiconductor device layer to a bonding substrate.
較佳地，其中該接合基板的材質係選自由一銅材質、一鋁材質、一矽材質、一鑽石材質、一銅合金材質、一鋁合金材質及其組合所組成的群組其中之一。Preferably, the material of the bonding substrate is selected from the group consisting of a copper material, an aluminum material, a tantalum material, a diamond material, a copper alloy material, an aluminum alloy material and combinations thereof.
較佳地，其中該半導體元件層是一氮化物材質，而該成長基板係選自由一氧化鋁材質、一藍寶石(Sapphire)材質、一碳化矽(SiC)材質及一矽(Si)材質所組成的群組其中之一。Preferably, the semiconductor device layer is made of a nitride material, and the growth substrate is selected from the group consisting of an alumina material, a sapphire material, a silicon carbide (SiC) material, and a germanium (Si) material. One of the groups.
較佳地，其中在該成長基板形成該凹凸結構是透過一化學濕式蝕刻或一乾式蝕刻來圖形化該成長基板而形成該凹凸結構。Preferably, the concave-convex structure is formed on the growth substrate by patterning the growth substrate by chemical wet etching or dry etching to form the uneven structure.
較佳地，其中該化學濕式蝕刻係使用一氫氧化鉀(KOH)溶液進行蝕刻。Preferably, the chemical wet etching is performed using a potassium hydroxide (KOH) solution.
較佳地，其中在該成長基板上形成該半導體元件層之前更包括以下步驟：在該成長基板的一上表面形成一介電阻擋層；以及以曝光、顯影與蝕刻的方式使該介電阻擋層裸露出該上表面一區域。Preferably, the step of forming the semiconductor device layer on the growth substrate further comprises the steps of: forming a dielectric barrier layer on an upper surface of the growth substrate; and blocking the dielectric barrier by exposure, development and etching. The layer exposes an area of the upper surface.
較佳地，其中在該半導體基板上形成該凹凸結構之前更包括以下步驟：以一濕式蝕刻方式蝕刻該區域以形成該凹凸結構。Preferably, before the forming the concave-convex structure on the semiconductor substrate, the method further comprises the step of etching the region by a wet etching to form the concave-convex structure.
較佳地，其中該濕式蝕刻方式係使用一氟化氫(HF)溶液。Preferably, the wet etching method uses a hydrogen fluoride (HF) solution.
較佳地，其中該介電阻擋層係一二氧化矽材質。Preferably, the dielectric barrier layer is made of a cerium oxide material.
根據本發明的第二構想，提供一種半導體製程方法，包含下列步驟：提供一具有一上表面之成長基板；形成一具有一下表面之半導體元件層於該成長基板上；減少該上表面與該下表面間的一接觸面積；以及加熱該成長基板與該半導體元件層。According to a second aspect of the present invention, a semiconductor processing method includes the steps of: providing a growth substrate having an upper surface; forming a semiconductor device layer having a lower surface on the growth substrate; reducing the upper surface and the lower surface a contact area between the surfaces; and heating the growth substrate and the semiconductor element layer.
根據本發明的第三構想，提供一種半導體製程方法，包含下列步驟：提供一具有一第一表面之成長基板；提供一具有一第二表面之半導體元件層，其中該第二表面與該第一表面接觸；以及加熱該第一成長基板與該半導體元件層，以使該第一表面與該第二表面處於一分離狀態。According to a third aspect of the present invention, a semiconductor processing method includes the steps of: providing a growth substrate having a first surface; providing a semiconductor device layer having a second surface, wherein the second surface and the first Surface contacting; and heating the first growth substrate and the semiconductor device layer such that the first surface and the second surface are in a separated state.
根據本發明的第四構想，提供一種半導體製程方法，包含下列步驟：提供一具有一第一表面之成長基板；提供一具有一第二表面之半導體元件層，其中該第二表面與該第一表面接觸；以及使該第一表面與該第二表面至少兩者之一全部處於一受熱狀態而得以相互分離。According to a fourth aspect of the present invention, a semiconductor processing method includes the steps of: providing a growth substrate having a first surface; providing a semiconductor device layer having a second surface, wherein the second surface and the first Surface contact; and causing at least one of the first surface and the second surface to be in a heated state to be separated from each other.
根據本發明的第五構想，提供一種半導體製程方法，包含下列步驟：提供一具有一第一表面之成長基板；提供一具有一第二表面之半導體元件層，其中該第二表面與該第一表面接觸；以及使該第一表面形成一不平整表面，以減少該第一表面與該第二表面之一接觸面積。According to a fifth aspect of the present invention, a semiconductor processing method includes the steps of: providing a growth substrate having a first surface; providing a semiconductor device layer having a second surface, wherein the second surface and the first Surface contacting; and forming the first surface with an uneven surface to reduce a contact area of the first surface with the second surface.
根據本發明的第六構想，提供一種半導體製程用之一成長基板，用以成長一半導體元件層，包含：一成長基板本體；以及一不平整表面，形成於該成長基板本體上，以減少該半導體元件層與該不平整表面之一接觸面積。According to a sixth aspect of the present invention, a growth substrate for a semiconductor process for growing a semiconductor device layer includes: a growth substrate body; and an uneven surface formed on the growth substrate body to reduce the A contact area of the semiconductor element layer with one of the uneven surfaces.
本案將可由以下的實施例說明而得到充分瞭解，使得熟習本技藝之人士可以據以完成之，然本案之實施並非可由下列實施案例而被限制其實施型態。其中相同的標號始終代表相同的組件。The present invention will be fully understood by the following examples, so that those skilled in the art can do so. However, the implementation of the present invention may not be limited by the following embodiments. Where the same reference numerals always represent the same components.
請參考第一圖至第四圖，其中第一圖係本發明一較佳實施例的流程圖，而第二圖至第四圖係說明此較佳實施例的結構圖。該較佳實施例包含步驟S11～S14，以下分別作說明。Please refer to the first to fourth figures, wherein the first drawing is a flow chart of a preferred embodiment of the present invention, and the second to fourth drawings are structural views of the preferred embodiment. The preferred embodiment includes steps S11-S14, which are described below.
步驟S11：如第二圖所示，提供一成長基板1，成長基板1較佳為一氧化鋁(Al2O3)材質、一藍寶石(Sapphire)材質、一碳化矽(SiC)材質或一矽(Si)材質其中之一。Step S11: As shown in the second figure, a growth substrate 1 is provided. The growth substrate 1 is preferably made of aluminum oxide (Al 2 O 3 ), a sapphire material, a silicon carbide (SiC) material or a crucible. One of the (Si) materials.
步驟S12：圖形化該成長基板1，而在成長基板1上形成一凹凸結構1a，如第三圖所示。本領域具一般技藝人士可理解的是凹凸結構1a可透過一化學濕式蝕刻(如使用氫氧化鉀(KOH)溶液等)或一乾式蝕刻來圖形化成長基板1而形成。Step S12: The growth substrate 1 is patterned, and a concave-convex structure 1a is formed on the growth substrate 1, as shown in the third figure. It will be understood by those skilled in the art that the uneven structure 1a can be formed by patterning the growth substrate 1 by a chemical wet etching (such as using a potassium hydroxide (KOH) solution or the like) or a dry etching.
步驟S13：進行後續元件製作，在成長基板1上形成半導體元件層2。步驟S12中形成的凹凸結構1a減少了半導體元件層2與成長基板1間的接觸面積。Step S13: Subsequent element fabrication is performed, and the semiconductor element layer 2 is formed on the growth substrate 1. The uneven structure 1a formed in the step S12 reduces the contact area between the semiconductor element layer 2 and the growth substrate 1.
步驟S14：如第四圖所示，進行晶圓接合，在晶圓接合過程中改變成長基板1與半導體元件層2的溫度，成長基板1與半導體元件層2將被加熱，且受到一壓力使半導體元件層2接合至接合基板3，其中接合基板3的材質較佳為一銅材質、一鋁材質、一矽材質、一鑽石材質、一銅合金材質或一鋁合金材質其中之一。Step S14: as shown in the fourth figure, wafer bonding is performed, and the temperature of the growth substrate 1 and the semiconductor element layer 2 is changed during the wafer bonding process, and the growth substrate 1 and the semiconductor element layer 2 are heated and subjected to a pressure. The semiconductor device layer 2 is bonded to the bonding substrate 3, wherein the bonding substrate 3 is preferably made of a copper material, an aluminum material, a germanium material, a diamond material, a copper alloy material or an aluminum alloy material.
在晶圓接合過程中，成長基板1與半導體元件層2的溫度改變，而由於成長基板1與半導體元件層2的熱膨脹係數不同，產生應力集中於成長基板1與半導體元件層2之交接處，並由於成長基板1與半導體元件層2之接觸面積減少，致使成長基板1自半導體元件層2剝離。In the wafer bonding process, the temperature of the growth substrate 1 and the semiconductor element layer 2 is changed, and since the thermal expansion coefficients of the growth substrate 1 and the semiconductor element layer 2 are different, stress is concentrated on the intersection of the growth substrate 1 and the semiconductor element layer 2, Further, since the contact area between the growth substrate 1 and the semiconductor element layer 2 is reduced, the growth substrate 1 is peeled off from the semiconductor element layer 2.
而可以為本領域技術人士理解的是，凹凸結構1a用於減少半導體元件層2與成長基板1間的接觸面積，因此凹凸結構1a可在形成半導體元件層2之後與晶圓接合之前的任一步驟形成。而凹凸結構1a也不限於第三圖與第四圖所示規則排列的凹凸結構，只要是可以減少半導體元件層2與成長基板1間的接觸面積的凹凸結構皆可達到本發明的效果，例如：線狀凹凸結構或點狀凹凸結構。It can be understood by those skilled in the art that the uneven structure 1a is for reducing the contact area between the semiconductor element layer 2 and the growth substrate 1, and thus the uneven structure 1a can be bonded to the wafer after the semiconductor element layer 2 is formed. The steps are formed. The uneven structure 1a is not limited to the uneven structure in the regular arrangement shown in the third and fourth figures, and the effect of the present invention can be attained as long as it is a concave-convex structure capable of reducing the contact area between the semiconductor element layer 2 and the growth substrate 1. : Linear relief structure or point relief structure.
然而，形成上述凹凸結構的方法不限於上述實施例所提供的流程。請繼續參考第五圖至第十圖，其中第五圖係本發明形成上述凹凸結構之另一較佳實施方式的流程圖，而第六圖至第十圖係相對應之結構圖，茲說明第六圖步驟如下。However, the method of forming the above-described uneven structure is not limited to the flow provided by the above embodiment. Please refer to the fifth to tenth drawings, wherein the fifth figure is a flow chart of another preferred embodiment of the present invention for forming the above-mentioned uneven structure, and the sixth to tenth drawings are corresponding structural diagrams. The steps in the sixth figure are as follows.
步驟S21：提供一成長基板1，如前一較佳實施例所述，該成長基板1較佳為一氧化鋁(Al2O3)材質、一藍寶石(Sapphire)材質、一碳化矽(SiC)材質或一矽(Si)材質其中之一。Step S21: providing a growth substrate 1. As described in the previous preferred embodiment, the growth substrate 1 is preferably made of aluminum oxide (Al 2 O 3 ), a sapphire material, and a silicon carbide (SiC). One of the materials or one (Si) material.
步驟S22：如第六圖所示，在成長基板1的上表面形成介電阻擋層4，並以曝光、顯影與蝕刻的方式使該介電阻擋層4形成線狀介電阻擋層4a而裸露出成長基板1的上表面的一區域。接著以濕式蝕刻方式蝕刻該區域以形成凹凸結構1a，如第七圖(b)所示，而第七圖(a)為其對應之俯視圖。Step S22: As shown in FIG. 6, a dielectric barrier layer 4 is formed on the upper surface of the growth substrate 1, and the dielectric barrier layer 4 is exposed to the linear dielectric barrier layer 4a by exposure, development, and etching. A region of the upper surface of the growth substrate 1 is grown. The region is then etched by wet etching to form the relief structure 1a as shown in the seventh diagram (b), and the seventh diagram (a) is a corresponding top view thereof.
除此之外，亦可用曝光、顯影與蝕刻的方式使該介電阻擋層4形成點狀介電阻擋層4b，而裸露出該上表面的一區域。接著以蝕刻方式蝕刻該區域以形成凹凸結構1a(如第八圖(b)所示，而第八圖(a)為其對應之俯視圖。)。凹凸結構1a完成後之側視圖如第九圖所示，其中介電阻擋層4a/4b較佳為採用二氧化矽材質，而該濕式蝕刻方式較佳係使用一氟化氫(HF)溶液。In addition, the dielectric barrier layer 4 may be formed into a punctiform dielectric barrier layer 4b by exposure, development, and etching to expose a region of the upper surface. The region is then etched to form the relief structure 1a (as shown in the eighth diagram (b), and the eighth diagram (a) is its corresponding top view). The side view after the completion of the uneven structure 1a is as shown in FIG. 9, wherein the dielectric barrier layer 4a/4b is preferably made of cerium oxide, and the wet etching method is preferably a hydrogen fluoride (HF) solution.
步驟S23：接著再以濕式蝕刻的方式去除介電阻擋層4a/4b，形成如第十圖所示之凹凸結構1a。Step S23: Next, the dielectric barrier layer 4a/4b is removed by wet etching to form the uneven structure 1a as shown in FIG.
本發明所形成之凹凸結構，可以是任意排列方式的凹凸結構不限於上述實施例所示規則排列的凹凸結構，只要是在半導體元件層2與成長基板1間形成凹凸結構或在成長基板1上形成不平整表面，使半導體元件層2與成長基板1間的接觸面積減少，皆可達到本發明的效果。The uneven structure formed by the present invention may be an uneven structure in which the arrangement is not limited to the irregular structure arranged in the above-described embodiment, as long as the uneven structure is formed between the semiconductor element layer 2 and the growth substrate 1 or on the growth substrate 1. The uneven surface is formed, and the contact area between the semiconductor element layer 2 and the growth substrate 1 is reduced, and the effects of the present invention can be attained.
總結而言，本案實為一難得一見，值得珍惜的難得發明，惟以上所述者，僅為本發明之最佳實施例而已，當不能以之限定本發明所實施之範圍。即大凡依本發明申請專利範圍所作之均等變化與修飾，皆應仍屬於本發明專利涵蓋之範圍內，謹請貴審查委員明鑑，並祈惠准，是所至禱。In summary, the present invention is a rare and incomprehensible invention, but the above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto. That is to say, the equivalent changes and modifications made by the applicants in accordance with the scope of the patent application of the present invention should still fall within the scope covered by the patent of the present invention. I would like to ask your review committee to give a clear explanation and pray for the best.
1．．．成長基板1. . . Growth substrate
1a．．．凹凸結構1a. . . Concave structure
2．．．半導體元件層2. . . Semiconductor component layer
3．．．接合基板3. . . Bonded substrate
4．．．介電阻擋層4. . . Dielectric barrier
4a．．．線狀介電阻擋層4a. . . Linear dielectric barrier
4b．．．點狀介電阻擋層4b. . . Dot dielectric barrier
第一圖為本發明一較佳實施例的流程圖。The first figure is a flow chart of a preferred embodiment of the present invention.
第二圖為說明較佳實施例的結構圖。The second figure is a block diagram showing the preferred embodiment.
第三圖為說明較佳實施例的結構圖。The third figure is a structural view illustrating the preferred embodiment.
第四圖為說明較佳實施例的結構圖。The fourth figure is a structural view illustrating the preferred embodiment.
第五圖為說明形成凹凸結構的一較佳實施方式之流程圖。The fifth figure is a flow chart illustrating a preferred embodiment of forming a textured structure.
第六圖係說明第五圖之相應結構圖。The sixth figure is a diagram showing the corresponding structure of the fifth figure.
第七圖(a)與第七圖(b)係說明第五圖之相應結構圖。The seventh (a) and seventh (b) diagrams show the corresponding structural diagrams of the fifth figure.
第八圖(a)與第八圖(b)係說明第五圖之相應結構圖。The eighth (a) and eighth (b) drawings illustrate the corresponding structural diagrams of the fifth figure.
第九圖係說明第五圖之相應結構圖。The ninth figure is a diagram showing the corresponding structure of the fifth figure.
第十圖係說明第五圖之相應結構圖。The tenth figure is a diagram showing the corresponding structure of the fifth figure.
S11-S14．．．步驟S11-S14. . . step
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