TW201250876A - A semiconductor package of a flipped MOSFET and its manufacturing method - Google Patents

A semiconductor package of a flipped MOSFET and its manufacturing method Download PDF

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Publication number
TW201250876A
TW201250876A TW100120730A TW100120730A TW201250876A TW 201250876 A TW201250876 A TW 201250876A TW 100120730 A TW100120730 A TW 100120730A TW 100120730 A TW100120730 A TW 100120730A TW 201250876 A TW201250876 A TW 201250876A
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Taiwan
Prior art keywords
wafer
pedestal
top surface
base
electrode
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Application number
TW100120730A
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Chinese (zh)
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TWI478252B (en
Inventor
Yan Xun Xue
Yueh-Se Ho
Hamza Yilmaz
Jun Lu
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Alpha & Omega Semiconductor
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Priority to TW100120730A priority Critical patent/TWI478252B/en
Publication of TW201250876A publication Critical patent/TW201250876A/en
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Publication of TWI478252B publication Critical patent/TWI478252B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

This invention is aims to providing a flipped MOSFET and its manufacturing method, also providing a lead frame structure, which can support to flipped FET attach on lead frame with solder or adhesive directly, thus enhance the device thermal performance. Half etch or punch the area of lead frame to form some grooves which separate die paddle into several pieces, at least including Gate connecting area and Source connecting areas. All grooves are formed based to FET size, and there is at least a surrounding groove so as to ensure the remaining scribe of wafer place on the groove to avoid electrical short. Dispense solder paste or conductive adhesive on each pieces of die paddle, and then flipped FET and attach on die paddle, due to separate whole die paddle into several smaller. pieces and have grooves to protect paste/adhesive bleed out, which enhance the connection between FET and die paddle.

Description

201250876 六、發明說明： 【發明所屬之技術領域】 剛树明-般涉及-種倒裝晶片的半導體裝置及方法， 確切的說，本發明涉及一種利用倒裝晶片的封裝方式， 製備的包含金屬I化物半導體場效應電晶體的半導2 置及其製造方法。 裝 [先前技術] _隨著積體電路㈣錄造工藝的發展以及晶片按照比例尺 寸縮小的趨勢，裝置熱傳導工程在半導體工藝和裝置= 能改善方面所起的作用越來越明顯。尤其是在—些特殊 的晶片類型上’如-些應用於功率晶月上的金屬氧化物 半導體裝置》 通常，在半導料置的複雜製紅藝絲中，尤其是封 裝過程中，晶片存在各種各樣的熱傳導設計方式，由於 裝置尺寸的逐步縮小，很多散熱方式相對較佳的封裝形 式對裝置的性能是有改善的。專利號 的美國專利申請公開了一種利用倒裝晶片制程製造的半 導體裝置，圖1是該發明中由功率晶片102構成的半導體 封裝裝置100，該半導體封裝裝置100包括應用於晶片 102上方的金屬架110的電性連接及散熱途徑，及通過互 連結構104等將晶片1〇2電性連接至引腳1〇6、108上。在 該半導體封裝裝置100中’金屬架11〇及引腳1〇6、1〇8與 晶片1 0 2的佈局未能達到最佳的散熱效果，因為晶片J 〇 2 是通過焊錫球類或焊接凸塊類的互連結構1〇4電性連接至 引腳106、108 ’而並非直接與引腳1〇6、1〇8接觸。 實際上，如果針對類似如應用於功率裝置的雙擴散金屬 100120730 表單編號 A0101 第 4 頁/共 24 頁 1003248382-0 201250876 氧化物半導體場效應電晶體DMOSFET ( Double-di f-fusion metal-oxide-semiconductor FET)等晶片 類型而言，晶片的表面一般只有栅極和源極，若是再利 用焊錫球（Solder ball)或焊接凸塊（Bump)來將拇 極、源極連接至引腳，則會較為明顯的影響到裳置熱性 能。正是鑒於以上情況，基於晶片封裝工藝中的倒裝晶 片（Flip Chip)技術，提出了本發明所提供的各種實 施例。 ^ 【發明内容】 [0003]鑒於上述所提及的問題，本發明提供—種倒裝晶片的半 導體裝置，包括：一晶片安裝單元，至少包含第一基座 以及設置在第-基座附近並與第—基座分離開的第二基 座和引線座，並且在所述第一基座的頂面、第二基座的 頂面均形成有多條包括橫向及縱向的凹槽，其中，位於 第-基座㈣面的凹槽將第—基座的頂面分割成包含多 個第-類枯貼區的多個區域’位於第二基座的頂面的凹 〇 槽將第二基座的頂面分割成至少包含-個第二類枯姑區 的多個區域；以及 倒裝枯貼至第-基座、第二基座上的晶片，其中，所述 晶片包括位於晶片正面的第—電極和第二電極，所述晶 片的=-電極與所述多個第—類概區接觸並_在一 起，晶片的第二電極與第二類粘貼區接觸並粘貼在，起 〇 上述的倒裝晶心半導體裝置，位料—基座頂面邊緣 處的-橫向凹槽對應與位於第二基座頂面邊緣處^橫 100120730 1003248382-0 =Γ—直if·並且位於第-基座頂面邊緣處 第5頁/共24頁 - 201250876 的一縱向凹槽對應與位於第二基座頂面邊緣處的一縱向 凹槽處於同一直線上。 上述的倒裝晶片的半導體裝置，處於同一直線上的第一 基座頂面邊緣處的橫向凹槽和第二基座頂面邊緣處的橫 向凹槽，以及處於同一直線上的第一基座頂面邊緣處的 縱向凹槽和第二基座頂面邊緣處的縱向凹槽，與第一基 座頂面邊緣處的另一橫向凹槽和另一縱向凹槽圍繞構成 一矩形的周邊槽。 上述的倒裝晶片的半導體裝置，所述晶片為一金屬氧化 物半導體場效應管，並且所述第一電極為晶片的源極， 第二電極為晶月的桃極，位於晶片背面的第二電極為晶 片的漏極。上述的倒裝晶片的半導體裝置，其中，所述 晶片的第三電極通過鍵合線進一步電性連接至引線座上 0 上述的倒裝晶片的半導體裝置，晶片邊緣四周的切割區 位於所述周邊槽的正上方。 此外，本發明還提供一種倒裝晶片的半導體裝置的製造 方法，包括以下步驟：提供包含多個由第一基座、第二 基座及引線座構成的晶片安裝單元的引線框架，其中， 第一基座的頂面包含多個第一類粘貼區，第二基座的頂 面至少包含一個第二類粘貼區； 在第一類粘貼區、第二類粘貼區塗覆導電材料，將一晶 片倒裝粘貼至第一基座、第二基座上，晶片的第一電極 與第一類粘貼區接觸並粘貼在一起，晶片的第二電極與 第二類粘貼區接觸並粘貼在一起； 利用鍵合線將位於晶片背面的第三電極電性連接至引線 100120730 表單編號A0101 第6頁/共24頁 201250876 座上； 利用塑封料封裝所述引線框架、晶片及鍵合線，然後對 所述引線框架及塑封料進行切割用於將以塑封體塑封晶 片、鍵合線、晶片安裝單元的封裝體分離出來； 其中，第二基座及引線座設置在第一基座附近並均與第 一基座分離開，在第一基座的頂面、第二基座的頂面均 形成有多條包括橫向及縱向的凹槽，位於第一基座的頂 面的凹槽將第一基座的頂面分割成包含多個第一類粘貼 區的多個區域，位於第二基座的頂面的凹槽將第二基座 的頂面分割成至少包含一個第二類粘貼區的多個區域。 上述的方法，所述橫向及縱向的凹槽是在第一基座、第 二基座及引線座各自的頂面上進行半刻蝕或模壓實現的 〇 上述的方法，位於第一基座頂面邊緣處的一橫向凹槽對 應與位於第二基座頂面邊緣處的一橫向凹槽處於同一直 線上，並且位於第一基座頂面邊緣處的一縱向凹槽對應 與位於第二基座頂面邊緣處的一縱向凹槽處於同一直線 上。上述的方法，處於同一直線上的第一基座頂面邊緣 處的橫向凹槽和第二基座頂面邊緣處的橫向凹槽，以及 處於同一直線上的第一基座頂面邊緣處的縱向凹槽和第 二基座頂面邊緣處的縱向凹槽，與第一基座頂面邊緣處 的另一橫向凹槽和另一縱向凹槽圍繞構成一矩形的周邊 槽。 上述的方法，將所述晶片倒裝粘貼至第一基座、第二基 座上時，所述晶片邊緣四周的切割區位於所述周邊槽的 正上方。 100120730 表單編號A0101 第7頁/共24頁 1003248382-0 201250876 上述的方法，所述晶片為一金屬氧化物半導體場效應管 ，並且所述第一電極為晶片的源極，第二電極為晶片的 柵極，位於晶片背面的第三電極為晶片的漏極。 本領域的技術人員閱讀以下較佳實施例的詳細說明，並 參照附圖之後，本發明的這些和其他方面的優勢無疑將 顯而易見。 【實施方式】 [0004] 100120730 第2A圖所示出的包含第一基座2〇1、第二基座202、引線 座203的晶片安裝單元200與第3圖所示出的晶片300封裝 在一起就構成了第4圖所示出的半導體裝置4〇〇。在第2A 圖的晶片安裝單元200中，第二基座2 02、引線座203設 置在第一基座201附近並與第一基座2〇1分離斷開，第2B 圖是第2A圖的平面俯視圖，在第一基座201的頂面形成有 多條包括橫向及縱向的凹槽，如縱向凹槽204、204 a、 204b及橫向凹槽205、205a、205b ;同樣在第二基座 202的頂面形成有多條包括橫向及縱'向'的凹槽，如縱向凹 槽20 6a、206b及橫向凹槽207a、207b。其中，第2B圖 所描述的凹槽只是為了便於敍述說明，其數量並不受限 制。第2B圖中，位於第一基座201的頂面包括橫向及縱向 的凹槽（如凹槽204、204a、204b及凹槽205、205a、 205b)將第一基座201的頂面分割成包含多個第一類粘貼 區201b的多個區域，位於第二基座202的頂面包括橫向及 縱向的凹槽（如凹槽206a、206b及凹槽207a、207b) 將第二基座202的頂面分割成至少包含一個第二類粘貼區 202b的多個區域。 參見第2A圖及第2B圖，第一基座201還連接有多個引腳 表單編號A0101 第8頁/共24頁 1〇〇3 201250876 201a，第二基座202還連接有一個或多個引腳2〇2a，引 線座203還連接有多個引腳2〇3a。為了使於理解第2A圖 所示的在第一基座201的頂面、第二基座2〇2的頂面所形 成的多條包括橫向及縱向的凹槽，第2(：圖的晶片安裝單 元200’是第2A圖中晶片安裝單元200未形成凹槽的結構 形式。在晶片安裝單元2〇〇,中，有多種方式可以形成如 第2A圖及第2B圖那樣的橫向或縱向的凹槽，一種優選方 式是在第一基座201’、第二基座2〇2,、引線座203,各自 的頂面進行半刻蝕（Half etch)或進行模壓（punch) ，半刻姓疋}曰在厚度上部分刻.蚀第一基座2〇1’、第二基 座202’、引線座203’。 參見第3圖所示，晶片3〇〇為垂直式的功率裝置，例如頂 源底漏式的金屬氧化物半導體場效應電晶體，則晶片3 〇 〇 的第一電極301為源極、第二電極302為栅極，為晶片 300漏極的第三電極303位於晶片300的背面（未示出） 。參見第4圖所示，即是將晶片3〇〇以倒裝晶片的封裝方 》 式安置在第2A圖所示出的晶片安裝單元2〇〇上。在第4圖 中，晶片300焊接至第一基座2〇1、第二基座2〇2上，其 中，晶片300的第一電極3〇1與第一類粘貼區2〇1|^接觸並 焊接在一起，晶片300的第二電極3〇2與第二類粘貼區 202b接觸並焊接在一起，並且位於晶片3〇〇背面的第三電 極303通過鍵合線401進一步電性連接至引線座2〇3上。 鍵合線401還可以用其他的導體替代，例如金屬帶、金屬 片等。晶片300也有其他的可選類型，例如底源頂漏的垂 直金屬氧化物半導體場效應電晶體，則第一電極謝為漏 極、第二電極302為柵極，位於晶片3〇〇的背面的第三電 1003248382-0 100120730 表單編號A0101 第9頁/共24頁 201250876 極3 0 3為源極。 第5圖是第4圖的截面示意圖，在半導體裝置4〇〇的截面結 構中，參考第2A圖、第2B圖，位於第一基座2〇1頂面邊緣 處的一橫向凹槽205b對應與位於第二基座2〇2頂面邊緣處 的一橫向凹槽207b處於同一直線上，位於第一基座頂 面邊緣處的一縱向凹槽204b對應與位於第二基座202頂面 邊緣處的一縱向凹槽206b處於同一直線上。進而，處於 同一直線上的第一基座202頂面邊緣處的橫向凹槽2〇5b和 第二基座202頂面邊緣處的橫向凹槽2〇7b，以及處於同一 直線上的第一基座201頂面邊緣處的縱向凹槽4 b和第二 基座202頂面邊緣處的縱向凹槽20 6 b，與第一基座2 01頂 面邊緣處的另一縱向凹槽204 a和另一橫向凹槽2〇5a圍繞 構成一矩形的以虛線不出的周邊槽（Surrounding Groove) 208。而位於第二基座202頂面邊緣處的另一縱 向凹槽20 6a和另一橫向凹槽20 7a與縱向凹槽206b、橫向 凹槽207b圍繞構成另一以虛線示出的矩形槽2〇9，以將第 二類粘貼區202b圍繞在内。 如第5圖及第4圖所示’在粘貼晶片300至第一基座201、 第二基座202上的過程中，要保障晶片300邊緣四周的切 割區304位於周邊槽208的正上方，也就是說在垂直方向 上曰曰片300邊緣四周的切割區304位於周邊槽208内，以 防止晶片300與晶片安裝單元200的其他部位發生電氣接 觸而短路。切割區304原本是晶片300在同一晶圓上與其 他晶片鑄造連接在一起的部分，而晶片300被從晶圓上切 割下來後，切刻區（Scribe line) 304被部分切割掉但 還有部分遺留在晶片300的邊緣四周。切割區304位於周 100120730 表單編號A0101 第10頁/共24頁 1003248382-0 201250876 邊槽208的正上方也即是意味著切割區304的垂直投影落 在周邊槽208内。所以，基於晶片300的尺寸大小而要對 周邊槽208的尺寸進行調整’以使得周邊槽2〇8的尺寸比 晶片300的尺寸稍大。在第2B圖及第5圖中，如果縱向凹 槽204a、橫向凹槽205a、縱向凹槽2〇4b、縱向凹槽 206b、橫向凹槽20 7b、橫向凹槽20 5b中最小的凹槽寬度 為W ’則晶片300邊緣四周的切割區304在垂直方向上位於 這個W的寬度範圍内。 第2B圖所示的晶片安裝單元200還可以利用第6圖所示的 晶片安裝單元500代替。晶片安裝單元2〇〇與晶片安裝單 元500的結構並無較大的差異，只是晶片安裝單元5〇〇中 第一基座501的頂面被更多的橫向及縱向凹槽分割成更多 的包含多個第一類粘貼區5 01 b的多個區域。但是位於第 二基座502的頂面的凹槽僅僅為一橫向凹槽和一縱向凹槽 ，將第二基座502的頂面分割成包含一個第二類粘貼區 502b的多個區域。上述差異可以在第一基座5〇1、第二基 座502各自表面進行半刻姓或模壓的流程中，以不同的刻 蝕圖案或模壓圖案實現。 為了獲得第4圖示出的半導體裝置400並將其塑封，第 7A-7E圖展示了本發明的半導體裝置的製備流程示意圖。 第7A圖是引線框架6 05的平面俯視示意圖，引線框架6〇 5 包含多個晶片安裝單元600 (與第2A圖或第6圖所示的晶 片安裝單元相同），進一步而言，引線框架605包含多個 由第一基座601、第二基座602及引線座603 (與第2A圖 或第6圖所示的晶片安裝單元相同）構成的晶片安裝單元 600，其中，第一基座601的頂面包含多個第一類粘貼區 100120730 表單編號A0101 第11頁/共24頁 1003248382-0 201250876 (未示出’參考第2A圖或第6圖），第 至少包含一個第二類粘貼區（未示出， 第7B圖是晶片安裝單元咖的截面示 中，通過在第一類粘貼區、 ^ 圖 繼，將晶片700 (與第3圖^—類枯貼區塗覆導電材料 接至第一、第二基座二的^ ，與第一_區接觸並焊 電 一，二 =);將晶，裝_第:=二(二: ί02上還可以用共晶焊的方式進行，晶謂_第-電 第二電極m可以採用卿（Sn)或金錫（AU_ SrO合金作接觸面鑛層，第一電極m、第二電㈣2可 共晶焊接於财金或銀的第—_貼區、第二類枯貼區 上’晶片安裝單测〇被加熱至適合的共晶溫度時，令共 晶層固化並將晶片700緊固的焊於第一基座6〇1、第二基 座602上。其中，由於有橫向或縱向的凹槽的存在，使得 導電材料802不易從晶片安裝單元6〇〇溢出，並且多個第 一類粘貼區及第二類粘貼區的存在加強了晶片7〇〇與第一 基座601、第二基座602之間的連接強度。 如第7E圖所示’利用鍵合線801將位於晶片7〇〇背面的第 三電極電性連接至引線座603上，並利用塑封料8〇3封裝 引線框架605、晶片700及鍵合線801，如第7F圖完成以 塑封料803塑封引線框架605後的塑封料803、引線框架 605的截面示意圖。然後對引線框架605及塑封料803進 100120730 二基座602的頂面 參考第2A圖或第6201250876 VI. Description of the Invention: [Technical Field] The invention relates to a semiconductor device and method for flip chip mounting, and more particularly to a metal package prepared by flip chip mounting A semiconducting arrangement of a semiconductor semiconductor field effect transistor and a method of fabricating the same. [Previous Technology] _ With the development of the integrated circuit (4) recording process and the shrinking of the scale of the wafer, the role of the device heat conduction engineering in semiconductor process and device = improvement is becoming more and more obvious. Especially in some special wafer types, such as some metal oxide semiconductor devices used in power crystals. Generally, in the complex red silk of semi-conducting materials, especially in the packaging process, the wafer exists. A variety of thermal conduction design methods, due to the gradual reduction of the size of the device, a number of relatively good thermal insulation package styles have improved device performance. U.S. Patent Application Serial No. 5 discloses a semiconductor device fabricated by a flip chip process. FIG. 1 is a semiconductor package device 100 composed of a power die 102 in the invention, the semiconductor package device 100 including a metal frame applied over the wafer 102. The electrical connection and the heat dissipation path of the 110 are electrically connected to the pins 1〇6 and 108 through the interconnect structure 104 and the like. In the semiconductor package device 100, the layout of the metal frame 11 and the leads 1〇6, 1〇8 and the wafer 102 fails to achieve an optimum heat dissipation effect because the wafer J 〇2 is soldered or soldered. The bump-like interconnect structure 1〇4 is electrically connected to the pins 106, 108' and is not directly in contact with the pins 1〇6, 1〇8. In fact, if it is similar to double diffused metal 100120730 as applied to power devices, Form No. A0101 Page 4 of 24 1003248382-0 201250876 Oxide Semiconductor Field Effect Transistor DMOSFET (Double-di f-fusion metal-oxide-semiconductor For wafer types such as FET), the surface of the wafer generally has only the gate and the source. If a solder ball or a bump is used to connect the thumb and source to the leads, Significantly affected the thermal performance of the skirt. In view of the above, various embodiments provided by the present invention have been proposed based on the flip chip technology in the wafer packaging process. SUMMARY OF THE INVENTION [0003] In view of the above-mentioned problems, the present invention provides a semiconductor device for flip chip, comprising: a wafer mounting unit including at least a first pedestal and disposed adjacent to the first pedestal and a second base and a lead frame separated from the first base, and a plurality of grooves including a lateral direction and a longitudinal direction are formed on a top surface of the first base and a top surface of the second base, wherein a groove on the surface of the first base (four) divides the top surface of the first base into a plurality of regions including a plurality of first-type dead zones. The concave groove on the top surface of the second base will be the second base. The top surface of the socket is divided into a plurality of regions including at least a second type of uranium region; and a wafer that is flip-chip attached to the first pedestal and the second pedestal, wherein the wafer includes a front surface of the wafer a first electrode and a second electrode, wherein the = electrode of the wafer is in contact with the plurality of first-type regions, and the second electrode of the wafer is in contact with the second type of bonding region and is pasted thereon Flip-chip semiconductor device, material--transverse groove pair at the top edge of the pedestal It shall correspond to a longitudinal groove located at the edge of the top surface of the second base, horizontally 100120730 1003248382-0 = Γ- straight if and located at the edge of the top surface of the base - page 5 / total 24 pages - 201250876 A longitudinal groove at the edge of the top surface of the second base is in the same straight line. The flip chip semiconductor device described above, the lateral grooves at the top surface of the first pedestal on the same line and the lateral grooves at the edge of the top surface of the second pedestal, and the first pedestal on the same line The longitudinal groove at the top edge and the longitudinal groove at the edge of the top surface of the second base, and the other lateral groove at the edge of the top surface of the first base and the other longitudinal groove surround a peripheral groove forming a rectangle . In the above flip-chip semiconductor device, the wafer is a metal oxide semiconductor field effect transistor, and the first electrode is a source of the wafer, the second electrode is a peach moon, and the second surface is on the back side of the wafer. The electrode is the drain of the wafer. In the above flip-chip semiconductor device, the third electrode of the wafer is further electrically connected to the flip-chip semiconductor device of the above-mentioned flip chip by a bonding wire, and a dicing area around the edge of the wafer is located at the periphery Just above the slot. In addition, the present invention also provides a method of fabricating a flip-chip semiconductor device, comprising the steps of: providing a lead frame including a plurality of wafer mounting units composed of a first pedestal, a second pedestal, and a lead frame, wherein The top surface of a pedestal comprises a plurality of first type of affixing areas, and the top surface of the second pedestal comprises at least one second type of affixing area; and the first type of affixing area and the second type of affixing area are coated with a conductive material, The wafer is flip-chip bonded to the first base and the second base, the first electrode of the wafer is in contact with and adhered to the first type of bonding area, and the second electrode of the wafer is in contact with and adhered to the second type of bonding area; The third electrode on the back surface of the wafer is electrically connected to the lead 100120730 by a bonding wire. Form No. A0101, page 6 / page 24, 201250876; the lead frame, the wafer and the bonding wire are encapsulated by a molding compound, and then The lead frame and the molding compound are cut for separating the package body of the plastic packaged wafer, the bonding wire, and the wafer mounting unit; wherein the second base and the lead seat are disposed at the first base The first base is separated from the first base, and a plurality of grooves including lateral and longitudinal directions are formed on the top surface of the first base and the top surface of the second base, and the top surface of the first base is concave. The groove divides a top surface of the first base into a plurality of regions including a plurality of first type of pasting regions, and the groove on the top surface of the second base divides a top surface of the second base into at least one second Multiple areas of the class pasting area. In the above method, the lateral and longitudinal grooves are semi-etched or molded on the top surfaces of the first base, the second base and the lead frame, and the method is the same as the above method. A lateral groove at the edge of the face corresponds to a transverse groove at the edge of the top surface of the second base, and a longitudinal groove at the edge of the top surface of the first base corresponds to and is located at the second base. A longitudinal groove at the edge of the top surface is in the same straight line. The above method, the lateral grooves at the top surface of the first pedestal on the same straight line and the lateral grooves at the edge of the top surface of the second pedestal, and the top surface of the first pedestal at the same straight line The longitudinal grooves and the longitudinal grooves at the edge of the top surface of the second base surround the other lateral grooves and the other longitudinal grooves at the edge of the top surface of the first base to form a rectangular peripheral groove. In the above method, when the wafer is flip-chip bonded to the first base and the second base, the cutting area around the edge of the wafer is located directly above the peripheral groove. 100120730 Form No. A0101 Page 7 of 24 1003248382-0 201250876 In the above method, the wafer is a metal oxide semiconductor field effect transistor, and the first electrode is a source of the wafer, and the second electrode is a wafer. The gate, the third electrode on the back side of the wafer, is the drain of the wafer. These and other advantages of the present invention will no doubt become apparent to those skilled in the <RTIgt; [Embodiment] 100120730 The wafer mounting unit 200 including the first pedestal 2, the second pedestal 202, and the lead frame 203 shown in FIG. 2A is packaged in the wafer 300 shown in FIG. Together, the semiconductor device 4 shown in Fig. 4 is constructed. In the wafer mounting unit 200 of FIG. 2A, the second pedestal 206 and the lead frame 203 are disposed in the vicinity of the first pedestal 201 and are separated from the first pedestal 2〇1, and FIG. 2B is a view of FIG. 2A. In plan view, a plurality of grooves including lateral and longitudinal directions, such as longitudinal grooves 204, 204a, 204b and lateral grooves 205, 205a, 205b, are formed on the top surface of the first base 201; The top surface of 202 is formed with a plurality of grooves including lateral and longitudinal 'directions', such as longitudinal grooves 20 6a, 206b and lateral grooves 207a, 207b. The grooves described in Fig. 2B are for illustrative purposes only and the number is not limited. In FIG. 2B, the top surface of the first pedestal 201 includes lateral and longitudinal grooves (eg, grooves 204, 204a, 204b and grooves 205, 205a, 205b) that divide the top surface of the first pedestal 201 into a plurality of regions including a plurality of first type pasting regions 201b, the top surface of the second base 202 includes lateral and longitudinal grooves (such as grooves 206a, 206b and grooves 207a, 207b). The top surface is divided into a plurality of areas including at least one second type of pasting area 202b. Referring to FIG. 2A and FIG. 2B , the first pedestal 201 is further connected with a plurality of pin form numbers A0101 8th page / 24 pages 1 〇〇 3 201250876 201a, and the second pedestal 202 is further connected with one or more Pin 2〇2a, lead pad 203 is also connected with a plurality of pins 2〇3a. In order to understand the plurality of grooves including the lateral direction and the longitudinal direction formed on the top surface of the first pedestal 201 and the top surface of the second pedestal 2 〇 2 shown in FIG. 2A, the second (: wafer of the figure) The mounting unit 200' is a structure in which the wafer mounting unit 200 is not formed with a groove in Fig. 2A. In the wafer mounting unit 2, there are various ways to form a lateral or vertical direction as in Figs. 2A and 2B. A preferred method of the recess is to perform a half etch or a punch on the top surface of the first pedestal 201', the second pedestal 2 〇 2, and the lead frame 203.曰 曰 部分 etched the first pedestal 2 〇 1 ′, the second pedestal 202 ′, the lead pedestal 203 ′. As shown in FIG. 3 , the wafer 3 〇〇 is a vertical power device, for example In the top-source drain-type MOSFET, the first electrode 301 of the wafer 3 is the source, the second electrode 302 is the gate, and the third electrode 303 of the drain of the wafer 300 is located on the wafer 300. The back side (not shown). See Figure 4, which is the package of the wafer 3 flip-chip package. Placed on the wafer mounting unit 2A shown in Fig. 2A. In Fig. 4, the wafer 300 is soldered to the first pedestal 2'1 and the second pedestal 2'2, wherein the wafer 300 is An electrode 3〇1 is in contact with and soldered to the first type of bonding region 2〇1|, and the second electrode 3〇2 of the wafer 300 is in contact with and soldered to the second type bonding region 202b, and is located on the wafer 3〇〇. The third electrode 303 on the back surface is further electrically connected to the lead frame 2〇3 through the bonding wire 401. The bonding wire 401 can also be replaced by other conductors, such as a metal strip, a metal sheet, etc. The wafer 300 also has other options. Type, such as a vertical metal oxide semiconductor field effect transistor with a bottom drain, the first electrode is the drain, the second electrode 302 is the gate, and the third electrode 100324838-0 100120730 is located on the back side of the wafer 3〇〇. Form No. A0101 Page 9 of 24 201250876 Pole 3 0 3 is the source. Fig. 5 is a schematic cross-sectional view of Fig. 4, in the cross-sectional structure of the semiconductor device 4, referring to Figs. 2A and 2B, a lateral groove 205b located at the top edge of the first base 2〇1 corresponds to and is located A lateral groove 207b at the top edge of the second base 2〇2 is on the same straight line, and a longitudinal groove 204b at the edge of the top surface of the first base corresponds to a portion located at the top edge of the second base 202. The longitudinal grooves 206b are on the same straight line. Further, the lateral grooves 2〇5b at the top edge of the first pedestal 202 and the lateral grooves 2〇7b at the top edge of the second pedestal 202 are on the same straight line, And a longitudinal groove 4 b at the top edge of the first base 201 and a longitudinal groove 20 6 b at the top edge of the second base 202 on the same line, and the top edge of the first base 2 01 The other longitudinal groove 204a and the other lateral groove 2〇5a surround a peripheral groove (Surrounding Groove) 208 which is formed by a broken line. The other longitudinal groove 20 6a and the other lateral groove 20 7a and the longitudinal groove 206b and the lateral groove 207b at the top edge of the second base 202 surround another rectangular groove 2 shown by a broken line. 9, to surround the second type of pasting area 202b. As shown in FIGS. 5 and 4, during the process of attaching the wafer 300 to the first pedestal 201 and the second pedestal 202, it is necessary to ensure that the dicing area 304 around the edge of the wafer 300 is located directly above the peripheral groove 208. That is, the dicing region 304 around the edge of the cymbal sheet 300 is located in the peripheral groove 208 in the vertical direction to prevent the wafer 300 from being short-circuited by electrical contact with other portions of the wafer mounting unit 200. The dicing area 304 is originally the portion of the wafer 300 that is cast and bonded to other wafers on the same wafer. After the wafer 300 is diced from the wafer, the Scribe line 304 is partially cut but still partially It remains around the edges of the wafer 300. The cutting zone 304 is located at the circumference 100120730 Form No. A0101 Page 10 of 24 1003248382-0 201250876 Just above the side slot 208 also means that the vertical projection of the cutting zone 304 falls within the peripheral groove 208. Therefore, the size of the peripheral groove 208 is adjusted based on the size of the wafer 300 so that the size of the peripheral groove 2〇8 is slightly larger than the size of the wafer 300. In FIGS. 2B and 5, if the longitudinal groove 204a, the lateral groove 205a, the longitudinal groove 2〇4b, the longitudinal groove 206b, the lateral groove 20 7b, and the lateral groove 20 5b have the smallest groove width For W', the cutting zone 304 around the edge of the wafer 300 is located in the width of this W in the vertical direction. The wafer mounting unit 200 shown in Fig. 2B can also be replaced by the wafer mounting unit 500 shown in Fig. 6. The structure of the wafer mounting unit 2 is not significantly different from that of the wafer mounting unit 500, except that the top surface of the first pedestal 501 in the wafer mounting unit 5 is divided into more by lateral and longitudinal grooves. A plurality of regions including a plurality of first type pasting areas 5 01 b. However, the groove on the top surface of the second base 502 is only a lateral groove and a longitudinal groove, and the top surface of the second base 502 is divided into a plurality of regions including a second type of pasting region 502b. The above difference can be achieved in a different etching pattern or molding pattern in the process of performing half-inscription or molding on the respective surfaces of the first pedestal 5 〇 1 and the second pedestal 502. In order to obtain and mold the semiconductor device 400 shown in Fig. 4, Figs. 7A-7E are views showing the flow of the preparation of the semiconductor device of the present invention. 7A is a plan top plan view of the lead frame 605, the lead frame 6〇5 includes a plurality of wafer mounting units 600 (same as the wafer mounting unit shown in FIG. 2A or FIG. 6), and further, the lead frame 605 A plurality of wafer mounting units 600 including a first pedestal 601, a second pedestal 602, and a leadframe 603 (the same as the wafer mounting unit shown in FIG. 2A or FIG. 6), wherein the first pedestal 601 is included The top surface contains a plurality of first type pasting areas 100120730 Form No. A0101 No. 11 / Total 24 pages 1003248382-0 201250876 (not shown 'Refer to Figure 2A or Figure 6), at least one second type of pasting area (not shown, FIG. 7B is a cross-sectional view of the wafer mounting unit, and the wafer 700 is attached to the conductive material of the third type by the first type of bonding area, FIG. The first and second pedestal two are in contact with the first _ region and are soldered one, two =); the crystal, the _:: two (two: ί02 can also be performed by eutectic soldering, The crystal front _ first-electric second electrode m can be used as a contact layer or a gold-tin (Sn) or gold tin (AU_SrO alloy as the contact surface layer, first The electrode m and the second electric (4) 2 can be eutectic soldered to the first-paste region of the financial or silver, and the second type of dead region. When the wafer is mounted, the eutectic layer is heated to a suitable eutectic temperature. The wafer 700 is cured and soldered to the first pedestal 〇1, the second pedestal 602. The conductive material 802 is not easily detached from the wafer mounting unit 6 due to the presence of lateral or longitudinal grooves. The overflow, and the presence of the plurality of first type pasting areas and the second type of pasting areas enhances the connection strength between the wafer 7A and the first base 601 and the second base 602. As shown in FIG. 7E The bonding wire 801 electrically connects the third electrode on the back surface of the wafer 7 to the lead frame 603, and encapsulates the lead frame 605, the wafer 700 and the bonding wire 801 by using the molding material 8〇3, as shown in FIG. The molding compound 803 plasticizes the cross-section of the molding compound 803 and the lead frame 605 after the lead frame 605. Then, the lead frame 605 and the molding compound 803 are entered into the top surface of the base 602 with reference to FIG. 2A or 6

表單編號A0101 第12頁/共24頁 II 201250876 =切割用於將以塑封體8〇3,塑封晶片700、鍵合線8〇1、 文衷單元6〇0的封裝體9〇0從引線框架6〇5及塑封料 中刀離出來，以形成單獨的裝置，如第76圖所示。Form No. A0101 Page 12 / Total 24 Pages 201250876 = Cutting for the package body 9〇0 from the lead frame with the molded body 8〇3, the molded wafer 700, the bonding wire 8〇1, the text unit 6〇0 6〇5 and the cutter in the molding compound are separated to form a separate device, as shown in Fig. 76.

^晶片安装單元_中，其引腳（未示出，類同如第湖 八的弓1腳2〇la、2〇2a、203a)可作為晶片安裝單元 及&quot;、弓丨線框架6〇5連接的連筋，引腳在對引線框架6〇5 對^封料8〇3的切割過程中被切斷，並且塑封體803,源於 舉封料803的切割。而且在上述步驟中，將晶片7〇〇倒 接至第—基座6〇1、第二基座6〇2上時，要保障晶片 0邊緣四周的切割區804位於晶片安裝單元6〇〇的周邊 808 (參考第7E圖及第5圖）的正上方。在本申請的一 優選實施方式中，晶片7〇〇為一金屬氧化物半導體場效 應營，笛^In the wafer mounting unit_, its pin (not shown, like the bow 1 foot 2〇2, 2〇2a, 203a of the first lake eight) can be used as a wafer mounting unit and &quot;, bow line frame 6〇 5 connected ribs, the pins are cut during the cutting process of the lead frame 6〇5 to the sealing material 8〇3, and the molding body 803 is derived from the cutting of the sealing material 803. Moreover, in the above step, when the wafer 7 is inverted onto the first base 6〇1 and the second base 6〇2, the cutting area 804 around the edge of the wafer 0 is ensured to be located at the wafer mounting unit 6〇〇. The top of the perimeter 808 (refer to Figures 7E and 5). In a preferred embodiment of the present application, the wafer 7 is a metal oxide semiconductor field effect camp, flute

弟—電極701為晶片700的源極，第二電極7〇2為 曰0片的柵極，第三電極為晶片7〇〇的漏極。而在另一種可 故的實施方式中，晶片700為一金屬氧化物半導體場效應 第電極701為晶片700的漏極’第二電極7〇2為晶 的概極’並且第三電極為晶片700的源極。 通過說明和附圖，給出了具體實施方式的特定結構的典 實施例，例如，本案是以金屬氧化物半導體電晶體裝 置進行闌述，基於本發明精神，晶片還可作其他類型的 轉換。儘營上述發明提出了現有的較佳實施例，然而， 這些内容並不作為局限。 子於本領域的技術人員而言，閱讀上述說明後，各種變 化和修正無疑將顯而易見。因此，所附的申請專利範圍 應看作是涵蓋本發明的真實意圖和範圍的全部變化和修 正。在申請專利範圍内任何和所有等價的範圍與内容， 100120730The electrode 701 is the source of the wafer 700, the second electrode 7〇2 is the gate of the NMOS, and the third electrode is the drain of the wafer 7. In another exemplary embodiment, the wafer 700 is a metal oxide semiconductor field effect. The first electrode 701 is the drain of the wafer 700. The second electrode 7〇2 is a crystal of the anode' and the third electrode is the wafer 700. The source. Exemplary embodiments of the specific structure of the specific embodiment are given by way of illustration and the accompanying drawings. For example, the present invention is described in terms of a metal oxide semiconductor transistor device, and the wafer can be converted into other types based on the spirit of the present invention. The above preferred embodiments are presented in the above-described invention, however, these are not intended to be limiting. Various changes and modifications will no doubt become apparent to those skilled in the <RTIgt; Accordingly, the appended claims are intended to cover all such modifications and modifications Any and all equivalent ranges and contents within the scope of the patent application, 100120730

表單編號A010I 第13頁/共24頁 1003248382-0 201250876 都應認為仍屬本發明的意圖和範圍内。 【圖式簡單說明】 [0005] 參考所附附圖，以更加充分的描述本發明的實施例。然 而，所附附圖僅用於說明和闡述，並不構成對本發明範 圍的限制。 第1圖是背景技術中公開了的利用倒裝晶片制程製造的半 導體裝置。 第2A圖是本發明第一基座附近的第二基座、引線座組合 在一起的立體結構示意圖。 第3B圖是本發明第一基座附近的第二基座、引線座組合 在一起的俯視示意圖。 第2C圖是第一基座、第二基座各自的表面未經刻蝕或模 壓前的結構示意圖。 第3圖是在本發明中晶片的結構示意圖。 第4圖是晶片焊接在第一基座、第二基座、引線座上的立 體結構示意圖。 第5圖是晶片焊接在第一基座、第二基座、引線座上的截 面示意圖。 第6圖是第一基座、第二基座各自表面進行刻蝕或模壓的 另外一種實施方式的示意圖。 第7A-7G圖是本發明的半導體裝置的製備流程示意圖。 【主要元件符號說明】 [0006] 400 半導體裝置 401、801 鍵合線 300 粘貼晶片 100120730 表單編號A0101 第14頁/共24頁 1003248382-0 201250876 201、 20Γ、501、601 第一基座 202、 202’、502、602 第二基座 203、 203’、603 引線座 106、108、201a、202a、203a 引腳 303 第三電極 100 半導體封裝裝置 102 功率晶片 104 互連結構 110 金屬架Form No. A010I Page 13 of 24 1003248382-0 201250876 is considered to be within the intent and scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS [0005] Embodiments of the present invention will be described more fully with reference to the accompanying drawings. The accompanying drawings are for the purpose of illustration and illustration only, Fig. 1 is a semiconductor device fabricated by a flip chip process as disclosed in the background art. Fig. 2A is a perspective view showing the structure of the second pedestal and the lead frame in the vicinity of the first pedestal of the present invention. Fig. 3B is a top plan view showing the second pedestal and the lead frame in the vicinity of the first pedestal of the present invention. Fig. 2C is a schematic view showing the structure of the surface of each of the first pedestal and the second susceptor before being etched or molded. Fig. 3 is a schematic view showing the structure of a wafer in the present invention. Fig. 4 is a schematic view showing the vertical structure of the wafer soldered to the first pedestal, the second pedestal, and the lead frame. Figure 5 is a schematic cross-sectional view showing the wafer soldered to the first pedestal, the second pedestal, and the leadframe. Fig. 6 is a schematic view showing another embodiment in which the surfaces of the first pedestal and the second pedestal are etched or molded. 7A-7G are schematic views showing the preparation flow of the semiconductor device of the present invention. [Main component symbol description] [0006] 400 semiconductor device 401, 801 bonding wire 300 pasting wafer 100120730 Form number A0101 page 14 / total 24 page 1003248382-0 201250876 201, 20 Γ, 501, 601 first pedestal 202, 202 ', 502, 602 second pedestal 203, 203', 603 leadframe 106, 108, 201a, 202a, 203a pin 303 third electrode 100 semiconductor package device 102 power chip 104 interconnect structure 110 metal frame

200、200’、500、600 晶片安裝單元 201b、501b 第一類粘貼區 202b、502b 第二類粘貼區 204、 204a、204b、206a、206b 縱向凹槽 205、 205a、205b、207a、207b 橫向凹槽 208、808 周邊槽 209 矩形槽 300、 700 晶片 301、 701 第一電極 302、 702 第二電極 304、804 切割區 605 引線框架 802 導電材料 803 塑封料 900 封裝體 1003248382-0 100120730 表單編號A0101 第15頁/共24頁200, 200', 500, 600 wafer mounting unit 201b, 501b first type bonding area 202b, 502b second type bonding area 204, 204a, 204b, 206a, 206b longitudinal grooves 205, 205a, 205b, 207a, 207b Slot 208, 808 Peripheral groove 209 Rectangular groove 300, 700 Wafer 301, 701 First electrode 302, 702 Second electrode 304, 804 Cutting area 605 Lead frame 802 Conductive material 803 Molding material 900 Package 1003248382-0 100120730 Form No. A0101 15 pages / total 24 pages

Claims (1)

201250876 七、申請專利範圍： 1 . 一種倒裝晶片的半導體裝置，包括： 一晶片安裝單元，至少包含第一基座以及設置在第一基座 附近並與第一基座分離開的第二基座和引線座，並且在所 述第一基座的頂面、第二基座的頂面均形成有多條包括橫 向及縱向的凹槽，其中，位於第一基座的頂面的凹槽將第 一基座的頂面分割成包含多個第一類粘貼區的多個區域， 位於第二基座的頂面的凹槽將第二基座的頂面分割成至少 包含一個第二類粘貼區的多個區域；以及 倒裝粘貼至第一基座、第二基座上的晶片，其中，所述晶 片包括位於晶片正面的第一電極和第二電極，所述晶片的 第一電極與所述多個第一類粘貼區接觸並粘貼在一起，所 述晶片的第二電極與第二類粘貼區接觸並粘貼在一起。 2 .如申請專利範圍第1項所述的倒裝晶片的半導體裝置，其 中，處於同一直線上的第一基座頂面邊緣處的橫向凹槽和 第二基座頂面邊緣處的橫向凹槽，以及處於同一直線上的 第一基座頂面邊緣處的縱向凹槽和第二基座頂面邊緣處的 縱向凹槽，與第一基座頂面邊緣處的另一橫向凹槽和另一 縱向凹槽圍繞構成一矩形的周邊槽。 3 .如申請專利範圍第2項所述的倒裝晶片的半導體裝置，其 中，所述晶片邊緣四周的切割區位於所述周邊槽的正上方 〇 4 .如申請專利範圍第1項所述的倒裝晶片的半導體裝置，其 中，所述晶片還包括位於晶片背面的第三電極，所述第三 電極通過鍵合線進一步電性連接至所述引線座上。 100120730 表單編號A0101 第16頁/共24頁 1003248382-0 201250876 5 .如申請專利範圍第4項所述的倒裝晶片的半導體裝置，其 特徵在於，所述晶片為一金屬氧化物半導體場效應管，並 且所述第·一電極為晶片的源極*弟—電極為晶片的棚'極* 位於晶片背面的第二電極為晶片的漏極。 6 . —種倒裝晶片的半導體裝置的製造方法，包括以下步驟： 提供包含多個由第一基座、第二基座及引線座構成的晶片 安裝單元的引線框架，其中，第一基座的頂面包含多個第 一類粘貼區，第二基座的頂面至少包含一個第二類粘貼區 9 ^ 在第一類粘貼區、第二類粘貼區塗覆導電材料，將一晶片 倒裝粘貼至第一基座、第二基座上，晶片的第一電極與第 一類粘貼區接觸並粘貼在一起，晶片的第二電極與第二類 粘貼區接觸並粘貼在一起； 利用鍵合線將位於晶片背面的第三電極電性連接至引線座 上； 利用塑封料封裝所述引線框架、晶片及鍵合線，然後對所 述引線框架及塑封料進行切割用於將以塑封體塑封晶片、 C) 鍵合線、晶片安裝單元的封裝體分離出來； 其中，第二基座及引線座設置在第一基座附近並均與第一 基座分離開，在第一基座的頂面、第二基座的頂面均形成 有多條包括橫向及縱向的凹槽，位於第一基座的頂面的凹 槽將第一基座的頂面分割成包含多個第一類粘貼區的多個 區域，位於第二基座的頂面的凹槽將第二基座的頂面分割 成至少包含一個第二類粘貼區的多個區域。 7 .如申請專利範圍第6項所述的方法，其中，所述橫向及縱 向的凹槽是在第一基座、第二基座及引線座各自的頂面上 100120730 表單編號A0101 第17頁/共24頁 1003248382-0 201250876 進行半刻蝕或模壓實現的。 8 .如申請專利範圍第6項所述的方法，其中，處於同一直線 上的第一基座頂面邊緣處的橫向凹槽和第二基座頂面邊緣 處的橫向凹槽，以及處於同一直線上的第一基座頂面邊緣 處的縱向凹槽和第二基座頂面邊緣處的縱向凹槽，與第一 基座頂面邊緣處的另一橫向凹槽和另一縱向凹槽圍繞構成 一矩形的周邊槽。 9 .如申請專利範圍第8項所述的方法，其中，將所述晶片倒 裝粘貼至第一基座、第二基座上時，所述晶片邊緣四周的 切割區位於所述周邊槽的正上方。 10 .如申請專利範圍第6項所述的方法，其中，所述晶片為一 金屬氧化物半導體場效應管，並且所述第一電極為晶片的 源極，第二電極為晶片的柵極，位於晶片背面的第三電極 為晶片的漏極。 100120730 表單編號A0101 第18頁/共24頁 1003248382-0201250876 VII. Patent application scope: 1. A flip-chip semiconductor device, comprising: a wafer mounting unit comprising at least a first pedestal and a second base disposed adjacent to the first pedestal and separated from the first pedestal And a lead frame, and a top surface of the first base and a top surface of the second base are formed with a plurality of grooves including a lateral direction and a longitudinal direction, wherein the groove on the top surface of the first base Dividing a top surface of the first pedestal into a plurality of regions including a plurality of first type of affixing regions, the recesses on the top surface of the second pedestal dividing the top surface of the second pedestal into at least one second class a plurality of regions of the pasting region; and a wafer flip-chip bonded to the first pedestal, the second pedestal, wherein the wafer includes a first electrode and a second electrode on a front side of the wafer, the first electrode of the wafer Contacting and pasting together with the plurality of first type pasting regions, the second electrode of the wafer is in contact with and pasted together with the second type of bonding area. The flip-chip semiconductor device of claim 1, wherein the lateral grooves at the top surface of the first pedestal on the same straight line and the lateral concave at the edge of the top surface of the second pedestal a slot, and a longitudinal groove at a top surface edge of the first base and a longitudinal groove at a top surface of the second base, and another lateral groove at the edge of the top surface of the first base Another longitudinal groove surrounds a peripheral groove that forms a rectangle. 3. The flip-chip semiconductor device of claim 2, wherein the dicing area around the edge of the wafer is located directly above the peripheral groove 〇4. As described in claim 1 A flip chip semiconductor device, wherein the wafer further includes a third electrode on a back surface of the wafer, the third electrode being further electrically connected to the lead frame by a bonding wire. The flip-chip semiconductor device of claim 4, wherein the wafer is a metal oxide semiconductor field effect transistor, and the flip-chip semiconductor device of claim 4, wherein the wafer is a metal oxide semiconductor field effect transistor. And the first electrode is the source of the wafer, the electrode is the shed of the wafer, and the second electrode located on the back surface of the wafer is the drain of the wafer. 6. A method of fabricating a flip-chip semiconductor device, comprising the steps of: providing a lead frame comprising a plurality of wafer mounting units comprising a first pedestal, a second pedestal, and a leadframe, wherein the first pedestal The top surface of the second base comprises a plurality of first type of pasting areas, and the top surface of the second base comprises at least one second type of pasting area 9 ^ coating a conductive material in the first type of pasting area and the second type of pasting area to pour a wafer Attached to the first base and the second base, the first electrode of the wafer is in contact with and adhered to the first type of bonding area, and the second electrode of the wafer is in contact with and adhered to the second type of bonding area; The bonding wire electrically connects the third electrode on the back surface of the wafer to the lead frame; encapsulating the lead frame, the wafer and the bonding wire with a molding compound, and then cutting the lead frame and the molding compound for molding the plastic body The packaged body of the plastic wafer, the C) bonding wire, and the wafer mounting unit are separated; wherein the second pedestal and the lead frame are disposed adjacent to the first pedestal and are separated from the first pedestal at the first pedestal Top surface The top surface of the second base is formed with a plurality of grooves including lateral and longitudinal directions, and the groove on the top surface of the first base divides the top surface of the first base into a plurality of first type pasting regions. The plurality of regions, the recesses on the top surface of the second pedestal divide the top surface of the second pedestal into a plurality of regions including at least one second type of affixing zone. The method of claim 6, wherein the lateral and longitudinal grooves are on a top surface of each of the first base, the second base, and the lead frame. 100120730 Form No. A0101 Page 17 / Total 24 pages 1003248382-0 201250876 Performed by half etching or molding. 8. The method of claim 6, wherein the lateral grooves at the top surface of the first pedestal on the same line and the lateral grooves at the edge of the top surface of the second pedestal are in the same a longitudinal groove at the top edge of the first pedestal on the straight line and a longitudinal groove at the edge of the top surface of the second pedestal, and another lateral groove and another longitudinal groove at the edge of the top surface of the first pedestal Around the perimeter groove that forms a rectangle. 9. The method of claim 8, wherein the dicing area around the edge of the wafer is located in the peripheral groove when the wafer is flip-chip bonded to the first pedestal and the second pedestal Directly above. 10. The method of claim 6, wherein the wafer is a metal oxide semiconductor field effect transistor, and the first electrode is a source of the wafer and the second electrode is a gate of the wafer. The third electrode on the back side of the wafer is the drain of the wafer. 100120730 Form No. A0101 Page 18 of 24 1003248382-0
TW100120730A 2011-06-14 2011-06-14 A semiconductor package of a flipped mosfet and its manufacturing method TWI478252B (en)

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US6307755B1 (en) * 1999-05-27 2001-10-23 Richard K. Williams Surface mount semiconductor package, die-leadframe combination and leadframe therefor and method of mounting leadframes to surfaces of semiconductor die
US6870254B1 (en) * 2000-04-13 2005-03-22 Fairchild Semiconductor Corporation Flip clip attach and copper clip attach on MOSFET device
US7598603B2 (en) * 2006-03-15 2009-10-06 Infineon Technologies Ag Electronic component having a power switch with an anode thereof mounted on a die attach region of a heat sink
US7777315B2 (en) * 2006-05-19 2010-08-17 Fairchild Semiconductor Corporation Dual side cooling integrated power device module and methods of manufacture
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