TW201246533A - Metamorphic integrated BiFETs - Google Patents

Metamorphic integrated BiFETs Download PDF

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TW201246533A
TW201246533A TW100116580A TW100116580A TW201246533A TW 201246533 A TW201246533 A TW 201246533A TW 100116580 A TW100116580 A TW 100116580A TW 100116580 A TW100116580 A TW 100116580A TW 201246533 A TW201246533 A TW 201246533A
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layer
undoped
field effect
inp
effect transistor
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TW100116580A
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TWI456755B (en
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Jung-Hui Tsai
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Univ Nat Kaohsiung Normal
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Abstract

A metamorphic integrated bipolar and field-effect transistors (BiFETs) is disclosed by the present invention. The metamorphic integrated BiFETs are fabricated on low-cost GaAs substrates. Among them, the bipolar transistor of the integrated BiFETs is fabricated on the undoped metamorphic buffer layer which graded from In0.52Ga0.48P to InP, and the device performance with high current gain and low collector-emitter offset voltage for reducing power consumption is achieved. Furthermore, the field-effect transistor is fabricated on the bipolar transistor, and the device characteristics with high drain current, transconductance, and linearity are obtained. The substantial advantages of the metamorphic integrated BiFETs, such as excellent characteristics of bipolar and field-effect transistors, simple structure, and low cost, are included in this invention. The over layers of the integrated devices are only more than four material layers, as compared with the metamorphic bipolar transistor. Consequently, the metamorphic integrated BiFETs are very promising for digital, analog, mixed-mode, and integrated circuit applications.

Description

201246533 六、發明說明: 【發明所屬之技術領域】 本發明揭示一種變晶性積體化雙極場效電晶體。盆 中,碌化銦/石中化銦鎵(InP/In〇 53Ga〇 47As)雙極性電晶體係ς 建構於磷化銦鎵(In〇.52Ga。48ρ)至磷化銦(Ιηρ)變晶性緩衝層 之上,且鱗化銦/坤化銦鎵場效電晶體係於建構於該碟化铜 /神化銦鎵雙極性電晶體之上,整體積體化元件僅較變晶性 雙極性電晶體多出四層材料層。本發明之變晶性積體化雙 極場效電晶體,特性佳,成本低,適於數位、m比、混模 信號及積體電路之使用。 【先前技術】 近年.來’拜磊晶技術精進之賜,各種晶格匹配、超晶 格(superlattice)、擬晶性(pseudomorphic)應力層與變晶性 (metamorphic)等結構製作之異質結構元件,如雨後春筍 般’持續出新。而異質接面雙極性電晶體(HBTs)因具有低 Ι/f雜訊、高速及高電流操作能力,已應用於數位及微波功 率方面;另一方面,異質結構場效電晶體場效電然晶體 (HFETs)具有低雜訊、高輸入阻抗、高密度及低功率消耗 等優點,且已廣範應用於積體電路。 對於HBTs而言,相較於砷化鎵(GaAs)相關材料系統, 磷化銦/砷化銦鎵(InP/In0.53Ga0.47As)材料系統因 In0 53Ga〇.47As材料層具有以下之優點:(1)低的表面復合速 率,(2)低的有效電子質量,(3)低的導通電壓,(4)可與長 201246533 * ;皮長光元件相容。因此’除具有高速、低功率消耗及訊號 放大功用之外,特別可應用於低雜訊振盪電路與i 3〜丨以瓜 ;皮長範圍之光電積體電路應用。另一方面,一系_:: HFETs有著絕佳的電晶體特性。由於In。5仙。"As之通道 中較高的銦含量,可使的元件具較高的電子移動率、較高 的飽和速度。此外,InP/In〇.53Ga。4山材料系統有大的= 導帶不連續,使元件具有較佳载子侷限能力,夠操作在較 大的閘極偏壓,以提升電流輸出能力。在許多應用上元件 的性能都比砷化鎵系列優異許多。 然而,由於磷化銦基板較昂貴且易破碎,亦沒有較大 的基板尺寸,使得在商業應用上增加了製程的困難度與生 產成本。於是,在砷化鎵基板上成長變晶式 InP/In0.53Ga0.47AS HBTs或HFETs已吸引高度的商業興 趣,在此變晶式結構中,變晶式緩衝層(metam〇rphic buffer) S元件特性扮演了非常重要的角色。它兩個重要的功能如 下.(1)可調變InP/InGaAs材料系統與碎化鎵基板間晶格的 不匹配’(2)將缺陷固定在緩衝層内,並防止其擴散至主動 層。因此,在砷化鎵基板上成長變晶式電晶體將同時具有 低成本及InGaAM才料之優越元件特性。無論如何,通常變 晶式緩衝層具有高的熱電阻,此將使元件之功率受限制。 對於變晶式HBT而言’其熱電阻是由集極下方之次 集極(SUbC〇UeCt〇r)、緩衝層和基板所決定。又GaAs基板的 熱傳導率(〇.44W/cm.IC)較Inp的熱傳導率(〇 68w/cm.K)為 低’故此將導致高的熱電P且。而藉由緩衝層中之III族原子 201246533 之alloy-disorder scattering可有效降低熱電阻。然而,過 量的dislocation亦將使熱傳導率慈化。通常變晶式緩衝層 有下列幾種結構方式:(1)在砷化鎵基板上以A1 As漸變至 Al0.48In0.52As ; (2)在砷化鎵基板上以in〇 52(3a〇 48p材質漸變 至InP ; (3)在砷化鎵基板上直接使用Inp作為緩衝層。過 去,Kim等人已論證:因InP有高的熱傳導率,Inp緩衝 層其熱電阻相當低。然而,砷化鎵與InP有相當之晶格常 數差異,若在珅化錁基板上直接使用InP作為緩衝層,其 表面將相當粗糙且有高的缺陷密度。而使用In〇 52Ga〇 48P 漸變至InP的緩衝層,其熱電阻亦較A1InAs為低,故此方 法將是一佳的選擇。 然而,僅建構單一元件已不符現今多功能、高積體化 之需求。而在同一基板上建造共積體化ΗΒτ與FET (BiFET) 可同時具有上述HBT與FET等優點,可大幅減少結構層數 目,並適於數位、類比、混模信號及微波積體電路上使用。 仁〜觀BiFET之製作,以Inp/InGaAs為主的積體化元件甚 少’且尚無以變晶性方式製作BiFET。 【發明内容】 本發明的一主要目的在提供一種變晶性積體化雙極場 效電晶體’其包含:―未務雜GaAs ♦導體基板;_位於該 未摻雜GaAS半導體基板上之至InP未摻雜漸 變層,一位於該InQ nGw 至Inp未摻雜漸變層上之未摻 雜InP層’位於該未摻雜InP層上之n+型摻雜 6 201246533201246533 VI. Description of the Invention: [Technical Field of the Invention] The present invention discloses a crystallized integrated bipolar field effect transistor. In the basin, indium/magnesium indium gallium (InP/In〇53Ga〇47As) bipolar electro-crystal system ς is constructed in indium gallium phosphide (In〇.52Ga.48ρ) to indium phosphide (Ιηρ) crystal Above the buffer layer, and the indium arsenide/indium gallium oxide field effect crystal system is constructed on the disc copper/desiced indium gallium bipolar transistor, and the whole volume of the element is only more transmorphic bipolar The transistor has four layers of material. The crystallized integrated bipolar field effect transistor of the invention has good characteristics and low cost, and is suitable for use in digital, m ratio, mixed mode signals and integrated circuits. [Prior Art] In recent years, we have come to the principle of “excellence of the crystal technology, various structural matching, superlattice, pseudomorphic stress layer and metamorphic structure. , like springing up, 'continuing new. Heterogeneous junction bipolar transistors (HBTs) have been used in digital and microwave power due to their low Ι/f noise, high speed and high current operation capability. On the other hand, heterostructure field effect transistor field effect Crystals (HFETs) have the advantages of low noise, high input impedance, high density, and low power consumption, and have been widely used in integrated circuits. For HBTs, the InP/In0.53Ga0.47As material system has the following advantages over the InP/In0.53Ga0.47As material layer compared to the gallium arsenide (GaAs) related material system: (1) low surface recombination rate, (2) low effective electron mass, (3) low on-voltage, (4) compatible with long 201246533*; Therefore, in addition to high-speed, low-power consumption and signal amplification, it can be applied to low noise oscillation circuits and optoelectronic integrated circuit applications. On the other hand, a series of _:: HFETs have excellent transistor characteristics. Thanks In. 5 cents. "As in the channel, the higher indium content enables the components to have higher electron mobility and higher saturation speed. In addition, InP/In〇.53Ga. 4 The mountain material system has a large = conduction band discontinuity, so that the component has better carrier limitation capability, and can operate at a larger gate bias to improve current output capability. The performance of components in many applications is much better than the gallium arsenide series. However, since the indium phosphide substrate is expensive and fragile, and has no large substrate size, the process difficulty and production cost are increased in commercial applications. Thus, the growth of crystal-morphic InP/In0.53Ga0.47AS HBTs or HFETs on gallium arsenide substrates has attracted a high commercial interest. In this crystal-morphic structure, the metamorphic buffer layer (SM) Features play a very important role. Its two important functions are as follows: (1) The lattice mismatch between the variable-change InP/InGaAs material system and the gallium-depleted substrate' (2) Fixes the defect in the buffer layer and prevents it from diffusing to the active layer. Therefore, the growth of a crystal-transformed transistor on a gallium arsenide substrate will have both low cost and superior component characteristics of InGaAM. In any event, typically the crystalline buffer layer has a high thermal resistance which will limit the power of the component. For a crystallographic HBT, the thermal resistance is determined by the sub-collector (SUbC〇UeCt〇r) under the collector, the buffer layer, and the substrate. Further, the thermal conductivity (〇.44 W/cm.IC) of the GaAs substrate is lower than that of Inp (〇68 w/cm.K), so that high thermoelectricity P is caused. The thermal resistance can be effectively reduced by the alloy-disorder scattering of the group III atom 201246533 in the buffer layer. However, excessive dislocation will also make the thermal conductivity favorable. Generally, the crystal buffer layer has the following structural modes: (1) grading to A4 As to Al0.48In0.52As on a gallium arsenide substrate; (2) in〇52 on a gallium arsenide substrate (3a〇48p) The material is graded to InP; (3) Inp is directly used as a buffer layer on the gallium arsenide substrate. In the past, Kim et al. have demonstrated that the thermal resistance of the Inp buffer layer is rather low due to the high thermal conductivity of InP. However, arsenic Gallium has a considerable lattice constant difference with InP. If InP is used as the buffer layer directly on the germanium germanium substrate, the surface will be quite rough and have a high defect density. The In〇52Ga〇48P is used to grade the buffer layer to InP. The thermal resistance is also lower than that of A1InAs, so this method will be a good choice. However, the construction of a single component has not met the needs of today's versatile and high-integration, and the construction of a total integrated ΗΒτ on the same substrate. FET (BiFET) can have the above advantages of HBT and FET, can greatly reduce the number of structural layers, and is suitable for digital, analog, mixed-mode signals and microwave integrated circuits. Manufacture of BiFETs to Inp/InGaAs There are very few integrated components A BiFET is produced in a crystallographic manner. SUMMARY OF THE INVENTION A primary object of the present invention is to provide a crystallized integrated bipolar field effect transistor that includes: a non-contained GaAs ♦ conductor substrate; An undoped graded layer on the undoped GaAS semiconductor substrate, an undoped InP layer on the InQ nGw to Inp undoped graded layer, n+ type doped 6 on the undoped InP layer 201246533

In〇.53Ga〇.47As次集極層;一位於該n+型摻雜In〇.53Ga〇.47As secondary collector layer; one is located in the n+ type doping

v °*53Ga〇 47AS 次集極層上之η型摻雜In0_53Ga0.47As集極層;_ m於§玄 型掺雜In〇.53Ga。·47As集極層上之ρ +型摻雜in。A式 極層;一位於該p+型摻雜InQ 53GaQ WAS基極層上之第一未 摻雜In〇.53Ga〇.47As間隙層;一位於該未摻雜 ” 0.53 vja〇 47 As 間隙層上之n+型摻雜單原子層;一位於該n+型摻雜單原 子層上之第二未摻雜In〇 53Ga〇 oAs間隙層;一位於該第_、 未摻雜In^Ga^As間隙層上之n型摻雜Inp射極層;— 位於該η型摻雜InP射極層上之n+型 ^ 诊濉丄n〇.53Ga〇.47As 射 極蓋層;一位於該n+型摻雜I r 主僇雜inowGa^As射極蓋層上之未 摻心句且隔層;-位於該未摻雜⑷且隔層上之n+型推雜 通道層;-位於該n+型摻雜、—。油通 道層上之未推·雜InP閘極層:一^屯必 十 位於該未摻雜InP閘極層上 之n+型摻雜in() nGamAs歐姆接觸層。 較佳的’該 In〇 52Ga〇 48p 至 Tril> 1 A…v °*53Ga〇 47AS The n-type doped In0_53Ga0.47As collector layer on the second collector layer; _ m is §-type doped In〇.53Ga. · ρ + type doping in the 47As collector layer. a type A pole layer; a first undoped In.53Ga〇.47As gap layer on the p+ type doped InQ 53GaQ WAS base layer; one on the undoped 0.53 vja〇47 As gap layer An n+-type doped monoatomic layer; a second undoped In〇53Ga〇oAs interstitial layer on the n+-type doped monoatomic layer; one located in the _th, undoped In^Ga^As gap layer An n-type doped Inp emitter layer; - an n+ type 濉丄n〇.53Ga〇.47As emitter cap layer on the n-type doped InP emitter layer; and a n+ type doping I r The undoped sentence on the main doping inowGa^As emitter cap layer and the interlayer; the n+ type doping channel layer on the undoped (4) and the spacer layer; - located in the n+ type doping, -. The undoped and indium InP gate layer on the oil channel layer: an n+ type doped in() nGamAs ohmic contact layer on the undoped InP gate layer. Preferred 'The In〇52Ga 〇48p to Tril> 1 A...

InP未推雜漸變層具有一 範圍介於7500〜20000埃的厚度。 、 較佳的,該未摻雜InP層具 目六'戈一範圍介於1〇〇〇〜35()() 埃的厚度。 較佳的’該n+型摻雜Ιηα 圍介於2000〜5000埃的厚度 〜4xl019原子cm-3的摻雜。 wGao.oAs次集極層具有一範 ’及—濃度範圍為η+=1χΐ〇18The InP unhybridized graded layer has a thickness ranging from 7500 to 20,000 angstroms. Preferably, the undoped InP layer has a thickness ranging from 1 〇〇〇 to 35 () () angstroms. Preferably, the n+ type doped Ιηα is doped to a thickness of from 2,000 to 5,000 angstroms to 4xl 019 atoms cm-3. The wGao.oAs sub-collector has a range ’ and the concentration range is η+=1χΐ〇18

WamAs集極層具有一範圍 及—濃度範圍為n_=lxl〇16 較佳的’該η—型摻雜InQ $ 介於2000〜10000埃的厚度, 〜8xl016原子cm_3的摻雜。 201246533 較佳的’該摻雜! 介於500〜2000埃的厚产,〜〇47As基極層具有一範圍 叫〇19原、子cm·3的摻雜:’及〜濃度範圍為Ρ+=3χ1〇18〜 較佳的,第-未摻雜in〇.S3Ga 介於30〜200埃的厚度。 〇·4 7 As間隙層具有一範圍 較佳的’該n+型摻雜單辱古 n+=lxl〇u〜4xl〇12原子咖-2的 層具有一濃度範圍為 較佳的,該第二未摻雜In〇5: ° 圍介於30〜200埃的厚度。 間隙層具有一範 較佳的’該n型摻雜Inp射極層具 〜2000埃的厚度,及—濃度 :…於500 a i l〇 〜8x1017® 工 cm·3的摻雜》 δ ΐϋ原子 較佳的,該n+型摻雜In〇.53Ga 圍介於Π)〇〇〜5_埃的厚度, 蓋層:有-乾 〜3,、子心、摻雜。 ,農度範圍…,18 較佳的’该未摻雜Inp阻隔層 麵埃的厚度。 ,層具有-範圍介於議〜 較佳的’該η+型摻雜in Δ 介於咖〜議埃的厚度,及一濃4二通道層具有-範圍 wo、子一雜。…圍為—、 較佳的,該未摻雜Ιηρ閘極層 800埃的厚度》 /、有一耗圍介於200〜The WamAs collector layer has a range and a concentration range of n_=lxl 〇16. Preferably, the η-type doping InQ $ is between 2000 and 10000 angstroms thick, and the doping of 〜8xl016 atoms cm_3. 201246533 The preferred 'this doping! Between 500~2000 angstroms of thick production, ~ 〇47As base layer has a range of 〇19 original, sub-cm·3 doping: 'and ~ concentration range is Ρ+= 3χ1〇18~ Preferably, the first-undoped in〇.S3Ga is between 30 and 200 angstroms thick. 〇·4 7 As gap layer has a better range 'the n+ type doping single humiliation n+=lxl〇u~4xl〇12 atomic coffee-2 layer has a concentration range is preferred, the second is not Doped In〇5: ° is surrounded by a thickness of 30 to 200 angstroms. The gap layer has a preferred 'the n-type doped Inp emitter layer has a thickness of 2,000 angstroms, and the concentration: ... is doped at 500 ail 〇 ~ 8 x 1017 Ω cm · 3 δ ΐϋ ΐϋ atoms are preferred The n+ type doped In〇.53Ga is surrounded by a thickness of Π) 〇〇 5 Å, and the cap layer: has - dry ~ 3, the center of the core, doping. , agronomic range..., 18 preferred 'the thickness of the undoped Inp barrier layer. The layer has a range of from - to - preferably 'the n + type doping in Δ is between the thickness of the coffee and the angstrom, and the one thick and two of the two channel layers have a range of wo, a sub-hetero. The circumference is -, preferably, the thickness of the undoped Ιηρ gate layer is 800 angstroms /, and the consumption is between 200~

較佳的,該η +型摻雜丨 G r . _47As歐姆接觸層具有一 fe圍介於200〜500埃的厚度,及一、曲 ,辰度範圍為n + = 3xl〇i8 8 .201246533 〜3xl〇19原子 em的摻雜。 【實施方式.】 本發明係以石申化嫁為基底製作高性能的碳化钢/坤化 銦嫁(InP/InGaAs)變晶性積體化雙極場效電晶體,具有高輸 出電仙河電流增益、低補償電壓、優異高頻特性之ΪΙΒΤ :件及w輸出電流、高線性轉導、佳的熱穩定度、優異 问頻特性之FET το件。本發明之變晶性積體化雙極場效電 μ體、.。構簡易’成本低’極適於數位、類比、混模信號及 積體電路上應用。 依本發明的一較佳具體實施例所完成的變晶性積體化 雙極場效電晶體,其結構如圖一所示。本發明之變晶性積 體化雙極場效電晶體100包含有一雙極性電晶體1〇1元件 區域及一場效電晶體102元件區域。在一未摻雜GaAs半導 體基板103上依序形成一 至Inp的未掺雜漸 變層104、一未摻雜111?層1〇5、一 n+型摻雜In〇53Ga^As 次集極層106、一 η—型摻雜In〇 53Ga() 47As集極層1〇7、一 P 型摻雜 In〇.53Ga〇.47As基極層 1〇8、一 未摻雜 in〇 53Ga〇47As 間隙層109、一 n+ ’型摻雜單原子層11〇、—未摻雜 In0.53Ga〇.47As間隙層m、一 n型摻雜InP射極層112、一 η型摻雜in〇53Ga〇.47As射極蓋層113、一未摻雜Inp阻隔 層114、一 n型摻雜in〇53Ga()47As通道層(Η、一未摻雜 InP閘極層116、一 n型摻雜InmGa〇 47As歐姆接觸層117。 本發明變晶性積體化雙極場效電晶體之製作步驟依序 201246533 如下:(1)光阻蓋住該場效電晶體102元件區域,雙極性 電aa體1 〇 1元件區域以化學性餘刻從該n+型摻雜 In〇.53Ga〇.47As歐姆接觸層 117钱刻至該 n+型捧雜 Ino.^GamAs射極蓋層113上方。定義射極金屬區,蒸鍍 射極金屬AnGeNi於該n+型摻雜in^Ga^As射極蓋層 113上;(2)光阻蓋住該場效電晶體1〇2元件區域,以射極 金屬為硬遮罩(hard mask) ’蝕刻至該p+型擦雜 InmGao.oAs基極層1〇8上方;(3)光阻蓋住該場效電晶體 102元件區域,蝕刻至該n+型摻雜InG53Ga〇47As次集極層 106上方,(4)足義該場效電晶體1〇2元件區域之没源極金 屬區’同時蒸鍍集極、汲源極金屬AuGeNi,並以高溫短時 間燒結(sintering),使金屬浸入,以完成集極與汲源極之歐 姆接觸;(5)光阻蓋住該場效電晶體1〇2元件區域,鍍上 AuZn金屬於該p +型摻雜Jn。53Ga〇 〇As基極層ι〇8上方, 以做為基極層接觸電極;(6)光阻蓋住該雙極性電晶體 兀件區域,以汲源極金屬為hard mask,蝕刻至該未摻雜hp 閘極層116上方;(7)光阻蓋住該雙極性電晶體1〇1元件區 域,鍍上Au金屬於該未摻雜Inp閘極層丨丨6上方,以做為 閘極接觸電極;(8)進行雙極性電晶體1〇1與場效電晶體 間之元件隔離(mesa)餘刻。 為使本發明更易瞭解及實施,請參見以下實施例說明: 於此實施例中,該1n^GaowP至InP的未摻雜漸變 層1〇4’厚度為15000A;該未摻雜Inp層1〇5,厚度為15〇〇釔 該η型摻雜inQ 53Ga() 47As次集極層ι〇6,厚度為乃〇〇及, 10 201246533 濃度為1 χ 1019原子cm·3 ;該n-刑 i 推雜 In〇.53Ga〇.47As 集極 層107,厚度為5000A,濃庶Α 9 1λ16 , 辰度為2 χ ι〇ΐ6原子cm-3 ;該ρ+ 型摻雜 In〇.53Ga〇.47As 基極層 1 r — t β 增108,厚度為1000Α,濃度為1 x 1 〇19原子cm·3 ;該未摻雜τ„ ^ ν 雜 In〇.53Ga0.47As 間隙層 1〇9,厚 度為50A;該n+型摻雜單原子層"〇;濃度為2 χ ι〇ι2原 子cm·2;該未摻雜In〇‘53Ga〇47As間隙層iu,厚度為5〇心 該η型掺雜InP射㈣112,厚度為1〇〇〇A,濃度&5x1〇17 原子cm·3 ;該n+型摻雜In〇 53Ga〇 47As射極蓋層ιΐ3,厚度 為3000a’濃度為1 x 10i9原子cm.3 ;該未推雜阻隔層 114’厚度為20001該n+型摻雜In〇53Ga〇 47As通道層115, 厚度為150A,濃度為3 x 1〇18原子cm_3;該未摻雜inp閘 極層116,厚度為300A;該n+型摻雜In()53GaQ47As歐姆接 觸層117 ’厚度為300A,濃度為1 χ i〇i9 cm·3。該雙極性 電晶體101射極尺度為50x50 μηι2 ;該場效電晶體1〇2閘 極尺度與沒源極間隙(spacing)分別為1 χ 70 μιη2及3 μηι。 本發明變晶性積體化雙極場效電晶體中之雙極性電晶 體101係蝕刻去除該積體化結構上面4層材料後層而形 成。圖二為本發明實施例之雙極性電晶體丨〇丨於熱平衡時 的1帶圖此能帶圖包含鱗化鋼録至鱗化姻變晶性緩衝 層。圖三為本發明實施例之雙極性電晶體1 〇 1於熱平衡時 的放大能帶圖。明顯地,基-射極(Β-Ε)接面之位障尖峰 (potential spike)可完全消除,此因在該第一未摻雜 In〇.53Ga〇.47As 間隙層 1〇9 與該第二未摻雜 In0.53Ga〇.47As 間 隙層111中加入—高濃度n+型摻雜單原子層11〇,可使射 11 201246533 極側之能帶拉低,進而消除位障尖峰及降低集-射(c—幻極 之補償電壓(offset voltage)。 圖四為本發明實施例之雙極性電晶體1 〇丨的三端電流_ 電壓(ι-ν)特性曲線圖。其最大電流約為13mA,當基極電 流Ib = 5 μΑ時,集-射極補償電壓約為1〇5 mV。由於Β·Ε 接面之位障尖峰被該η+型摻雜單原子層丨1〇有效降低,故 有低的集-射極補償電壓。 圖五為本發明實施例之雙極性電晶體1〇1於基集極電 壓為零時的Gummel圖。明顯地,當集極電流Ic = 1 μΑ時, 其Β-Ε極導通電壓(turn_on v〇ltage)為〇 4V,此低的導通電 壓*Τ有效降低元件的操作電壓及集-射極補償電壓’極適於 低功率消耗之電路應用,值得注意是,當Vbe電壓為〇31v 時,其電流增益已達一。由於基極層為小能隙的 hmGamAs材質,有助於降低Β_Ε驅動電壓νΒΕ。圖中 亦可看出’該元件的集極電流理想因子(ideality fact〇r)〜 於低電流時幾乎等於卜此表示電子傳輸經過B_E接面由 擴散機制所支配,且B-E接面之位障尖峰應已被所加之該 η型摻雜單原子層11 〇消除。此外,該基極電流理想因子 〜於 0.2V < VBE < 〇.4V 與 0.4V < VBE < 0.6V 時分別為 2.09 與1.94 ’此表示基極電流幾由復合機制所支配。圖六為本 發明實施例之雙極性電晶體1〇1於基_集極電壓為零時的電 流增益對集極電流關係圖。當集極電流1 μΑ與1mA時,其 增益已達7與132 ’而最大電流增益為255。此大的電流增 日 |人| 疋因InP/IriQ 53GaQ 47八8異質接面有大的價電帶不連續 12 201246533 值 能有效侷限電洞從基極注入至射極 晶體中之場效 厚度薄且濃度 關於本發明變晶性積體化雙極場效電 電晶體102,該通道為in〇 53Ga〇 47As材質, 高,又該通道電子可被大能隙的未擦# Inp間㈣ιΐ6與 未摻雜InP阻隔層114所偈限。圖七為本發明實施例之場 效電晶體!G2於熱平衡時的能帶圖。熱平衡時摻雜通道部 分被空乏,故本發明實施例之場效電晶體為空乏式。由於 InP/In^Ga^As有佳的蝕刻選擇比,閘極金屬易於控制 沉積於未#雜InP閉極層116上,而其 異質接面之導電帶不連續值AEc約為〇.25 ,此將提供 相當的能障以避免通道電子進入閘極且增加閘極順向操 作電壓。此外,因熱平衡時在Ιη〇 53GaQ 47AS應力摻雜通道 量子井内已形成有miniband及二維電子雲氣(2dEG),因 此摻雜通道的有效濃度可將增加,以降低通道電阻值。 圖八為本發明實施例之場效電晶體i 〇 2的三端電流_ 電壓特性曲線圖。在此空乏式元件中,當閘_源極電壓為零 時沒-源極飽和電壓(saturation voltage)僅為〇.2 V,此 saturation voltage較過去推雜通道場效電晶體(DCFETs)為 甚低。當閘極電壓加至+1.25V時,閘極漏電流仍不大。當 閘極電壓為正時,空乏區將縮至上層摻雜通道,且Preferably, the η + -type doped 丨G r . _47As ohmic contact layer has a thickness of 200 to 500 angstroms, and a range of curvatures, and a range of n + = 3xl 〇 i8 8 . 201246533 〜 3xl〇19 atomic em doping. [Embodiment.] The present invention is a high-performance carbonized steel/indium/indium-doped (InP/InGaAs) crystallized integrated bipolar field effect transistor with a high-output electric fairy river. Current gain, low compensation voltage, excellent high-frequency characteristics: FET τ ο οf οf The crystallized integrated bipolar field effect electric body of the present invention, Simple construction 'low cost' is ideal for digital, analog, mixed-mode signals and integrated circuit applications. A crystallized integrated bipolar field effect transistor completed in accordance with a preferred embodiment of the present invention has a structure as shown in FIG. The crystallized integrated bipolar field effect transistor 100 of the present invention comprises a bipolar transistor 1〇1 element region and a field effect transistor 102 element region. An undoped graded layer 104 of Inp, an undoped 111 layer 1〇5, an n+ type doped In〇53Ga^As subcollector layer 106 are sequentially formed on an undoped GaAs semiconductor substrate 103, A η-type doped In〇53Ga() 47As collector layer 1〇7, a P-type doped In〇.53Ga〇.47As base layer 1〇8, an undoped in〇53Ga〇47As gap layer 109 , an n+ 'doped monoatomic layer 11〇, an undoped In0.53Ga〇.47As gap layer m, an n-type doped InP emitter layer 112, an n-type doping in〇53Ga〇.47As shot The cap layer 113, an undoped Inp barrier layer 114, an n-type doped in〇53Ga()47As channel layer (Η, an undoped InP gate layer 116, an n-doped InmGa〇47As ohmic contact) Layer 117. The manufacturing step of the crystallized integrated bipolar field effect transistor of the present invention is sequentially performed in 201246533 as follows: (1) The photoresist covers the element region of the field effect transistor 102, and the bipolar electric aa body 1 〇1 element The region is chemically engraved from the n+ type doped In〇.53Ga〇.47As ohmic contact layer 117 to the n+ type dopant Ino.^GamAs emitter cap layer 113. The emitter metal region is defined, and the evaporation is performed. Emitter metal AnGeNi n + type doping in ^ Ga ^ As emitter cap layer 113; (2) photoresist to cover the field effect transistor 1 〇 2 element area, with the emitter metal as a hard mask 'etched to the The p+ type is infused with the InmGao.oAs base layer 1〇8; (3) the photoresist covers the element field of the field effect transistor 102, and is etched to the n+ type doped InG53Ga〇47As subcollector layer 106, (4) ) The field source has no source metal region in the 1〇2 element region. At the same time, the collector and the bismuth source metal AuGeNi are vapor-deposited, and sintering is performed at a high temperature for a short time to immerse the metal to complete the concentrator. Ohmic contact with the source of the erbium; (5) the photoresist covers the area of the 〇2 element of the field effect transistor, and is plated with AuZn metal on the p + type doped Jn. Above the 53Ga 〇〇 As base layer ι 8 (6) the photoresist covers the bipolar transistor element region, and the source metal is used as a hard mask, and is etched onto the undoped hp gate layer 116; (7) The photoresist covers the area of the bipolar transistor 1〇1 element, and is plated with Au metal over the undoped Inp gate layer 丨丨6 to serve as a gate contact electrode; (8) for double The element isolation (mesa) between the transistor 1〇1 and the field effect transistor. To make the invention easier to understand and implement, please refer to the following examples: In this embodiment, the 1n^GaowP to InP The undoped graded layer 1〇4' has a thickness of 15000A; the undoped Inp layer 1〇5 has a thickness of 15〇〇钇, and the n-type doped inQ 53Ga() 47As secondary collector layer ι〇6 has a thickness of 〇〇和, 10 201246533 The concentration is 1 χ 1019 atom cm·3; the n- penalty i 杂In〇.53Ga〇.47As collector layer 107, thickness 5000A, concentrated 1 9 1λ16, and the degree is 2 χ 〇ΐ6 atoms cm-3; the ρ+ type doped In〇.53Ga〇.47As base layer 1 r — t β is increased by 108, the thickness is 1000Α, and the concentration is 1 x 1 〇19 atoms cm·3; Doping τ„^ ν 〇In〇.53Ga0.47As gap layer 1〇9, thickness 50A; the n+ type doped monoatomic layer"〇; concentration is 2 χ ι〇ι2 atom cm·2; a hetero-In''53Ga〇47As interstitial layer iu, a thickness of 5 〇, the n-type doped InP shot (four) 112, a thickness of 1 〇〇〇A, a concentration & 5x1〇17 atom cm·3; the n+ type doped In 〇53Ga〇47As emitter cover ιΐ3, thickness 3000a The concentration is 1 x 10i9 atoms cm.3; the thickness of the undoped barrier layer 114' is 20001, the n+ type doped In〇53Ga〇47As channel layer 115 has a thickness of 150 A and a concentration of 3 x 1 〇 18 atoms cm_3; The undoped inp gate layer 116 has a thickness of 300 A; the n+ type doped In() 53GaQ47As ohmic contact layer 117' has a thickness of 300 A and a concentration of 1 χ i〇i9 cm·3. The bipolar transistor 101 has an emitter scale of 50 x 50 μηι 2 ; the field-effect transistor has a gate-scale and a source-less spacing of 1 χ 70 μιη 2 and 3 μηι, respectively. The bipolar electromorph 101 in the crystallized integrated bipolar field effect transistor of the present invention is formed by etching away the four layers of the upper layer of the integrated structure. Figure 2 is a band diagram of a bipolar transistor in thermal equilibrium according to an embodiment of the present invention. The energy band diagram includes a scaled steel recorded to a scalar crystallized buffer layer. Fig. 3 is an enlarged energy band diagram of the bipolar transistor 1 〇 1 in thermal equilibrium according to an embodiment of the present invention. Obviously, the potential spike of the base-electrode (Β-Ε) junction can be completely eliminated, because the first undoped In.53Ga〇.47As gap layer 1〇9 and the first The addition of a high-concentration n+-doped monoatomic layer 11〇 to the undoped In0.53Ga〇.47As gap layer 111 can lower the energy band of the emitter of 2012201233, thereby eliminating the barrier peaks and reducing the set- Fig. 4 is a three-terminal current_voltage (ι-ν) characteristic curve of the bipolar transistor 1 为本 according to an embodiment of the present invention. The maximum current is about 13 mA. When the base current Ib = 5 μΑ, the collector-emitter compensation voltage is about 1〇5 mV. Since the barrier peak of the Β·Ε junction is effectively reduced by the η+ type doped monoatomic layer 丨1〇, Therefore, there is a low set-emitter compensation voltage. Figure 5 is a Gummel diagram of the bipolar transistor 1〇1 when the base collector voltage is zero. Obviously, when the collector current Ic = 1 μΑ , its turn-on voltage (turn_on v〇ltage) is 〇4V, this low turn-on voltage*Τ effectively reduces the operating voltage of the component and the set-emitter compensation The voltage is very suitable for low power consumption circuit applications. It is worth noting that when the Vbe voltage is 〇31v, its current gain has reached one. Since the base layer is a small energy gap hmGamAs material, it helps to reduce the Β_Ε driving voltage. νΒΕ. It can also be seen that the 'ideality fact〇r of the element is almost equal to the low current. This means that the electron transmission is dominated by the diffusion mechanism through the B_E junction, and the BE junction The barrier peak should have been removed by the added n-doped monoatomic layer 11. In addition, the base current ideal factor is ~0.2V < VBE < V.4V and 0.4V < VBE < 0.6V The time is 2.09 and 1.94 respectively. This means that the base current is dominated by the composite mechanism. Figure 6 is the current gain versus collector current of the bipolar transistor 1〇1 when the base_collector voltage is zero. Diagram. When the collector current is 1 μΑ and 1 mA, the gain has reached 7 and 132 ′ and the maximum current gain is 255. This large current increase is daily | 人 | InP/IriQ 53GaQ 47 8 8 Heterojunction Large price band is not continuous 12 201246533 value can effectively limit electricity The thickness of the field effect injected from the base into the emitter crystal is thin and the concentration is about the crystallized integrated bipolar field effect transistor 102 of the present invention. The channel is made of in〇53Ga〇47As, which is high in the channel. It is limited by the unfilled #Inp(4) ιΐ6 and the undoped InP barrier layer 114. Figure 7 is a field effect transistor of an embodiment of the present invention! Band diagram of G2 at thermal equilibrium. The doped channel portion is depleted during heat balance, so the field effect transistor of the embodiment of the present invention is depleted. Since the InP/In^Ga^As has a good etching selectivity, the gate metal is easily controlled to be deposited on the #Pon InP closed layer 116, and the discontinuous value AEC of the heterojunction is about 〇.25. This will provide a comparable energy barrier to prevent channel electrons from entering the gate and increasing the gate forward operating voltage. In addition, due to thermal equilibrium, miniband and two-dimensional electron gas (2dEG) have been formed in the Ιη〇 53GaQ 47AS stress-doped channel quantum well, so the effective concentration of the doped channel can be increased to reduce the channel resistance. FIG. 8 is a graph showing the three-terminal current_voltage characteristic of the field effect transistor i 〇 2 according to the embodiment of the present invention. In this depletion element, when the gate-source voltage is zero, the non-source saturation voltage is only 〇.2 V, which is higher than the past-passive channel field effect transistors (DCFETs). low. When the gate voltage is applied to +1.25V, the gate leakage current is still small. When the gate voltage is positive, the depletion region will shrink to the upper doped channel, and

InmGao.qAs通道内之2DEG載子將隨閘極電壓調變而增 加’使摻雜通道内的有效濃度亦增加,線性區之電流將快 速上升。且源(汲)極至閘極之間隙距離僅為1 μπ1,其間隙 距離之寄生電阻相當低(因通道濃度高),源-汲極飽和電壓 13 201246533 可有效地降低,因此適於訊號放大之源-汲極操作電壓範圍 較為寬廣。 圖九為本發明實施例之場效電晶體102當vDS = +2.5 V 時外質轉導(extrinsic transconductance)與飽和電流 密度(saturation current density)對於閘極電壓的關係圖。 其臨界電壓(threshold voltage)約為-0.6 V。寬廣的閘極電 壓擺幅(swing)可從VGS = -0.6V至+1.25 V,此大的閘極 電壓擺幅可降低third-harmonic distortion且可應用於線性 及大訊號放大器。最大外質轉導為265 mS/mm,且最大飽 和電流密度為281mA/mm。此外,於-0.3V < VGS < 0.4 V 間其飽和電流隨閘極電壓增加两線性呈現增加,這是因通 道為重摻雜且很薄。 雖然本發明己利用上述實施例說明,但是本發明並不 被所揭露的實施例所限制,熟悉本項技藝之人士仍可作出 不脫離本發明範圍之修飾及變化。 【圖式簡單說明】 圖一係本發明實施例之變晶性積體化雙極場效電晶體 結構示意圖。 圖二係.本發明實施例之雙極性電晶體於熱平衡時的能 帶圖。 圖三係本發明實施例之雙極性電晶體於熱平衡時的放 大能帶圖。 圖四係本發明實施例之雙極性電晶體的三端電流-電 14 201246533 - 壓特性曲線圖。 圖五係本發明實施例之雙極性電晶體於基-集極電壓 為零時的Gupimel圖。 圖六係本發明實施例之雙極性電晶體於基·集極電壓 為零時的電流增益對集極電流關係圖。 圖七係本發明實施例之場效電晶體於熱平衡時的能帶 圖。 圖八係本發明實施例之場效電晶體的三端電流_電壓 特性曲線圖。 圖九係本發明實施例之場效電晶體的外質轉導與飽和 電流密度對於開極電壓的關係圖。 【主要元件符號說明】 1 00變晶性積體化雙極場效電晶體 101雙極性電晶體 1 0 2場效電晶體 1 03未摻雜GaAs半導體基板 104In(K52Ga() 48P至化?的未摻雜漸變層 105未摻雜InP層 η型摻雜In〇.53GaG.47As次集極層 11 型摻雜 In〇_53Ga〇.47As 集極層 型摻雜In〇.53Ga〇.4 7As基極層 109第一未摻雜In〇 53Ga〇 47as間隙層 110 η型摻雜單原子層The 2DEG carrier in the InmGao.qAs channel will increase with the gate voltage modulation, and the effective concentration in the doped channel will also increase, and the current in the linear region will rise rapidly. The distance between the source (汲) and the gate is only 1 μπ1, and the parasitic resistance of the gap distance is relatively low (due to the high channel concentration). The source-drain saturation voltage 13 201246533 can be effectively reduced, so it is suitable for signal amplification. The source-bungee operating voltage range is relatively wide. Figure 9 is a graph showing the relationship between extrinsic transconductance and saturation current density for gate voltage when the field effect transistor 102 of the embodiment of the present invention is vDS = +2.5 V. Its threshold voltage is about -0.6 V. The wide gate voltage swing can range from VGS = -0.6V to +1.25 V. This large gate voltage swing reduces third-harmonic distortion and can be applied to both linear and large signal amplifiers. The maximum external mass transfer is 265 mS/mm and the maximum saturation current density is 281 mA/mm. In addition, the saturation current increases linearly with the increase of the gate voltage between -0.3V < VGS < 0.4 V because the channel is heavily doped and very thin. While the present invention has been described by the foregoing embodiments, the invention is not limited by the scope of the invention, and those skilled in the art can make modifications and variations without departing from the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing the structure of a crystallized integrated bipolar field effect transistor according to an embodiment of the present invention. Fig. 2 is a diagram showing the energy band of the bipolar transistor of the embodiment of the present invention in thermal equilibrium. Fig. 3 is an enlarged energy band diagram of the bipolar transistor of the embodiment of the present invention in thermal equilibrium. Figure 4 is a graph showing the three-terminal current-electricity of the bipolar transistor of the embodiment of the present invention. Figure 5 is a Gupimel diagram of a bipolar transistor of the embodiment of the invention with a base-collector voltage of zero. Fig. 6 is a graph showing the relationship between the current gain and the collector current of the bipolar transistor of the embodiment of the present invention when the base and collector voltages are zero. Figure 7 is an energy band diagram of the field effect transistor of the embodiment of the present invention in thermal equilibrium. Figure 8 is a graph showing the three-terminal current-voltage characteristic of the field effect transistor of the embodiment of the present invention. Figure 9 is a graph showing the relationship between the external mass transfer and the saturation current density of the field effect transistor of the embodiment of the present invention. [Major component symbol description] 100 00 crystallized integrated bipolar field effect transistor 101 bipolar transistor 1 0 2 field effect transistor 01 03 undoped GaAs semiconductor substrate 104In (K52Ga() 48P to ? Undoped graded layer 105 undoped InP layer n-type doped In〇.53GaG.47As secondary collector layer type 11 doped In〇_53Ga〇.47As collector layer doped In〇.53Ga〇.4 7As Base layer 109 first undoped In〇53Ga〇47as gap layer 110 n-type doped monoatomic layer

S 15 201246533 111第二未摻雜In〇.53Ga〇.47As間隙層 112η型摻雜InP射極層 113 n+型掺雜In〇.53Ga〇.47As射極蓋層 114未摻雜InP阻隔層 115 n+麼摻雜In〇 53Ga〇.4?As通道層 116未摻雜InP閘極層 117 n+型摻雜In〇.53Ga〇.47As歐姆接觸層 16S 15 201246533 111 second undoped In〇.53Ga〇.47As gap layer 112 n-type doped InP emitter layer 113 n+ type doped In〇.53Ga〇.47As emitter cap layer 114 undoped InP barrier layer 115 n+? doped In〇53Ga〇.4? As channel layer 116 undoped InP gate layer 117 n+ type doped In〇.53Ga〇.47As ohmic contact layer 16

Claims (1)

201246533 七、申請專利範圍: 1. 一種變晶性積體化雙極場效電晶體,包含:— 木得雜 GaAs半導體基板;一位於該未摻雜GaAs半導體基板上 之Ino.nGao·48?至Inp未摻雜漸變層;—位於1 In〇_52Ga〇_48P至InP未摻雜漸變層上之未摻雜層一 位於該未摻雜InP層上之n+型摻雜InQ 5山心〇As次集極 層;一位於該n+型摻雜次集極層上^之' 型摻雜InG.53GaG.47As集極層;一位於該γ型摻雜 In0.53GaQ.47As 集極層上之 ρ+型摻雜 InG53Gaa 層;一位於該〆型摻雜In〇oh基極層上之第二未 推雜In〇.53Ga〇.47AS @隙層;一位於該未推雜 In〇.53Ga().47As間隙層上之n+型摻雜單原子層;一位於$ n+型接雜單原子層上之第二未摻雜W“7As„ 層;-位於該第二未摻雜In。5而。“s間隙層上之型 推雜InP射極層;一位於該n #推雜inp射極層上之γ 型摻雜In。為.47As射極蓋層;一位於該^型摻雜 k^Ga^As射極蓋層上之未摻雜inp阻隔層·一位於 該未掺雜W阻隔層上之n +型摻雜111〇 53叫油通道 層位於該n型摻雜In〇_53Ga〇47As通道層上之未接雜 W閘極層;—位於該未摻雜Inp閘極層上< ^型推雜 In0_53Ga0 47As歐姆接觸層。 2.如申請專利範圍第1項之變晶性積體化雙極場效電晶 、中i In0.52Ga0.48P至inp未摻雜漸變層具有一範圍 S 17 201246533 介於7500〜20000埃的厚度。 3.如申請專利範圍第1 夕μ s 弗項之變晶性積體化雙極場效電晶 體,其中該未搂雜InP層真古 ^ . 席具有一範圍介於1000〜3500埃 的厚度。 4_如申請專利範圍第1頊夕綴^ a 項之變日日性積體化雙極場效電晶 體’其_該n+型摻雜r ., 雜oh次集極層具有一範圍 介於2000〜5000埃的厘麻 Λ 爷的厚度,及一濃度範圍為η+=1χ1〇18 〜4x1019原子cm·3的摻雜。 5.如申請專利範圍第1項之變晶性積體化雙極場效電晶 體八中°亥η型摻雜In〇.53Ga〇.47As集極層具有一範圍介 於2000〜10000埃的厚度,及一濃度範圍為n-=lxlol6〜 8xl016原子cm_3的摻雜。 6·如申請專利範圍第1 不1項之變晶性積體化雙極場效電晶 體,其中該ρ +型摻雜 ” 〇53Ga〇_47As基極層具有一範圍介 於500〜2000埃的厘痒 的厚度’及一濃度範圍為ρ+=3χ1〇18〜 4xl〇19原子cm·3的摻雜。 7.如申請專利範圍第〗 第1項之變晶性積體化雙極場效電晶 體,其中该第一未摻雜 ^ 〇 53Ga0_47As間隙層具有一猫圚 介於30〜200埃的厚度。 18 201246533 8. 如申請專利筋圍M s _ 第1項之變晶性積體化雙極場效電晶 八中該η型摻雜單原子層具有一濃度範圍為 n+=lxl〇12 〜4χ1〇12 原子 cm-2 的摻雜。 9. 如申請專利範圍第 乐1 2項之變晶性積體化雙極場效電晶 體,3亥第二未推雜& p 雅ino.uGao.oAs間隙層具有一範圍介於 30〜200埃的厚度。 10.如申晴專利範圍第1谓之鐵曰^ 士 A 乐1項之變晶性積體化雙極場效電晶 體’其中該η型摻雜 修雜InP射極層具有一範圍介於5〇〇〜 2000埃的厚度,及一嚿 /晨度範圍為n=lxl〇17〜8χ1〇17原子 cm_3的摻雜。 申月專利la圍帛1項之變晶性積體化雙極場效電晶 體”中該η型摻雜In〇53Ga〇.47As射極蓋層具有一範圍 介於 1000〜5〇〇〇 λλ, m ^ 埃的厚度’及一濃度範圍為η+=3χ1018 〜3xl019原子cm-3的摻雜。 1 2.如申請專利範圍第 體,其中該未摻雜 5000埃的厚度。 13 _如申請專利範圍第 1項之變晶性積體化雙極場效電晶 £ 19 1 項之變晶性積體化雙極場效電晶 2 InI>阻隔層具有一範圍介於1000〜 201246533 體,其中該n+型掺雜In〇.53Ga〇.47As通道層具有一範圍介 於100〜800埃的厚度,及一濃度範圍為η+=1χ1018〜 5xl018原子(;1^3的摻雜。 14. 如申請專利範圍第1項之變晶性積體化雙極場效電晶 體,其中該未摻雜InP閘極層具有一範圍介於200〜800 埃的厚度。 15. 如申請專利範圍第1項之變晶性積體化雙極場效電晶 體,其中該η+型摻雜In〇.53Ga〇.47As歐姆接觸層具有一範 圍介於200〜500埃的厚度,及一濃度範圍為n+=3 χΙΟ18 〜3xl019原子cm_3的摻雜。 20201246533 VII. Patent application scope: 1. A crystallized integrated bipolar field effect transistor, comprising: - a wood-doped GaAs semiconductor substrate; and an Ino.nGao·48 on the undoped GaAs semiconductor substrate? To Inp undoped graded layer; - undoped layer on 1 In〇_52Ga〇_48P to InP undoped graded layer - n+ type doped InQ 5 mountain core on the undoped InP layer As sub-collector; a 'type-doped InG.53GaG.47As collector layer on the n+-type doped collector layer; one on the γ-doped In0.53GaQ.47As collector layer a ρ+-doped InG53Gaa layer; a second undoped In〇.53Ga〇.47AS @gap layer on the 〆-type doped In〇oh base layer; one located in the undoped In〇.53Ga ( An n+ type doped monoatomic layer on the .47As gap layer; a second undoped W "7As" layer on the $n+ type doped monoatomic layer; - located in the second undoped In. 5 and. "The type of erbium InP emitter layer on the s gap layer; a gamma-type doped In on the n # 推p inp emitter layer. The .47As emitter cap layer; one is located in the ^ type doping k^ An undoped inp barrier layer on the Ga^As emitter cap layer. An n+ type doping 111〇53 on the undoped W barrier layer is called the oil channel layer at the n-type doped In〇_53Ga〇. The unconnected W gate layer on the 47As channel layer; - on the undoped Inp gate layer < ^ type push-in In0_53Ga0 47As ohmic contact layer. 2. The crystallized product as in claim 1 The body of the bipolar field effect transistor, the medium i In0.52Ga0.48P to inp undoped graded layer has a range of S 17 201246533 between 7500 and 20000 angstroms. 3. As claimed in the first day of the s The variable crystallized integrated bipolar field effect transistor, wherein the undoped InP layer has a thickness ranging from 1000 to 3500 angstroms. 4_ as claimed in the first semester ^ a variable of the daily integrated bipolar field effect transistor 'the _ the n + type doping r., the hetero oh subcollector layer has a thickness ranging from 2000 to 5000 angstroms ,and The concentration range is η+=1χ1〇18 ~4x1019 atomic cm·3 doping. 5. The crystallized integrated bipolar field effect transistor of the first item of claim 1 is zhonghe η-type doped In The 53.53Ga〇.47As collector layer has a thickness ranging from 2000 to 10000 angstroms, and a concentration ranging from n-=lxlol6 to 8xl016 atoms cm_3. 6·If the patent application scope is No. 1 A crystallized integrated bipolar field effect transistor, wherein the ρ + -type doped 〇53Ga〇_47As base layer has a thickness of itch of 500~2000 angstroms and a concentration range of ρ +=3χ1〇18~ 4xl〇19 atomic cm·3 doping. 7. The crystallized integrated bipolar field effect transistor of claim 1, wherein the first undoped 〇53Ga0_47As interstitial layer has a thickness of between 30 and 200 angstroms. 18 201246533 8. The n-type doped monoatomic layer has a concentration range of n+=lxl〇12 〜4χ1 in the case of the patented ribbed M s _ 1 Doping of 〇12 atoms cm-2. 9. For example, if you apply for the patented range of Le 12, the crystallized integrated bipolar field effect transistor, 3 hai second undoped & p ya ino.uGao.oAs gap layer has a range of 30~ 200 angstroms in thickness. 10. For example, Shen Qing's patent scope is called the 曰 曰 ^ 士 A 乐 1 variable crystallized integrated bipolar field effect transistor 'where the η-type doped InP emitter layer has a range 5 〇〇 ~ 2000 angstroms of thickness, and a 嚿 / morning range of n = lxl 〇 17 ~ 8 χ 1 〇 17 atoms cm_3 doping. The n-type doped In〇53Ga〇.47As emitter cap layer has a range of 1000~5〇〇〇λλ in the variable crystallized integrated bipolar field effect transistor of Shenyue patent la 帛1 , m ^ angstrom thickness 'and a concentration range of η + = 3 χ 1018 ~ 3 x l019 atom cm -3 doping. 1 2. As claimed in the scope of the body, wherein the undoped 5000 angstrom thickness. 13 _ apply The variable crystallized integrated bipolar field effect electro-crystal of the first item of the patent range is £19, and the variable-crystalline integrated bipolar field effect electro-crystal 2 InI> barrier layer has a range of 1000~201246533, The n+ type doped In〇.53Ga〇.47As channel layer has a thickness ranging from 100 to 800 angstroms, and a concentration range of η+=1χ1018~5xl018 atoms (1^3 doping. The crystallized integrated bipolar field effect transistor of claim 1, wherein the undoped InP gate layer has a thickness ranging from 200 to 800 angstroms. The variable crystallized integrated bipolar field effect transistor, wherein the η+ type doped In〇.53Ga〇.47As ohmic contact layer has a range of 200 a thickness of ~500 angstroms, and a concentration range of n+=3 χΙΟ18 〜3xl019 atoms cm_3 doping.
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