TWI424565B - Semiconductor device - Google Patents

Description

Semiconductor component

This invention relates to a semiconductor component, and more particularly to a high speed component based on gallium arsenide.

Monolithic Microwave Integrated Circuit (MMIC) is generally composed of a compound semiconductor-based high-electron Mobility Transistor (HEMT), and mainly uses indium gallium arsenide as the main channel. Material. The indium gallium arsenide quantum wells have a carrier-binding ability (confinement and electron refinement capacity), which are important performance characteristics such as linear operation and breakdown voltage. Therefore, they seek high-speed conduction and high carrier binding ability. The channel structure is a major issue facing the industry.

At present, conventional techniques have been proposed to use a nitrogen-doped indium gallium arsenide (InGaAsN) quaternary compound structure as a channel material. The heterostructure junction of indium gallium arsenide and gallium arsenide has a high discontinuous energy level of the conduction band, which can form a deep quantum well on the junction surface and increase the limitation of the conductive carrier. Under high temperature operation, the sub-pole does not easily jump out of the quantum well to form leakage current, thereby improving component characteristics.

However, because of the growth of indium gallium arsenide, it is limited to certain specific low temperature conditions, and leads to poor epitaxial quality and severely reduces carrier conductivity. Therefore, there is a need to provide a high-speed electron-moving transistor having a channel structure with high-speed conduction and high carrier-binding capability to effectively improve operational characteristics such as element linearity and component leakage current.

In view of the above, one of the objects of the present invention is to provide a semiconductor device comprising: a semiconductor substrate, an indium aluminum arsenide (InAlAsSb) buffer layer, an indium aluminum arsenide (InAlAsSb) buffer layer, and a germanium doped layer. a hetero-indium gallium arsenide channel layer, a first insulating layer, a first delta-doped carrier supply layer, a germanium indium arsenide gate Schottky contact layer, and a germanium/source ohmic contact layer. A germanium indium arsenide buffer layer is disposed on the semiconductor substrate. The indium gallium arsenide channel layer is located on the buffer layer of indium arsenide aluminum; wherein the germanium doping ratio is substantially less than 5%, and the indium gallium arsenide channel layer has a bicomponent composition that exhibits a symmetric linear change (InxGa1- Doping design of xAs1-ySby). The first insulation layer is on the channel layer. The first delta-doped carrier supply layer is on the isolation layer. The indium arsenide aluminum gate Schottky contact layer is on the delta-doped carrier supply layer. The 汲/source ohmic contact layer is on the germanium indium arsenide gate Schottky contact layer.

In an embodiment of the invention, the semiconductor substrate and the indium aluminum arsenide buffer layer comprise a crystal-transparent buffer layer.

In one embodiment of the invention, a germanium arsenide aluminum gate Schottky contact layer and the germanium/source ohmic contact layer comprise a selective etch stop layer.

In one embodiment of the invention, the germanium/source ohmic contact layer comprises a cap layer.

In an embodiment of the invention, the material constituting the 汲/source ohmic contact layer may be selected from the group consisting of highly doped gallium arsenide, indium phosphide, indium gallium arsenide, aluminum gallium arsenide, and any combination thereof. One of the groups that make up.

In an embodiment of the invention, the semiconductor device further comprises a germanium/source plate on the germanium/source ohmic contact layer, and the germanium/source plate is a multilayer alloy of gold/nickel/gold/silver Composed of.

In an embodiment of the invention, the semiconductor device further includes a gate plate on the germanium indium arsenide gate Schottky contact layer, and the gate plate is made of nickel, gold, white or any combination thereof. composition.

In one embodiment of the invention, between the indium antimonide arsenide buffer layer and the indium gallium arsenide channel layer, a second delta-doped carrier supply layer and a second isolation layer are included.

In an embodiment of the invention, the first δ-doped carrier supply layer and the second δ-doped carrier supply layer respectively have a substantial thickness of between 1×10 ¹² cm ⁻² and 5×10 ¹² cm ^{− The} amount of bismuth (Si) doping between ² .

In one embodiment of the invention, the semiconductor component is a heterostructure field effect transistor having a Metal-Organic Chemical Vapor Deposition (MOCVD) or a Molecular Beam Epitaxy (Molecular Beam Epitaxy). MBE) The grown semiconductor epitaxial structure.

According to the above embodiment, the present invention provides a high electron mobility transistor having a high Schottky barrier and a dilute channel (InxGa1-xAs1-ySby) in which the indium and bismuth compositions are symmetrically linearly changed. By adding a trace amount of cerium doping, it acts as a layer surfactant to effectively increase the discontinuous barrier height of the conductive strip. Combined with the design of the V-type change of the two components of bismuth and indium, it has the advantages of improving the carrier binding force, conduction characteristics, high linear gain, etc., which can effectively reduce the gate/substrate leakage current and improve the gate-drainage The breakdown voltage, the Power Added Efficiency (PAE), and the improved carrier transmission capability. Moreover, the kink effects are effectively reduced, thereby reducing the gate leakage current and improving the gate collapse characteristics, thereby achieving the above object.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

SUMMARY OF THE INVENTION It is an object of the present invention to provide a high electron mobility transistor having a high Schottky barrier and a symmetrical linear change of dual composition components (InxGa1-xAs1-ySby) to effectively improve component linearity and Operating characteristics such as component leakage current.

The above and other objects, features and advantages of the present invention will become more apparent and understood. as follows. The use of similar or identical component symbols is merely representative of similar or identical components and is not intended to limit the structural correspondence between the different embodiments.

Then, multiple electrical analysis of these high electron mobility transistors is performed separately. It is confirmed that high-electron mobility transistor with high Schottky barrier and dilute channel (InxGa1-xAs1-ySby) with symmetrical linear changes in dual composition can effectively reduce gate/substrate leakage current and improve The breakdown voltage between the gate and the drain, improves the power added efficiency, enhances the carrier transmission capability, and effectively reduces the knot effect.

Referring to FIG. 1A to FIG. 1C, FIG. 1A to FIG. 1C are cross-sectional views showing a process of fabricating a high electron mobility transistor 100 according to a preferred embodiment of the present invention. The high electron mobility transistor 100 is prepared by the following steps: firstly, indium aluminide arsenide (InzAl1-zAs) is grown on the gallium arsenide substrate 101 by metal organic chemical vapor deposition or molecular beam epitaxy. a crystal buffer layer 102, an indium aluminum arsenide buffer layer 103, an indium aluminum arsenide buffer layer 104, an indium arsenide buffer layer 105, a δ-doped carrier supply layer 106, an indium arsenide isolation layer 107,锑-doped yttrium-indium gallium arsenide channel layer 108, indium arsenide isolation layer 109, δ-doped carrier supply layer 110, indium arsenide aluminum gate Schottky contact layer 111, and indium gallium arsenide The semiconductor epitaxial structure of the cap layer 112 (as shown in FIG. 1A).

In some embodiments of the invention, the gallium arsenide substrate 101 is a semi-insulating gallium arsenide epitaxial layer having a lattice orientation of {100}. The thickness of the indium aluminide (InzAl1-zAs) crystal buffer layer 102 is preferably about 500 nm, and the z ratio of indium element ratio is substantially between 0 and 0.52, and varies linearly with increasing thickness. The indium arsenide (In0.52Al0.48As) buffer layer 103 preferably has a thickness of about 100 nm, and the element ratio of arsenic, indium, and aluminum is preferably 1:0.52:0.48. The indium aluminide (In0.34Al0.66As0.85Sb0.15) buffer layer 104 preferably has a thickness of about 50 nm, and the element ratio of bismuth, arsenic, indium and aluminum is preferably 0.15:0.85:0.34:0.66. The indium arsenide (In0.52Al0.48As) buffer layer 105 and the indium arsenide buffer layer 103 are made of the same material, but have a thickness of preferably 5 nm. The delta-doped carrier supply layer 106 is a gallium arsenide layer that is passed through a cerium (Si) dopant source. For example, a gallium arsenide layer which is epitaxially grown in a methane (SiH4) atmosphere is preferred. The thickness thereof is preferably 5 nm, and the doping concentration of cerium is substantially between 1 × 10 ¹² cm ^-2 and 5 × 10 ¹² cm ^-2 , preferably 1 × 10 ¹² cm ^-2 . The indium arsenide isolation layer 107 and the indium aluminide buffer layer 103 are made of the same material, and the thickness is preferably 5 nm.

The thickness of the germanium indium arsenide channel layer 108 is preferably 20 nm, and the element ratio of germanium is preferably between 0.01 and 0.02; and the element ratio of indium is preferably between 0.53 and 0.63. The elemental ratios of arsenic and gallium are complementary to the elemental ratios of bismuth and indium, respectively (the two are added together to one). The indium arsenide isolation layer 109 and the indium arsenide buffer layer 103 and the indium arsenide isolation layer 107 are made of the same material, and preferably have a thickness of 5 nm. The delta-doped carrier supply layer 110, like the delta-doped carrier supply layer 106, is also formed by a planar doping method, and the germanium-doped gallium arsenide layer is formed to have a thickness of 5 nm. The doping concentration of cerium is substantially between 1 × 10 ¹² cm ^-2 and 5 × 10 ¹² cm ^-2 , preferably 4 × 10 ¹² cm ^-2 . The indium arsenide aluminum gate Schottky contact layer 111 is an indium aluminum arsenide layer, preferably having a thickness of about 25 nm, and the element ratio of germanium, arsenic, indium and aluminum is preferably 0.15:0.85:0.34: 0.66. The indium gallium arsenide cap layer 112 has a thickness of preferably about 30 nm, and an element ratio of arsenic, indium, and gallium is preferably 1:0.53:0.47, and has an n+ doping concentration of 1 10 ¹⁹ cm ^-3 . .

More notably, the indium gallium arsenide channel layer 108 has a dual composition doping design of indium and germanium doping. Wherein the doping ratio of germanium is substantially less than 5%; and the doping ratio of indium (expressed in x) and the doping ratio of germanium (indicated by y) are determined by the center of the germanium indium gallium arsenide channel layer 108 along The thickness of the upper and lower sides is a V-shaped symmetrical linear change (InxGa1-xAs1-ySby). In the present embodiment, the doping ratio x of indium changes with the thickness from 0.53 to 0.63, and then to 0.53; the doping ratio y of ytterbium changes with thickness, and the change of presentation changes from 0.01 to 0.01. It is 0.02 and then converted to 0.01.

Next, the indium gallium arsenide cap layer 112 is subjected to a lithography process, and a solution of phosphoric acid (H3PO4), hydrogen peroxide (H2O2), and water (H2O) in a ratio of 1:1:30 is used as an etchant to remove a portion. The indium gallium arsenide cap layer 112 is formed to form at least one germanium/source ohmic contact layer 113, and a portion of the indium antimonide arsenide gate Schottky contact layer 111 is exposed (as shown in FIG. 1B) .

Metal deposition and Rapid Thermal Annealing (RTA) are then performed on the germanium/source ohmic contact layer 113 to form at least one set of germanium/source plates 114. The material of the crucible/source electrode plate 114 is preferably gold-nickel nickel/gold (AuGeNi/Au). And on the exposed Schottky contact layer 111, a metal deposition lift-off process is performed to form at least one gate plate 115, and the high electron mobility transistor 100 as shown in FIG. 1C is completed.

The gate plate 115 is a two-layer metal stack layer, preferably a stacked layer of gold/nickel (Au/Ni), thereby forming Ni/InAlAsSb with the indium arsenide aluminum gate Schottky contact layer 111. Schottky contact.

Please refer to FIG. 2. FIG. 2 is a cross-sectional view showing the structure of a high electron mobility transistor 200 according to another preferred embodiment of the present invention. The structure of the high electron mobility transistor 200 and the high electron mobility transistor 100 are similar, except that the indium arsenide arsenide cap layer 112 is not included before the germanium indium arsenide gate Schottky A selective etch stop layer 216 is formed on the contact layer 111. An indium gallium arsenide cap layer 112 (germanium/source ohmic contact layer 113) and a drain/source pad 114 are then formed on the etch stop layer 216. Further, a gate plate 115 is also formed over the etch stop layer 216. That is, the etch stop layer 216 is formed between the germanium indium arsenide gate Schottky contact layer 111 and the germanium/source ohmic contact layer 113 and the gate plate 115. In the present embodiment, the material of the etch stop layer 216 is preferably indium phosphide (InP).

Please refer to FIG. 3. FIG. 3 is a cross-sectional view showing the structure of a high electron mobility transistor 300 according to another preferred embodiment of the present invention. The structure of the high electron mobility transistor 300 and the high electron mobility transistor 200 are similar except that the gate plate 315 of the high electron mobility transistor 300 is composed of a platinum/aluminum (Au/Pt) double layer metal. The stacked layers, and through the etch stop layer 216, form a Pt/InAlAsSb Schottky contact with the germanium indium arsenide gate Schottky contact layer 111 (as shown in FIG. 3).

Thereafter, the high electron mobility transistors 100, 200, and 300 described above were electrically analyzed. Please refer to FIG. 4. FIG. 4 is a graph showing the gate-drain current-voltage (IGD-VGD) characteristic curves of the high electron mobility transistors 100, 200, and 300 under the operating conditions of 300 K.

4, the horizontal axis represents the gate-drain voltage value (VGD), and the vertical axis represents the gate-drain current amount (IGD). The inside illustration is an enlarged view of the characteristic curve of the gate-bungee forward bias. The square curve represents the high electron mobility transistor 100; the triangular curve represents the high electron mobility transistor 200; and the circular curve represents the high electron mobility transistor 300.

It can be clearly seen from Fig. 4 that the high-electron mobility transistors 100, 200, and 300 have a breakdown voltage across the gate-drain when the gate-throwth current (IGD) is equal to 1 mA/mm (Breakdown Voltage, BVGD). The turn-on voltage value (VGD) ratio (BVGD/Von) to the gate-drain is -9.7V/0.87V, -5.3V/0.71V, and -15V/1.08V, respectively. The ratio is significantly higher than the well-known high electron mobility transistor.

In addition, comparing the three high electron mobility transistors 100, 200, and 300 proposed by the embodiments of the present invention, it can be found that the BVGD/Von of the transistor 300 is obtained separately from the transistors 100 and 200, respectively. 55/24% and 183/52% have increased significantly. The Ni/InAlAsSb and Pt/InAlAsSb Schottky contacts used in the transistors 100 and 200 are shown to improve the barrier height, reduce the occurrence of leakage current of the gate device, and improve the pinch off characteristics of the device.

Please refer to FIG. 5. FIG. 5 is a diagram showing the external mass transduction obtained by the high electron mobility transistors 100, 200, and 300 under the operating conditions of a temperature of 300 K and a 汲-source voltage value (VDS) of 3V. Gain (gm) and gate-source voltage (VGS) characteristics. The horizontal axis represents the gate-source voltage value (VGS), and the vertical axis represents the element's external mass transfer gain (gm). The square curve represents the high electron mobility transistor 100; the triangular curve represents the high electron mobility transistor 200; and the circular curve represents the high electron mobility transistor 300.

It can be observed from the characteristic diagram of Fig. 5 that the high electron mobility transistors 100, 200 and 300 provided by the above embodiments all have a considerable degree of intrinsic transduction gain. However, it is worth noting that the transistor 200 has a large external mass transfer gain (real value is 304 mS) compared to the external transduction gain value of the transistor 200 (gm, max real value is 281 mS/mm). /mm), the transistor 300 has a maximum external mass transfer gain value (gm, max real value is 349 mS/mm). The main reason is that the electron mobility transistors 200 and 100 are directly contacted with the indium aluminum arsenide gate Schottky contact layer 111 by the double metal gate plate 115, thereby reducing the distance between the gate and the channel. Improve the modulation function of the gate, thereby increasing the concentration of the two-dimensional electron cloud.

Please refer to FIG. 6. FIG. 6 is a diagram showing the essential voltage gain (AV), the external mass transfer gain (gm), and the output of the high electron mobility transistors 100, 200, and 300 under the operating conditions of 300 K. Characteristic curve of conductance (gd). The horizontal axis represents the 汲-source voltage value (VDS), and the vertical axis represents the element's external mass transfer gain (gm), output conductance (gd), and essential voltage gain (AV), respectively. The square curve represents the high electron mobility transistor 100; the triangular curve represents the high electron mobility transistor 200; and the circular curve represents the high electron mobility transistor 300. Wherein, the conductance (gd) is the reciprocal of the output resistance r0, and the essential voltage gain (AV) can be derived from the external mass transfer gain (gm) and the output conductance (gd), as follows:

It can be observed from Fig. 6 that under high voltage operation, the output conductance (gd) is not stepped up and down due to the high speed conduction of the channel carriers, resulting in an unexpected drop in the essential voltage gain (AV). Therefore, it can be proved that the dilute channel design of the symmetrical linear change of the indium and bismuth components provided by the present invention can alleviate the kink effects of the channel carriers causing collision freeness due to high-speed conduction. In the present embodiment, the essential voltages of the high electron mobility transistors 100, 200, and 300 when the gate-source voltage value (VGS) bias voltage is -1.4 V, -1.7 V, and -1.6 V, respectively. The gain (AV) is up to 18.2 (304/16.7 mS/mm), 9.14 (281/30.74 mS/mm) and 59.25 (349/5.89 mS/mm).

Please refer to FIG. 7. FIG. 7 is a diagram showing output power (Pout), power gain (GS), and power addition obtained by the high electron mobility transistors 100, 200, and 300 under operating conditions of 300 K and 2.4 GHz. Characteristic curve of effect (PAE). The horizontal axis represents the input power (in), and the vertical axis represents the output power (Pout), power gain (GS), and power added effect (P.A.E.) obtained under class AB conditions. The square curve represents the high electron mobility transistor 100; the triangular curve represents the high electron mobility transistor 200; and the circular curve represents the high electron mobility transistor 300.

According to Figure 7, the output power/power gain values (Pout/GS) of the high electron mobility transistors 100, 200, and 300 are 17.3/19.92 dBm/dB, 16.9/19.07 dBm/dB, and 16.4/17.8 dBm/dB, respectively; The power added effect (PAE) values were 36.7%, 29.6%, and 46.5%, respectively. It is apparent that the high electron mobility transistors 100, 200, and 300 provided by the above embodiments have high external mass transfer gain values (gm, max), output power, and power added effects (P.A.E.).

According to the above embodiment, the present invention provides a high electron mobility transistor having a high Schottky barrier and a dilute channel (InxGa1-xAs1-ySby) in which the indium and bismuth compositions are symmetrically linearly changed. By adding a trace amount of cerium doping, it acts as a layer surfactant to effectively increase the discontinuous barrier height of the conductive strip. In addition, the combination of the composition of bismuth and indium exhibits a V-shaped change, which improves the carrier binding force, conduction characteristics, and high linear gain in the channel. It can effectively reduce the gate/substrate leakage current, improve the breakdown voltage between the gate and the drain, improve the power added efficiency (PAE), enhance the carrier transmission capacity and effectively reduce the button junction effect, thereby reducing the gate leakage current and improving the gate. The crash feature achieves the above object.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100. . . High electron mobility transistor

101. . . Gallium arsenide substrate

102. . . Indium arsenide crystal buffer layer

103. . . Indium arsenide buffer layer

104. . .锑Indium arsenide aluminum buffer layer

105. . . Indium arsenide buffer layer

106. . . Δ-doped carrier supply layer

107. . . Indium arsenide isolation layer

108. . . Indium gallium arsenide channel layer

109. . . Indium arsenide isolation layer

110. . . Δ-doped carrier supply layer

111. . . Indium arsenide aluminum gate Schottky contact layer

112. . . Indium gallium arsenide coating

113. . .汲/source ohmic contact layer

114. . .汲/source plate

115. . . Gate plate

200. . . High electron mobility transistor

216. . . Etch stop layer

300. . . High electron mobility transistor

315. . . Gate plate

1A-1C are cross-sectional views showing a process for fabricating a high electron mobility transistor in accordance with a preferred embodiment of the present invention.

2 is a cross-sectional view showing the structure of a high electron mobility transistor according to another preferred embodiment of the present invention.

3 is a cross-sectional view showing the structure of a high electron mobility transistor according to still another preferred embodiment of the present invention.

4 is a graph showing the current-voltage (IGD-VGD) characteristics of the gate-drain electrodes at a temperature of 300 K under the operating conditions of the high electron mobility transistor provided by the present invention.

FIG. 5 is a graph showing the external mass transfer gain (gm) and the gate-source voltage value (VGS) characteristic of the high electron mobility transistor provided by the present invention under operating conditions of 300 K. .

6 is a graph showing the essential voltage gain (AV), the external mass transfer gain (gm), and the output conductance (gd) of a high electron mobility transistor provided by the present invention under operating conditions of 300 K. Characteristic chart.

7 is a graph showing the output power (Pout), power gain (GS), and power added effect (PAE) obtained by the high electron mobility transistor of the present invention under operating conditions of 300 K and 2.4 GHz. Characteristic curve.

101. . . Gallium arsenide substrate

102. . . Indium arsenide crystal buffer layer

103. . . Indium arsenide buffer layer

104. . .锑Indium arsenide aluminum buffer layer

105. . . Indium arsenide buffer layer

106. . . Δ-doped carrier supply layer

107. . . Indium arsenide isolation layer

108. . . Indium gallium arsenide channel layer

109. . . Indium arsenide isolation layer

110. . . Δ-doped carrier supply layer

111. . . Indium arsenide aluminum gate Schottky contact layer

113. . .汲/source ohmic contact layer

114. . .汲/source plate

216. . . Etch stop layer

300. . . High electron mobility transistor

315. . . Gate plate

Claims (10)

A semiconductor device having a structure comprising: a semiconductor substrate; a buffer layer of indium aluminum arsenide (InAlAsSb) on the semiconductor substrate; and a germanium-doped indium gallium arsenide channel layer on the buffer layer Indium and bismuth having substantially less than 5% of bismuth doping ratio, and the indium bismuth arsenide channel layer has a doping design with a symmetrical linear change (InxGa1-xAs1-ySby); An isolation layer is disposed on the channel layer; a first δ-doped carrier supply layer is disposed on the isolation layer; and a germanium arsenide aluminum gate Schottky contact layer is disposed on the δ-doped carrier And a germanium/source ohmic contact layer on the germanium indium arsenide gate Schottky contact layer. The semiconductor device of claim 1, wherein the semiconductor substrate and the indium aluminum arsenide buffer layer comprise a crystal buffer layer. The semiconductor device of claim 1, wherein the germanium indium arsenide gate Schottky contact layer and the germanium/source ohmic contact layer comprise a selective etch stop layer. The semiconductor device of claim 1, wherein the germanium/source ohmic contact layer comprises a cap layer. The semiconductor device of claim 1, wherein the material constituting the germanium/source ohmic contact layer is selected from the group consisting of highly doped gallium arsenide, indium phosphide, indium gallium arsenide, and arsenic. A group of aluminum gallium and any combination of the above. The semiconductor device of claim 1, further comprising a germanium/source plate disposed on the germanium/source ohmic contact layer, and the germanium/source plate is made of gold/nickel/gold / Silver multi-layer alloy. The semiconductor device of claim 1, further comprising a gate plate on the germanium indium arsenide gate Schottky contact layer, and the gate plate is made of nickel, gold, white or Any combination of the above. The semiconductor device of claim 1, wherein the indium antimonide aluminum arsenide buffer layer and the germanium-doped germanium indium gallium arsenide channel layer comprise a second delta-doped carrier for The layer should be a second insulation layer. The semiconductor device according to claim 8, wherein the first δ-doped carrier supply layer and the second δ-doped carrier supply layer have a substantial difference of 1×10 ¹² cm ⁻ A 矽 (Si) doping amount between ² and 5 × 10 ¹² cm ^-2 . The semiconductor device according to claim 1 is a heterostructure field effect transistor which is grown by a metal organic chemical vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method. A semiconductor epitaxial structure.