JP2010267793A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the semiconductor device, such that while a decrease in characteristics of the semiconductor device operating in a high frequency band is suppressed, manufacturing costs can be lowered. <P>SOLUTION: The semiconductor device 100 includes: a field effect type transistor; a heterojunction bipolar transistor; a base epitaxial resistance element 28 formed using a GaAs base layer 7 of the heterojunction bipolar transistor; a wiring portion 26 formed using an InGaAs channel layer 4 of the field effect type transistor; an increased-resistance region 27 insulating the wiring portion 26 and base epitaxial resistance element 28 from each other; and an insulating element isolation region 24 surrounding the wiring potion 26 in a horizontal direction. Further, the base epitaxial resistance element 28 has a base epitaxial resistance element region 29 crossing the wiring portion 26 when being viewed from a direction perpendicular to a principal surface of a semi-insulating GaAs substrate 1. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a heterojunction bipolar transistor and a field effect transistor and a manufacturing method thereof.

  The group III-V compound semiconductor has a feature that electron mobility is higher than that of a Si (silicon) semiconductor. As a result, III-V compound semiconductors are widely used in devices that require high-speed operation and high-efficiency operation. In particular, in a heterojunction bipolar transistor (hereinafter referred to as HBT) using a heterojunction for the junction between the emitter and the base, the band gap of the emitter layer is wider than the band gap of the base layer. As a result, the HBT has excellent characteristics such as excellent high-frequency characteristics, low-distortion signal amplification, and use with a single power source. Therefore, the HBT has been widely used as a semiconductor component that operates in a high frequency band such as a power amplifier for a mobile phone.

  However, recent mobile phone terminals are required to be multiband and more complicated operation control, but are also required to reduce the number of parts to reduce the manufacturing cost. Therefore, semiconductor components for mobile phones must satisfy these conflicting requirements at the same time.

  In order to realize this requirement, research and development of a Bi-FET process technology in which an HBT and a field effect transistor (hereinafter referred to as an FET) are formed on the same semiconductor chip have been promoted recently. By this Bi-FET process technology, a high-frequency signal amplification circuit and a switching circuit can be realized on a single chip.

  In addition, with the development of multi-band, in order to realize a complex switching function between multiple bands in one chip in the future, in addition to HBT and FET, the control circuit part such as logic circuit is also the same chip It is expected to form on top.

  For example, there is a technique described in Patent Document 1 as a technique for forming an HBT and a resistance element that can be used for a control circuit or the like on the same chip.

  Hereinafter, a semiconductor device 700 in which an HBT, an FET, and a logic circuit, which are assumed from a conventional Bi-FET process, are formed on the same chip will be described.

  7A is a plan view of the semiconductor device 700, and FIG. 7B is a cross-sectional view of the semiconductor device 700 taken along the plane C0-C1 in FIG. 7A.

  As shown in FIGS. 7A and 7B, the semiconductor device 700 includes a semi-insulating GaAs substrate 701, an HBT region 722, an FET region 723, an element isolation region 724, and a logic circuit region 725.

  The HBT region 722 is formed on the semi-insulating GaAs substrate 701. The HBT region 722 is formed in the following order from the semi-insulating GaAs substrate 701 side, and includes a GaAs / AlGaAs superlattice layer 702, an AlGaAs barrier layer 703A, an InGaAs channel layer 704, an AlGaAs barrier layer 703B, A GaAs subcollector / cap layer 705, a collector electrode 714, a first wiring layer 717, and a second wiring layer 718 are included. The HBT region 722 includes a base mesa region 720 formed between the collector electrodes 714.

  The base mesa region 720 is formed on the GaAs subcollector / cap layer 705. The base mesa region 720 is formed in the following order from the GaAs subcollector / cap layer 705 side, and includes a GaAs collector layer 706, a GaAs base layer 707, an InGaP emitter layer 708, a GaAs emitter cap layer 709, An InGaAs emitter contact layer 710 and an emitter electrode 716 are included. The base mesa region 720 is between the emitter electrode 716 and a base electrode 715 formed on the surface of the GaAs base layer 707, and a first wiring layer 717 formed on the emitter electrode 716 and the base electrode 715. including.

  The FET region 723 includes a GaAs / AlGaAs superlattice layer 702, an AlGaAs barrier layer 703A, an InGaAs channel layer 704, an AlGaAs barrier layer 703B, a GaAs subcollector / cap layer 705, a drain electrode 711, and a source electrode 712. , A gate electrode 713 and a first wiring layer 717.

  The logic circuit region 725 includes a base epiresistance element 728, a contact electrode 730 connected to the base epiresistance element 728, a first wiring layer 717, a second wiring layer 718, and an enhancement mode field effect transistor (not shown). including.

  Note that an element isolation region 724 is formed between the HBT region 722, the FET region 723, and the logic circuit region 725. By this element isolation region 724, each region is insulated and isolated. In addition, the element isolation region 724 is disposed at an appropriate location so as to insulate and isolate each element constituting the logic circuit in the logic circuit region 725.

  In the device structure formed by the Bi-FET process, the arrangement of the HBT and the FET with respect to the lowermost semi-insulating GaAs substrate 701 is a point. At present, a structure in which an HBT is disposed on the upper layer side and an FET is disposed on the lower layer side when the semi-insulating GaAs substrate 701 is disposed on the lower side is common from the viewpoint of process difficulty.

  In addition, when the logic circuit region 725 is formed on the same chip as the HBT and FET using the conventional Bi-FET process, the chip is connected to the HBT and FET devices and the first connected to them. The wiring layer 717 and the second wiring layer 718, and a base epiresistance element 728 using an epilayer used as the base layer of the HBT (GaAs base layer 707) are included.

  Furthermore, the logic circuit region 725 has a very dense layout because a large number of wirings, resistance elements, and the like are required to be arranged due to its configuration.

Japanese Patent Laid-Open No. 10-107042

  However, the first wiring layer 717 and the second wiring layer 718 used in forming the logic circuit region 725 are used for connection to the HBT and FET devices as described above. Therefore, in order to prevent deterioration of an RF (Radio Frequency) signal passing through the first wiring layer 717 and the second wiring layer 718, it is necessary to use a thick metal for the first wiring layer 717 and the second wiring layer 718. is there. Here, the thick metal wiring has severe restrictions on the mask rules for pattern formation (minimum adjacent intervals LA and LB and minimum width). Therefore, in the semiconductor device 700, when many wirings are arranged using the first wiring layer 717 and the second wiring layer 718, there is a problem that a manufacturing cost increases due to an increase in chip size.

  Further, since the base epiresistance element 728 used as a resistance element included in the logic circuit region 725 does not have a high sheet resistance, the size of each base epiresistance element 728 is increased. As a result, in the semiconductor device 700, when a large number of base epiresistance elements 728 are arranged, there is a problem that the manufacturing cost increases due to an increase in chip size.

  On the other hand, if an attempt is made to increase the sheet resistance of the base layer used for the base epiresistance element 728 in order to avoid the above problem, the RF characteristics of the HBT device using the same layer will deteriorate. Therefore, the sheet resistance of the base epiresistance element 728 cannot be increased.

For example, since the sheet resistance of the base epi-resistance element 728 is increased, the h _FE (DC current amplification factor) of the HBT is decreased, and thus the characteristics of the semiconductor device such as the deterioration of the gain of the RF characteristics are deteriorated. The problem will occur.

  In view of the above problems, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can reduce the manufacturing cost while suppressing the deterioration of the characteristics of the semiconductor device operating in a high frequency band.

  In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device, which includes a semiconductor substrate, a field effect transistor formed on the semiconductor substrate, and a heterojunction formed on the semiconductor substrate. Bipolar transistor, a resistance element formed on the semiconductor substrate and formed using a base layer or a subcollector layer of the heterojunction bipolar transistor, and a wiring portion formed using a channel layer of the field effect transistor And increasing the resistance of the wiring layer connected to the field effect transistor, the heterojunction bipolar transistor and the resistance element, and the active layer between the wiring portion and the base layer or the subcollector layer. Formed on the main surface of the semiconductor substrate, and a high resistance region that insulates the wiring portion from the resistance element. An insulating element isolation region surrounding the periphery of the wiring portion in a flat direction, and the resistance element intersects the wiring portion when viewed from a direction perpendicular to the main surface of the semiconductor substrate. Has a region.

  According to this configuration, the semiconductor device according to the present invention has the same connection relation as the conventional two-layer wiring using the first wiring layer and the second wiring layer, and the wiring using the first wiring layer and the channel layer. It can be realized by a two-layer wiring using a part. Here, in the wiring portion using the channel layer, the mask rule restrictions such as the minimum line width and the minimum adjacent interval are greatly relaxed as compared with the first wiring layer and the second wiring layer using metal. As a result, the semiconductor device according to the present invention can arrange a larger number of wirings in a smaller area as compared with the prior art, so that the manufacturing cost due to the area saving can be reduced.

  Furthermore, in the semiconductor device according to the present invention, the vertical direction of the resistance element and the wiring portion is partitioned by the high resistance region. As a result, the resistance element and the wiring portion can be crossed, so that there are no restrictions on routing.

  Furthermore, noble metals such as Au are often used for the first wiring layer and the second wiring layer, but the amount of noble metal used can be reduced by replacing some of these with wiring portions using a channel layer. can do. Thereby, the manufacturing cost of the semiconductor device according to the present invention can be reduced.

  Furthermore, in the semiconductor device according to the present invention, when the conventionally used first wiring layer and second wiring layer are also used as they are, the degree of freedom in wiring layout is greatly increased. As a result, the semiconductor device according to the present invention can further reduce the area, which can further reduce the manufacturing cost.

  The semiconductor device includes a field effect transistor region in which the field effect transistor is formed, a heterojunction bipolar transistor region in which the heterojunction bipolar transistor is formed, and a control circuit including the resistance element. A logic circuit region, wherein the element isolation region is formed at a boundary between the field effect transistor region, the heterojunction bipolar transistor region, and the logic circuit region, and the field effect transistor region and the heterojunction bipolar The transistor region may be insulated from the logic circuit region, and the wiring portion may be formed in the logic circuit region.

  According to this configuration, in the logic circuit area where a large number of wirings and resistance elements are densely used, the wiring area using the channel layer can be used, so that the area can be further reduced, so that the manufacturing cost can be further reduced.

  Further, the high resistance region may be a region whose resistance is increased by implanting first ions into the active layer.

  The element isolation region may be a region whose resistance is increased by performing ion implantation on at least a part of the active layer and the channel layer.

  According to this configuration, the wiring portion using the channel layer can be formed with a smaller minimum line width and a minimum adjacent interval. Thereby, the semiconductor device according to the present invention can realize a reduction in manufacturing cost due to the area saving.

  The crossing region may have a higher resistance value than the base layer or the subcollector layer included in the heterojunction bipolar transistor.

  Further, the crossing region may have a high resistance by ion implantation of the first ions into the base layer or the subcollector layer.

  Further, the crossing region included in the resistance element may have a higher resistance value than the region other than the crossing region included in the resistance element.

  The resistance element may include a region having a resistance value higher than that of the base layer or the subcollector layer of the heterojunction bipolar transistor in addition to the intersection region.

  According to this configuration, by optimizing the ion implantation conditions for forming the high resistance region, the resistance value of the portion used as the resistance element in the base layer or the subcollector layer is not completely insulated but is heterogeneous. The sheet resistance value can be adjusted to be several times that of the base layer or the subcollector layer in the junction bipolar transistor region. Thereby, since the sheet resistance value of a resistance element can be increased without adding a manufacturing process, the area area | region of a resistance element can be reduced. Therefore, the semiconductor device according to the present invention further reduces the manufacturing cost.

  Moreover, the present invention can be realized not only as such a semiconductor device but also as a method for manufacturing a semiconductor device for manufacturing such a semiconductor device.

  As described above, the present invention can provide a semiconductor device and a manufacturing method thereof that can reduce the manufacturing cost while suppressing the deterioration of the characteristics of the semiconductor device operating in the high frequency band.

1 is a plan view of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing in the manufacturing process of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing in the manufacturing process of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing in the manufacturing process of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing in the manufacturing process of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing in the manufacturing process of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing in the manufacturing process of the semiconductor device which concerns on Embodiment 1 of this invention. It is a figure which shows the chip size of the semiconductor device which concerns on Embodiment 1 and Embodiment 2 of this invention, and the conventional semiconductor device. It is a top view of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing in the manufacturing process of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing in the manufacturing process of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing in the manufacturing process of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing in the manufacturing process of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing in the manufacturing process of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing in the manufacturing process of the semiconductor device which concerns on Embodiment 2 of this invention. It is a graph which shows the relationship between the ion implantation conditions based on Embodiment 2 of this invention, and the sheet resistance value of the implanted base layer, and the sheet resistance value of a channel layer. It is a graph which shows the relationship between the ion implantation conditions based on Embodiment 2 of this invention, and the leakage current between a channel layer and its upper layer. It is a top view of a semiconductor device using the conventional Bi-FET process. It is sectional drawing of the semiconductor device using the conventional Bi-FET process.

(Embodiment 1)
The semiconductor device 100 according to the first embodiment of the present invention is a semiconductor device including an HBT, an FET, and a logic circuit region in which a logic circuit including a base epiresistance element using a base layer of the HBT is formed. In the semiconductor device 100, a wiring portion using a channel layer of FET is used as wiring in the logic circuit region. Thereby, the semiconductor device 100 according to the first embodiment of the present invention can reduce the manufacturing cost while suppressing the deterioration of the characteristics of the semiconductor device operating in the high frequency band.

  Hereinafter, the semiconductor device 100 according to the first embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1A is a plan view of the semiconductor device 100 according to the first embodiment of the present invention. 1B is a cross-sectional view of the semiconductor device 100 taken along the A0-A1 plane shown in FIG. 1A.

  As shown in FIGS. 1A and 1B, the semiconductor device 100 includes a semi-insulating GaAs substrate 1, a first wiring layer 17, a second wiring layer 18, an HBT region 22, an FET region 23, and an element isolation region. 24 and a logic circuit area 25.

  The semi-insulating GaAs substrate 1 is a semiconductor substrate on which a plurality of semiconductor elements are formed.

  The HBT region 22, the FET region 23, and the logic circuit region 25 are formed on the semi-insulating GaAs substrate 1. The HBT region 22 is a region where an HBT is formed, and the FET region 23 is a region where an FET is formed. Here, the FET formed in the FET region 23 is, for example, a heterojunction field effect transistor (HFET).

  The logic circuit region 25 is a region where a control circuit including the base epiresistance element 28 and an enhancement mode field effect transistor (not shown) is formed.

  The HBT region 22, the FET region 23, and the logic circuit region 25 are formed on the semi-insulating GaAs substrate 1 from the lower layer side in the following order, and the GaAs / AlGaAs superlattice layer 2 and the AlGaAs barrier layer 3A. And an InGaAs channel layer 4, an AlGaAs barrier layer 3 </ b> B, and a GaAs subcollector / cap layer 5.

  The HBT region 22 includes a collector electrode 14 formed on the GaAs subcollector / cap layer 5 and a base mesa region 20 formed on the GaAs subcollector / cap layer 5 and between the collector electrodes 14.

  The base mesa region 20 is formed in the following order from the lower layer side, the GaAs collector layer 6, the GaAs base layer 7, the InGaP emitter layer 8, the GaAs emitter cap layer 9, the InGaAs emitter contact layer 10, And an emitter electrode 16.

  Here, the GaAs base layer 7 and the InGaP emitter layer 8 form an InGaP / GaAs heterojunction.

  The base mesa region 20 includes a base electrode 15 formed on the GaAs base layer 7.

  The HBT region 22 includes a first wiring layer 17 formed on the collector electrode 14 and the emitter electrode 16 and a second wiring layer 18 formed on the first wiring layer 17.

  The FET region 23 includes a gate digging region 21, a gate electrode 13, a source electrode 12, and a drain electrode 11.

  The gate digging region 21 is a region where the GaAs subcollector / cap layer 5 has been removed.

  The gate electrode 13 is formed on the AlGaAs barrier layer 3 </ b> B in the gate digging region 21.

  The source electrode 12 and the drain electrode 11 are formed on the GaAs subcollector / cap layer 5 so as to sandwich the gate electrode 13.

  A first wiring layer 17 that is electrically connected to the source electrode 12 and the drain electrode 11 is formed on the source electrode 12 and the drain electrode 11.

  Here, the current applied between the drain electrode 11 and the source electrode 12 is controlled by the voltage applied to the gate electrode 13 affecting the carriers traveling in the InGaAs channel layer 4.

  The GaAs / AlGaAs superlattice layer 2, AlGaAs barrier layers 3A and 3B, InGaAs channel layer 4, GaAs subcollector / cap layer 5, GaAs collector layer 6, GaAs base layer 7, and InGaP emitter layer 8 The GaAs emitter cap layer 9 and the InGaAs emitter contact layer 10 are a plurality of semiconductor layers stacked on a semiconductor substrate (semi-insulating GaAs substrate 1), and function as active layers.

  The element isolation region 24 is an insulating region and is formed at the boundary between the HBT region 22, the FET region 23, and the logic circuit region 25. The element isolation region 24 is increased in resistance (insulation) by ion implantation over a plurality of semiconductor layers. Thereby, the element isolation region 24 insulates and isolates the HBT region 22, the FET region 23, and the logic circuit region 25 from each other. The element isolation region 24 is also disposed in an appropriate place in the logic circuit region 25 in order to insulate and isolate each element constituting the logic circuit.

  The logic circuit region 25 includes a wiring portion 26, a high resistance region 27, a base epiresistance element 28, a contact electrode 30, a channel wiring connection electrode 31, a first wiring layer 17, and an enhancement mode field effect transistor ( (Not shown).

  The wiring part 26 is a wiring formed using the InGaAs channel layer 4. In addition, the horizontal direction of the wiring portion 26 (plane direction parallel to the main surface of the semi-insulating GaAs substrate 1) is partitioned by an element isolation region 24. Specifically, the element isolation region 24 is formed so as to surround the periphery of the wiring portion 26 in the horizontal direction.

  The high resistance region 27 is a region where the resistance of the GaAs subcollector / cap layer 5 on the wiring portion 26 is increased by ion implantation. The high resistance region 27 partitions the wiring portion 26 in the vertical direction (direction perpendicular to the main surface of the semi-insulating GaAs substrate 1). That is, the high resistance region 27 insulates the wiring part 26 from the base epiresistance element 28 formed on the wiring part 26.

  The base epiresistance element 28 is a resistance element formed using an epilayer used as a base layer (GaAs base layer 7) of the HBT. Base epiresistance element 28 includes a base epiresistance element region 29.

  The base epiresistance element region 29 is a region located on the high resistance region 27 in the region of the base epiresistance element 28. In other words, the base epiresistance element region 29 is a region that intersects the wiring portion 26 when viewed from the direction perpendicular to the main surface of the semi-insulating GaAs substrate 1 in the region of the base epiresistance element 28. That is, the base epiresistance element 28 and the wiring part 26 intersect three-dimensionally.

  The base epiresistance element region 29 is increased in resistance by being ion-implanted at the same time as the ion implantation for forming the high-resistance region 27, and the GaAs base layer 7 in the HBT region and the base epiresistance element 28. It has a higher sheet resistance than other regions. For example, the base epiresistance element region 29 has a sheet resistance value several times that of the GaAs base layer 7 in the HBT region and other regions of the base epiresistance element 28.

  The contact electrode 30 is formed on the end portion of the base epiresistance element 28 and electrically connects the base epiresistance element 28 and the first wiring layer 17.

  The channel wiring connection electrode 31 is formed on the GaAs subcollector / cap layer 5 and is electrically connected to the wiring section 26 via the GaAs subcollector / cap layer 5 and the AlGaAs barrier layer 3A. In addition, the first wiring layer 17 that is electrically connected to the channel wiring connection electrode 31 is formed on the channel wiring connection electrode 31.

  As described above, in the logic circuit region 25, a large number of wiring portions 26, base epiresistance elements 28, channel wiring connection electrodes 31, the first wiring layer 17, enhanced mode field effect transistors (not shown), and the like are densely arranged. Has been.

  Next, a method for manufacturing the semiconductor device 100 will be described. 2A to 2F are cross-sectional views in the manufacturing process of the semiconductor device 100 according to the first embodiment of the present invention.

  First, a GaAs / AlGaAs superlattice layer 2, an AlGaAs barrier layer 3A, an InGaAs channel layer 4, an AlGaAs barrier layer 3B, and a GaAs subcollector / cap layer 5 on a semi-insulating GaAs substrate 1 in this order from the lower layer. The GaAs collector layer 6, the GaAs base layer 7, the InGaP emitter layer 8, the GaAs emitter cap layer 9, and the InGaAs emitter contact layer 10 are formed by epitaxial growth (FIG. 2A).

  Next, a resist is patterned on the plurality of semiconductor layers shown in FIG. 2A by using a photolithography method, and then the resist opening is etched by using a dry etching method to form an emitter mesa region 19. Subsequently, the resist is patterned in the same manner for the portion of the portion where the wiring portion 26 using the InGaAs channel layer 4 is to be formed, except for the portion where the channel wiring connection electrode 31 that contacts the wiring portion 26 is formed. By implanting appropriate ion species into the resist opening under appropriate implantation conditions, a high resistance region 27 that partitions the wiring portion 26 in the vertical direction is formed (FIG. 2B).

  In this manufacturing process, the ion species and implantation conditions used when forming the high resistance region 27 are such that the semiconductor layer (GaAs subcollector and cap layer 5) above the portion where the wiring portion 26 is formed is completely. It is optimized for the ion species to be insulated and the implantation conditions. Detailed conditions for this ion implantation will be described later.

  Next, the base mesa region 20 and the base epiresistance element 28 are formed by the same method as when the emitter mesa region 19 is formed. Note that the portion where the high resistance region 27 and the base epiresistance element 28 formed in advance overlap with each other is clearly indicated as a base epiresistance element region 29 having a higher sheet resistance (FIG. 2C).

  Next, the part other than the place where the element isolation is performed is protected with a resist, and then a He + ion is implanted under an appropriate implantation condition to form the element isolation region 24 having a high resistance. Thus, the HBT region 22, the FET region 23, and the logic circuit region 25 are partitioned, and each element in the logic circuit region 25 is partitioned. Further, a part of the InGaAs channel layer 4 is partitioned by the element isolation region 24 in the horizontal direction and by the high resistance region 27 in the vertical direction. Thereby, the wiring part 26 using the InGaAs channel layer 4 is formed (FIG. 2D).

  Next, after forming the insulating film, the insulating film in the portion where the emitter electrode 16, the base electrode 15 and the collector electrode 14 are formed, and the InGaP emitter layer 8 in the portion where the base electrode 15 is formed are removed. Next, an emitter electrode 16 made of Ti / Pt / Au or the like that contacts the InGaAs emitter contact layer 10 and a base electrode made of Ti / Pt / Au or the like that contacts the GaAs base layer 7 are formed on the part from which the insulating film has been removed. 15 and a collector electrode 14 made of AuGe / Ni / Au or the like in contact with the GaAs subcollector / cap layer 5 are sequentially formed.

  Next, the insulating film in the portion where the drain electrode 11, the source electrode 12, and the channel wiring connection electrode 31 are formed is removed. Next, the drain electrode 11 made of AuGe / Ni / Au or the like that contacts the GaAs subcollector / cap layer 5, the source electrode 12, and the channel wiring connection electrode 31 are formed in the portion where the insulating film is removed. Further, after removing the insulating film in the portion where the gate electrode 13 is to be formed, the gate digging region 21 is formed by removing the GaAs subcollector / cap layer 5 in that portion. Next, the gate electrode 13 made of Ti / Al / Ti or the like in contact with the AlGaAs barrier layer 3B is formed in the gate digging region 21 (FIG. 2E).

  Next, after an insulating film is formed on the structure shown in FIG. 2E, contact portions to the formed electrodes are opened, and a first wiring layer 17 is formed thereon.

  Next, after forming an insulating film on the first wiring layer 17, the insulating film at the place where the first wiring layer 17 and the second wiring layer 18 are contacted is removed. Next, the second wiring layer 18 is formed on the portion to be connected to the first wiring layer 17 by using a plating method or the like (FIG. 2F).

  Finally, after forming a final protective film on the structure shown in FIG. 2F, the protective film of each pad and scribe line portion is removed.

Through the above steps, the semiconductor device 100 is formed.
As described above, according to the semiconductor device 100 and the manufacturing method thereof according to the first embodiment of the present invention, the step of forming the wiring portion 26 using the InGaAs channel layer 4 is performed so that a part of the InGaAs channel layer 4 is in the horizontal direction. It is formed in the element isolation region 24 and partitioned by a high resistance region 27 that partitions the wiring portion 26 in the vertical direction, which is formed by ion implantation in the vertical direction. As a result, the mask rule (minimum line width and minimum adjacent interval) of the wiring portion 26 is restricted only by the patterning limit dimension of the resist used when forming the element isolation region 24.

  On the other hand, for the first wiring layer 17 and the second wiring layer 18 that use a thick metal layer, a resist having a large film thickness must be used. The conditions for ensuring the lift-off property of this are also added to the constraints.

  Therefore, as compared with the first wiring layer 17 and the second wiring layer 18, many wirings can be arranged in a narrower region in the wiring portion 26 using the InGaAs channel layer 4. Thereby, a part of the first wiring layer 17 and the second wiring layer 18 can be replaced with the wiring part 26 using the InGaAs channel layer 4, so that the chip size can be reduced. Therefore, the manufacturing cost of the semiconductor device 100 can be reduced. Moreover, since the area of the 1st wiring layer 17 and the 2nd wiring layer 18 which use noble metals, such as Au, can be reduced by this, a manufacturing cost can be reduced also from the surface of material cost.

  In the first embodiment of the present invention, in the step of forming the base electrode 15 shown in FIG. 2D, a material that diffuses into a semiconductor layer such as Pt is adopted as the bottom layer of the base electrode 15, and then an InGaP emitter. The base electrode 15 may be formed on the InGaP emitter layer 8 without removing the layer 8.

  Further, in the first embodiment of the present invention, the step of forming the collector electrode 14, the source electrode 12, the drain electrode 11 and the channel wiring connection electrode 31 shown in FIG. It may be carried out simultaneously with one mask including the film removal step. By this simultaneous formation, in the manufacturing method of the semiconductor device 100 according to the first embodiment of the present invention, the addition from the conventional manufacturing method is to increase the resistance to partition the wiring portion 26 in the vertical direction by ion implantation. There is only one step of forming the region 27. That is, there is almost no increase in cost due to the addition of the manufacturing method.

  Hereinafter, the effect of reducing the chip size of the semiconductor device 100 according to the first embodiment of the present invention will be described.

  FIG. 3 is a diagram showing a comparative example of chip sizes of the semiconductor device 100 according to the first embodiment of the present invention, the semiconductor device 200 according to the second embodiment to be described later, and a conventional semiconductor device. The horizontal axis of FIG. 3 shows the type of the semiconductor device, the left is the conventional semiconductor device, the middle is the semiconductor device 100 according to the first embodiment of the present invention, and the right is the semiconductor device according to the second embodiment of the present invention. 200 is shown. Also, the vertical axis of FIG. 3 indicates the chip size of each semiconductor device when the chip size of the conventional semiconductor device is 100.

  Note that the chip size shown in FIG. 3 shows a case where the present invention is applied based on a certain circuit configuration, and the numerical value of the chip size is only a reference value, and the specific chip size is the circuit configuration. It depends on.

  The semiconductor device 100 according to the first embodiment of the present invention has a logic circuit region 25 in which a base epi-resistance element 28 and a wiring portion 26 using the InGaAs channel layer 4 are formed, and a part of them intersects. As shown in FIG. 3, it can be seen that the chip size can be greatly reduced while maintaining the same circuit configuration.

  From the above, the semiconductor device 100 according to the first embodiment of the present invention can reduce the manufacturing cost due to the area saving and the material cost reduction while suppressing the deterioration of the characteristics of the semiconductor device operating in the high frequency band. realizable.

(Embodiment 2)
The semiconductor device 200 according to the second embodiment of the present invention is a modification of the semiconductor device 100 according to the first embodiment described above. In this semiconductor device 200, not only a portion of the base epiresistance element 28 that intersects the wiring portion 26 that uses the InGaAs channel layer 4 but also all regions of the base epiresistance element 28 divide the InGaAs channel layer 4 in the vertical direction. When the resistance region 27 is formed, the base epiresistance element region 29 is ion-implanted at the same time. Thereby, the semiconductor device 200 according to the second embodiment of the present invention can increase the sheet resistance of the layer used as the resistance of the base epiresistance element 28, so that the area of the base epiresistance element 28 can be saved. Thereby, the semiconductor device 200 according to the second embodiment of the present invention can further reduce the manufacturing cost.

  Hereinafter, the semiconductor device 200 according to the second embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 4A is a plan view of the semiconductor device 200 according to Embodiment 2 of the present invention. FIG. 4B is a cross-sectional view of the semiconductor device 200 on the B0-B1 plane shown in FIG. 4A.

  4A and 4B, the semiconductor device 200 includes a semi-insulating GaAs substrate 1, a drain electrode 11, a source electrode 12, a gate electrode 13, a collector electrode 14, a base electrode 15, and an emitter electrode. 16, the first wiring layer 17, the second wiring layer 18, the HBT region 22, the FET region 23, the element isolation region 24, the logic circuit region 25, and the wiring part 26 using the InGaAs channel layer 4. And a high resistance region 27 which is formed by ion implantation and partitions the wiring portion 26 in the vertical direction, a base epiresistance element region 29 having a high sheet resistance, and a channel wiring connection electrode 31.

  4A and 4B, the semiconductor device 200 shown in FIGS. 4A and 4B has ion implantation for partitioning the wiring portion 26 in the vertical direction in all of the base epiresistance elements 28, as compared with the semiconductor device 100 shown in FIGS. 1A and 1B. Only the points given are different. That is, the semiconductor device 200 does not include the normal base epiresistance element 28, and all of them are the base epiresistance element region 29 having a higher sheet resistance. The description of the same points as those of the semiconductor device 100 shown in FIGS. 1A and 1B will be omitted, and only different points will be described below.

  In the present invention, the high resistance region 27 that partitions the wiring portion 26 in the vertical direction is formed for all the base epi resistance elements 28 formed on the chip regardless of the logic circuit region 25 and other regions. Ion implantation is performed at the same time. Therefore, all of the base epiresistance elements are the base epiresistance element region 29 having a high sheet resistance. Thereby, compared with the base epiresistance element 28 shown in FIGS. 1A and 1B, the base epiresistance element shown in FIGS. 4A and 4B can realize the same resistance value with a small area. Thereby, the semiconductor device 200 according to the second embodiment of the present invention can realize further area saving than the semiconductor device 100 according to the first embodiment, and thus can further reduce the manufacturing cost.

  Here, an example is shown in which all the regions of the base epiresistance element 28 become the base epiresistance element region 29 having a high sheet resistance, but the base epiresistance element 28 may include a region where the resistance is not increased.

  Next, a method for manufacturing the semiconductor device 200 described in FIGS. 4A and 4B will be described. 5A to 5F are cross-sectional views in the manufacturing process of the semiconductor device 200 according to the second embodiment of the present invention.

  First, a GaAs / AlGaAs superlattice layer 2, an AlGaAs barrier layer 3A, an InGaAs channel layer 4, an AlGaAs barrier layer 3B, and a GaAs subcollector / cap layer 5 on a semi-insulating GaAs substrate 1 in this order from the lower layer. The GaAs collector layer 6, the GaAs base layer 7, the InGaP emitter layer 8, the GaAs emitter cap layer 9, and the InGaAs emitter contact layer 10 are formed by epitaxial growth (FIG. 5A).

  Next, a resist is patterned on the plurality of semiconductor layers shown in FIG. 5A by using a photolithography method, and then the resist opening is etched by using a dry etching method to form an emitter mesa region 19. Subsequently, the resist is patterned in the same manner for the portion of the portion where the wiring portion 26 using the InGaAs channel layer 4 is to be formed, except for the portion where the channel wiring connection electrode 31 that contacts the wiring portion 26 is formed. By implanting an appropriate ion species into the resist opening under an appropriate implantation condition, a high resistance region 27 that partitions the wiring portion 26 in the vertical direction is formed (FIG. 5B).

  In this manufacturing process, the ion species and implantation conditions used when forming the high resistance region 27 are such that the semiconductor layer (GaAs subcollector and cap layer 5) above the portion where the wiring portion 26 is formed is completely. It is optimized for the ion species to be insulated and the implantation conditions.

  Next, the base mesa region 20 and the base epiresistance element region 29 are formed by the same method as when the emitter mesa region 19 is formed. In addition, since the high resistance region 27 formed in advance overlaps all the base epiresistance elements, there is no portion shown as a normal base epiresistance element 28 (FIG. 5C).

  Next, the part other than the place where the element isolation is performed is protected with a resist, and then a He + ion is implanted under an appropriate implantation condition to form the element isolation region 24 having a high resistance. Thus, the HBT region 22, the FET region 23, and the logic circuit region 25 are partitioned, and each element in the logic circuit region 25 is partitioned. Further, a part of the InGaAs channel layer 4 is partitioned by the element isolation region 24 in the horizontal direction and by the high resistance region 27 in the vertical direction. Thereby, the wiring part 26 using the InGaAs channel layer 4 is formed (FIG. 5D).

  Next, after forming the insulating film, the insulating film in the portion where the emitter electrode 16, the base electrode 15 and the collector electrode 14 are formed, and the InGaP emitter layer 8 in the portion where the base electrode 15 is formed are removed. Next, an emitter electrode 16 made of Ti / Pt / Au or the like that contacts the InGaAs emitter contact layer 10 and a base electrode made of Ti / Pt / Au or the like that contacts the GaAs base layer 7 are formed on the part from which the insulating film has been removed. 15 and a collector electrode 14 made of AuGe / Ni / Au or the like in contact with the GaAs subcollector / cap layer 5 are sequentially formed.

  Next, the insulating film in the portion where the drain electrode 11, the source electrode 12, and the channel wiring connection electrode 31 are formed is removed. Next, the drain electrode 11 made of AuGe / Ni / Au or the like that contacts the GaAs subcollector / cap layer 5, the source electrode 12, and the channel wiring connection electrode 31 are formed in the portion where the insulating film is removed. Further, after removing the insulating film in the portion where the gate electrode 13 is to be formed, the gate digging region 21 is formed by removing the GaAs subcollector / cap layer 5 in that portion. Next, the gate electrode 13 made of Ti / Al / Ti or the like in contact with the AlGaAs barrier layer 3B is formed in the gate digging region 21 (FIG. 5E).

  Next, after an insulating film is formed on the structure shown in FIG. 5E, contact portions to the formed electrodes are opened, and a first wiring layer 17 is formed thereon.

  Next, after forming an insulating film on the first wiring layer 17, the insulating film at the place where the first wiring layer 17 and the second wiring layer 18 are contacted is removed. Next, the second wiring layer 18 is formed on the portion to be connected to the first wiring layer 17 by using a plating method or the like (FIG. 5F).

  Finally, after forming a final protective film on the structure shown in FIG. 2F, the protective film of each pad and scribe line portion is removed.

Through the above steps, the semiconductor device 200 is formed.
Hereinafter, in Embodiments 1 and 2 of the present invention, ion species and ion implantation conditions used when forming the high resistance region 27 will be described.

  FIG. 6A is a graph showing ion implantation conditions and sheet resistance of the ion-implanted GaAs base layer 7 and InGaAs channel layer 4. FIG. 6B is a graph showing ion implantation conditions and leakage current between the InGaAs channel layer 4 and the upper layer (GaAs base layer 7). Moreover, the horizontal axis of FIG. 6A and FIG. 6B is the implantation energy of ion implantation. Moreover, the vertical axis | shaft of FIG. 6A is a sheet resistance value, and the vertical axis | shaft of FIG. 6B is a leakage current.

  Here, in the semiconductor devices 100 and 200 according to the first and second embodiments of the present invention described above, the ion species and the implantation conditions used for forming the high resistance region 27 are as shown in FIGS. 6A and 6B. In consideration of the sheet resistances 51 and 52 of the ion-implanted GaAs base layer 7, the sheet resistances 53 and 54 of the InGaAs channel layer 4, and the leakage currents 55 and 56 between the InGaAs channel layer 4 and the upper layer illustrated in FIG. The conditions are optimized.

  Specifically, as a first condition, leakage currents 55 and 56 between the InGaAs channel layer 4 and the upper layer thereof need to be sufficiently small. That is, the high resistance region 27 needs to be insulated. For example, when it is desired to set the leakage currents 55 and 56 to 0.01 or less, as shown in FIG. 6B, the ion species A may be ion-implanted under the condition of ion implantation acceleration energy of 50 to 150 keV.

  As a second condition, it is preferable that the sheet resistance value of the InGaAs channel layer 4 does not change from the case where ion implantation is not performed. Therefore, as shown in FIG. 6A, the ion species A may be ion-implanted under the condition of an ion implantation acceleration energy of 125 keV or less, or the ion species B may be ion-implanted.

  As a third condition, the sheet resistance value of the GaAs base layer 7 (base epiresistance element region 29) needs to be set to a desired high resistance value. Therefore, it is only necessary to select a condition that can achieve a desired sheet resistance value within a range that satisfies the above conditions 1 and 2. In this example, it is only necessary to select a condition that can realize a desired sheet resistance value among the conditions of the ion implantation acceleration energy of 50 to 125 keV for the ion species A.

  For example, when the sheet resistance value of the base epiresistance element region 29 is about 10 times that of the GaAs base layer 7 of the HBT region 22, the ion species A may be ion-implanted under the condition of ion implantation acceleration energy of about 125 keV.

A plurality of ion species may be ion-implanted when forming the high resistance region 27.
In the semiconductor device 200 according to the second embodiment of the present invention formed as described above, the wiring portion 26 is vertically arranged with respect to all the base epiresistance elements on the chip regardless of the logic circuit region 25 and other regions. Ion implantation for forming the high resistance region 27 partitioned in the direction is performed. Thereby, all the base epi-resistance elements are the base epi-resistance element regions 29 having a high sheet resistance. Therefore, the semiconductor device 200 can realize the same resistance value with a smaller area.

  Hereinafter, the effect of reducing the chip size of the semiconductor device 200 according to the second embodiment of the present invention will be described.

  FIG. 3 shows a comparative example of chip sizes between the semiconductor devices 100 and 200 according to the first and second embodiments of the present invention and a conventional semiconductor device. As can be seen from FIG. 3, the semiconductor device 200 according to the second embodiment of the present invention can further reduce the chip size than the semiconductor device 100 according to the first embodiment.

  Furthermore, the sheet resistance of the base epiresistance element can be adjusted with reference to the relationship shown in FIGS. 6A and 6B. Therefore, by taking into account characteristics, controllability, manufacturing cost, etc., by using a plurality of ion species under different conditions, etc., by using optimal conditions such that the sheet resistance of the base epiresistance element becomes high resistance, It is possible to further reduce the area.

  Furthermore, the increase in sheet resistance in the base epiresistance element region 29 naturally has no influence on the portion of the GaAs base layer 7 used as the HBT device. Therefore, the high frequency characteristics of the HBT device are not impaired at all.

  Further, as shown in FIG. 3, not only in the logic circuit region 25 but also in all base epiresistance elements on the chip, ion implantation for forming the high resistance region 27 that partitions the wiring portion 26 in the vertical direction is performed. By applying, the chip size can be further reduced.

  From the above, the semiconductor device 200 according to the second embodiment of the present invention can realize a reduction in manufacturing cost due to area saving.

  The semiconductor device and the manufacturing method thereof according to the present invention have been described based on the first and second embodiments. However, the present invention is not limited to these first and second embodiments. Unless it deviates from the meaning of the present invention, various modifications conceived by those skilled in the art have been made in this embodiment, and forms constructed by arbitrarily combining components in different embodiments are also within the scope of the present invention. included.

  For example, the material of each component shown above is an example, and other materials that can obtain the same effect may be used.

  Moreover, in each said figure, although the corner | angular part and edge | side of each component are described linearly, what rounded the corner | angular part and edge | side is also included in this invention for the reason on manufacture.

  In the above description, the semiconductor devices 100 and 200 including the base epiresistance element 28 formed using the epilayer used as the base layer of the HBT (GaAs base layer 7) have been described. The present invention can be similarly applied to a semiconductor device including a collector epiresistance element formed by using an epilayer used as a subcollector layer (GaAs subcollector / cap layer 5).

  In this case, the high resistance region that vertically insulates the collector epiresistance element and the wiring portion 26 is the GaAs subcollector / cap layer 5 that is an active layer between the collector epiresistance element and the wiring portion 26. This is a region in which at least one of the lower layer side and the AlGaAs barrier layer 3B has a high resistance by ion implantation.

  In general, the sheet resistance value of the base epiresistance element 28 is several hundred Ω / □, and the sheet resistance value of the collector epiresistance element is several tens Ω / □. Thus, the base epiresistance element 28 has a higher sheet resistance value than the collector epiresistance element. In addition, it is easier to form the high resistance region 27 when the base epiresistance element 28 is used than when the collector epiresistance element is used. For these reasons, it is more preferable to apply the present invention to a semiconductor device including the base epiresistance element 28.

  INDUSTRIAL APPLICABILITY The present invention is useful for a semiconductor device that operates in a high frequency band and a manufacturing method thereof, and is particularly suitable for a semiconductor device using a field effect transistor as a switching element.

DESCRIPTION OF SYMBOLS 1,701 Semi-insulating GaAs substrate 2,702 GaAs / AlGaAs superlattice layer 3A, 3B, 703A, 703B AlGaAs barrier layer 4,704 InGaAs channel layer 5,705 GaAs subcollector / cap layer 6,706 GaAs collector layer 7, 707 GaAs base layer 8, 708 InGaP emitter layer 9, 709 GaAs emitter cap layer 10, 710 InGaAs emitter contact layer 11, 711 Drain electrode 12, 712 Source electrode 13, 713 Gate electrode 14, 714 Collector electrode 15, 715 Base electrode 16 , 716 Emitter electrode 17, 717 First wiring layer 18, 718 Second wiring layer 19 Emitter mesa region 20, 720 Base mesa region 21 Gate digging region 22, 722 HBT region 23, 7 3 FET region 24, 724 Element isolation region 25, 725 Logic circuit region 26 Wiring part 27 High resistance region 28, 728 Base epi resistance element 29 Base epi resistance element region 30, 730 Contact electrode 31 Channel wiring connection electrode 51, 52, 53, 54 Sheet resistance 55, 56 Leakage current 100, 200, 700 Semiconductor device

Claims (12)

A semiconductor device,
A semiconductor substrate;
A field effect transistor formed on the semiconductor substrate;
A heterojunction bipolar transistor formed on the semiconductor substrate;
A resistance element formed on the semiconductor substrate and formed using a base layer or a subcollector layer of the heterojunction bipolar transistor;
A wiring layer formed using a channel layer of the field effect transistor, and a wiring layer connected to the field effect transistor, the heterojunction bipolar transistor, and the resistance element;
A high-resistance region formed by increasing the resistance of the active layer between the wiring portion and the base layer or the subcollector layer, and insulating the wiring portion and the resistance element;
An insulating element isolation region surrounding the periphery of the wiring portion in a direction horizontal to the main surface of the semiconductor substrate;
The resistance element has a crossing region that crosses the wiring part when viewed from a direction perpendicular to a main surface of the semiconductor substrate. The semiconductor device includes:
A field effect transistor region in which the field effect transistor is formed;
A heterojunction bipolar transistor region in which the heterojunction bipolar transistor is formed;
A logic circuit region in which a control circuit including the resistance element is formed,
The element isolation region is formed at a boundary between the field effect transistor region, the heterojunction bipolar transistor region, and the logic circuit region, and the field effect transistor region, the heterojunction bipolar transistor region, and the logic circuit. Insulate the area,
The semiconductor device according to claim 1, wherein the wiring portion is formed in the logic circuit region. The semiconductor device according to claim 1, wherein the high-resistance region is a region whose resistance is increased by ion implantation of first ions into the active layer. The semiconductor device according to claim 3, wherein the element isolation region is a region whose resistance is increased by performing ion implantation on at least a part of the active layer and the channel layer. The semiconductor device according to claim 3, wherein the intersection region has a higher resistance value than the base layer or the subcollector layer included in the heterojunction bipolar transistor. The semiconductor device according to claim 5, wherein the crossing region is increased in resistance by ion implantation of the first ions into the base layer or the subcollector layer. The semiconductor device according to claim 6, wherein the intersection region included in the resistance element has a higher resistance value than regions other than the intersection region included in the resistance element. The semiconductor device according to claim 6, wherein the resistance element includes a region having a resistance value higher than that of the base layer or the subcollector layer of the heterojunction bipolar transistor in addition to the intersection region. A method for manufacturing a semiconductor device, comprising:
A field effect transistor forming step of forming a field effect transistor on a semiconductor substrate;
Forming a heterojunction bipolar transistor on the semiconductor substrate;
Forming a resistance element using a base layer or a subcollector layer of the heterojunction bipolar transistor on the semiconductor substrate; and
A wiring layer forming step including a wiring portion formed using a channel layer of the field effect transistor, and forming a wiring layer connected to the field effect transistor, the heterojunction bipolar transistor, and the resistance element;
A high resistance region forming step for forming a high resistance region that insulates the wiring portion from the resistance element by increasing the resistance of the active layer between the wiring portion and the base layer or the subcollector layer. When,
An element isolation region forming step for forming an element isolation region surrounding the periphery of the wiring portion in a direction horizontal to the main surface of the semiconductor substrate;
The resistance element has an intersecting region intersecting with the wiring portion when viewed from a direction perpendicular to a main surface of the semiconductor substrate. The method of manufacturing a semiconductor device according to claim 9, wherein in the high resistance region forming step, the high resistance region is formed by implanting first ions into the active layer. In the high resistance region forming step, the high resistance region is formed by simultaneously implanting the first ions into the active layer and the base layer or the subcollector layer, and the heterojunction bipolar transistor. The method of manufacturing a semiconductor device according to claim 10, wherein the crossing region having a resistance value higher than that of the base layer or the subcollector layer is formed. In the high resistance region forming step, the first ions are implanted into the active layer and the base layer or the subcollector layer at the same time, so that the region other than the intersecting region is included in the resistor element. The method of manufacturing a semiconductor device according to claim 11, wherein a resistance value of the region is higher than a resistance value of the base layer or the subcollector layer of the heterojunction bipolar transistor.

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