201246392 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種開關元件，且特別是有關於—種 具有漏電流抑制層（leakage current restrain layer)以及材料 誘發空乏區(material-induced depletion region)之開關元件。 【先前技術】 近年來’薄膜電晶體在液晶顯示器（Liquid Crystal201246392 VI. Description of the Invention: [Technical Field] The present invention relates to a switching element, and more particularly to a leakage current restraining layer and a material-induced depletion region (material-induced depletion) Switching element of region). [Prior Art] In recent years, thin film transistors are in liquid crystal displays (Liquid Crystal)
Display ’ LCD)的應用曰趨廣泛，且相關的產品也在陸續量 產中。一般而言，薄膜電晶體大致上可區分為非晶矽薄膜 電晶體、多晶矽薄膜電晶體、氧化物半導體薄膜電晶體等。 不論是何種型態之薄膜電晶體，其在關閉狀態(〇ff state) 下的漏電流是無法完全避免的。漏電流產生的原因主要是 因為通道層的厚度過厚以及製程條件（如通道層的沈積條 件、主動層之後製程（如紫外光照射）、離子佈植之製程條 件等）不穩定所導致。當通道層的厚度過後或者形成通道 層之製程條件不穩定時，閘極對於通道層的控制能力便會 下降’導致背通道效應(back channel effect)。詳言之，在 與源極以及汲極接觸之通道層表面上會有漏電路徨 (leakage path)產生，此位於源極與沒極之間的漏電路徑將 使得漏電流無法被抑制’進而導致薄膜電晶體的電氣特性 惡化。 承上述，如何進一步改善薄膜電晶體的電氣特性，以 有效降低薄膜電晶體在關狀態下的漏電流，實為研發表 201246392 目前亟欲解決的問題之一。 【發明内容】 本發明提供一種具有漏電流抑制層以及由漏電流抑 制層誘發所形成之材料誘發空乏區之開關元件。 本發明提供一種開關元件，其包括一閘極、一通道 層、一閘絕緣層、一源極、一汲極以及一漏電流抑制層。 閘絕緣層配置於閘極與通道層之間，源極與没極分別與通 道層接觸，且源極與汲極彼此分離。漏電流抑制層配置於 通道層上，漏電流抑制層位於源極與汲極之間以於通道層 中形成一材料誘發空乏區。 在本發明之一實施例中，前述之漏電流抑制層不與源 極以及>及極接觸。 在本發明之一實施例中，前述之漏電流抑制層係電性 浮置(electrical floating)。 在本發明之一實施例中，前述之漏電流抑制層係電性 柄接於一固定電位。 在本發明之一實施例中’前述之漏電流抑制層與源極 電性連接或與沒極電性連接。 在本發明之一實施例中，前述之源極與汲極之材質相 同，而源極以及汲極之材質與漏電流抑制層之材質不同。 在本發明之一實施例中，前述之漏電流抑制層之材質 包括半導體或金屬。 在本發明之一實施例中，前述之通道層之材質包括矽 基(silicon-based)半導體、錯基(germanjum_based)半導體或 201246392 金屬氧化物半導體。 括-進-步包 喪韻刻終止層中並與通層’_電流抑制層係 括一 ίί=Γ=、中’前述之關元件可進一步包 蓋部分源極^分祕，、5極之賴層，射通道層係覆 並與通道層_ _電射卩婦錢於保護層中 其中通道層繼：源:=r制層之保護層， 電流:之:具制層以及由漏 開關良好的電氣特：二= 易懂:下之上述和其他目的、特徵和優點能更明顯 明如下 較佳實施例，並配合所附圖式，作詳細說 【實施方式】 【第一實施例】 铁來本f明第—實施例之主動元件的剖面示意圖。 t…圖本實施例之開關元件10〇包括一閘極G、一Display ’ LCDs are becoming more widely used and related products are in production. In general, a thin film transistor can be roughly classified into an amorphous germanium thin film transistor, a polycrystalline germanium thin film transistor, an oxide semiconductor thin film transistor, or the like. Regardless of the type of thin film transistor, the leakage current in the off state (〇ff state) cannot be completely avoided. Leakage current is mainly caused by the thickness of the channel layer being too thick and the process conditions (such as the deposition conditions of the channel layer, the process after the active layer (such as ultraviolet light irradiation), the process conditions of ion implantation, etc.). When the thickness of the channel layer is over or the process conditions for forming the channel layer are unstable, the gate's ability to control the channel layer is reduced, resulting in a back channel effect. In detail, there is a leakage path on the surface of the channel layer in contact with the source and the drain, and the leakage path between the source and the gate will prevent the leakage current from being suppressed. The electrical characteristics of the thin film transistor deteriorate. In view of the above, how to further improve the electrical characteristics of the thin film transistor to effectively reduce the leakage current of the thin film transistor in the off state is one of the problems currently being solved by the research and development table 201246392. SUMMARY OF THE INVENTION The present invention provides a switching element having a leakage current suppressing layer and a material induced depletion region induced by a leakage current suppressing layer. The invention provides a switching element comprising a gate, a channel layer, a gate insulating layer, a source, a drain and a leakage current suppressing layer. The gate insulating layer is disposed between the gate and the channel layer, the source and the gate are respectively in contact with the channel layer, and the source and the drain are separated from each other. The leakage current suppression layer is disposed on the channel layer, and the leakage current suppression layer is located between the source and the drain to form a material induced depletion region in the channel layer. In one embodiment of the invention, the leakage current suppression layer is not in contact with the source and > and the pole. In an embodiment of the invention, the leakage current suppression layer is electrically floating. In an embodiment of the invention, the leakage current suppression layer is electrically connected to a fixed potential. In an embodiment of the invention, the aforementioned leakage current suppression layer is electrically connected to the source or is not electrically connected. In an embodiment of the invention, the source and the drain are made of the same material, and the source and the drain are different in material from the leakage current suppression layer. In an embodiment of the invention, the material of the leakage current suppressing layer comprises a semiconductor or a metal. In an embodiment of the invention, the material of the channel layer comprises a silicon-based semiconductor, a germanjum-based semiconductor or a 201246392 metal oxide semiconductor. Including the -in-step package, the singularity of the layer is terminated in the layer and the layer _ current suppression layer is provided with a ίί=Γ=, the middle part of the above-mentioned element can further cover part of the source, and 5 poles Lay layer, the channel layer is covered and the channel layer _ _ 电 卩 钱 钱 保护 保护 保护 保护 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在The first embodiment and the other objects, features and advantages will be more apparent from the following preferred embodiments, and in conjunction with the drawings, a detailed description of the embodiments [first embodiment] A schematic cross-sectional view of an active component of the present invention. t... The switching element 10 of the embodiment of the present invention includes a gate G, a
電士:二〗閘絕緣層GI、一源極s、-汲極0以及-漏 Up制層110。閘絕緣層GI配置於閘極G與通道層C 201246392 之間’源極s與汲極D分別與通道層c接觸， 與沒極D彼此分離。此外，漏電流抑制層UG配置於 層c上’且漏電流抑制層11〇位於源極§與没極 於通道f C中形成一材料誘發空乏區12〇。 從圖1可知，本實施例之源極s與汲極D ，層C的部分區域上，且漏電流抑制層J不= =及沒極D接觸。舉例而言，本實施例之 =例如是電性浮置，或者是_於—固定電位。層 2^並3定漏電流抑制層110不得與源極8以及沒極 接觸’在其他可行的實關巾，漏電流抑制層11〇 擇性地與源極S電性連接或是無極D電性連接。此時， 漏電流抑制層11〇的電位便與所電性連接的源極s或没極 f相同。值得注意的是，漏電流抑制層⑽The electrician: two sluice insulation layer GI, a source s, - 汲 0 and - drain Up layer 110. The gate insulating layer GI is disposed between the gate G and the channel layer C 201246392. The source s and the drain D are in contact with the channel layer c, respectively, and are separated from the gate D. Further, the leakage current suppressing layer UG is disposed on the layer c' and the leakage current suppressing layer 11 is located at the source § and the non-polar channel f C to form a material-induced depletion region 12A. As can be seen from FIG. 1, the source s of the present embodiment is in a partial region of the drain D and the layer C, and the leakage current suppressing layer J is not == and the gate D is in contact. For example, the present embodiment is, for example, electrically floating, or is - fixed potential. The layer 2^3 constant leakage suppression layer 110 must not be in contact with the source 8 and the immersion pole. In other feasible real cleaning wipes, the leakage current suppression layer 11 is selectively electrically connected to the source S or the poleless D electricity. Sexual connection. At this time, the potential of the leakage current suppressing layer 11 is the same as that of the electrically connected source s or the dipole f. It is worth noting that the leakage current suppression layer (10)
極S以及祕D電性連接。 f丨U 請繼續參照圖1，主動元件励中的源極s與没極d 例^是採肋晴質製作，舉㈣言，源極§纽極〇例 如是藉由圖案化（例如微影侧製程）同—層導體層所形 成的。源極s與通道層c之間以及汲極D與通道層曰c ‘ 間會形成歐姆接觸(ohmic c〇ntact)e此外，源極s以^汲極 D之材質與漏電流抑制層110之材質不同，舉例而言' 源 =S與沒極D是藉由圖案化（例如微影餘刻製程一層、The pole S and the secret D are electrically connected. f丨U Please continue to refer to Figure 1, the source s and the immersion d in the active component excitation are made of ribs, and (4), the source § 〇 〇 is, for example, patterned (eg lithography) Side process) formed by the same layer conductor layer. An ohmic contact is formed between the source s and the channel layer c and between the drain D and the channel layer 曰c '. In addition, the source s is made of the material of the drain D and the leakage current suppressing layer 110. Different materials, for example, 'source=S and immersion D are patterned by (for example, lithography process layer,
St形ί的’而漏電流抑制層110是藉由圖案化(； 另一層導體層所形成的，本實施例不限 疋彝極S、汲極D與漏電流抑制層110的形成順序。 在本實施例中，漏電流抑制層110之材質例如為半導 201246392 體（例如矽、鍺、矽鍺化合物、銦錫氧化物或錮鋅氧化物） 或金屬（例如金、銀、妃、翻、鎢或鉬），而通道層c之 材質包括矽基半導體、鍺基半導體或金屬氧化物半導體（例 如銦的氧化物、鎵的氧化物、鋅的氧化物、錫的氧化物、 鉬的氧化物、鈒的氧化物、銻的氧化物、鉍的氧化物、銖 的氧化物、钽的氧化物、鎢的氧化物、鈮的氧化物或鎳的 氧化物）。 當漏電流抑制層110之材質為矽、鍺或矽鍺化合物 時，由於半導體可以透過摻雜的方式調整其本身的費米能 階(Fermi-level)’因此通道層c之材質可以從矽基半導體、 鍺基半導體以及金屬氧化物半導體中任意選擇。此時，只 要漏電流抑制層110之摻雜型態與通道層c的摻雜型態相 同（同為P型摻雜或同為N型掺雜），便可在通道層c中 形成材^料誘發空乏區120以達到抑制漏電流的效果。 當漏電流抑制層110之材質為銦錫氧化物或銦鋅氧化 物，而通道層C之材質為矽基半導體、鍺基半導體時，由 於銦錫氧彳b物或轉氧化物㈣函數(丽k funetiQn)接近 =錯或石夕鍺化合物之中間能帶(middle_band)，因此漏電 机P制層110與通道層c之間會形成蕭基接觸(Sch〇 Γ：ΓΓ)以於通道層C中形成材料誘發空乏區120，進而達 到抑制漏電流的效果。 物，制層110之材質為銦錫氧化物或銦鋅氧化 物或銦鋅n之材f為金屬氧化物半導體時，銦錫氧化 數由的功函數肢金屬氧㈣半導體的功函 …、通道層c之金屬氧化物半導體為離子晶體，The St-shaped '' leakage current suppressing layer 110 is formed by patterning (the other conductive layer is formed, and the present embodiment is not limited to the formation order of the drain S, the drain D, and the leakage current suppressing layer 110. In this embodiment, the material of the leakage current suppression layer 110 is, for example, a semiconductor semiconductor such as a semiconductor, a germanium, a germanium compound, an indium tin oxide or a germanium zinc oxide, or a metal (for example, gold, silver, germanium, turn, Tungsten or molybdenum), and the material of the channel layer c includes a germanium-based semiconductor, a germanium-based semiconductor or a metal oxide semiconductor (for example, an oxide of indium, an oxide of gallium, an oxide of zinc, an oxide of tin, an oxide of molybdenum) , oxides of cerium, oxides of cerium, oxides of cerium, oxides of cerium, oxides of cerium, oxides of tungsten, oxides of cerium or oxides of nickel). Materials of leakage current suppression layer 110 When it is a ruthenium, osmium or iridium compound, since the semiconductor can adjust its own Fermi-level by doping, the material of the channel layer c can be oxidized from a ruthenium-based semiconductor, a ruthenium-based semiconductor, and a metal. Arbitrary choice in semiconductors At this time, as long as the doping profile of the leakage current suppression layer 110 is the same as the doping profile of the channel layer c (same as P-type doping or the same N-type doping), the material can be formed in the channel layer c. The material induces the depletion region 120 to achieve the effect of suppressing leakage current. When the material of the leakage current suppression layer 110 is indium tin oxide or indium zinc oxide, and the material of the channel layer C is a germanium-based semiconductor or a germanium-based semiconductor, The indium tin oxide bismuth b or the conversion oxide (four) function (Li k funetiQn) is close to the middle band of the wrong or shixi compound, so the base of the leakage motor P layer 110 and the channel layer c will form Xiaoji. The contact (Sch〇Γ: ΓΓ) is formed in the channel layer C to induce the depletion region 120, thereby achieving the effect of suppressing leakage current. The material of the layer 110 is made of indium tin oxide or indium zinc oxide or indium zinc n. When the material f is a metal oxide semiconductor, the work function of the indium tin oxidation number is the work function of the metal oxygen (four) semiconductor, and the metal oxide semiconductor of the channel layer c is an ionic crystal.
7 S 2012463927 S 201246392
漏電流抑制層110與通道層C 層no能夠提供氧原子至通道1不同’且漏電流抑制 因此漏電流抑制層11〇與通道曰令M抑制背通道效應， 觸(Schottky contact),伸仍日之間雖不會形成蕭基接 當漏電流抑制電流的效果。 於金屬的功函數與石夕基半匕物半導體時，由 半導體的功函數不同體或金屬氧化物 流抑制層U0。舉例而言，當、金屬作為漏電 電流抑制層H0的材質例如為，；或：： ㈣換雜時，漏電流抑制層㈣的材質例如為田金、=白 【第二實施例】 請二第r:施例之主動元件的剖面示意圖。 =關元件類似，惟二者丄= ==件：:r步包括-配置於通道層c上 層、nn曰S與及極D覆蓋部分的姓刻終止 層130以及部分的通道層c，而 餘刻終止層130中並與通道層C接觸層0係嵌於 【第三實施例】 圖3林發明第三實_之线元件_面示意圖。 »月 圖1與圖3 ’本實施例之開關元件刚，， 例之開關元件腦類似，惟二者主要差異之處仙^實 201246392 施例之主動元件1〇〇”進-步包括一覆蓋通道層c，、源極s 與沒極D之賴層14G，而通道層c，係覆蓋部分源極s盘 部分没極D，且漏電流抑制層11〇係嵌於保護層14 ^ 與通道層C’接觸。 【第四實施例】 圖4為本發明第四實施例之主動元件的剖面示意圖。 請參照圖3與圖4 ’本實施例之開關元件1〇〇,，，盘第三每 施例之開關元件置，類似’惟二者主要差異之處在於:： 實施例之主動元件·，，進-步包括—覆錢道層c，、源 極3、汲極0與漏電流抑制層11〇之保護層14〇。詳言之， 漏電流抑制層110未外露。 13 【實驗例】 圖5A至圖5C為閘極電壓(gate v〇ltage)與汲極電流 (drain current)之關係圖。請參照圖5A’當通道層之材質為 氧化銦鎵鋅(IGZO) ’而無漏電流抑制層11〇設置時，從各 個閘極電壓歧㈣流之_曲_斷，线元件的臨界 電壓(Vth)飄移的十分嚴重。 请參知圖5B ’為了解決臨界電壓(νΛ)飄移的問題， 可利用紫外紐射的方式使臨界電壓(Vth)，但若紫外光照 射的控制不當極有可能導致氧化銦鎵鋅(IGZ〇)的半導體 特性喪失’如圖5B所tf。意即，氧化銦鎵鋅(IGZ〇)會因 漏電流路徑而讓源極與沒極意外導通。 请爹照圖5C ’本發明藉由設置漏電流抑制層，此處 9 201246392 漏電流抑制層之材質為金(Au) ’可以讓氧化銦鎵鋅(igz〇) 層中產生材料誘發空乏區120,進而使氧化銦鎵鋅(IGZ〇) 層的半導體特性恢復，並且阻斷漏電流路徑。 由於本發明之開關元件具有漏電流抑制層以及由漏 電流抑制層所誘發形成之材料誘發空乏區，因此本發明之 開關元件具有穩定且良好的電氣特性。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1為本發明第一實施例之主動元件的剖面示意圖。 圖2為本發明第二實施例之主動元件的剖面示意圖。 圖3為本發明第三實施例之主動元件的剖面示意圖。 圖4為本發明第四實施例之主動元件的剖面示意圖。 圖5A至圖5C為閘極電壓(gate voltage)與没極電流 (drain current)之關係圖。 【主要元件符號說明】 100、100’、100”、100’’’ ：主動元件 Π0 :漏電流抑制層 120 :材料誘發空乏區 13 0 :餘刻終止層 201246392 140 :保護層 G :閘極 GI :閘絕緣層 C、C，：通道層 S :源極 D :汲極The leakage current suppressing layer 110 and the channel layer C layer no can provide oxygen atoms to the channel 1 differently' and the leakage current is suppressed. Therefore, the leakage current suppressing layer 11〇 and the channel 曰M suppress the back channel effect, and the touch (Schottky contact) is extended. Although there is no effect between Xiaoji and the leakage current suppression current. In the case of the work function of the metal and the Shihki semiconductor semiconductor, the layer U0 is suppressed by the work function of the semiconductor or the metal oxide flow. For example, when the material of the metal as the leakage current suppression layer H0 is, for example, or: (4), the material of the leakage current suppression layer (4) is, for example, Tian Jin, = white [Second embodiment] r: Schematic diagram of the active element of the embodiment. = the closing element is similar, but the two 丄 = = = piece:: r step includes - the upper layer of the channel layer c, the nn曰S and the portion of the pole D covering the stop layer 130 and the part of the channel layer c, while In the engraving stop layer 130 and in contact with the channel layer C, the layer 0 is embedded in the third embodiment. »月图1 and Fig.3 'The switching element of this embodiment is just the same as the switching element brain of the example, but the main difference between the two is the fact that the active component of the example 2012. The channel layer c, the source s and the immersion layer 14G, and the channel layer c cover part of the source s disk portion of the pole D, and the leakage current suppression layer 11 is embedded in the protective layer 14 ^ and the channel [Fourth Embodiment] Fig. 4 is a cross-sectional view showing an active device according to a fourth embodiment of the present invention. Referring to Figures 3 and 4, the switching element of the present embodiment is 〇〇, The switching element of each embodiment is similar to 'the only difference between the two is:: the active component of the embodiment ·, the step-by-step includes - the methane layer c, the source 3, the drain 0 and the leakage current The protective layer 14 of the suppression layer 11A. In detail, the leakage current suppressing layer 110 is not exposed. 13 [Experimental Example] FIGS. 5A to 5C show the gate voltage (gate v〇ltage) and the drain current (drain current). Refer to Figure 5A' when the material of the channel layer is indium gallium zinc oxide (IGZO)' and no leakage current suppression layer 11〇 From the threshold voltage (four) of each gate voltage, the threshold voltage (Vth) of the line component drifts very seriously. Please refer to Figure 5B. In order to solve the problem of the critical voltage (νΛ) drift, UV beam can be used. The way to make the threshold voltage (Vth), but if the improper control of ultraviolet light irradiation is very likely to cause the loss of semiconductor properties of indium gallium zinc oxide (IGZ〇) as shown in Figure 5B tf. That is, indium gallium zinc oxide (IGZ〇) The source and the pole are accidentally turned on due to the leakage current path. Please refer to Figure 5C'. The present invention is provided with a leakage current suppression layer, where the material of the leakage current suppression layer is gold (Au). The material in the indium gallium zinc oxide (igz〇) layer induces the depletion region 120, thereby recovering the semiconductor characteristics of the indium gallium zinc oxide (IGZ〇) layer and blocking the leakage current path. Since the switching element of the present invention has leakage current suppression The layer and the material induced by the leakage current suppression layer induce a depletion region, and thus the switching element of the present invention has stable and good electrical characteristics. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. It is to be understood that the scope of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing an active device according to a first embodiment of the present invention. Fig. 2 is a cross-sectional view showing an active device according to a second embodiment of the present invention. Fig. 3 is a cross-sectional view showing an active device according to a third embodiment of the present invention. Fig. 4 is a cross-sectional view showing an active device according to a fourth embodiment of the present invention. Fig. 5A to Fig. 5C are diagrams showing a relationship between a gate voltage and a drain current. [Explanation of main component symbols] 100, 100', 100", 100"': active element Π 0: leakage current suppression layer 120: material induced depletion region 13 0: residual termination layer 201246392 140: protective layer G: gate GI : Gate insulation C, C,: Channel layer S: Source D: Bungee