201245731 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種使用對例如LSI(Large Scale Integration，大型積體電路）元件、或LED(Light Emitting Diode，發光二極體）元件及雷射元件等發光元件等檢查對 • 象裝置檢查ESD(Electro-Static discharge，靜電釋放）耐性 . 之ESD測試裝置來進行高電壓施加檢查之高電壓檢查裝 置。 【先前技術】 先前，就LSI元件而言係於輸入電路側連接有保護二極 體’檢查保護二極體之ESD耐性。就LED元件及雷射元件 等發光元件而言’發光元件本身具有二極體構造。該二極 體構造係由p型擴散層與η型擴散層之pn接面所構成，故而 ESD耐性根據p型擴散層與n型擴散層之接合結果而不同， 因此必須全數檢查ESD耐性。 先前之ESD施加所必需之基本之ESD電路係由高電壓電 源、遵循ESD規格（HBM(Human Body Model，人體模式）、 MM(Machine Model，機械模式）等）之高壓電容器、使用有 施加電阻及水銀之高耐壓繼電器所構成。 ESD電路之施加輸出部分係使用將用以相對於裝置之端 子而連接之接觸探針固定搭載於基板上而形成之探針卡、 或將該接觸探針固定於支臂上而形成之操作器等向檢查對 象之裝置通電。 向檢查對象之裝置之供給電壓之大小係以可靠性檢查中 163040.doc 201245731 具代表性之ESD測試（靜電釋放可靠性測試）等作為對象， 以大概1〜10 KV位準之高電壓作為對象。對來自人體或機 械之靜電流入LSI晶片等檢查對象之裝置中之情形時之耐 久性進行測試。 圖21係模式性地表示先前之E s 〇測試裝置之構成例之電 路圖。 於圖21中’先前之ESD測試裝置1〇〇中，高電壓電源 之一端子通過高耐壓繼電器102、1〇3連接於施加電阻ι〇4 之一端。該施加電阻104之另一端連接於檢査對象之裝置 105之一端子。裝置1〇5之另一端子連接於高電壓電源ι〇1 之另一端子。該等高耐壓繼電器102、1〇3之連接點通過高 壓電容器106’連接於裝置1〇5之另一端子與高電壓電源 101之另一端子之連接點’且該連接點接地。設置有控制 該等高对壓繼電器102、103之接通/斷開之時序控制器 107。用以驅動該等尚咐壓繼電器1〇2、1〇3之電源需要另 外設置》 根據上述構成，首先，藉由時序控制器1〇7而充電用高 耐壓繼電器102接通且來自高電壓電源1 〇 1之電流儲存於高 壓電容器106中。此時，放電用高耐壓繼電器1〇3藉由時序 控制器107而成為斷開狀態。 其次，於藉由時序控制器107而充電用高耐壓繼電器1〇2 斷開之後，以使放電用高耐壓繼電器103接通之方式進行 控制。藉此，儲存於高壓電容器106中之高電壓自高耐壓 繼電器103通過施加電阻1 〇4施加至檢查對象之裝置105之 163040.doc 201245731 一端子。 如此，可藉由時序控制器107對該等充電用高耐壓繼電 器102、放電用高耐壓繼電器103進行接通/斷開切換，對 高壓電容器106充電或放電，向檢查對象之裝置105施加特 定之高電壓。充電用高耐壓繼電器102、放電用高耐壓繼 電器103之切換動作係藉由時序控制器107以規定之時序進 行。ESD測試藉由數種施加模式、與分別決定有規格向檢 查對象之裝置105施加之電流波形（或電壓波形）而判斷是否 適合。 综上所述，ESD測試係自高電壓電源經由ESD施加電 路、進而經由插座、支臂等接觸失具向檢查對象之裝置施 加高電壓。使高電壓之供給源側端子〇根）及 GND(GroUnd ’地面）側蜱子（1根）與檢查對象之裝置之各端 子接觸從而對檢查對象之裝置施加高電壓。於該情形時， 檢查對象之裝置係單體地進行高電壓施加處理。儘管有將 檢查對象之裝置組成複數組之裝置，但實際之ESD測試係 連續地改變端子而進行處理。此情況於專利文獻2中有所 揭示。與此相對地，量產地進行ESD測試之情況於專利文 獻1中有所揭示。 圖22係模式性地表示專利文獻i中所揭示之先前之ESD 測試裝置之構成例之立體圖。 於圖22中’作為先前之ESD測試裝置之靜電釋放測試用 炎具200係以如下方式運作者：於對安裝有電子零件加之 P刷配線板202進行靜電釋放測試時，使用下一個測試用 163040.doc 201245731 夹具，於1次測試中使靜電同時向複數片印刷配線板2〇2施 加。於在作為被測試對象物之載置台而準備之導電板2〇3 之板上一角設定靜電施加點之後，將把印刷配線板2〇2以 起立姿勢支持於自該靜電施加點分別每隔開等距離之位置 處之複數個印刷板支持具204排列成放射狀而分散配備。 又’具備與靜電施加點對準位置而組裝靜電產生搶2〇5之 搶保持具206。於各印刷板支持具204上將印刷配線板2〇2 逐片地以使其沿其配線圖案202a與導電板203導通接觸之 方向起立之姿勢充電，並於該狀態下自靜電產生搶2〇5向 靜電施加點釋放靜電。藉此，自靜電產生搶205，統一地 使靜電向經由導電板203而載置於板上之複數片各印刷配 線板202施加。從而，可於1次測試中使靜電同時向複數片 印刷電路板202施加而謀求準備時間之縮短化。 [先行技術文獻] [專利文獻] [專利文獻1]日本專利特開2005-201706號公報 [專利文獻2]曰本專利特開2000-32981 8號公報 【發明内容】 [發明所欲解決之問題] 於專利文獻1中所揭示之上述先前之靜電釋放測試用夾 具200中，靜電產生搶2〇5即施加源為單體，與此相對地檢 査對象之裝置存在複數個，因此存在對於各個檢查對象之 裝置’難以證明是否進行了適合於規定電壓/規定次數之 規格之ESD施加之問題。综上所述，由於ESD施加時之極 163040.doc 201245731 小之距離差異，所以有對複數個裝置中之一個裝置主要地 施加ESD施加電壓之虞，從而無法成為明確之副施加測 試。 本發明係解決上述先前之問題者，其目的在於提供可對 檢查對象之複數個裝置統一地，以適合於規格之電流波形 (或電壓波形）明確且正確地進行高電壓施加測試，大幅且 高效地進行高電壓檢查之高電壓檢查裝置。 尤其，於形成在同一半導體晶圓上之多個裝置中，當對 檢查對象之複數個裝置統一地，以適合於規格之電流波形 (或電壓波形）明確且正確地進行高電壓施加測試之情形 時，如圖12所示，若於正電源下設^反向偏壓之狀態，則 產生會自裝置6之陰極端子向鄰接裝置6之陽極端子之短 路，所施加之電荷量分散於n_GaN基板上，自相同裝置6之 陰極端子通過陽極端子之電荷量變得不定。當混雜有短路 不良之情形時，於短路位置處貫通之電荷集中，因此自 ESD規定脫離。 本發明係解決上述先前之問題者，其目的在於提供即便 於對檢查對象之複數個裝置統一地，以適合於規格之電流 波形（或電壓波形）明確且正確地進行高電壓施加測試之情 形時，亦可以簡單之構成不混雜有短路不良地，大幅且高 效地進行高電壓檢查之高電壓檢查裝置。 又，尤其，於專利文獻2中所揭示之上述先前之先前之 ESD測試裝置1〇〇中，利用使用有水銀之高耐壓繼電器。 該使用有水銀之高耐壓繼電器不僅高價，且由於使用有水 163040.doc 201245731 銀而成為限制對象（RoHS指令，（Restrjcti〇n 〇f Hazardous Substances)，《關於限制在電子電器設備中使用某些有害 成分之指令》）。又，於統一地同時檢查複數個裝置之情 形時’必需多個該使用有水銀之高耐壓繼電器。又，於使 用有水銀之高耐壓繼電器中，於繼電器動作時間上會產生 msec單位之時間差。進而，必需控制高耐壓繼電器之驅動 時序之單元，並且驅動高耐壓繼電器之電源必需另外設 置。 本發明係解決上述先前之問題者，其目的在於提供可不 使用高耐壓繼電器而將整體構成簡化，以適合於規格之電 流波形（或電壓波形）進行高電壓施加測試之高電壓檢查裝 置。 [解決問題之技術手段] 本發明之尚電壓檢查裝置係對複數個檢查對象裝置檢查 ESD耐性者，且包含：高電壓電源，其輸出特定之高電 壓；及ESD電路，其分別對該複數個檢查對象裝置統一地 同時施加來自該高電壓電源之各特定之高電壓；藉由此構 成達成上述目的。 本發明之高電壓檢査裝置係對複數個檢査對象裝置檢查 ESD耐性者，i包含：高電壓電源，其輸出特定之負高電 壓’·及ESD電路’其分別對配設於半導體晶圓上之複數個 檢查對象裝置之各二極體構造以分別成為反向偏壓之方式 統-地同時施加來自該高電壓電源之各特定之負高電壓； 藉由此構成達成上述目的。 163040.doc 201245731 本發明之向電壓檢查裝置係對一個或複數個檢查對象裝 置檢查ESD耐性者，且藉由搭载有該一個或複數個檢查對 象裝置之接觸平台之上下動作，使開關機構打開/關閉， 將1對1對應於一個或複數個檢查對象裝置之各高電壓電容 機構之南電壓充電/放電，藉由來自該各高電壓電容機構 之放電進行該一個或複數個檢查對象裝置之ESD檢查；藉 由此構成達成上述目的。 又’較佳為’本發明之高電壓檢查裝置包含：高電壓電 源’其輸出特定之高電壓；上述一個或複數個高電壓電容 機構’其儲存來自該高電壓電源之特定之高電壓；及一個 或複數個高電壓輸出部，其輸出來自該一個或複數個高電 壓電容機構之特定之高電壓；且，藉由上述接觸平台之上 下動作切換第1動作與第2動作，該第1動作係使該高電壓 輸出部與上述一個或複數個檢查對象裝置之各端子隔離， 並且藉由上述開關機構將該一個或複數個高電壓電容機構 連接於該高電壓電源側；該第2動作係藉由該開關機構將 該一個或複數個高電壓電容機構與該高電壓電源斷開，並 且將該高電壓輸出部連接於上述一個或複數個檢查對象裝 置之各端子。 進而’較佳為，本發明之高電壓檢查裝置藉由搭載有複 數個檢查對象裝置之接觸平台之上下動作，使開關機構打 開/關閉，將1對1對應於複數個檢查對象裝置之各高電壓 電容機構之高電壓充電/放電，藉由來自該各高電壓電容 機構之放電而進行該複數個檢查對象裝置之ESD檢查β I63040.doc 201245731 進而’較佳為，於本發明之高電壓檢查裝置中包含：高 電壓電源其輸出特定之高電壓；上述一個或複數個高電 壓電容機構，其储存來自該高電壓電源之特定之高電壓； 個或複數個间電塵輸出部，其輸出來自該一個或複數 :高電麼電容機構之特定之高電Mi，藉由上述接觸平 =之上下動作切換第m作與第2動作，該第i動作係使該 高電壓輸出部與上述—個或複數個檢查對象裝置之各端子 隔離，並且藉由上述開關機構將該一個或複數個高電壓電 容機構連接於該高電壓電源側；該第2動作係藉由該開關 機構將該-個或複數個高電壓電容機構與該高電壓電源斷 開’並且將該高電㈣出部連接於上述—個或複數個檢查 對象裝置之各端子之第2動作。 進而，較佳為，本發明之高電壓檢査裝置中之_電路 具有應統一施加處理上述特定之高電壓之裝置個數之同一 電路構成。 進而，較佳為，本發明之高電壓檢查裝置中之esd電路 包含：複數個高電壓電容機構，其儲存來自上述高電壓電 源之特定之高電麼；複數個高電壓輸出部，其分別通過各 電阻而輸出來自該複數個高電壓電容機構之各特定之高電 壓；及複數個切換機構，其以分別連接於該高電壓電源側 或分別連接於該高電壓輸出部側之方式分別切換該複數個 高電壓電容機構。 進而，較佳為，本發明之高電壓檢查裝置中之同一電路 構成獨立地具有上述應統一施加處理之裝置個數之自上述 163040.doc -10· 201245731 進而通過上述電阻到 南電壓電容機構通過上述切換機構 達上述尚電壓輸出部之電路。 進：’較佳為’本發明之高電壓檢查裝置中之高電壓電 源選疋具有與上述應統—施加處理之裝置個數之上述複數 個高電壓電容機構相應之充電處理能力者。 進而：較佳為，本發明之高電壓檢查裝置包含複數個搭 載一個或複數個同一電路構成之ESD基板。 進而’較佳為，本發明之高電壓檢查裝置將一個或複數 個ESD基板收容於框體内。 進而，較佳為，本發明之高電壓檢查裝置構成為：複數 個ESD基板空出中央圓形部而豐立地以放射狀配置，該複 數個ESD基板上之複數個同—電路構成之各輸出端子分別 朝向該中央圓形部側設置’且可自該複數個同一電路構成 之各輸出端子將上述複數個高電壓輸出部之各者相對於設 置在該中央圓形部之下方侧之上述複數個檢查對象裝置之 各端子電性連接。 進而，較佳為，本發明之高電壓檢査裝置構成為：複數 個框體空出中央圓形部而以放射狀配置，收容於該複數個 框體内之複數個ESD基板之複數個同一電路構成中之各輸 出端子分別朝向該中央圓形部側而設置，且可自該複數個 同一電路構成之各輸出端子將上述複數個高電壓輸出部之 各者相對於設置在該中央圆形部之下方側之上述複數個檢 查對象裝置之各端子電性連接。 進而’較佳為’本發明之高電壓檢查裝置構成為：自複 163040.doc 201245731 數個同一電路構成之各輸出端子通過上述高電壓輸出部之 各者至上述複數個檢查對象裝置為止之、包含上述應統一 施加處理之裝置個數之獨立之配線之距離全部設定為相同 距離’而使來自上述高電壓電源之相同ESD施加電壓波形 分別同時對該複數個檢查對象裝置施加。 進而，較佳為，本發明之高電壓檢査裝置中，高電壓輸 出部及連接於GND電壓源之GND電壓輸出部分別具有接觸 機構，其於上表面連接來自上述複數個同一電路構成之各 高電壓輸出端子及GND輸出端子之複數條配線，於下表面 配設有以對應於該複數條配線之方式連接、且相對於上述 複數個檢查對象裝置之各端子可電性連接之複數個接觸構 件。 進而’較佳為’本發明之高電壓檢查裝置中之接觸機構 為於支臂上固定有複數個接觸構件之操作器'與固定有複 數個接觸構件之探針卡中任一者。 進而，較佳為，本發明之高電壓檢查裝置之高電壓輸出 部及連接於GND電壓源之GND電壓輸出部分別具有接觸機 構，其配設有相對於上述一個或複數個檢查對象裝置之各 端子可電性連接之複數個接觸構件。 進而，較佳為，本發明之高電壓檢查裝置使用將由帕申 法則（Paschen's Law)計算求出之放電極限值相對於導電構 件間距離之關係之理論值、與實際進行ESD測試而求出之 實測值之最短距離相連之直線，作為該導電構件間距離之 最小設計值。 163040.doc -12- 201245731 進而’較佳為，本發明之高電壓檢查裝置中之高電壓電 源以相對於配設在半導體晶圓上之複數個檢查對象裝置之 -一極體構造成為反向偏壓之方式施加負高電壓。 進而’較佳為，本發明之高電壓檢查裝置中，對配置於 半導體晶圓上之複數個檢查對象裝置之連接處理係使用自 動搬送裝置而連續地進行。 進而’較佳為’本發明之高電壓檢查裝置中之ESD基板 具有用於零件更換之插座部。 進而，較佳為’本發明之高電壓檢查裝置中之接觸構件 使用放電熱耐性之銦或鎢之材質。 進而，較佳為，本發明之高電壓檢查裝置中之探針卡之 基板為避免放電用之表層配線基板。 進而’較佳為’本贅明之高電壓檢查裝置中，使用將由 帕申法則計算求出之放電極限值相對於因接觸平台之上下 動作而產生之導電構件間距離之關係之理論值、與實際進 行ESD測試而求出之實測值之最短距離相連之直線，作為 該導電構件間距離之最小設計值。 進而’較佳為，本發明之高電壓檢查裝置中之接觸構件 保持避免放電用之接觸構件間距離。 進而’較佳為，本發明之高電壓檢查裝置中，作為監視 來自高電壓箕源之ESD施加電壓波形之機構，於上述探針 卡之基板之接觸構件之安裝根部設置有圓銷連接器。 進而’較佳為’本發明之高電壓檢查裝置中之高電壓電 源構成為相對於GND電位搭載有正電源與負電源，且可切 】63040.doc -13· 201245731 換該正電源與該負電源，且構成為相對於上述複數個檢查 對象裝置可切換順方向偏壓與反方向偏壓。 進而’較佳為’本發明之高電壓檢查裝置中，配置於半 導體晶圓上之複數個檢査對象裝置間經短路處理為Gnd電 位。 進而’較佳為’本發明之高電壓檢查裝置中，半導體晶 圓之導電外周部經電性短路處理為上述GND電位，將於上 述複數個檢查對象裝置間短路之GND電位、電性連接該半 導體晶圓之導電外周部之晶圓平台導電層之Gnd電位、及 上述ESD電路之GND電位作為共通GND電位而連接，藉此 省略對該複數個檢查對象裝置之GND端子之連接處理。 進而’較佳為，本發明之高電壓檢查裝置中之電腦系統 對控制由上述切換機構進行之切換之ESD控制器及探針儀 之動作進行控制，並根據表示上述複數個檢查對象裝置之 位址之晶圓映射進行探測控制。 進而’較佳為，於本發明之高電壓檢査裝置中，於探針 卡中，有複數個之探針之立針設計基準係使用將由帕申法 則計算求出之放電極限值相對於導電構件間距離之關係之 理論值、與實際進行ESD測試而求出之實測值之最短距離 相連之直線’作為該導電構件間距離之最小設計值者，於 需要有半導體晶片尺寸以上之距離之情形時，設計為保持 例如將半導體晶片跳過1個或跳過2個以上之空間距離。進 而’較佳為，本發明之高電壓檢查裝置中，於探針卡中， 以1次接觸無法探測之空間區域之半導體晶片藉由以個人 I63040.doc • 14· 201245731 電腦PC(Personal Computer)為主體之探測控制依序進行接 觸處理，而無遺漏地執行ESD施加》 根據上述構成，以下’對本發明之作用進行說明。 於本發明中，在對複數個檢查對象裝置檢查ESD耐性之 高電壓檢查裝置中，包含：高電壓電源，其輸出特定之高 電壓；及ESD電路，其對該複數個檢查對象裝置統一地同 時施加來自該高電壓電源之特定之高電壓。 藉此’對檢查對象之複數個裝置統一地，以適合於規格 之電流波形（或電壓波形）明確且正確地進行高電壓施加測 試’藉此可大幅且高效地進行高電壓檢查。 尤其，於本發明中’在對複數個檢查對象裝置檢查esd 耐性之高電壓檢查裝置中’包含：高電壓電源，其輸出特 定之負高t壓；及ESD電路’其分別對配設在半導體晶圓 上之複數個檢查對象裝置之各二極體構造以分別成為反向 偏壓之方式統一地同時施加來自高電壓電源之各特定之負 高電壓。 藉此，即便於對檢查對象之複數個裝置統一地，以適合 於規格之電流波形（或電壓波形）明確且正確地進行高電壓 施加測試之情形時，亦可以簡單之構成不混雜有短路不良 地’大幅且高效地進行高電壓檢查。 又，尤其，於本發明中，在對一個或複數個檢查對象裝 置檢查ESD耐性之高電壓檢查裝置中，藉由搭載有該一個 或複數個檢查對象裝置之接觸平台之上下動作，使開關機 構打開/關閉’將1對1對應於一個或複數個檢查對象裝置 163040.doc •15· 201245731 之各高電壓電容機構之高電壓充電/放電，藉由來自該各 高電壓電容機構之放電進行該一個或複數個檢查對象裝置 之ESD檢查。 藉此’可不使用高耐壓繼電器而將整體構成簡化，以適 合於規格之電流波形（或電壓波形）進行高電壓施加測試。 [發明之效果] 藉由以上說明’根據本發明，因係對檢査對象之複數個 裝置統一地，以適合於規格之電流波形（或電壓波形）明確 且正確地進行高電壓施加測試，故而可大幅且高效地進行 高電壓檢查。 又’即便於對檢查對象之複數個裝置統一地，以適合於 規格之電流波形（或電壓波形）明確且正確地進行高電壓施 加測試之情形時’亦可以簡單之構成不混雜有短路不良 地’大幅且高效地進行高電壓檢查。 進而，可不使用高耐壓繼電器而將整體構成簡化，以適 合於規格之電流波形（或電壓波形）進行高電壓施加測試。 【實施方式】 以下，作為本發明之高電壓檢查裝置之實施形態丨〜3， 針對應用於ESD^裝置中之情形參關式詳細地進行說 明。再者’使用上述實施形態3之開關52與接觸平台Μ之 上下動機構及其周邊控制電&，取代上述實施形態i之高 时壓繼電器3及其驅動電源、咖控制器，藉此可省略使 用水銀之高耐壓繼電器3，而將上述實施形態i應用於上述 實施形態3中。再者，各圖中之構成構件之各者之厚度或 163040.doc • 16 - 201245731 長度等自圖式製作上之觀點而言’並非限定於圖示之構 成。 (實施形態1) 圖1係表示本發明之實施形態1中之E S D測試裝置之構成 例之電路圖。 於圖1中，作為本實施形態！之高電壓檢查裝置之ESD測 試裝置1具有：高電壓電源2,其輸出特定之高電壓；及 ESD電路1〇，其對複數個檢查對象裝置6統一地同時施加 來自高電壓電源2之特定之高電壓；該ESD測試裝置丨對複 數個檢查對象裝置6檢查ESD耐性。 該ESD電路1〇具有：複數個高壓電容器4，其作為儲存 來自高電壓電源2之特定之高電壓之高電壓電容機構；複 數個尚電壓輸出部，其使來自複數個高壓電容器4之各特 定之高電壓分別通過施加電阻5而輸出；及高耐壓繼電器 3’其作為以將來自該高電壓電源2之特定之高電壓連接於 高壓電容器4側、或將來自高壓電容器4之特定之高電壓連 接於高電壓輸出部側之方式進行切換之複數個切換機構； 作為同一電路構成，獨立且並列地具有應統一施加處理之 複數個檢查對象裝置6之個數之自高壓電容器4通過高耐壓 繼電器3、進而通過施加電阻5而到達高電壓輸出部之電 路。 ESD測試裝置1中’高電壓電源2之一端子分別經由多接 點（此處為8接點）之高耐壓繼電器3之各接點而連接於複數 個（此處為8個）高壓電容器4之各一電極，且複數個（此處為 163040.doc 201245731 8個）高壓電容器4之各另一電極分別連接於高電壓電源2之 另一端子並且接地。複數個（此處為8個）高壓電容器4之各 一電極分別自多接點（此處為8接點）之高耐壓繼電器3之各 接點’分別通過各施加電阻5而自高電壓輸出部分別連接 於檢查對象之各裝置6之一端子。各裝置6之另一端子分別 自GND電壓輸出部分別連接於高電壓電源2之另一端子並 且接地。此處雖未圖示，但設置有下述ESD控制器9，其 以特定時序控制多接點（此處為8接點）之高耐壓繼電器3之 同時連接切換。用以驅動該多接點（此處為8接點）之高耐壓 繼電器3之電源需要另外設置。 尚電壓電源2根據應統一處理之高壓電容器4之個數之電 容而選定具有適當之充電處理能力者並共用。 高耐壓繼電器3使用於設置上具有方向性之水銀繼電 器，此處可為8接點之高耐壓繼電器，其可為使用2個4接 點者亦可為使用4個2接點者。亦可設置8個1接點之高耐 壓繼電器3來取代8接點之高耐壓繼電器3。高耐壓繼電器3 對於高壓電容器4 ’藉由未圖示之ESD控制器…接點同 時以高磨t容器4側為中心而在高電壓電源2側肖裝請 之間切換。針對自8個高應電容器4向8個裝置6之高電麼之 獨立之統一施加而向高耐壓繼電器3傳送之控制信號設定 為單-同時控制。若高耐壓繼電器3堆疊而配置 由線圏磁場進行動作之零件，而有可能引起誤動作，所= 不佳。 又’如下述圖21般 亦可為如同充電用之高耐壓繼電器 163040.doc 201245731 102與放電用之高耐壓繼電器103般獨立之高财壓繼電器之 構成。 向壓電容器4此處使用8個’選定具有適於測試電壓之财 性者，於電容之選定時，以與ESD測試之規格一致之方 式’選疋針對每個測試模式而決定者。例如，若為Ηβ μ規 格則為100 pF，若為ΜΜ規格則為200 pF。 施加電阻5此處使用8個’例如若為HBM規格則使用1.5 ΚΩ左右者，若規格則設為〇 κω(無電阻）。該等高壓 電容器4與施加電阻5於電性獨立之狀態下搭載有與應統一 處理之裝置6之個數相同之個數。 裝置6例如為LSI元件、或LED元件及雷射元件等發光元 件等》 根據上述構成’首先’藉φ未闺示之ESD控制器9而高 耐壓繼電器3之8個接點於高電壓電源2側接通電流自高電 壓電源2分支成8股流入至各高壓電容器4中並以高電麼電 源2之咼電壓均等地儲存。此時，高財壓繼電器3之裝置6 側之8個接點藉由ESD控制器9變成斷開狀態。 其久’於藉由ESD控制器9而南财壓繼電器3之高電壓電 源2側之8個接點斷開之後，以使高耐壓繼電器3之裝置6側 之8個接點接通之方式進行控制。藉此，儲存於高壓電容 器4中之高電壓自高耐壓繼電器3之8個接點分別通過各施 加電阻5而分別向檢查對象之各裝置6之一端子施加。於該 情形時，各高壓電容器4與檢查對象之各裝置6成1對1地對 應，大幅且高效地進行明確且正確之ESD檢查。 I63040.doc 201245731 如此，可藉由ESD控制器9而將該等高耐壓繼電器3之8 個接點自高電壓電源2側切換成檢查對象之各裝置6側，對 8個高壓電容器4充電或放電，自8個高壓電容器4將特定之 明確且正確之高電壓分別自各高電壓輸出部分別向檢查對 象之各裝置6施加。高耐壓繼電器3之8個接點之切換動作 係藉由ESD控制器9以規定之時序同時進行。ESD測試藉由 數種施加模式、與分別決定有規格向檢查對象之各裝置6 施加之ESD電流波形（或ESD電壓波形）而判斷是否適合。 ESD測試係自高電壓電源2經由高耐壓繼電器3之8個接 點，經由並列地連接有8個高壓電容器4與施加電阻5之串 聯電路之ESD施加電路，進而除插座以外亦經由於支臂上 固定有複數個探針（接觸構件）之操作器、固定有複數個探 針（接觸構件）之探針卡等作為接觸機構之接觸夾具向檢查 對象之各裝置6分別施加高電壓。使高電壓之供給源側端 子（1根）及GND側端子（1根）分別與檢查對象之裝置6之各端 子接觸從而對檢查對象之各裝置6將高電壓8個同時地施 加。於該情形時，檢査對象之各裝置6係8個同時地進行高 電壓施加處理。 圖2係模式性地表示於半導體晶圓平面内排列成多個矩 陣狀之半導體晶片之4個鄰接縱橫之平面圖。 於圖2中，在作為於半導體晶圓平面内排列成多個矩陣 狀之檢查對象之裝置6之半導體晶片丨丨之兩側分別設置有 對向之端子12 ^如此，於每個半導體晶片u上設置有2個 端子12，有時作為以箭頭表示之高電壓施加用之接觸構件 I63040.doc •20· 201245731 之例如探針13與端子12之對向方向（三角△)接觸，有時以 箭頭表不之高電壓施加用之探針13與端子12之鄰接方向 (又號X)接觸。 圖3係表示以理論值與實測值作為參數之放電極限值相 對於電極間距離之關係之圖。 以圖3之二角圖形▲表示之對向端子間之實測值係如圖2 所示’使以箭頭表示之高電壓施加用之探針13與端子12之 對向方向（二角△)接觸之情形時之觀測結果。又，以圖3之 叉號圖形X表示之鄰接端子間之實測值係如圖2所示，使以 箭頭表示之高電壓施加用之探針13與端子12之鄰接方向 (又號X)接觸之情形時之觀測結果。 於圖3中，示出放電極限值相對於電極間距離之關係， _四角圖形係由帕申法貝彳（求解於向端子間施加有高電壓之 狀態下將距離縮小至何處方會放電）計算求出之理論值， 與此相對地三角圖形▲及叉號圖形X係於實際進行ESD測 試之狀態下求出之實測值，且自高壓電容器4向裝置6之端 子間急遽且瞬間地施加ESD施加電壓波形之情形時之觀測 結果。三角圖形▲為對向端子間之實測值（向半導體晶片i 1 之對向之2端子間施加高電壓彼此之情形時之放電距離）， 叉號圖形X為鄰接端子間之實測值（向鄰接之半導體晶片i i 間之都接端子間施加高電壓彼此之情形時之放電距離）。 於自高電壓電源2而儲存於高壓電容器4中之高電壓例如為 1500 V之情形時，將放電開始電壓設定為15〇〇 v，於四角 圖形之理論值中’放電極限值之電極間距離為14〇 μιη& 163040.doc -21 - 201245731 右於二角圖形▲之對向端子間之實測值中，放電極限值 之電極間距離為50 μΠΐ左右，與此相對地於叉號圖形X之鄰 接端子間之實測值中，放電極限值之電極間距離為％ 左右。由此可知’比起鄰接端子間之實測值而對向端子間 之實測值之放電極限值較短β 連接該等實測值與理論值之最短距離之直線可作為放電 極限值相對於ESD電路10、電極間距離及探針間距離之設 計值之關係而使用。於該情形時，在理論值之直線上，端 子間距離為1 50 μηι〜200 μπι之間且向實測值之直線（叉號圖 形X為鄰接端子間之實測值之直線）移行。從而，相對於應 施加之高電壓關於放電極限值之電極間距離，於高電壓卡 較低之電壓值側使用理論值之直線，於較高之電壓值側使 用實測值之直線。因此’當自高電壓電源2而儲存於高壓 電容器4中之咼電壓例如為較低之電壓值侧之例如1 $ 〇 〇 ν 之情形時’若將放電開始電壓設定為1500 V，則必需超過 理論值140 μηι之電極間距離。 圖4係模式性地表示與圖1之ESD測試裝置1中之裝置6之 接觸狀態下之放大示意之立體圖。圖5係模式性地表示圖1 之ESD測試裝置1之ESD施加時之構成示意例之立體圖。 於圖4及圖5中，在圖1之ESD測試裝置1中，為了安全起 見將搭載有1台高電壓電源2、8接點之高耐壓繼電器3、8 個南壓電容器4、8個施加電阻5、及其他附加電路之esd 基板收容於框體内，且包括8 ch之ESD基板箱21，其具有 自咼壓電容器4通過高对壓繼電器3之接點到達施加電阻5 I63040.doc •22· 201245731 之串聯電路之8電路程度之配線輸出部21a;及探針卡22, 其中來自ESD基板箱2 1之配線輸出部2 1 a之各配線23經由 設置於上表面之連接器24分別連接於下表面側之8組探針 22a、22b ’ 8組探針22a、22b以1對1地對應於各裝置6之2 端子6a、6b之方式自下表面突出而分別設置；於晶圓平台 7上之半導體晶圓8上以矩陣狀設置有多個之檢查對象之8 個各裝置6之各端子6a、6b與分別連接於各高壓電容器4之 8組探針22a、22b以1對1地對應之方式配置。 藉由自ESD基板箱21之配線輸出部21a至探針卡22之配 線長之改變，而ESD施加電壓波形變化。從而，使自高壓 電谷器4至裝置6之各端子6a、6b為止之配線長全部為相同 配線長且使向裝置6之各端子6a、6b施加之ESD電壓波形 為相同。ESD基板亦可具有插座部用於零件更換。 圖6係模式性地表示圖1之ESD測試裝置1中之複數個ESD 施加器之設置示意例之平面圖。 如圖ό所示，ESD測試裝置ία中，作為複數個ESD施加 器之複數個ESD基板31空出中央圓形部32於其周圍豎立並 以放射狀配置’該複數個ESD基板3丨上之複數個同一電路 構成之各輸出端子分別朝向中央圓形部32側而設置。構成 為自複數個同一電路構成之各輸出端子可將複數個高電壓 輸出部之各者相對於設置在中央圓形部32之下方側之複數 個檢查對象裝置6之各端子而電性連接。以自複數個同一 電路構成之各輸出端子至通過高電壓輸出部之各者之複數 個檢查對象裝置6為止之包含應統一施加處理之裝置個數 163040.doc 23· 201245731 之獨立之配線在内之距離全部設為相同距離，且來自高電 壓電源2之相同ESD施加電壓波形分別同時明確且確實地 向複數個檢査對象裝置6之各端子施加之方式構成。 作為該ESD測試裝置1A，搭載有ESD電路10之複數接點 之高耐壓繼電器3、複數個高壓電容器4及複數個施加電阻 5之複數個ESD基板31以除去中央圓形部32所成之圓環狀 複數放射狀地（相對於中央圓形部32之中心為放射狀）配 置》高耐壓繼電器3之厚度於通用之4000 V耐壓用時大概 為15 mm，於8000 V耐壓用時，大概為30 mm。藉由該厚 度決定可配置多少片ESD基板31。當高耐壓繼電器3之厚 度為4000 V耐壓用之15 mm且中央圓形部32之内周直徑為 40 cm之情形時，可配置64片ESD基板3 1。 又，由於係藉由高耐壓繼電器3之厚度決定ESD基板31 之厚度，所以較佳為使用高耐壓繼電器3之厚度較薄者。 例如於1片ESD基板31為4 ch之情形下，當搭載8個1接點之 高耐壓繼電器3時，若高耐壓繼電器3之厚度於4000 V耐壓 用時為13.5 mm ’則有可以放射狀搭載83片ESD基板31全 部為332 ch(可同時對332個裝置6進行ESD測試）之能力。 該情形時之ESD基板31之外周直徑約為50 cm左右。 配線23自複數個ESD基板31之内周側引出並連接於探針 卡22之連接器24，將設置於探針卡22之下表面之複數組探 針22a、22b與於吸附在晶圓平台7上之半導體晶圓8上以矩 陣狀設置有多個檢查對象之各裝置6之端子6a、6b以1對i 地對應之方式連接而進行ESD測試。探針22a、22b與裝置 163040.doc • 24· 201245731 6之端子6a、6b之位置關係可一面使構成自動搬送裝置之 探針儀之晶圓平台7側正確地移動一面藉由圖像識認而正 確地定位。此處，可每64個為i行地對4〇〇 μιηχ2〇〇 μπι尺寸 之半導體晶片11進行ESD測試並反覆該操作，依序自動地 處理晶圓之晶片全部（例如10萬個）。由於難以於相鄰之行 上立起探針22a、22b，所以比起2行以上地進行ESD測 試’ 1行地進行不易引起接觸失誤故而較佳。 又，於探針卡之立針設計中，當連接由帕申法則計算求 出之放電極限值相對於導電構件間距離之關係之理論值、 與實際進行ESD測試而求出之實測值之最短距離必須為半 導體晶片尺寸以上之情形時，例如形成保持跳過丨個半導 體aa片或跳過2個以上之空間距離之設計，以避免對鄰接 探針間_之放電。藉由1次接觸無法探測之空間之半導體晶 片可藉由以下述個人電腦PC為主體之而探測控制，依序進 行接觸處理’而無遺漏地執行ESD施加。 自ESD基板31至裝置6為止之配線長作為圖8(b)之ESD施 加電壓波形之規格保持較理想的是2〇 cm以下。使自各 ESD基板31至8個裝置6之各端子為止之配線長全部為相同 配線長且使向裝置6之各端子施加之圖8(b)之ESD電壓波形 為相同。藉此，ESD測試變得均一。 圖7(a)係模式性地表示圖試裝置1中之複數個 ESD施加器之另一設置示意例之平面圖，圖7(b)係圖7(幻之 ESD施加器與探針卡及探針儀之縱剖面圖。圖8(a)係模式 性地表示圖7(a)之ESD施加器之立體圖，圖8(b)係表示於 163040.doc •25· 201245731 ESD測試中所使用之ESD施加電壓波形之圖。 於圖7(a)、圖7(b)及圖8(a)中，ESD測試裝置1B中，複數 個框體即複數個ESD基板箱21空出中央圓形部25並於其周 圍以放射狀配置。收容於複數個ESD基板箱21内之複數個 ESD基板3 1之複數個同一電路構成之各輸出端子分別朝向 中央圓形部25側而設置。構成為自複數個同一電路構成之 各輸出端子可將複數個高電壓輸出部之各者相對於設置在 中央圓形部25之下方側之複數個檢查對象裝置6之各端子 6a、6b而電性連接。以自複數個同一電路構成之各輸出端 子通過各高電壓輸出部之各者至複數個檢查對象裝置6為 止之包含應統一施加處理之裝置個數之獨立之配線23在内 之距離全部設定為相同距離，且來自高電壓電源2之相同 ESD施加電壓波形分別同時向複數個檢査對象裝置6施加 之方式構成。再者’作為高電壓輸出部，既可為同一電路 構成之輸出端子，亦可包含自該輸出端子經由配線至探針 卡22之探針22a、22b為止。 作為ESD測試裝置1B，將搭載有i台高電壓電源2、8接 點之高耐壓繼電器3、8個高壓電容器4、8個施加電阻5、 及其他附加電路之複數個ESD基板31收容於框體内，且具 有自高壓電容器4通過高耐壓繼電器3之接點到達施加電阻 5之串聯電路之8電路程度之配線輸出部21a之8 ch之ESD基 板箱21以放射狀配設有8個。配線23自8個ESD基板箱21之 内周側引出並連接於探針卡22之連接器24，將設置於探針 卡22之下表面之8組探針22a、22b、與於構成自動搬送裝 163040.doc •26· 201245731 置之探針儀之晶圓平台7上之半導體晶圓8上以矩陣狀設置 有多個之多個裝置6中之檢查對象之8個各裝置6之各端子 6a、6b以1對1地對應之方式連接而進行ESD測試反覆此 搡作。 自該8 ch之ESD基板箱21之配線輸出部21a至各裝置6為 止之配線長作為圖8(b)之ESD施加電壓波形之規格保持較 理想的是20 cm以下。使自各ESD基板箱2丨之各配線輸出 部21a至8個各裝置6之各端子為止之配線長全部為相同配 線長且使向各裝置6之各端子施加之圖8(b)之ESD電壓波形 為相同。藉此，ESD測試變得均一。 圖9係表示以個人電腦pC為主體之晶圓映射與探測管理 之方塊圖。 於圖9中’冬實施形態1之ESD測試裝置1具有：個人電 腦PC ’其進行探測管理；1台高電壓電源2 ; ESD控制器 9，其接收來自個人電腦PC之指示而驅動；ESD電路10， 其由8個並聯電路所構成，該8個並聯電路係藉由ESD控制 器9，將高耐壓繼電器3之8接點同時切換成高電壓電源2側 並將來自高電壓電源2之高電壓儲存於8個高壓電容器4 中，其後，以特定之時序將高耐壓繼電器3之8接點同時切 換成8個各施加電阻5側；及探針儀20，其係用以：於使晶 圓平台7之半導體晶圓8移動之後使自ESD電路10分別經由 8個各施加電阻5之ESD施加電壓上升，使8組探針卡22之 探針22a、22b分別與8個裝置6之各端子6a、6b接觸而藉由 該8組探針22a、22b向該各端子6a、6b施加。於對半導體 163040.doc •27- 201245731 晶圓8之多達l〇萬個之多個晶片依序進行ESD測試之情形 時’使用探針儀20等自動搬送裝連續地進行探測。 探測管理可以個人電腦PC為主體，相對於半導體晶圓8 上之晶圓映射即表示以矩陣狀配置於半導體晶圓8上之多 個（例如10萬個）半導體晶片1丨之位置之位址，記憶對哪個 位址範圍之半導體晶片11進行ESC)測試，哪個位址之半導 體晶片11為ESD耐壓不良》ESD耐壓不良係於半導體晶片 11之二極體構造之反方向電壓造成之漏電流高於特定值之 情形時藉由測定器對此測定而認定為不良，並將該半導體 晶片11之位址記憶於個人電腦PC中。 ESD控制器9不僅進行ESD電路之高耐壓繼電器3之動作 控制’亦依照應施加之電壓位準之設定、或以程式等預先 設定施加次數、施加之極性條件之序列而動作。 藉由以上說明’根據本實施形態1，於量產時，對檢查 對象之複數個裝置6統一地，以適合於規格之ESD施加電 屋波形明確且正確地進行尚電塵施加測試，藉此可大幅且 高效地進行高電壓檢查。 再者’於本實施形態1中，雖未特別詳細地說明，但除 了對以矩陣狀配設於半導體晶圓8上之個片化前（切斷前）之 作為多個裝置6之各半導體晶片11進行esd測試以外，亦 可對個片化後（切斷後）且帶有保持台之狀態（以矩陣狀排列 有半導體晶片11之狀態）下之各半導體晶片J i進行ESD測 試β 再者’於上述實施形態1中，雖未特別詳細地說明，但 163040.doc -28· 201245731 间電壓電源2構成為相對於GND電位搭載有正電源與負電 源，且可切換正電源與負電源，亦可構成為相對於複數個 檢查對象裝置6’可切換順方向偏壓與反方向偏壓。 (實施形態2) 於上述實施形態1中，對使來自高電壓電源2之特定之高 電壓相對於複數個檢查對象裝置6統一而同時正確地施加 相同ESD施加電壓波形之情形進行了說明，於本實施形態 2中’除此以外，亦對於半導體晶片丨i之gnd側之各端子 12b為電性地短路狀之半導體晶圓之情形時，穩定地進行 以矩陣狀配置於該半導體晶圓上之多個檢查對象裝置6之 ESD耐壓檢查之情形進行說明。 又，於ESD測試時裝置之動作極性中，有順方向偏壓施 々口與反方向偏壓施加$.2種碎加方琴^一般公知的是以反 向偏壓施加進行測試可保證較高之可靠性，此處，特別地 對用以保持反方向偏壓時之ESD規格之裝置構成、及結合 裝置之出廠式樣可進行雙方向之偏壓施加之裝置之構成進 行說明。 圖10係表示本發明之實施形態2中之ESD測試裝置之構 成例之電路圖》 於圖10中’作為本實施形態2之高電壓檢查裝置之ESD 測試裝置1C具有：高電壓電源2C，其輸出特定之負高電 壓；及ESD電路i〇c，其對以矩陣狀配置在半導體晶圓8上 之多個檢查對象裝置6中之特定數之檢查對象裝置6統一地 同時施加來自高電壓電源2C之特定之負高電壓；該esd測 163040.doc -29- 201245731 试裝置ic對半導體晶圓8上之複數個檢查對象裝置6檢査 ESD耐性。 該ESD電路l〇c具有：複數個高壓電容器4，其作為儲存 來自尚電壓電源2之特定之負高電壓之複數個高電壓電容 機構；複數個高電壓輸出部，其使來自複數個高壓電容器 4之各特疋之負高電壓分別通過施加電阻5而輸出；及一個 或複數個高耐壓繼電器3，其作為以將來自該複數個高電 壓電源2C之特定之負高電壓連接於高壓電容器4側或將來 自尚壓電容器4之特定之高電壓連接於高電壓輸出部側之 方式進行切換之複數個切換機構；作為同一電路構成，獨 立且並列有與應統一施加處理之複數個檢查對象裝置6之 個數相同之個數地具有自高壓電容器4通過高耐壓繼電器3 進而通過施加電阻5而到達高電壓輸出部之電路。 ESD電路10C係由8個並聯電路所構成，該8個並聯電路 係藉由ESD控制器9，將高耐壓繼電器3之8接點同時切換 成高電壓電源2C側並將來自高電壓電源2(：之負高電壓儲 存於8個高壓電容器4中，錢’以特定之時序將高耐壓繼 電器3之8接點同時切換成8個各施加電阻5側，來自8個高 壓電容器4之負高電壓分別經由高耐壓繼電器3之8接點分 別到達8個各施加電阻5側。 該情形時之檢查對象之裝置6係於其内部具有二極體構 造之㈣元件或雷射元件等發光元件。藉由利用高電魔電 源2C進行儲存之高壓電容器4 ’以相對於以矩陣狀配置在 半導體晶圓8上之複數個檢查對象裝置6之二極體構造成為 163040.doc -30- 201245731 反向偏壓之方式施加負高電壓。 ESD測試裝置ic中，輸出負高電壓之高電壓電源2C之一 端子分別經由多接點（此處為8接點）之高耐壓繼電器3之各 接點連接於複數個（此處為8個）高壓電容器4之各一電極， 複數個（此處為8個）高壓電容器4之各另一電極分別連接於 高電壓電源2C之另一端子並接地。複數個（此處為8個）高 壓電容器4之各一電極分別自多接點（此處為8接點）之高耐 壓繼電器3之各接點分別通過各施加電阻5自高電壓輸出部 分別連接於檢查對象之各裝置6之一端子。各裝置6之另一 端子分別自GND電壓輸出部分別連接於高電壓電源2C之另 端子並接地。此處雖未圖示’但設置有以特定時序控制 多接點（此處為8接點）之高耐壓繼電器3之同時連接切換之 下述ESD控制器9。用以驅動該多锋點（此處為8接點）之高 耐壓繼電器3之電源需要另外設置。 圖11係使用圖10之ESD測試裝置1C，進行以矩陣狀配置 於半導體晶圓8上之多個檢查對象裝置6之£5〇耐壓檢查之 情形時之模式圖。 於圖11中，對ESD測試裝置⑴中之高壓電容器4充電以負 高電壓，例如向檢查對象之各裝置6之陽極端子施加_15〇〇 v， 向陰極端子施加0 V。如此，因係向各裝置6之陽極端子施 加-1500 V之負高電壓，向陰極端子施加〇 v，故而向二極 體構造施加ESD反方向電壓而進行ESD測試。於該情形 時，將高電壓電源2C設為電源。ESD1〇c之電壓供給源側 與GND側反轉。為了自n-GaN基板經由陽極端子吸引高壓 163040.doc -31 · 201245731 電容器4之電荷規定量（例如1〇〇 pF)，通過陽極端子之電荷 量為固定。陽極電極以裝置單位獨立，故而作為咖條件 不成問題。從而，可對各裝置6分別確冑地保證高壓電容 器4之電荷規定量（例如100 pF)之施加。進而，若將高電壓 電源2C設為+電源，則可實現順方向偏壓。 與此相對地，如圖12所示，若使用正電源，將施加電路 (GND)之極性反轉藉此設定反向偏壓之狀態則當產生自 裝置6之陰極端子向鄰接裝置6之陽極端子之短路之情形 時，所施加之電荷量分散於n_GaN基板上，自相同裝置6之 陰極端子通過陽極端子之電荷量變得不定。如此，當混雜 有短路不良之情形時，於短路位置處貫通之電荷集令，因 此自ESD規定脫離。此可藉由負高電壓之圖測試 裝置1C而消除。 圖13係作為於圖1〇之ESD測試裝置1C中以複數個裝置為 ESD施加對象時之探測實施例，用以說明向半導體晶片i 1 之各端子之探針配置之平面圖。 如圖13所示，向ESD電荷供給源即探針22a之各端子12a 之接觸係以裝置單位（每個半導體晶片丨丨地）獨立地進行， 實施施加電路（包含ESD電路10C與高電壓輸出部之電路）之 搭載與探針接觸。如此’向施加圖8(b)之ESD電壓波形之 半導體晶片11之各端子12a之探針22a係針對每個半導體晶 片11獨立地設置’向GND側端子即半導體晶片11之各端子 12b之探針22b於半導體晶片11之GND側之各端子12b為電 性地短路狀態下之半導體晶圓之情形時，對於ESD電壓波 163040.doc -32· 201245731 形之施加處理只要以丨點（或半導體晶片丨丨之每複數個元件） 為接觸對象即可。複數個裝置之GND侧之各端子12b均於 晶圓8内電性短路，故而連接於ESD電路1〇c之gnd(COM) 之探針22b只要於GND側之複數個端子12b中之至少1點接 觸’即變成和與每整個裝置接觸之狀態相同之狀態β藉 此’可至少保留1個GND侧之接觸探針而無需剩下其他。 圖14係模式性地表示省略gnd側之探針之情形時之向檢 查對象之裝置6之連接之圖。 於圖14中’在晶圓平台絕緣層41之表面側，設置有經接 地之晶圓平台導電層42,在晶圓平台導電層42上搭載有半 導體晶圓8。以矩陣狀配置於半導體晶圓8上之複數個檢查 對象裝置6在製造製程中以於複數個檢查對象裝置6間之 GND側短路之方式被獐極地實施短路處理。又，於半導體 晶圓8之邊緣側面形成導電性膜，自檢查對象裝置6之接地 端子（GND端子）即各端子12b經由晶圓邊緣側面之導電性 膜電性連接於晶圓平台導電層42。來自配線輸出部21a之 各配線23經由設置於探針卡22之上表面之連接器24分別連 接於探針卡22之下表面側之探針22a，以1對1地對應於各 裝置6之方式探針22a自下表面突出而分別設置。 將於各裝置6間短路之GND、晶圓平台導電層42之 GND、ESD電路10C之GND作為共通GND而連接，藉此可 完全無需對各裝置6之GND端子之探測。 藉由以上說明，根據本實施形態2，對檢查對象之複數 個裝置6統一地，以適合於規格之ESD施加電壓波形明確 163040.doc -33- 201245731 且正確地進行高電壓施加測試，藉此可大幅且高效地進行 高電壓檢查。除此以外，即便當以矩陣狀配置於半導體晶 圓8上之多個檢查對象裝置6間於GND側短路之情形時或使 用裝置6間於GND側短路之晶圓之情形時，亦可正確且穩 定地大幅且高效地進行ESD耐壓檢查。 再者，於上述實施形態1、2中，雖未特別說明，但探針 卡22之基板並非多層配線基板，而係避免放電用之表層配 線基板。於使用多層配線基板作為探針卡22之基板之情形 時，為數千V之高電壓，因此需考慮配線間之介電率（避免 放電特性）、距離/電壓。較佳為探針使用放電熱耐性之銦 或鎢之材質。探針保持避免放電用之探針間距離。作為監 視ESD施加電壓波形之機構，較理想的是於探針卡22之基 板之探針22a、22b之根部設置有圓銷連接器。 (實施形態3) 於本實施形態3中，對不使用作為高耐壓繼電器3之水銀 繼電器而進行ESD測試之情形進行說明。 圖15係模式性地表示於本發明之實施形態3之ESD測試 裝置中接觸平台處於上位置之情形時之縱剖面圖。圖16係 模式性地表示於圖15iESD測試裝置中接觸平台處於下位 置之情形時之縱剖面圖。 於圖15中，在對一個或複數個檢查對象裝置檢查esd耐 性之本實施形態3之ESD測試裝置⑴中，藉由搭載有一個 或複數個檢査對象裝置54之接觸平台53之上下動作，作為 開關機構之開關52打開/關閉，將作為…地對應於一個 I63040.doc -34· 201245731 或複數個檢查對象裝置54之各高電壓電容機構之高壓電容 器56之尚電壓充電/放電’藉由來自各高壓電容器56之放 電進行該一個或複數個檢査對象裝置54之ESd檢查。 本實施形態3之ESD測試裝置1£)具有：高電壓電源55， 其輸出特定之高電壓；一個或複數個高壓電容器56，其儲 存來自尚電壓電源55之特定之高電壓；及探針卡57之探針 57a、57b，其作為輸出來自一個或複數個高壓電容器56之 特定之高電壓之一個或複數個高電壓輸出部；且藉由接觸 平台53之上下動作而切換使探針卡57之探針57&、57b與一 個或複數個檢查對象裝置54之各端子54&、54b隔離並且藉 由開關52將一個或複數個高壓電容器56連接於高電壓電源 5 5側之第1動作、與藉由開關52而將一個或複數個高壓電 容器56與高電壓電源55斷開並且分別通過探針卡57<探針 57a、57b分別連接於一個或複數個檢查對象裝置54之各端 子54a、54b之第2動作。 進而詳細地進行說明。於基礎體51上固定有開關52之一 接點仏’於接觸平台53之下表面且開關52之-接點52a正 上方固定有開關52之另—接點52b。於接觸平台”上，固 定有檢查對象之裝置54,接觸平台53構成為以特定間隔自 如地上下移動。雖然檢查對象之裝置54此處僅標示出i 個’但實際於前後方向上設置有複數個檢查對象之裝置 54 ° 開關52之一接點52a連接於高電壓電源55，開關π之另 一接點52b經由高壓雷宜典工μ ,L _ ^ 冤谷器56而接地。咼壓電容器56連接 163040.doc -35- 201245731 於探針卡57之高電壓側，探針卡側接地。 以1對1地對應於各裝置54之2端子54a、54b之方式而探 針57a、57b自探針卡57之下表面突出而分別設置。各裝置 54之各端子54a ' 54b與分別連接於高壓電容器56之探針卡 57之探針57a、57b以1對1地對應之方式配置。 咼電壓電源55選定具有與應統一施加處理之裝置個數之 複數個各高壓電容器5 6相應之充電處理能力者。 高電壓輸出部、及連接於GND電壓源之GND電壓輸出部 分別具有配設有可相對於一個或複數個檢查對象裝置54之 各端子54a、54b而電性連接之複數個接觸構件之接觸機 構。該接觸機構為於支臂上固定有複數個接觸構件之操作 器與固定有複數個接觸構件之探針卡57中任一者。作為接 觸構件，使用放電熱耐性之銦或鎢之材質。此處，使用探 針卡57作為接觸機構，使用探針57a、5几作為複數個接觸 構件。探針卡57之基板被施加高電壓，故而並不設定為多 層配線基板’而設定為避免放電用之表層配線基板。 根據上述構成’於圖15中’接觸平台53處於上位置，來 自兩壓電容器56之南電壓經由探針卡57之高電壓側之探針 57a向各裝置54之端子54a施加而進行ESD測試。即，當接 觸平台53處於上位置時相對於高壓電容器56高電壓電源55 斷開’來自各向壓電容器56之相同ESD施加電壓波形自各 探針57a向各裝置54之端子54a施加》此時，各裝置54之端 子54b經由探針57b而接地。 於圖16中，接觸平台53處於下位置，來自高電壓電源55 163040.doc •36· 201245731 之高電壓經由開關52對高壓電容器56充 ㈣處於下位置時探針57a、57b與裝置54之各端备子接M觸；: 54b隔離’高電壓電源55連接於高壓電容器％而充電。 圖17係示出圖15之_52之接點間間隙，虛線表示接觸 彳台53之下位置’實線表示接觸平台”之上位置之圖。 於圖17中，間隙長A為探針57a、57b之接觸高度，間隙 長B為開關52之接點52a、52b之接觸高度。該探針^、 Μ於特定之行程範圍内’藉由彈著或彈性體等以一定賦 能力得到賦能而與裝置54之各端子心⑽接觸。又，開 關52之接點52a、52b亦於胜中从《η 邓於特疋之仃程範圍内，藉由彈簧或 彈性體等以一定賦能力得到賦能而相互連接。 使用連接由帕申法則計算求出之放電極限值相對於因接 觸平台53之上下動作而產生之導電構件間距離(探針5、、 5%與裝置54之各端子54a、糾之距離、或開關52之接點 間距離）之關係之理論值、與實際進行咖測試而求出之實 測值之最短距離之直線，作為導電構件間距離之設計值。 構成半導體晶圓8之自動搬送裝置之探針儀之接觸平台 53原本不僅吸附複數個檢查對象之裝以（或半導體晶: )進仃上下動，而且為了進行下個複數個檢查對象之裝 置54之ESD檢查而於平面水平移動，並垂直移動。接觸平 台53之上下動作（垂直移動）與咖電路所必需之高耐壓繼 電器(水銀繼電器)之動作對應，代替電性之電路動作。 藉由以上說明’根據本實施形態3，藉由接觸平台以 上下動作而開關52打開/關閉且對高壓電容器^充電/放 163040.doc •37- 201245731 電’可無需為了進行檢查對象之裝置54之ESD檢查，而設 置與檢查對象之裝置54數量相當多之高耐壓繼電器（水銀 繼電器）’並且亦可無需使其驅動之電源及ESD控制器。 於本實施形態3中，亦與上述實施形態1、2之情形同樣 地’於量產時，對檢查對象之複數個裝置6統一地，以適 合於規格之ESD施加電壓波形明確且正確地進行高電壓施 加測試，藉此可大幅且高效地進行高電壓檢查。 再者’於本實施形態3中，構成為相對於一個高壓電容 器56探針5 7a、57b與裝置54之各端子54a、54b分別1對1地 對應，以1對1地對應於檢查對象之裝置之方式將高壓電容 器56之數量設定為與檢查對象之裝置個數相同之個數。 再者’於本實施形態3中，藉由接觸平台53之上下動作 打開、關閉開關52而控制高壓電容器56之充電/放電，但 並不限於此’於ESD測試裝置1E中，亦可設置圖18之絕緣 氣體填充開關61 ’取代開關52 »絕緣氣體填充開關61為高 電壓’故而即便於收容開關接點之密閉空間内之接點間引 出電弧’亦可將絕緣耐性較高之氣體填充於該密閉空間 内’故而壽命較長。 右於存在高電壓差之狀態下，進行開關52(或接觸探針 間）之電性之開閉，則可確認放射光或熱之放電現象。當 因開關52(或接觸探針間）而引起放電之情形時，於開關52 之接點會產生氣中放電所造成之發熱，因此由於該放電熱 使得接觸面氧化，導致電性之接觸本身變得困難，或者由 於開關52之接觸f阻之變化而無法持續進行遵循規格之 163040.doc •38- 201245731 ESD施加。 上述高電壓之放電閾值係根據施加電壓或開關之接點間 距離、溫度、濕度等而變化。作為現行技術，已知有使用 作為高電壓設備中之絕緣開閉裝置等電力機器之絕緣媒體 或消弧媒體而利用之具有高絕緣性之氣體，作為同樣之方 法可使用如下對策：將開關接點位置密閉並填充絕緣性氣 體，藉此如絕緣氣體填充開關6丨般而實現開關之保護之目 的。 作為接觸探針部之保護，針對由於探針之表面氧化而造 成之接觸電阻之增大，藉由針尖之監視與定期之研磨處理 而持續進行基於規格之ESD施加。或者，若為無有害性之 氣體’則對接觸部分始終噴附該氣體亦為有效之方法。 再者，於本實施形態3中，藉由接觸平台53(晶圓探針 儀）之上下動作打開、關閉開關52而控制高壓電容器56之 充電/放電，但並不限於此，於圖丨9中，在ESD測試裝置11? 上，設置有作為進行接觸平台53之上下動作之驅動源之軸 71及使其上下驅動之齒條與小齒輪72來取代開關52，於軸 71之前端部（下端面）亦可設置開關73 ^即，於使上表面固 定有半導體晶圓58之接觸平台53上下動作之軸（shaft71)i 下端面亦可設置開關73。於接觸平台53與軸71—併向下側 移動時開關73打開，高電壓電源55對高壓電容器56充電。 又於接觸平台53與轴71 —併向上側移動時開關73關閉’ 间電壓電源55與高壓電容器56斷開，執行ESd測試。 再者於本實施形態3中，藉由接觸平台53(晶圓探針 163040.doc -39- 201245731 儀）之上下動作打開、關閉開關52而控制高壓電容器56之 充電/放電，但並不限於此，於圖20中，在ESD測試裝置 1G上，基礎體51上之開關52之接點52a接地，於接觸平台 53側之開關52之接點52b上連接有5 V左右之電壓源，該5 V 左右之低電壓源82連接於高耐壓電晶體81(絕緣柵雙極型 電晶體IGBT，Insulated Gate Bipolar Transistor)之控制端 子，高電壓電源55經由高耐壓電晶體81而連接於高壓電容 器56。藉由開關52打開而使5 V左右之低電壓源82發揮功 能，高耐壓電晶體81(絕緣柵雙極型電晶體IGBT)接通，來 自高電壓電源55之高電壓充電於高壓電容器56。又，若開 關52關閉’則已對高壓電容器56充電之高電壓作為ESD施 加電壓波形向各裝置54之各端子5 4a施加。此時，低電壓 源82不發揮功能，藉此高耐壓電晶體81 (絕緣柵雙極型電 晶體IGBT)斷開，高壓電容器56相對於高電壓電源55成為 斷開狀態》其優點為與圖17之情形時相比，高達數千v之 高電壓並不向機械之開關52直接施加，安全且高壽命。201245731 VI. Description of the Invention: [Technical Field] The present invention relates to a use of, for example, an LSI (Large Scale Integration) component, or an LED (Light Emitting Diode) component and a laser Check the ESD (Electro-Static discharge) resistance of the light-emitting device such as components. The ESD test device is used to perform a high voltage check device for high voltage application inspection. [Prior Art] Previously, in the case of an LSI element, the protective diode was connected to the input circuit side to check the ESD resistance of the protective diode. In the case of a light-emitting element such as an LED element or a laser element, the light-emitting element itself has a diode structure. Since the diode structure is composed of the pn junction of the p-type diffusion layer and the n-type diffusion layer, the ESD resistance differs depending on the result of the bonding between the p-type diffusion layer and the n-type diffusion layer, and therefore ESD tolerance must be checked in all. The basic ESD circuits necessary for the previous ESD application are high voltage power supplies, high voltage capacitors that follow ESD specifications (HBM (Human Body Model), MM (Machine Model), etc., using applied resistors and Mercury high pressure relay. The application output portion of the ESD circuit is an actuator formed by fixing a probe card for mounting a contact probe connected to a terminal of the device to a substrate, or fixing the contact probe to the arm. Wait for the device to be inspected to be powered. The magnitude of the supply voltage to the device to be inspected is checked by reliability 163040. Doc 201245731 A representative ESD test (electrostatic discharge reliability test) is targeted at a high voltage of approximately 1 to 10 KV. The durability in the case where static electricity from a human body or a machine flows into a device to be inspected such as an LSI wafer is tested. Fig. 21 is a circuit diagram schematically showing a configuration example of the previous E s 〇 test apparatus. In the 'previous ESD test apparatus 1' of Fig. 21, one of the terminals of the high voltage power source is connected to one end of the applied resistor ι4 through the high withstand voltage relays 102, 1〇3. The other end of the applied resistor 104 is connected to one of the terminals of the device 105 to be inspected. The other terminal of the device 1〇5 is connected to the other terminal of the high voltage power supply ι〇1. The connection point of the high withstand voltage relays 102, 1〇3 is connected to the connection point ' of the other terminal of the device 1〇5 and the other terminal of the high voltage power supply 101 through the high voltage capacitor 106' and the connection point is grounded. A timing controller 107 for controlling the on/off of the high voltage biasing relays 102, 103 is provided. According to the above configuration, first, the high-voltage relay 102 for charging is turned on by the timing controller 1〇7 and is supplied from a high voltage. The current of the power supply 1 储存1 is stored in the high voltage capacitor 106. At this time, the discharge high-voltage relay 1〇3 is turned off by the timing controller 107. Then, after the high-voltage withstand voltage relay 1〇2 is turned off by the timing controller 107, the discharge high-voltage relay 103 is controlled to be turned on. Thereby, the high voltage stored in the high voltage capacitor 106 is applied from the high withstand voltage relay 103 to the device 105 of the inspection object by applying the resistor 1 〇4. Doc 201245731 One terminal. In this manner, the high voltage relay 102 for discharge and the high voltage withstand relay 103 for discharge are switched on and off by the timing controller 107, and the high voltage capacitor 106 is charged or discharged, and is applied to the device 105 to be inspected. Specific high voltage. The switching operation of the charging high-voltage relay 102 and the discharging high-voltage relay 103 is performed by the timing controller 107 at a predetermined timing. The ESD test determines whether or not it is suitable by a plurality of application modes and a current waveform (or voltage waveform) applied to the device 105 that has a specification to the inspection target. In summary, the ESD test applies a high voltage to a device to be inspected from a high voltage power source via an ESD application circuit and a contact loss via a socket or an arm. The high-voltage supply-side terminal terminal and the GND (GroUnd's) side scorpion (one) are brought into contact with the respective terminals of the device to be inspected to apply a high voltage to the device to be inspected. In this case, the apparatus to be inspected performs a high voltage application process individually. Although there is a device that combines the devices of the inspection object into a complex array, the actual ESD test continuously changes the terminals for processing. This case is disclosed in Patent Document 2. In contrast, the case of ESD testing in a production area is disclosed in Patent Document 1. Fig. 22 is a perspective view schematically showing a configuration example of a prior ESD test apparatus disclosed in Patent Document i. In FIG. 22 'as the electrostatic discharge test previously the ESD test apparatus of 200 lines in the following manner the operating person with arthritis has: When in pair of mounting an electronic component coupled P brush wiring board 202 for electrostatic discharge test, using the next test 163 040 . Doc 201245731 Fixture, in one test, static electricity is simultaneously applied to a plurality of printed wiring boards 2〇2. After the electrostatic application point is set at a corner of the plate of the conductive plate 2〇3 prepared as the mounting table of the object to be tested, the printed wiring board 2〇2 is supported in a standing position for each separation from the electrostatic application point. A plurality of printing plate support members 204 at equidistant positions are arranged in a radial arrangement and dispersed. Further, there is provided a grab holder 206 which is provided with an electrostatic discharge generating position in alignment with the electrostatic application point. The printed wiring board 2〇2 is charged one by one on each of the printing plate holders 204 in a direction in which the wiring pattern 202a and the conductive plate 203 are in contact with each other, and is self-generated in this state. 5 Discharge static electricity to the electrostatic application point. Thereby, the 205 is generated from the static electricity, and the static electricity is uniformly applied to the plurality of printing wiring boards 202 placed on the board via the conductive plate 203. Therefore, static electricity can be simultaneously applied to the plurality of printed circuit boards 202 in one test, and the preparation time can be shortened. [PRIOR ART DOCUMENT] [Patent Document 1] Japanese Laid-Open Patent Publication No. 2005-201706 [Patent Document 2] Japanese Patent Laid-Open Publication No. 2000-32981 No. In the above-described conventional electrostatic discharge test jig 200 disclosed in Patent Document 1, the electrostatic generation is 2, 5, that is, the application source is a single body, and there are a plurality of devices for inspecting the object, and thus there are a plurality of inspections. The device of the object 'it is difficult to prove whether or not the problem of ESD application suitable for a predetermined voltage/specified number of times has been performed. In summary, due to the extreme application of ESD 163040. Doc 201245731 The small distance difference, so there is a possibility that the ESD voltage is applied to one of the plurality of devices, so that it cannot be a definite sub-application test. The present invention has been made in view of the above problems, and an object of the present invention is to provide a high-voltage application test that can be performed on a plurality of devices to be inspected uniformly and accurately and accurately in a current waveform (or voltage waveform) suitable for a specification. High voltage inspection device for high voltage inspection. In particular, in a plurality of devices formed on the same semiconductor wafer, when a plurality of devices to be inspected are collectively and subjected to a high voltage application test in a current waveform (or voltage waveform) suitable for a specification When, as shown in FIG. 12, a reverse bias state is provided under the positive power source, a short circuit occurs from the cathode terminal of the device 6 to the anode terminal of the adjacent device 6, and the amount of applied charge is dispersed on the n-GaN substrate. Upper, the amount of charge passing through the anode terminal from the cathode terminal of the same device 6 becomes indefinite. When there is a short circuit failure, the charge that penetrates at the short-circuit position is concentrated, and thus is detached from the ESD. The present invention has been made in view of the above problems, and it is an object of the present invention to provide a case where a plurality of devices to be inspected are uniformly integrated with a current waveform (or a voltage waveform) suitable for a specification to accurately and accurately perform a high voltage application test. It is also possible to easily configure a high-voltage inspection device that performs high-voltage inspections in a large and highly efficient manner without being mixed with short-circuit defects. Further, in particular, in the above-mentioned prior art ESD test apparatus 1 disclosed in Patent Document 2, a high withstand voltage relay using mercury is used. The use of high-pressure relays with mercury is not only expensive, but also due to the use of water 163040. Doc 201245731 Silver becomes a restricted object (RoHS Directive, Restrjcti〇n 〇f Hazardous Substances, Directive on Restricting the Use of Certain Harmful Ingredients in Electrical and Electronic Equipment). Further, when a plurality of devices are collectively inspected at the same time, it is necessary to use a plurality of high-voltage relays using mercury. Further, in the high-withstand voltage relay using mercury, a time difference of msec units is generated in the relay operation time. Further, it is necessary to control the unit of the driving timing of the high withstand voltage relay, and the power source for driving the high withstand voltage relay must be additionally set. The present invention has been made in view of the above problems, and an object of the present invention is to provide a high voltage inspection apparatus which can simplify the overall configuration without using a high withstand voltage relay and perform a high voltage application test suitable for a current waveform (or voltage waveform) of a specification. [Technical means for solving the problem] The voltage inspection device of the present invention checks the ESD tolerance for a plurality of inspection target devices, and includes: a high voltage power supply that outputs a specific high voltage; and an ESD circuit that respectively pairs the plurality of The inspection target device uniformly applies the respective specific high voltages from the high-voltage power source at the same time; thereby achieving the above object. The high voltage inspection device of the present invention checks ESD resistance for a plurality of inspection target devices, i includes: a high voltage power supply that outputs a specific negative high voltage '· and an ESD circuit' that are respectively disposed on a semiconductor wafer. Each of the plurality of diode structures of the plurality of inspection target devices simultaneously applies respective specific negative high voltages from the high voltage power source in a manner of being reverse biased, respectively, by which the above object is achieved. 163040. Doc 201245731 The voltage inspecting device of the present invention inspects one or more inspection target devices for ESD tolerance, and the switching mechanism is turned on/off by the upper and lower operations of the contact platform on which the one or more inspection target devices are mounted. 1 to 1 corresponds to the south voltage charging/discharging of each high voltage capacitor mechanism of one or a plurality of inspection target devices, and performing ESD inspection of the one or more inspection target devices by discharging from the high voltage capacitor mechanisms; By doing so, the above object is achieved. Further preferably, the high voltage inspection apparatus of the present invention comprises: a high voltage power supply 'which outputs a specific high voltage; the one or more high voltage capacitance mechanisms 'which store a specific high voltage from the high voltage power supply; One or a plurality of high voltage output units outputting a specific high voltage from the one or more high voltage capacitor mechanisms; and switching the first operation and the second operation by the upper and lower operations of the contact platform, the first action The high voltage output unit is isolated from the terminals of the one or more inspection target devices, and the one or more high voltage capacitor mechanisms are connected to the high voltage power supply side by the switching mechanism; the second operating system The one or more high voltage capacitor mechanisms are disconnected from the high voltage power source by the switching mechanism, and the high voltage output portion is connected to each of the one or more of the inspection target devices. Further, it is preferable that the high-voltage inspection apparatus of the present invention opens and closes the switching mechanism by the contact platform on which the plurality of inspection target devices are mounted, and the one-to-one correspondence corresponds to the respective heights of the plurality of inspection target devices. The high voltage charging/discharging of the voltage-capacitor mechanism performs ESD inspection of the plurality of inspection target devices by discharge from the high-voltage capacitor mechanisms β I63040. Doc 201245731 Further, preferably, in the high voltage inspection device of the present invention, the high voltage power supply outputs a specific high voltage; and the one or more high voltage capacitor mechanisms store the specific high voltage from the high voltage power supply. Voltage; one or a plurality of inter-dust output portions, the output of which is derived from the one or more: high-power capacitor mechanism specific high-power Mi, by the above-mentioned contact level = upper and lower actions switch the mth and the second action, The i-th operation is configured to isolate the high-voltage output unit from each of the terminals of the one or more inspection target devices, and connect the one or more high-voltage capacitor mechanisms to the high-voltage power supply side by the switching mechanism; The second operation is to disconnect the one or more high voltage capacitor mechanisms from the high voltage power supply by the switching mechanism and connect the high power (four) output unit to each of the one or more inspection target devices. The second action of the terminal. Further, it is preferable that the circuit of the high voltage inspection device of the present invention has the same circuit configuration in which the number of devices for processing the specific high voltage is uniformly applied. Further, preferably, the esd circuit in the high voltage inspection device of the present invention comprises: a plurality of high voltage capacitor mechanisms for storing a specific high voltage from the high voltage power source; and a plurality of high voltage output portions respectively passing through Each of the resistors outputs a specific high voltage from the plurality of high voltage capacitor mechanisms; and a plurality of switching mechanisms respectively switch between the high voltage power supply side and the high voltage output unit side respectively A plurality of high voltage capacitor mechanisms. Further, it is preferable that the same circuit in the high voltage inspection device of the present invention has the number of devices independently of the above-described application processing from the above-mentioned 163040. Doc -10· 201245731 Further, through the above-mentioned resistor to the south voltage capacitor mechanism, the above-mentioned switching mechanism is used to reach the above-mentioned circuit of the voltage output unit. Further, the high voltage power source of the high voltage inspecting apparatus of the present invention has a charging processing capability corresponding to the plurality of high voltage capacitor mechanisms of the above-described number of devices to be processed. Further, preferably, the high voltage inspection apparatus of the present invention comprises a plurality of ESD substrates which are stacked with one or a plurality of identical circuits. Further, it is preferable that the high voltage inspection apparatus of the present invention accommodates one or a plurality of ESD boards in the casing. Furthermore, it is preferable that the high-voltage inspection device of the present invention is configured such that a plurality of ESD substrates are vacated from the central circular portion and are radially arranged in abundance, and the respective outputs of the plurality of identical circuits on the plurality of ESD substrates are configured. Each of the terminals is disposed toward the central circular portion side, and each of the plurality of high voltage output portions is provided to each of the plurality of high voltage output portions on the lower side of the central circular portion from each of the plurality of output terminals configured by the same circuit Each terminal of the inspection target device is electrically connected. Furthermore, it is preferable that the high voltage inspection device of the present invention is configured such that a plurality of frames are vacantly arranged in a central circular portion and radially arranged, and a plurality of the same circuits of the plurality of ESD substrates housed in the plurality of frames are arranged Each of the output terminals in the configuration is disposed toward the central circular portion side, and each of the plurality of high voltage output portions can be disposed in the central circular portion from each of the plurality of output terminals configured by the same circuit The respective terminals of the plurality of inspection target devices on the lower side are electrically connected. Further, the 'high-voltage inspection apparatus of the present invention is configured to be self-recovering 163040. Doc 201245731 Each of the output terminals of the same circuit configuration is set to the same distance from each of the high voltage output units to the plurality of inspection target devices, including the number of independent wirings to which the application processing is to be uniformly applied. The distance E' is applied to the same plurality of inspection target devices simultaneously from the same ESD applied voltage waveform from the high voltage power source. Further, in the high voltage inspection device of the present invention, the high voltage output unit and the GND voltage output unit connected to the GND voltage source each have a contact mechanism, and the upper surface is connected to each of the plurality of identical circuits. a plurality of contact members of the voltage output terminal and the GND output terminal, and a plurality of contact members that are connected to the plurality of wires and electrically connected to the terminals of the plurality of inspection target devices are disposed on the lower surface . Further, the contact mechanism in the high-voltage inspection apparatus of the present invention is any one of an actuator 'with a plurality of contact members fixed to the arm and a probe card to which a plurality of contact members are fixed. Furthermore, it is preferable that the high voltage output unit of the high voltage inspection device of the present invention and the GND voltage output unit connected to the GND voltage source each have a contact mechanism provided with respect to each of the one or more inspection target devices. The terminal can electrically connect the plurality of contact members. Further, it is preferable that the high-voltage inspection apparatus of the present invention obtains a theoretical value of a relationship between a discharge limit value calculated by Paschen's Law and a distance between conductive members, and an actual ESD test. The straight line connecting the shortest distances of the measured values is the minimum design value of the distance between the conductive members. 163040. Doc -12-201245731 Further, preferably, the high voltage power supply in the high voltage inspection device of the present invention is reverse biased with respect to a plurality of inspection target devices disposed on the semiconductor wafer. The way is to apply a negative high voltage. Further, in the high-voltage inspection apparatus of the present invention, the connection processing of the plurality of inspection target devices disposed on the semiconductor wafer is continuously performed using the automatic transfer device. Further, it is preferable that the ESD substrate in the high voltage inspection device of the present invention has a socket portion for replacement of parts. Further, it is preferable that the contact member in the high voltage inspection device of the present invention uses a material of indium or tungsten which is thermally resistant to discharge. Furthermore, it is preferable that the substrate of the probe card in the high voltage inspection device of the present invention is a surface wiring substrate for avoiding discharge. Further, in the high-voltage inspection apparatus of the present invention, the theoretical value and the actual relationship between the discharge limit value calculated by the Paschen's law and the distance between the conductive members due to the upper and lower operations of the contact platform are used. The straight line connecting the shortest distances of the measured values obtained by the ESD test is used as the minimum design value of the distance between the conductive members. Further, it is preferable that the contact member in the high voltage inspection device of the present invention maintains the distance between the contact members for avoiding discharge. Further, in the high voltage inspection apparatus of the present invention, as a mechanism for monitoring the waveform of the voltage applied to the ESD from the high voltage source, a round pin connector is provided at the mounting base of the contact member of the substrate of the probe card. Further, the high voltage power source of the high voltage inspection device of the present invention is configured such that a positive power source and a negative power source are mounted with respect to the GND potential, and can be cut to 63040. Doc -13· 201245731 The positive power source and the negative power source are replaced, and the forward bias and the reverse bias are switched with respect to the plurality of inspection target devices. Further, in the high voltage inspection device of the present invention, the plurality of inspection target devices disposed on the semiconductor wafer are short-circuited to the Gnd potential. Further, in the high-voltage inspection apparatus of the present invention, the conductive outer peripheral portion of the semiconductor wafer is electrically short-circuited to the GND potential, and the GND potential which is short-circuited between the plurality of inspection target devices is electrically connected. The Gnd potential of the wafer platform conductive layer on the conductive outer peripheral portion of the semiconductor wafer and the GND potential of the ESD circuit are connected as a common GND potential, thereby eliminating the connection processing of the GND terminals of the plurality of inspection target devices. Further, preferably, the computer system in the high voltage inspection device of the present invention controls the operation of the ESD controller and the probe device that controls switching by the switching mechanism, and is based on the position of the plurality of inspection target devices. The wafer mapping of the site performs probing control. Further, preferably, in the high voltage inspection apparatus of the present invention, in the probe card, the vertical needle design basis of the plurality of probes uses the discharge limit value calculated by the Paschen's law relative to the conductive member. The theoretical value of the relationship between the distances and the shortest distance from the actual measured value obtained by actually performing the ESD test 'as the minimum design value of the distance between the conductive members, when a distance larger than the size of the semiconductor wafer is required Designed to keep, for example, skip one semiconductor wafer or skip more than two spatial distances. Further, preferably, in the high voltage inspection apparatus of the present invention, in the probe card, the semiconductor wafer in the space region which cannot be detected by one contact is used by the individual I63040. Doc • 14·201245731 The computer PC (Personal Computer) performs the contact processing in the order of the detection control of the main body, and the ESD application is performed without fail. According to the above configuration, the operation of the present invention will be described below. In the present invention, a high voltage inspection device for inspecting ESD tolerance for a plurality of inspection target devices includes: a high voltage power supply that outputs a specific high voltage; and an ESD circuit that uniformly simultaneously performs the plurality of inspection target devices A specific high voltage from the high voltage power supply is applied. In this way, a plurality of devices to be inspected are collectively and a high voltage application test is performed accurately and accurately in a current waveform (or voltage waveform) suitable for the specification, whereby the high voltage inspection can be performed in a large and efficient manner. In particular, in the present invention, 'in a high voltage inspection device for checking esd resistance for a plurality of inspection target devices' includes: a high voltage power supply that outputs a specific negative high t voltage; and an ESD circuit 'which is respectively disposed in the semiconductor Each of the diode structures of the plurality of inspection target devices on the wafer uniformly applies respective specific negative high voltages from the high voltage power source in a manner of being reverse biased. Therefore, even when a plurality of devices to be inspected are unified, and a high-voltage application test is performed accurately and accurately for a current waveform (or voltage waveform) suitable for the specification, it is also possible to easily form a short-circuit defect. The ground's large-scale and efficient high-voltage inspection. Further, in the present invention, in the high voltage inspection apparatus for inspecting the ESD tolerance of one or a plurality of inspection target devices, the switching mechanism is driven by the contact platform on which the one or more inspection target devices are mounted. Open/close '1 to 1 corresponds to one or a plurality of inspection object devices 163040. Doc •15· 201245731 High voltage charging/discharging of each high voltage capacitor mechanism, ESD inspection of the one or more inspection target devices is performed by discharge from the respective high voltage capacitor mechanisms. Therefore, the overall configuration can be simplified without using a high withstand voltage relay, and the high voltage application test can be performed with a current waveform (or voltage waveform) suitable for the specification. [Effects of the Invention] According to the present invention, the plurality of devices to be inspected are uniformly and accurately applied to the current waveform (or voltage waveform) suitable for the specification, so that the high voltage application test can be performed accurately. High voltage inspection is performed in a large and efficient manner. In addition, even when a plurality of devices to be inspected are uniformly integrated, and a high-voltage application test is performed accurately and accurately for a current waveform (or voltage waveform) suitable for the specification, it is also possible to simply form a short circuit. 'High voltage inspection is performed in a large and efficient manner. Further, the overall configuration can be simplified without using a high withstand voltage relay, and the high voltage application test can be performed with a current waveform (or voltage waveform) suitable for the specification. [Embodiment] Hereinafter, embodiments 丨 to 3 of the high-voltage inspection apparatus of the present invention will be described in detail in the case of application to an ESD device. Further, by using the switch 52 of the above-described third embodiment and the lowering mechanism on the contact stage 及其 and its peripheral control electric power, instead of the high-time pressure relay 3 of the above-described embodiment i and its driving power source and coffee controller, The above-described embodiment i is applied to the above-described third embodiment, omitting the high-withstand voltage relay 3 using mercury. Furthermore, the thickness of each of the constituent members in each figure or 163040. Doc • 16 - 201245731 The length and the like are not limited to the illustrations from the point of view of the production of the drawings. (Embodiment 1) FIG. 1 is a circuit diagram showing an example of the configuration of an E S D test apparatus according to Embodiment 1 of the present invention. In Fig. 1, as this embodiment! The ESD test apparatus 1 of the high voltage check device has a high voltage power supply 2 that outputs a specific high voltage, and an ESD circuit 1 that uniformly applies a specific voltage from the high voltage power source 2 to the plurality of inspection target devices 6 at the same time. High voltage; the ESD test device 检查 checks ESD tolerance for a plurality of inspection target devices 6. The ESD circuit 1 has a plurality of high voltage capacitors 4 as a high voltage capacitor mechanism for storing a specific high voltage from the high voltage power source 2, and a plurality of voltage output portions for making specific ones from the plurality of high voltage capacitors 4. The high voltage is output by applying the resistor 5, respectively; and the high withstand voltage relay 3' serves as a high voltage to connect the high voltage from the high voltage power source 2 to the high voltage capacitor 4 side, or to a specific high voltage from the high voltage capacitor 4. A plurality of switching mechanisms that switch between voltages connected to the high voltage output unit side; and the number of the plurality of inspection target devices 6 that are to be uniformly applied to each other independently and in parallel, is high resistance from the high voltage capacitor 4 The voltage relay 3 and the resistor 5 are further applied to the circuit of the high voltage output portion. In the ESD test device 1, one of the terminals of the high-voltage power source 2 is connected to a plurality of (here, eight) high-voltage capacitors via respective contacts of the high-voltage relay 3 of the multi-contact (here, the 8-contact). 4 each electrode, and a plurality of (here is 163040. Doc 201245731 8) Each of the other electrodes of the high voltage capacitor 4 is connected to the other terminal of the high voltage power source 2 and grounded. Each of the plurality of (here, eight) high voltage capacitors 4 is connected to each of the contacts of the high withstand voltage relay 3 from the plurality of contacts (here, the eight contacts) by the respective applied resistors 5 from the high voltage. The output unit is connected to one of the terminals of each device 6 to be inspected. The other terminals of the respective devices 6 are respectively connected to the other terminal of the high voltage power source 2 from the GND voltage output portion and grounded. Although not shown here, an ESD controller 9 is provided which controls simultaneous switching of the high withstand voltage relay 3 of a plurality of contacts (here, 8 contacts) at a specific timing. The power supply of the high withstand voltage relay 3 for driving the multi-contact (here, the 8-contact) needs to be additionally set. The voltage source 2 is selected and shared by the appropriate charging processing capability according to the capacitance of the number of high voltage capacitors 4 to be uniformly processed. The high withstand voltage relay 3 is used for a mercury relay with directionality. Here, it can be a high-voltage relay with 8 contacts. It can be used for two 4 contacts or four 2 contacts. It is also possible to set eight high-resistance relays 1 of 1 contact to replace the high-voltage relay 3 of the 8-contact. The high-voltage capacitor 4 is switched between the high-voltage power supply 2 side and the high-voltage power supply 2 side by the ESD controller ... contact (not shown). The control signal transmitted to the high withstand voltage relay 3 for independent application of the high voltage from the eight high-voltage capacitors 4 to the eight devices 6 is set to single-simultaneous control. If the high-voltage relays 3 are stacked and the components that are operated by the magnetic field of the coil are arranged, the malfunction may occur, which is not good. Also, as shown in Figure 21 below, it can be a high-voltage relay like 163040. Doc 201245731 102 is a high-capacity relay with independent high-voltage relay 103 for discharge. The voltage capacitor 4 is used here to select the one that has the right to be suitable for the test voltage. When the capacitor is selected, it is selected in accordance with the specification of the ESD test, and is selected for each test mode. For example, if it is Ηβ μ, it is 100 pF, and if it is ΜΜ, it is 200 pF. Applying a resistor 5 here uses 8 ', for example, if it is a HBM specification, use 1. 5 Κ Ω or so, if the specification is set to 〇 κω (no resistance). The high-voltage capacitor 4 and the applied resistor 5 are electrically connected to each other in the same number as the number of devices 6 to be collectively processed. The device 6 is, for example, an LSI element, or a light-emitting element such as an LED element or a laser element, etc. According to the above configuration, the first contact of the high-voltage relay 3 of the high-voltage relay 3 by the ESD controller 9 not shown by φ is applied to the high-voltage power supply. The two side turn-on currents are branched from the high voltage power source 2 into 8 strands and flow into the respective high voltage capacitors 4 and are equally stored at a high voltage of the power source 2. At this time, the eight contacts on the device 6 side of the high-yield relay 3 are turned off by the ESD controller 9. After the eight contacts of the high voltage power supply 2 side of the south financial pressure relay 3 are disconnected by the ESD controller 9, the eight contacts of the device 6 side of the high withstand voltage relay 3 are turned on. Way to control. Thereby, the high voltages stored in the high voltage capacitor 4 are applied to the terminals of the respective devices 6 to be inspected by the respective application resistors 5 through the eight contacts of the high withstand voltage relay 3. In this case, each of the high-voltage capacitors 4 is in a one-to-one correspondence with each of the devices 6 to be inspected, and a clear and accurate ESD inspection is performed in a large and efficient manner. I63040. Doc 201245731 Thus, the eight contacts of the high withstand voltage relay 3 can be switched from the high voltage power source 2 side to the respective device 6 side of the inspection object by the ESD controller 9, and the eight high voltage capacitors 4 are charged or discharged. From the eight high-voltage capacitors 4, specific and accurate high voltages are respectively applied from the respective high voltage output units to the respective devices 6 to be inspected. The switching operation of the eight contacts of the high withstand voltage relay 3 is simultaneously performed by the ESD controller 9 at a predetermined timing. The ESD test determines whether or not it is suitable by a plurality of application modes and an ESD current waveform (or an ESD voltage waveform) applied to each device 6 to be inspected. The ESD test system is connected from the high voltage power source 2 to the eight contacts of the high withstand voltage relay 3 via an ESD application circuit in which eight high voltage capacitors 4 and a series circuit of the applied resistors 5 are connected in parallel, thereby passing through the socket. A high voltage is applied to each of the devices 6 to be inspected by an operator that fixes a plurality of probes (contact members) to the arm, a probe card to which a plurality of probes (contact members) are fixed, and the like as a contact jig. Each of the supply-side terminal (one) and the GND-side terminal (one) of the high voltage is brought into contact with each terminal of the device 6 to be inspected, and eight high voltages are simultaneously applied to each device 6 to be inspected. In this case, each of the devices 6 to be inspected performs high voltage application processing at the same time. Fig. 2 is a plan view schematically showing four adjacent vertical and horizontal cross-sections of a semiconductor wafer arranged in a plurality of matrix shapes in a plane of a semiconductor wafer. In FIG. 2, opposite terminals 12 are provided on both sides of a semiconductor wafer as a device 6 for inspecting a plurality of matrix-shaped inspection objects in a plane of a semiconductor wafer. Thus, for each semiconductor wafer u There are two terminals 12 provided on it, and it is sometimes used as a contact member I63040 for high voltage application indicated by an arrow. Doc • 20· 201245731 For example, the probe 13 is in contact with the opposite direction (triangle △) of the terminal 12, and sometimes the probe 13 for high voltage application by the arrow is in contact with the abutting direction (number X) of the terminal 12. . Fig. 3 is a graph showing the relationship between the discharge limit value of the theoretical value and the measured value as a parameter with respect to the distance between the electrodes. The measured value between the opposite terminals indicated by the angle ▲ of Fig. 3 is as shown in Fig. 2, and the probe 13 for high voltage application indicated by the arrow is in contact with the opposite direction (two angles Δ) of the terminal 12. The observations in the case of the situation. Further, the measured value between the adjacent terminals indicated by the cross pattern X of Fig. 3 is as shown in Fig. 2, and the probe 13 for high voltage application indicated by an arrow is brought into contact with the adjacent direction (number X) of the terminal 12. The observations in the case of the situation. In FIG. 3, the relationship between the discharge limit value and the distance between the electrodes is shown, and the _ four-corner pattern is obtained by Paschen method (solving to reduce the distance to the prescription when a high voltage is applied between the terminals). The theoretical value obtained is calculated, and the triangular pattern ▲ and the cross pattern X are obtained from the actual measured values in the state where the ESD test is actually performed, and are instantaneously and instantaneously applied from the high voltage capacitor 4 to the terminals of the device 6. The observation when the ESD applies a voltage waveform. The triangular pattern ▲ is the measured value between the opposing terminals (discharge distance when a high voltage is applied between the two terminals facing the semiconductor wafer i 1 ), and the cross-sectional pattern X is the measured value between adjacent terminals (toward the adjacent The discharge distance between the semiconductor wafers ii and the terminals where high voltages are applied to each other. When the high voltage stored in the high voltage capacitor 4 from the high voltage power source 2 is, for example, 1500 V, the discharge start voltage is set to 15 〇〇 v, and the interelectrode distance of the discharge limit value in the theoretical value of the square pattern is For 14〇μιη& 163040. Doc -21 - 201245731 In the measured value between the opposite terminals of the right angle pattern ▲, the distance between the electrodes of the discharge limit value is about 50 μΠΐ, which is opposite to the measured value between the adjacent terminals of the fork pattern X. The distance between the electrodes of the discharge limit value is about %. Therefore, it can be seen that 'the discharge limit value of the measured value between the opposing terminals is shorter than the measured value between the adjacent terminals. β The straight line connecting the measured values to the shortest distance between the measured values and the theoretical value can be used as the discharge limit value with respect to the ESD circuit 10. The relationship between the distance between the electrodes and the design value of the distance between the probes is used. In this case, on the straight line of the theoretical value, the distance between the terminals is between 1 50 μηι and 200 μπι and is shifted to the straight line of the measured value (the cross-shaped pattern X is the straight line of the measured value between the adjacent terminals). Therefore, a straight line of the theoretical value is used on the lower voltage value side of the high voltage card and a straight line of the measured value is used on the higher voltage value side with respect to the interelectrode distance with respect to the discharge limit value of the high voltage to be applied. Therefore, 'when the voltage stored in the high-voltage capacitor 4 from the high-voltage power source 2 is, for example, a lower voltage value side such as 1 $ 〇〇ν, 'If the discharge start voltage is set to 1500 V, it is necessary to exceed The theoretical value is the distance between the electrodes of 140 μηι. Fig. 4 is a perspective view showing an enlarged schematic view of a state in contact with the device 6 in the ESD test apparatus 1 of Fig. 1. Fig. 5 is a perspective view schematically showing a configuration example of the ESD application device 1 of Fig. 1 when ESD is applied. In FIG. 4 and FIG. 5, in the ESD test apparatus 1 of FIG. 1, for the sake of safety, a high-voltage power supply 2 and 8 contact high-voltage relays 3 and 8 south-voltage capacitors 4 are mounted. The eight esd substrates to which the resistor 5 and other additional circuits are applied are housed in the casing, and include an 8 ch ESD substrate box 21 having a self-pressurizing capacitor 4 passing through the junction of the high voltage matching relay 3 to reach the applied resistor 5 I63040. Doc • 22·201245731 series circuit 8 wiring output portion 21a; and probe card 22, wherein each wiring 23 from the wiring output portion 2 1 a of the ESD substrate box 21 passes through a connector provided on the upper surface 24 sets of probes 22a and 22b respectively connected to the lower surface side. 8 sets of probes 22a and 22b are respectively protruded from the lower surface so as to correspond to the two terminals 6a and 6b of each device 6 in a one-to-one manner; The semiconductor wafers 8 on the wafer platform 7 are provided with a plurality of terminals 6a and 6b of a plurality of devices 6 and a plurality of probes 22a and 22b respectively connected to the respective high voltage capacitors 4 in a matrix. 1 to 1 corresponding to the configuration. The ESD applied voltage waveform changes by a change in the wiring length from the wiring output portion 21a of the ESD substrate box 21 to the probe card 22. Therefore, the wiring lengths from the respective terminals 6a and 6b of the high voltage electric grid 4 to the device 6 are all the same wiring length, and the ESD voltage waveforms applied to the respective terminals 6a and 6b of the device 6 are the same. The ESD substrate may also have a socket portion for part replacement. Fig. 6 is a plan view schematically showing a schematic example of the arrangement of a plurality of ESD applicators in the ESD test apparatus 1 of Fig. 1. As shown in FIG. ,, in the ESD test apparatus ία, a plurality of ESD substrates 31 as a plurality of ESD applicators vacate the central circular portion 32 and are erected around them and radially arranged 'the plurality of ESD substrates 3' Each of the plurality of output terminals having the same circuit configuration is disposed toward the central circular portion 32 side. Each of the plurality of high voltage output portions can be electrically connected to each of the plurality of inspection target devices 6 provided on the lower side of the central circular portion 32, for each of the output terminals of the plurality of high voltage output portions. The number of devices to be uniformly applied is included in each of the output terminals of the same circuit from the plurality of output terminals to the plurality of inspection target devices 6 each passing through the high voltage output portion. The distances of the independent wirings of doc 23·201245731 are all set to the same distance, and the same ESD applied voltage waveforms from the high-voltage power source 2 are simultaneously and surely applied to the respective terminals of the plurality of inspection target devices 6 . As the ESD test apparatus 1A, a plurality of high-voltage relays 3 of a plurality of contacts of the ESD circuit 10, a plurality of high-voltage capacitors 4, and a plurality of ESD substrates 31 for applying the resistors 5 are mounted to remove the central circular portion 32. The annular shape is radially (relative to the center of the central circular portion 32). The thickness of the high withstand voltage relay 3 is approximately 15 mm for the common 4000 V withstand voltage, and is 8000 V withstand voltage. When, it is about 30 mm. How many pieces of ESD substrate 31 can be configured by this thickness. When the thickness of the high withstand voltage relay 3 is 15 mm for a withstand voltage of 4000 V and the inner circumference of the central circular portion 32 is 40 cm, 64 ESD substrates 31 can be disposed. Further, since the thickness of the ESD substrate 31 is determined by the thickness of the high withstand voltage relay 3, it is preferable to use the thickness of the high withstand voltage relay 3 to be thin. For example, when one ESD substrate 31 is 4 ch, when eight high-voltage relays 3 with one contact are mounted, if the thickness of the high withstand voltage relay 3 is 4000 V, the voltage is 13. 5 mm ' has the ability to radially mount 83 ESD substrates 31 all at 332 ch (ESD test can be performed on 332 devices 6 at the same time). In this case, the outer circumference of the ESD substrate 31 is about 50 cm in diameter. The wiring 23 is drawn from the inner peripheral side of the plurality of ESD substrates 31 and connected to the connector 24 of the probe card 22, and the complex array probes 22a and 22b disposed on the lower surface of the probe card 22 are attached to the wafer platform. The terminals 6a and 6b of the respective devices 6 in which a plurality of inspection objects are arranged in a matrix on the semiconductor wafer 8 on the seventh substrate are connected in a one-to-one manner to perform an ESD test. Probes 22a, 22b and device 163040. Doc • 24· 201245731 The positional relationship of the terminals 6a and 6b can be correctly positioned by the image recognition while the wafer platform 7 side of the probe device constituting the automatic transfer device is correctly moved. Here, the ESD test can be performed on the semiconductor wafer 11 of 4 μm μm 2 μm size for every 64 lines, and the operation is repeated, and all wafer wafers (for example, 100,000) are automatically processed in sequence. Since it is difficult to raise the probes 22a and 22b in the adjacent rows, it is preferable to carry out the ESD test in two rows or more in one row, which is less likely to cause a contact failure. Moreover, in the design of the needle of the probe card, the theoretical value of the relationship between the discharge limit value calculated by the Paschen's law and the distance between the conductive members is connected, and the actual value obtained by actually performing the ESD test is the shortest. When the distance must be greater than or equal to the size of the semiconductor wafer, for example, a design is formed in which the semiconductor aa slices are skipped or two or more spatial distances are skipped to avoid discharge between adjacent probes. The semiconductor wafer in which the space which cannot be detected by one contact can be detected by the following personal computer PC, and the contact processing is performed in order, and the ESD application is performed without fail. The wiring length from the ESD substrate 31 to the device 6 is preferably 2 〇 cm or less as the specification of the ESD applied voltage waveform of Fig. 8(b). The wiring lengths from the respective terminals of the ESD substrates 31 to the eight devices 6 are all the same wiring length, and the ESD voltage waveforms of Fig. 8(b) applied to the respective terminals of the device 6 are the same. In this way, the ESD test becomes uniform. Figure 7 (a) is a plan view schematically showing another setting example of a plurality of ESD applicators in the drawing device 1, and Figure 7 (b) is a Figure 7 (the magic ESD applicator and probe card and probe A longitudinal sectional view of the needle device. Fig. 8(a) is a perspective view schematically showing the ESD applicator of Fig. 7(a), and Fig. 8(b) is shown at 163040. Doc •25· 201245731 Diagram of the ESD applied voltage waveform used in the ESD test. In FIGS. 7(a), 7(b) and 8(a), in the ESD test apparatus 1B, a plurality of frames, that is, a plurality of ESD substrate boxes 21, vacate the central circular portion 25 and radiate around them. Configuration. The respective output terminals of the plurality of ESD substrates 31 housed in the plurality of ESD substrate boxes 21 having the same circuit configuration are disposed toward the central circular portion 25 side. Each of the output terminals of the plurality of high voltage output units can be electrically connected to each of the terminals 6a and 6b of the plurality of inspection target devices 6 provided on the lower side of the central circular portion 25. Sexual connection. The respective distances from the respective high-voltage output units to the plurality of inspection target devices 6 including the number of independent wirings 23 to which the number of devices to be uniformly applied are uniformly set are set to The same distance and the same ESD applied voltage waveform from the high voltage power source 2 are simultaneously applied to a plurality of inspection target devices 6. Further, the high voltage output unit may be an output terminal formed of the same circuit or may be connected to the probes 22a and 22b of the probe card 22 via the output terminal. As the ESD test apparatus 1B, a plurality of ESD substrates 31 equipped with a high-voltage power source 2 and an 8-contact high-voltage relay 3, eight high-voltage capacitors 4, eight applied resistors 5, and other additional circuits are housed in the ESD test apparatus 1B. The ESD substrate case 21 of the wiring output portion 21a of the circuit 8 of the series circuit of the series circuit of the high-voltage capacitor 4 is passed from the junction of the high-voltage capacitor 4 to the circuit of the high-voltage capacitor 3, and is arranged radially. One. The wiring 23 is drawn from the inner peripheral side of the eight ESD substrate boxes 21 and connected to the connector 24 of the probe card 22, and the eight sets of probes 22a and 22b provided on the lower surface of the probe card 22 are automatically transported. Packed 163040. Doc • 26· 201245731 The semiconductor wafer 8 on the wafer platform 7 of the prober is provided with a matrix of 8 terminals 6a, 6b of each of the plurality of devices 6 in a plurality of devices 6 ESD testing is performed in a one-to-one correspondence to repeat this operation. The wiring length from the wiring output portion 21a of the 8th ESD substrate case 21 to the respective devices 6 is preferably 20 cm or less as the specification of the ESD applied voltage waveform of Fig. 8(b). The wiring lengths from the respective wiring output portions 21a of the respective ESD substrate boxes 2 to the respective terminals of the eight devices 6 are all the same wiring length, and the ESD voltage of FIG. 8(b) applied to each terminal of each device 6 is applied. The waveform is the same. In this way, the ESD test becomes uniform. Fig. 9 is a block diagram showing wafer mapping and detection management mainly based on a personal computer pC. In Fig. 9, the ESD test apparatus 1 of the winter embodiment 1 has a personal computer PC that performs probe management, a high voltage power supply 2, and an ESD controller 9, which receives an instruction from a personal computer PC to drive; the ESD circuit 10, which is composed of 8 parallel circuits, which are simultaneously switched to the high voltage power supply 2 side by the ESD controller 9 and the 8 contacts of the high withstand voltage relay 3 and will be from the high voltage power supply 2 The high voltage is stored in the eight high voltage capacitors 4, and thereafter, the 8 contacts of the high withstand voltage relay 3 are simultaneously switched to the sides of the eight applied resistors 5 at a specific timing; and the probe 20 is used to: After the semiconductor wafer 8 of the wafer stage 7 is moved, the ESD voltage is applied from the ESD circuit 10 via the eight applied resistors 5, and the probes 22a and 22b of the eight sets of probe cards 22 are respectively connected to the eight devices. Each of the terminals 6a, 6b of 6 is brought into contact with each of the terminals 6a, 6b by the eight sets of probes 22a, 22b. For the semiconductor 163040. Doc •27- 201245731 When up to ten million wafers of wafer 8 are sequentially subjected to ESD test, the probes 20 are automatically transported and continuously detected. The detection management may be based on a personal computer PC, and the wafer mapping on the semiconductor wafer 8 indicates the address of a plurality of (for example, 100,000) semiconductor wafers arranged in a matrix on the semiconductor wafer 8. The semiconductor wafer 11 of which address range is subjected to ESC test, and the semiconductor wafer 11 of which address is ESD withstand voltage failure. The ESD withstand voltage is caused by the voltage in the opposite direction of the diode structure of the semiconductor wafer 11. When the current is higher than a specific value, it is determined to be defective by the measuring device, and the address of the semiconductor wafer 11 is memorized in the personal computer PC. The ESD controller 9 not only performs the operation control of the high withstand voltage relay 3 of the ESD circuit, but also operates in accordance with the setting of the voltage level to be applied, or the sequence of the number of applications and the polarity conditions to be applied in advance by a program or the like. According to the first embodiment, in the case of mass production, the plurality of devices 6 to be inspected are collectively and the electric dust application test is performed accurately and accurately by the ESD application electric field waveform suitable for the specification. High voltage inspection can be performed in a large and efficient manner. Further, in the first embodiment, although not described in detail, each of the semiconductors serving as the plurality of devices 6 before being sliced (before cutting) arranged in a matrix on the semiconductor wafer 8 is used. In addition to the esd test, the wafer 11 may be subjected to an ESD test for each semiconductor wafer J i after being sliced (after cutting) and having a state of holding the substrate (a state in which the semiconductor wafer 11 is arranged in a matrix). 'In the first embodiment, although not described in detail, but 163040. Doc -28· 201245731 The voltage source 2 is configured to be equipped with a positive power supply and a negative power supply with respect to the GND potential, and can switch between the positive power supply and the negative power supply, and can be configured to switch the forward direction with respect to the plurality of inspection target devices 6'. The voltage is biased in the opposite direction. (Embodiment 2) In the first embodiment, the case where the specific high voltage from the high-voltage power source 2 is unified with respect to the plurality of inspection target devices 6 and the same ESD applied voltage waveform is correctly applied is described. In the second embodiment, in the case where the terminals 12b on the gnd side of the semiconductor wafer 为i are electrically short-circuited, the semiconductor wafers are stably arranged in a matrix on the semiconductor wafer. The case of the ESD withstand voltage inspection of the plurality of inspection target devices 6 will be described. Moreover, in the action polarity of the device during the ESD test, there is a forward biasing of the mouth and a reverse biasing of $. Two kinds of broken square pianos are generally known to be tested by reverse bias application to ensure high reliability. Here, in particular, the device is constructed and combined with the ESD specification for maintaining the reverse bias voltage. The configuration of the apparatus in which the device is designed to perform bidirectional bias application will be described. Fig. 10 is a circuit diagram showing a configuration example of an ESD test apparatus according to a second embodiment of the present invention. In Fig. 10, the ESD test apparatus 1C as the high voltage inspection apparatus of the second embodiment has a high voltage power supply 2C and an output thereof. a specific negative high voltage; and an ESD circuit i〇c that collectively applies the same from the high voltage power supply 2C to the specific number of inspection target devices 6 of the plurality of inspection target devices 6 arranged in a matrix on the semiconductor wafer 8. The specific negative high voltage; the esd measured 163040. Doc -29-201245731 The test apparatus ic checks ESD resistance against a plurality of inspection target devices 6 on the semiconductor wafer 8. The ESD circuit 10c has a plurality of high voltage capacitors 4 as a plurality of high voltage capacitor mechanisms for storing a specific negative high voltage from the voltage source 2; a plurality of high voltage output portions for a plurality of high voltage capacitors The negative high voltages of the respective characteristics of 4 are respectively output by applying the resistor 5; and one or a plurality of high withstand voltage relays 3 are connected as a high voltage capacitor for connecting a specific negative high voltage from the plurality of high voltage power sources 2C 4 sides or a plurality of switching mechanisms for switching the specific high voltage from the capacitor 4 to the high voltage output side; as the same circuit configuration, a plurality of checks are performed independently and in parallel with the uniform application processing The number of the target devices 6 has the same number of circuits from the high-voltage capacitor 4 through the high withstand voltage relay 3 and further to the high voltage output portion by applying the resistor 5. The ESD circuit 10C is composed of eight parallel circuits which simultaneously switch the 8 contacts of the high withstand voltage relay 3 to the high voltage power supply 2C side by the ESD controller 9, and from the high voltage power supply 2 (The negative high voltage is stored in the 8 high voltage capacitors 4, and the money contacts the 8 contacts of the high withstand voltage relay 3 at the same timing to the 8 applied resistors 5 side, and the negative voltage from the 8 high voltage capacitors 4 The high voltage reaches the respective sides of the respective applied resistors 5 via the 8 contacts of the high withstand voltage relay 3, respectively. In this case, the device 6 to be inspected is connected to the (4) element or the laser element having the diode structure inside. The high-voltage capacitor 4' stored by the high-power magic power supply 2C is 163040 with respect to the diode structure of the plurality of inspection target devices 6 arranged in a matrix on the semiconductor wafer 8. Doc -30- 201245731 Apply a negative high voltage in the reverse bias mode. In the ESD test device ic, one of the terminals of the high-voltage power supply 2C that outputs a negative high voltage is connected to each of the plurality of high-voltage relays 3 via a multi-contact (here, an 8-contact) (here, 8) Each of the electrodes of the high voltage capacitor 4, and the other of the plurality of (here, eight) high voltage capacitors 4 are respectively connected to the other terminal of the high voltage power source 2C and grounded. Each of the plurality of (here, eight) high-voltage capacitors 4 is connected to each of the high-voltage relays 3 of the multi-contact (here, 8 contacts) through the respective application resistors 5 from the high-voltage output portion. Do not connect to one of the terminals of each device 6 of the inspection object. The other terminals of the respective devices 6 are respectively connected to the other terminals of the high-voltage power source 2C from the GND voltage output portion and grounded. Although not shown here, the following ESD controller 9 is connected to the high-withstand voltage relay 3 that controls the multi-contact (here, the 8-contact) at a specific timing. The power supply of the high withstand voltage relay 3 for driving the multi-point (here, the 8-contact) needs to be additionally set. Fig. 11 is a schematic view showing a case where a plurality of inspection target devices 6 arranged in a matrix on the semiconductor wafer 8 are subjected to a withstand voltage inspection using the ESD test apparatus 1C of Fig. 10 . In Fig. 11, the high voltage capacitor 4 in the ESD test apparatus (1) is charged with a negative high voltage, for example, _15 〇〇 v is applied to the anode terminals of the respective devices 6 to be inspected, and 0 V is applied to the cathode terminals. As described above, since a negative high voltage of -1500 V is applied to the anode terminal of each device 6, and 〇 v is applied to the cathode terminal, an ESD reverse voltage is applied to the diode structure to perform an ESD test. In this case, the high voltage power supply 2C is set as the power source. The voltage supply side and the GND side of ESD1〇c are inverted. In order to attract high voltage from the n-GaN substrate via the anode terminal 163040. Doc -31 · 201245731 The charge amount of capacitor 4 (for example, 1 〇〇 pF), the amount of charge passing through the anode terminal is fixed. The anode electrode is independent of the unit of the device, so that it is not a problem as a coffee condition. Thereby, the application of the predetermined amount of charge (e.g., 100 pF) of the high voltage capacitor 4 can be surely ensured for each of the devices 6. Further, when the high-voltage power source 2C is set to the + power source, the forward bias can be realized. On the other hand, as shown in FIG. 12, if a positive power source is used, the polarity of the application circuit (GND) is reversed to thereby set the state of the reverse bias when the cathode terminal of the device 6 is generated to the anode of the adjacent device 6. In the case of a short circuit of the terminals, the amount of charge applied is dispersed on the n-GaN substrate, and the amount of charge from the cathode terminal of the same device 6 through the anode terminal becomes indefinite. Thus, when there is a short circuit failure, the charge set at the short-circuit position is detached from the ESD. This can be eliminated by the negative high voltage map test device 1C. Fig. 13 is a plan view showing a probe arrangement for each of the terminals of the semiconductor wafer i 1 as an example of detection in the case where a plurality of devices are applied to the ESD in the ESD test apparatus 1C of Fig. 1 . As shown in FIG. 13, the contact to each terminal 12a of the ESD charge supply source, that is, the probe 22a, is independently performed in units of devices (each semiconductor wafer), and an application circuit (including the ESD circuit 10C and the high voltage output) is implemented. The circuit of the part is mounted in contact with the probe. Thus, the probe 22a of each terminal 12a of the semiconductor wafer 11 to which the ESD voltage waveform of FIG. 8(b) is applied is independently provided for each semiconductor wafer 11 as the GND side terminal, that is, the terminal 12b of the semiconductor wafer 11. When the pin 22b is in the case of the semiconductor wafer in the electrically short-circuited state on the GND side of the semiconductor wafer 11, the ESD voltage wave is 163040. Doc -32· 201245731 The application process of the shape may be performed by using a defect (or a plurality of components of the semiconductor wafer). Each of the terminals 12b on the GND side of the plurality of devices is electrically short-circuited in the wafer 8, so that the probe 22b connected to the gnd (COM) of the ESD circuit 1〇c is at least one of the plurality of terminals 12b on the GND side. The point contact ' becomes the same state as the state in which it is in contact with the entire device. Thus, at least one contact probe on the GND side can be reserved without leaving the rest. Fig. 14 is a view schematically showing the connection to the apparatus 6 to be inspected when the probe on the gnd side is omitted. In Fig. 14, a grounded wafer stage conductive layer 42 is provided on the surface side of the wafer stage insulating layer 41, and a semiconductor wafer 8 is mounted on the wafer stage conductive layer 42. The plurality of inspection target devices 6 arranged in a matrix on the semiconductor wafer 8 are subjected to short-circuit processing in a state where the GND side between the plurality of inspection target devices 6 is short-circuited in the manufacturing process. Further, a conductive film is formed on the side surface of the semiconductor wafer 8, and the ground terminal (GND terminal) of the inspection target device 6 is electrically connected to the wafer platform conductive layer 42 via the conductive film on the side of the wafer edge. . Each of the wires 23 from the wiring output portion 21a is connected to the probe 22a on the lower surface side of the probe card 22 via a connector 24 provided on the upper surface of the probe card 22, and corresponds to each device 6 in a one-to-one manner. The mode probes 22a are respectively protruded from the lower surface and are provided separately. The GND of each of the devices 6 short-circuited, the GND of the wafer platform conductive layer 42, and the GND of the ESD circuit 10C are connected as a common GND, whereby the detection of the GND terminal of each device 6 is eliminated at all. As described above, according to the second embodiment, the plurality of devices 6 to be inspected are uniformly defined by the ESD voltage waveform suitable for the specification 163040. Doc -33- 201245731 and the high voltage application test is performed correctly, so that the high voltage check can be performed in a large and efficient manner. In addition, even when a plurality of inspection target devices 6 arranged in a matrix on the semiconductor wafer 8 are short-circuited on the GND side or when a wafer short-circuited on the GND side between the devices 6 is used, it is correct. The ESD withstand voltage test is performed stably and efficiently and efficiently. Further, in the first and second embodiments, the substrate of the probe card 22 is not a multilayer wiring substrate, and the surface wiring substrate for discharge is avoided. In the case where a multilayer wiring board is used as the substrate of the probe card 22, it is a high voltage of several thousand V, and therefore it is necessary to consider the dielectric constant (avoidance of discharge characteristics) and distance/voltage between the wirings. Preferably, the probe is made of a material of indium or tungsten which is thermally resistant to discharge. The probe maintains the distance between the probes for avoiding discharge. As a mechanism for monitoring the voltage waveform applied by the ESD, it is preferable that a round pin connector is provided at the root of the probes 22a and 22b of the substrate of the probe card 22. (Embodiment 3) In the third embodiment, the case where the ESD test is performed without using the mercury relay as the high withstand voltage relay 3 will be described. Fig. 15 is a longitudinal sectional view schematically showing a state in which the contact platform is in the upper position in the ESD test apparatus according to the third embodiment of the present invention. Fig. 16 is a longitudinal sectional view schematically showing the state in which the contact platform is in the lower position in Fig. 15iESD test apparatus. In the ESD test apparatus (1) of the third embodiment, in which the esd tolerance is checked for one or a plurality of inspection target devices, the contact platform 53 on which one or a plurality of inspection target devices 54 are mounted is operated up and down. The switch 52 of the switch mechanism is turned on/off, which will correspond to an I63040 as... Doc -34·201245731 or the voltage charging/discharging of the high voltage capacitor 56 of each of the high voltage capacitor mechanisms of the plurality of inspection target devices 54. The ESd of the one or more inspection target devices 54 is performed by the discharge from the respective high voltage capacitors 56. an examination. The ESD test apparatus 1 of the third embodiment has: a high voltage power supply 55 that outputs a specific high voltage; one or a plurality of high voltage capacitors 56 that store a specific high voltage from the voltage source 55; and a probe card The probes 57a, 57b of 57 are used as one or a plurality of high voltage output portions for outputting a specific high voltage from one or a plurality of high voltage capacitors 56; and the probe card 57 is switched by the upper and lower operations of the contact platform 53. The probes 57&, 57b are isolated from the terminals 54&, 54b of one or more of the inspection target devices 54, and the first operation of connecting one or a plurality of high voltage capacitors 56 to the high voltage power supply 5 5 side by the switch 52, And one or more high voltage capacitors 56 are disconnected from the high voltage power source 55 by the switch 52 and passed through the probe card 57, respectively. <The probes 57a and 57b are respectively connected to the second operation of each of the terminals 54a and 54b of one or a plurality of inspection target devices 54. Further description will be made. One of the contacts 52 is fixed to the base body 51. The contact point 仏' is on the lower surface of the contact platform 53 and the other contact 52b of the switch 52 is fixed directly above the contact 52a of the switch 52. On the contact platform, a device 54 for inspecting the object is fixed, and the contact platform 53 is configured to move up and down freely at a specific interval. Although the device 54 to be inspected only indicates i's here, the actual number is actually set in the front-rear direction. One device to be inspected 54 ° One of the contacts 52a of the switch 52 is connected to the high voltage power source 55, and the other contact 52b of the switch π is grounded via the high voltage ray 典 μ, the L _ ^ 冤 器 56. The rolling capacitor 56 connection 163040.doc -35- 201245731 On the high voltage side of the probe card 57, the probe card side is grounded. The probes 57a, 57b are self-contained in a one-to-one manner corresponding to the two terminals 54a, 54b of each device 54. The lower surface of the probe card 57 is protruded and provided separately. The terminals 54a' to 54b of the respective devices 54 are disposed in a one-to-one correspondence with the probes 57a and 57b of the probe card 57 respectively connected to the high-voltage capacitor 56. The voltage source 55 selects a charging processing capability corresponding to a plurality of high voltage capacitors 56 corresponding to the number of devices to be uniformly applied. The high voltage output unit and the GND voltage output unit connected to the GND voltage source are respectively provided. Can be relative to one or a plurality of contact members of the plurality of contact members electrically connected to the terminals 54a and 54b of the inspection target device 54. The contact mechanism is an operator having a plurality of contact members fixed to the support arm and a plurality of contact members fixed thereto Any one of the probe cards 57. As the contact member, a material of indium or tungsten of heat resistance to discharge is used. Here, the probe card 57 is used as a contact mechanism, and the probes 57a and 5 are used as a plurality of contact members. Since the substrate of the card 57 is applied with a high voltage, it is not set as the multilayer wiring substrate ′, and is set as a surface wiring substrate for avoiding discharge. According to the above configuration, 'the contact platform 53 is in the upper position in FIG. The south voltage of the container 56 is applied to the terminal 54a of each device 54 via the probe 57a on the high voltage side of the probe card 57 for ESD testing. That is, the high voltage power source 55 with respect to the high voltage capacitor 56 when the contact platform 53 is in the upper position. The same ESD applied voltage waveform from the respective piezoelectric capacitors 56 is turned off from each probe 57a to the terminal 54a of each device 54. At this time, the terminal 54b of each device 54 is via the probe 57b. In Fig. 16, the contact platform 53 is in the down position, and the high voltage source 55 163040.doc • 36·201245731 high voltage is charged to the high voltage capacitor 56 via the switch 52 (4) when the probe 57a, 57b and the device 54 are in the down position. Each of the terminals is connected to the M-touch; 54b isolating the 'high-voltage power source 55 is connected to the high-voltage capacitor % and charged. Fig. 17 shows the gap between the contacts of _52 of Fig. 15, and the broken line indicates the position below the contact platform 53. 'The solid line indicates the position above the contact platform'. In Fig. 17, the gap length A is the contact height of the probes 57a, 57b, and the gap length B is the contact height of the contacts 52a, 52b of the switch 52. The probes are in contact with the respective terminal cores (10) of the device 54 by being energized by a spring or an elastomer or the like within a specific range of travel. Further, the contacts 52a, 52b of the switch 52 are also connected to each other from the range of "η邓特特疋", which is energized by a spring or an elastic body with a certain ability to be energized. The distance between the conductive members calculated by the Paschen's law is calculated relative to the distance between the conductive members due to the upper and lower operations of the contact platform 53 (probe 5, 5%, and the terminal 54a of the device 54, the distance corrected, or The straight line of the relationship between the theoretical value of the relationship between the contacts of the switch 52 and the actual measured value obtained by the actual coffee test is used as the design value of the distance between the conductive members. The contact platform 53 of the probe device constituting the automatic transfer device of the semiconductor wafer 8 originally adsorbs not only a plurality of inspection targets (or semiconductor crystals), but also a device for performing the next plurality of inspection objects. The ESD check moves horizontally in the plane and moves vertically. The upper and lower movements of the contact platform 53 (vertical movement) correspond to the operation of the high-voltage relay (mercury relay) necessary for the coffee circuit, instead of the electrical circuit operation. According to the above description, according to the third embodiment, the switch 52 is turned on/off by the upper and lower sides of the contact platform, and the high voltage capacitor is charged/discharged 163040.doc • 37 - 201245731 electric 'can be used for the device to be inspected 54 The ESD check, and the number of devices 54 to be inspected is quite high, and the high-voltage relay (mercury relay) is also provided, and the power supply and the ESD controller that do not need to be driven are also required. In the third embodiment, as in the case of the first and second embodiments, in the case of mass production, the plurality of devices 6 to be inspected are collectively and clearly and accurately performed with the ESD voltage waveform suitable for the specification. The high voltage application test allows high voltage inspection to be performed in a large and efficient manner. Further, in the third embodiment, the probes 5 7a and 57b of the one high voltage capacitor 56 are respectively provided in one-to-one correspondence with the respective terminals 54a and 54b of the device 54, and correspond to the inspection target in a one-to-one manner. In the manner of the device, the number of the high voltage capacitors 56 is set to be the same as the number of devices to be inspected. Further, in the third embodiment, the charging/discharging of the high-voltage capacitor 56 is controlled by opening and closing the switch 52 by the upper and lower sides of the contact platform 53, but the present invention is not limited to this, and the image may be provided in the ESD testing device 1E. The insulating gas-filled switch 61 of 18' replaces the switch 52. The insulating gas-filled switch 61 has a high voltage, so that even if an arc is drawn between the contacts in the sealed space in which the switch contacts are accommodated, a gas having a high insulation resistance can be filled. In this confined space, the life is longer. When the switch 52 (or between the probes) is electrically opened and closed in a state where there is a high voltage difference, the discharge phenomenon of the emitted light or the heat can be confirmed. When the discharge is caused by the switch 52 (or between the contact probes), the heat generated by the discharge in the gas is generated at the junction of the switch 52, so that the contact surface is oxidized due to the heat of discharge, resulting in electrical contact itself. It becomes difficult, or due to changes in the contact f resistance of the switch 52, it is not possible to continue to follow the specifications of the 163040.doc •38-201245731 ESD application. The discharge threshold of the above high voltage varies depending on the applied voltage or the distance between the contacts of the switch, temperature, humidity, and the like. As a conventional technique, a gas having high insulating properties, which is used as an insulating medium or an arc extinguishing medium of an electric power device such as an insulated switchgear in a high voltage device, is known. As a method, the following countermeasures can be used: a switch contact is used. The position is sealed and filled with an insulating gas, thereby protecting the switch by filling the switch 6 with an insulating gas. As the protection of the contact probe portion, the contact resistance due to the surface oxidation of the probe is increased, and the ESD application based on the specification is continued by the monitoring of the needle tip and the periodic polishing process. Alternatively, if it is a non-harmful gas, it is also effective to always spray the gas to the contact portion. Further, in the third embodiment, the charging/discharging of the high-voltage capacitor 56 is controlled by opening and closing the switch 52 by the upper surface of the contact platform 53 (wafer prober), but the present invention is not limited thereto. In the ESD test apparatus 11?, a shaft 71 as a drive source for performing the upper and lower operations of the contact platform 53 and a rack and pinion 72 for driving up and down are provided instead of the switch 52 at the front end of the shaft 71 ( The lower end surface may be provided with a switch 73. That is, a switch 73 may be provided on the lower end surface of the shaft (shaft 71) i for moving the contact platform 53 on which the semiconductor wafer 58 is fixed on the upper surface. The switch 73 is opened when the contact platform 53 and the shaft 71 are moved to the lower side, and the high voltage power source 55 charges the high voltage capacitor 56. Further, when the contact platform 53 and the shaft 71 are moved to the upper side, the switch 73 is turned off, and the voltage source 55 is disconnected from the high voltage capacitor 56, and the ESd test is performed. Further, in the third embodiment, the charging/discharging of the high voltage capacitor 56 is controlled by the upper and lower opening and closing switches 52 of the contact platform 53 (wafer probe 163040.doc - 39 - 201245731), but it is not limited thereto. Therefore, in FIG. 20, on the ESD testing device 1G, the contact 52a of the switch 52 on the base body 51 is grounded, and a voltage source of about 5 V is connected to the contact 52b of the switch 52 on the side of the contact platform 53. A low voltage source 82 of about 5 V is connected to a control terminal of a high-resistance piezoelectric crystal 81 (Insulated Gate Bipolar Transistor), and the high voltage power source 55 is connected to the high voltage via a high resistance piezoelectric crystal 81. Capacitor 56. The low voltage source 82 of about 5 V is activated by the opening of the switch 52, the high resistance piezoelectric crystal 81 (insulated gate bipolar transistor IGBT) is turned on, and the high voltage from the high voltage power source 55 is charged to the high voltage capacitor 56. . Further, if the switch 52 is turned off, the high voltage that has charged the high voltage capacitor 56 is applied to the respective terminals 54a of the respective devices 54 as ESD applying voltage waveforms. At this time, the low voltage source 82 does not function, whereby the high resistance piezoelectric crystal 81 (insulated gate bipolar transistor IGBT) is turned off, and the high voltage capacitor 56 is turned off with respect to the high voltage power source 55. In the case of Figure 17, a high voltage of up to several thousand v is not directly applied to the mechanical switch 52, which is safe and has a long life.
再者’於本實施形態3中’雖未特別說明，但可應用上 述實施形態2之參考例。即，高電壓電源55以於接觸平台 53(晶圓探針儀）上搭載有半導體晶圓，相對於配設於該半 導體晶圓上之複數個檢查對象裝置54之二極體構造成為反 向偏Μ之方式施加負尚電壓。於該情形時，配置於半導體 晶圓上之複數個檢查對象裝置間經短路處理為GND電位。 進而，亦可形成為半導體晶圓之導電外周部經電性短路處 理為GND電位，將於複數個檢查對象裝置54間短路之GND I63040.doc -40· 201245731 電位、電性連接半導體晶圓之導電外周部之接觸平台53之 上表面導電層之GND電位、以及包含高壓電容器56及高電 壓輸出部之ESD電路之GND電位作為共通gNd電位而連 接’藉此無需對複數個檢查對象裝置54之GND端子之連接 處理。 再者’於本實施形態3中，雖未特別說明，但可應用上 述實施形態1之參考例。使用本實施形態3之開關52與接觸 平台53之上下動機構及其周邊控制電路，取代上述實施形 態1之南耐壓繼電器3及其驅動電源、ESD控制器9，藉此 可不利用使用有水銀之高耐壓繼電器3，而應用上述實施 形態1之參考例》即，於接觸平台53(晶圓探針儀）上搭載有 半導體晶圓’對配置於該半導體晶圓上之複數個檢查對象 裝置5 4之連.接處理使用探針儀而連續地進行。電腦系統係 控制接觸平台53之上下動作並且控制探針儀之動作，根據 表示複數個檢查對象裝置54之位址之晶圓映射進行探測控 制者。高電壓電源55構成為相對於GND電位搭載有正電源 與負電源’且可切換正電源與負電源，又構成為相對於複 數個檢查對象裝置54可切換順方向偏壓與反方向偏壓。 再者，於本實施形態3中，雖未特別詳細地說明，但於 具有沿半導體測試裝置之垂直方向及水平方向振幅之接觸 平台53之裝置中’該振幅動作代替ESD施加所必需之電性 之電路動作。接觸平台53之振幅機構為ESD施加電路所必 需之開關機構。無需高耐壓繼電器3、該動作所必需之時 序控制器即ESD控制器9、及高耐壓繼電器驅動電源。共 163040.doc -41- 201245731 用開關52，增加用以對裝置54進行ESD施加之配線與高壓 電容器56 ’藉此可實現多個裝置統一處理。開關52對複數 個施加對象’形成一律而同步控制。將高電壓輸出部形成 為探針卡57之構成，於晶圓狀態下處理裝置54。上文已作 敍述’於驅動接觸平台53之軸之端面具有開關機構。其為 藉由接觸平台53之振幅動作，自高電壓電源55對高耐壓電 容器56充電之功能。藉由接觸平台53之振幅動作，將已充 電至高耐壓電容器56之電荷向裝置54通電。裝置接觸53之 上下動作本身為ESD施加之開關機構。開關52之接點或探 針57a、57b與各端子54a ' 54b之間隙長係由接觸平台53之 振幅距離而決定。開關52之接點或探針57a、57b與各端子 54a、54b之間隙長作為用以避免高電壓放電之基準，係由 遵循Paschen之計算值而決定。開關52亦可設置為填充絕 緣耐性較高之氣體而密閉之狀態。 如上所述’使用本發明之較佳實施形態例示了本發 明’但本發明並非應限定於該實施形態1〜3而解釋者。而 疋理解為本發明係應僅藉由專利申請之範圍而解釋其範圍 者。業者要理解可自本發明之具體之較佳實施形態1〜3之 記載’根據本發明之記載及技術常識實施等效之範圍。要 理解為本說明書中所引用之專利、專利申請案及文獻係與 其内容本身具體地記載於本說明書中同樣地其内容應作為 對本說明書.之參考而引用。 [產業上之可利用性] 本發明係於使用對例如LSI元件、或led元件及雷射元 163040.doc •42· 201245731 件等發光元件等檢査對象裝置檢查ESD耐性之ESD測試裝 置進行高電壓施加檢查之高電壓檢查裝置之領域，對檢查 對象之複數個裝置統一地，以適合於規格之電流波形（或 電壓波形）明確且正確地進行高電壓施加測試，藉此可大 幅且高效地進行高電壓檢查。 【圖式簡單說明】 圖1係表示本發明之實施形態1中之ESD測試裝置之構成 例之電路圖。 圖2係模式性地表示於半導體晶圓平面内排列成多個矩 陣狀之半導體晶片之4個鄰接縱橫之平面圖。 圖3係表示以理論值與實測值作為參數之放電極限值相 對於電極間距離之關係之圖。 圖4係模式性地表示與圆1之ESD測試裝置中之裝置之接 觸狀態下之放大示意之立體圖。 圖5係模式性地表示圖1之ESD測試裝置之ESD施加時之 構成示意例之立體圖。 圖6係模式性地表示圖1之ESD測試裝置中之複數個eSI) 施加器之設置示意例之平面圖。 圖7(a)係模式性地表示圖1之ESD測試裝置1中之複數個 ESE>施加器之另一設置示意例之平面圖，（b)係（a)之ESD施 加器與探針卡及探針儀之縱剖面圖。 圖8(a)係模式性地表示圖7(a)之ESD施加器之立體圖， (b)係表示於ESD測試中所使用之ESD施加電壓波形之圖。 圖9係表示以個人電腦PC為主體之晶圓映射與探測管理 163040.doc •43- 201245731 之方塊圖。 圖10係表示本發明之實施形態2中之ESD測試裝置之構 成例之電路圖。 圖11係使用圖10之ESD測試裝置，進行以矩陣狀配置於 半導體晶圓上之多個檢查對象裝置之ESD耐壓檢查之情形 時之模式圖。 圖12係使用圖1之ESD測試裝置於正電源下設定反向偏 壓之狀態之情形時之模式圖。 圖13係作為於圖10之別〇測試裝置中以複數個裝置為 ESD施加對象時之探測實施例，用以說明向半導體晶片之 各端子之探針配置之平面圖。 圖14係模式性地表示省略GND側之探針之情形時之檢查 對象裝置之連接之圖。 圖15係模式性地表示於本發明之實施形態3之ESD測試 裝置中接觸平台處於上位置之情形時之縱剖面圖。 圖16係模式性地表示於圖152ESd測試裝置中接觸平台 處於下位置之情形時之縱剖面圖。 圖17係示出圖15之開關之接點間間隙，虛線表示接觸平 台之下位置，實線表示接觸平台之上位置之圖。 圖18係表示本發明之實施形態3中之ESD測試裝置之另 一構成例之縱剖面圖。 圖19係表示本發明之實施形態3中之ESD測試裝置之進 而另一構成例之縱剖面圖。 圖20係表示本發明之實施形態3中之ESD測試裝置之又 163040.doc 201245731 一構成例之縱剖面圖β 圖21係模式性地表示先前之咖剛試裝置之構成例 路圖。Further, in the third embodiment, although not specifically described, the reference example of the second embodiment can be applied. That is, the high-voltage power source 55 mounts the semiconductor wafer on the contact platform 53 (wafer prober), and reverses the diode structure with respect to the plurality of inspection target devices 54 disposed on the semiconductor wafer. A negative voltage is applied in a biased manner. In this case, a plurality of inspection target devices disposed on the semiconductor wafer are short-circuited to a GND potential. Further, it may be formed such that the conductive outer peripheral portion of the semiconductor wafer is electrically short-circuited to the GND potential, and is short-circuited between the plurality of inspection target devices 54. I63040.doc -40·201245731 Potential, electrically connected to the semiconductor wafer The GND potential of the surface conductive layer on the contact platform 53 of the conductive outer peripheral portion, and the GND potential of the ESD circuit including the high voltage capacitor 56 and the high voltage output portion are connected as a common gNd potential, thereby eliminating the need for a plurality of inspection target devices 54. Connection processing of the GND terminal. Further, in the third embodiment, the reference example of the first embodiment described above can be applied unless otherwise specified. The switch 52 of the third embodiment and the lowering mechanism on the contact platform 53 and its peripheral control circuit are used instead of the south withstand voltage relay 3 of the first embodiment and its driving power source and ESD controller 9, whereby mercury can be used without using In the high-voltage relay 3, the reference example of the first embodiment is applied, that is, a semiconductor wafer is mounted on the contact platform 53 (wafer prober) for a plurality of inspection objects placed on the semiconductor wafer. The connection of the device 54 is continuously performed using a prober. The computer system controls the upper and lower movements of the contact platform 53 and controls the operation of the probe device, and the detection controller is based on the wafer map indicating the addresses of the plurality of inspection target devices 54. The high-voltage power supply 55 is configured to be equipped with a positive power supply and a negative power supply ’ with respect to the GND potential, and is capable of switching between the positive power supply and the negative power supply, and is configured to switch the forward bias and the reverse bias with respect to the plurality of inspection target devices 54. Further, in the third embodiment, although not described in detail, in the device having the contact platform 53 having the amplitude in the vertical direction and the horizontal direction of the semiconductor test device, the electric power required for the amplitude action instead of the ESD application is used. The circuit action. The amplitude mechanism of the contact platform 53 is the switching mechanism necessary for the ESD application circuit. There is no need for a high withstand voltage relay 3, a timing controller necessary for this operation, that is, an ESD controller 9, and a high withstand voltage relay driving power supply. A total of 163040.doc -41-201245731 With the switch 52, the wiring for the ESD application of the device 54 and the high voltage capacitor 56' are added, whereby a plurality of devices can be uniformly processed. The switch 52 is uniformly controlled for a plurality of application objects'. The high voltage output portion is formed as a probe card 57, and the device 54 is processed in a wafer state. As described above, the end face of the shaft that drives the contact platform 53 has a switching mechanism. This is a function of charging the high-resistance piezoelectric container 56 from the high-voltage power source 55 by the amplitude action of the contact platform 53. The charge that has been charged to the high withstand voltage capacitor 56 is energized to the device 54 by the amplitude action of the contact platform 53. The up and down motion of the device contact 53 is itself a switching mechanism applied by the ESD. The gap between the contacts of the switch 52 or the probes 57a, 57b and the terminals 54a' 54b is determined by the amplitude distance of the contact platform 53. The gap between the contacts of the switch 52 or the probes 57a, 57b and the terminals 54a, 54b is used as a reference for avoiding high voltage discharge, which is determined by following the calculation of Paschen. The switch 52 can also be provided in a state of being sealed by filling a gas having high insulation resistance. As described above, the present invention has been exemplified by the preferred embodiments of the present invention, but the present invention is not limited to the embodiments 1 to 3 and explained. It is to be understood that the invention is intended to be limited only by the scope of the patent application. It is to be understood that the specific embodiments of the present invention can be understood from the description of the preferred embodiments 1 to 3 of the present invention. It is to be understood that the patents, patent applications, and documents cited in this specification are hereby incorporated by reference in their entirety in their entirety in their entirety in the entireties in [Industrial Applicability] The present invention is a high voltage using an ESD test apparatus for inspecting an ESD tolerance of an inspection target device such as an LSI element or a LED element and a light-emitting element such as a laser element 163040.doc • 42·201245731. In the field of the high-voltage inspection device to be inspected, the plurality of devices to be inspected are uniformly and accurately subjected to the high-voltage application test with a current waveform (or voltage waveform) suitable for the specification, thereby enabling the large-scale and efficient operation. High voltage check. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram showing an example of a configuration of an ESD test apparatus according to a first embodiment of the present invention. Fig. 2 is a plan view schematically showing four adjacent vertical and horizontal cross-sections of a semiconductor wafer arranged in a plurality of matrix shapes in a plane of a semiconductor wafer. Fig. 3 is a graph showing the relationship between the discharge limit value of the theoretical value and the measured value as a parameter with respect to the distance between the electrodes. Fig. 4 is a perspective view schematically showing an enlarged schematic view of a state in contact with a device in the ESD test apparatus of the circle 1. Fig. 5 is a perspective view schematically showing a configuration example of the ESD application of the ESD test apparatus of Fig. 1. Fig. 6 is a plan view schematically showing a schematic example of the arrangement of a plurality of eSI) applicators in the ESD test apparatus of Fig. 1. Figure 7 (a) is a plan view schematically showing another arrangement example of a plurality of ESEs of the ESD test device 1 of Figure 1, (b) an ESD applicator and a probe card of the type (a); Longitudinal section of the probe. Fig. 8(a) is a perspective view schematically showing the ESD applicator of Fig. 7(a), and Fig. 8(b) is a view showing a waveform of an ESD applied voltage used in the ESD test. Figure 9 is a block diagram showing wafer mapping and probing management based on a personal computer PC 163040.doc •43- 201245731. Fig. 10 is a circuit diagram showing an example of the configuration of an ESD test apparatus according to the second embodiment of the present invention. Fig. 11 is a schematic view showing a state in which ESD withstand voltage inspection of a plurality of inspection target devices arranged in a matrix on a semiconductor wafer is performed using the ESD test apparatus of Fig. 10. Fig. 12 is a schematic view showing a state in which the reverse bias voltage is set under the positive power source using the ESD test apparatus of Fig. 1. Fig. 13 is a plan view showing a configuration in which a plurality of devices are applied to an ESD in a different test device of Fig. 10 for explaining a probe arrangement to each terminal of a semiconductor wafer. Fig. 14 is a view schematically showing the connection of the inspection target device when the probe on the GND side is omitted. Fig. 15 is a longitudinal sectional view schematically showing a state in which the contact platform is in the upper position in the ESD test apparatus according to the third embodiment of the present invention. Figure 16 is a longitudinal cross-sectional view schematically showing the state in which the contact platform is in the lower position in the 152 ESd test apparatus. Figure 17 is a diagram showing the inter-contact gap of the switch of Figure 15, the broken line indicating the position below the contact platform, and the solid line indicating the position above the contact platform. Fig. 18 is a longitudinal sectional view showing another configuration example of the ESD test apparatus in the third embodiment of the present invention. Fig. 19 is a longitudinal sectional view showing another configuration example of the ESD test apparatus in the third embodiment of the present invention. Fig. 20 is a cross-sectional view showing a configuration of an ESD test apparatus according to a third embodiment of the present invention. 163040.doc 201245731 A longitudinal sectional view of a configuration example Fig. 21 is a schematic view showing a configuration example of a conventional coffee machine.
圖22係模式性地表示專利文獻丨中 測試裝置之構成例之立體圖。 前之ESD 【主要元件符號說明】 1 、 1A〜1G ESD測試裝置 2、2C 高電壓電源 3 高耐壓繼電器 4 高壓電容器 5 施加電阻 6 檢查對象裝置 6a ' 6b 端子 7 晶圓平台 8 半導體晶圓 9 ESD控制器 10、10C ESD電路 11 半導體晶片 12、12a、12b 端子 13 探針 20 探針儀（自動搬送裝置） 21 ESD基板箱 21a 配線輸出部 22 探針卡（接觸機構） 163040.doc -45· 201245731 22a、22b 探針（接觸構件） 23 配線 24 連接器 25 中央圓形部 31 ESD基板 32 中央圓形部 41 晶圓平台絕緣層 42 晶圓平台導電層 51 基礎體 52 開關 52a 一接點 52b 另一接點 53 接觸平台 54a、54b 端子 54 檢查對象之裝置 55 高電壓電源 56 高壓電容器 57 探針卡 57a、57b 探針 58 半導體晶圓 61 絕緣氣體填充開關 71 軸承 72 小齒輪 73 開關 163040.doc ·46· 201245731 81 高耐壓電晶體（絕緣柵雙極型電晶體 IGBT) 82 低電壓源 100 先前型之ESD測試裝置 101 高電壓電源 102 充電用高耐壓繼電器 103 放電用高耐壓繼電器 104 施加電阻 105 檢查對象裝置 106 高壓電容器 107 時序控制器 200 靜電放電測試用夾具 201 電子零件 202 印刷配線板 202a 配線圖案 203 導電板 204 印刷板支持具 205 靜電產生搶 206 搶保持具 PC 個人電腦 163040.doc - 47 -Fig. 22 is a perspective view schematically showing a configuration example of a test apparatus in the patent document 。. Previous ESD [Main component symbol description] 1 , 1A to 1G ESD test device 2, 2C High voltage power supply 3 High withstand voltage relay 4 High voltage capacitor 5 Applied resistor 6 Check target device 6a ' 6b Terminal 7 Wafer platform 8 Semiconductor wafer 9 ESD controller 10, 10C ESD circuit 11 Semiconductor wafer 12, 12a, 12b Terminal 13 Probe 20 Probe device (automatic conveying device) 21 ESD substrate box 21a Wiring output unit 22 Probe card (contact mechanism) 163040.doc - 45· 201245731 22a, 22b Probe (contact member) 23 Wiring 24 Connector 25 Central circular portion 31 ESD substrate 32 Central circular portion 41 Wafer platform insulating layer 42 Wafer platform conductive layer 51 Base body 52 Switch 52a Point 52b Another contact 53 Contact platform 54a, 54b Terminal 54 Device to check object 55 High voltage power supply 56 High voltage capacitor 57 Probe card 57a, 57b Probe 58 Semiconductor wafer 61 Insulating gas filled switch 71 Bearing 72 Pinion 73 Switch 163040.doc ·46· 201245731 81 Highly resistant piezoelectric crystal (insulated gate bipolar transistor IGBT) 82 Low voltage source 100 Previous type ESD test apparatus 101 High voltage power supply 102 High voltage relay for charging 103 High voltage relay for discharge 104 Application of resistance 105 Inspection target device 106 High voltage capacitor 107 Timing controller 200 Electrostatic discharge test fixture 201 Electronic parts 202 Printed wiring Board 202a Wiring pattern 203 Conductive board 204 Print board support 205 Electrostatic generation grab 206 Grab holder PC PC 163040.doc - 47 -