JP5244210B2 - High voltage inspection device - Google Patents

Description

  The present invention relates to a high-voltage inspection apparatus that performs high-voltage application inspection using an ESD test apparatus that inspects ESD tolerance for inspection target devices such as LSI elements, light-emitting elements such as LED elements and laser elements.

  Conventionally, in an LSI element, a protection diode is connected to the input circuit side, and the ESD resistance of the protection diode is inspected. In light emitting elements such as LED elements and laser elements, the light emitting elements themselves have a diode structure. Since this diode structure is composed of a pn junction of a p-type diffusion layer and an n-type diffusion layer, the ESD resistance differs depending on the quality of the p-type diffusion layer and the n-type diffusion layer. Need to be examined.

  The basic ESD circuit required for conventional ESD application is a high-voltage power supply and a high-voltage capacitor that uses ESD standards (HBM (Human Body Model), MM (Machine Model), etc.), applied resistance, and mercury. Consists of relays.

  The applied output portion of the ESD circuit energizes the device to be inspected by using a probe card in which a contact probe for connecting to the terminal of the device is fixedly mounted on the substrate, or a manipulator in which this contact probe is fixed to the arm. It is like that.

  The magnitude of the supply voltage to the device to be inspected is intended for a typical ESD test (electrostatic discharge reliability test) or the like in the reliability inspection, and is intended for a high voltage of about 1 to 10 KV level. This test is for durability when static electricity from a human body or machine flows to a device to be inspected such as an LSI chip.

  FIG. 21 is a circuit diagram schematically showing a configuration example of a conventional ESD test apparatus.

  In the conventional ESD test apparatus 100 shown in FIG. 21, one terminal of a high voltage power supply 101 is connected to one end of an applied resistor 104 through high voltage relays 102 and 103. The other end of the applied resistor 104 is connected to one terminal of the device 105 to be inspected. The other terminal of the device 105 is connected to the other terminal of the high voltage power supply 101. The connection point of these high voltage relays 102 and 103 is connected to the connection point of the other terminal of the device 105 and the other terminal of the high voltage power supply 101 through the high voltage capacitor 106, and this connection point is grounded. A timing controller 107 for controlling on / off of these high voltage relays 102 and 103 is provided. A power supply for driving these high voltage relays 102 and 103 is required separately.

  With the above configuration, first, the charging high-voltage relay 102 is turned on by the timing controller 107 and the current from the high-voltage power supply 101 is accumulated in the high-voltage capacitor 106. At this time, the discharge high-voltage relay 103 is turned off by the timing controller 107.

  Next, after the charging high-voltage relay 102 is turned off by the timing controller 107, control is performed so that the discharging high-voltage relay 103 is turned on. As a result, the high voltage accumulated in the high-voltage capacitor 106 is applied from the high-voltage relay 103 to the one terminal of the device 105 to be inspected through the application resistor 104.

  As described above, the high-voltage relay 102 for charging and the high-voltage relay 103 for discharging are turned on / off by the timing controller 107 to charge or discharge the high-voltage capacitor 106, and a predetermined device 105 is inspected. A high voltage can be applied. The switching operation of the charging high-voltage relay 102 and the discharging high-voltage relay 103 is performed by the timing controller 107 at a specified timing. In the ESD test, several types of application models and standards are defined for each, and the conformity is determined by the current waveform (or voltage waveform) applied to the device 105 to be inspected.

  In short, in an ESD test, a high voltage is applied to a device to be inspected from a high voltage power source through an ESD application circuit and a contact jig such as a socket / arm. A high voltage is applied to the device to be inspected by bringing a high-voltage supply source side terminal (1) and a GND-side terminal (1) into contact with each terminal of the device to be inspected. In this case, the device to be inspected is subjected to a high voltage application process alone. Although there is an apparatus that can set a plurality of devices to be inspected, an actual ESD test is processed by changing terminals serially.

JP 2000-329818 A

  In the conventional ESD testing apparatus 100 disclosed in Patent Document 1, a high voltage relay using mercury is used. This high-voltage relay using mercury is not only expensive, but is also subject to regulation (RoHS directive) because it uses mercury. In addition, when a plurality of devices are simultaneously inspected, a large number of high voltage relays using mercury are required. Further, in a high voltage relay using mercury, a time difference of msec unit occurs in the relay operation time. Furthermore, a unit for controlling the drive timing of the high voltage relay is required, and a power source for driving the high voltage relay is separately required.

  The present invention solves the above-described conventional problems, and can simplify the overall configuration without using a high-voltage relay and can perform a high-voltage application test with a current waveform (or voltage waveform) conforming to the standard. An object is to provide a voltage inspection apparatus.

High-voltage testing device of the present invention is a high-voltage testing device for simultaneously testing the ESD resistance to more device under test, the vertical movement of the contact stages equipped with the plurality of device under test, switch means oN / oFF, charging / discharging a high voltage of the high voltage capacitive means for one-to-one correspondence with the device under test the plurality of by discharge from respective high voltage capacitive means of the plurality of device under test The ESD inspection is performed, and the above object is achieved.

Preferably, in the high-voltage testing device of the present invention, a high voltage power supply that outputs a predetermined high voltage, a plurality of high voltage capacitive means for storing a predetermined high voltage from the high voltage power source, said plurality of a plurality of high voltage output section that outputs a predetermined high voltage from the high voltage capacitor means and to separate the respective terminals of the with the plurality of high voltage output unit a plurality of device under test, said switching means first operation and, in conjunction with blocking the high voltage capacitive means and the high voltage power supply of said plurality of the said switch means, said plurality of high-voltage output unit for connecting the plurality of high voltage capacitive means to the high voltage side by the second operation and connected to each terminal of the plurality of device under test, switch the vertical movement of the contact stage.

Further, preferably, a high voltage power source in the high voltage inspection apparatus of the present invention is selected to have a charge processing capability corresponding to the plurality of high voltage capacity means corresponding to the number of devices to be collectively applied.

Further preferably, in the high voltage inspection apparatus according to the present invention, the high voltage output unit and the GND voltage output unit connected to the GND voltage source are electrically connected to the terminals of the plurality of devices to be inspected. It has a contact means provided with a plurality of contact members that can be connected.

  Further preferably, the contact means in the high voltage inspection device of the present invention is either a manipulator having a plurality of contact members fixed to an arm or a probe card having a plurality of contact members fixed thereto.

  Further preferably, the contact member in the high voltage inspection apparatus of the present invention uses a material of indium or tungsten which is resistant to discharge heat.

  Further preferably, the probe card substrate in the high voltage inspection apparatus of the present invention is a surface wiring substrate for avoiding discharge.

  Further, preferably, the relationship between the discharge limit value and the distance between the conductive members due to the vertical movement of the contact stage in the high voltage inspection apparatus of the present invention is obtained by actually conducting an ESD test and a theoretical value obtained by calculation from Passen's law. The shortest distance line connecting the measured values was used as the design value of the distance between the conductive members for avoiding adjacent discharge.

  Further preferably, the high voltage power supply in the high voltage inspection apparatus of the present invention applies a negative high voltage so as to be reverse-biased with respect to the diode structures of a plurality of devices to be inspected disposed on the semiconductor wafer.

  Further, preferably, a plurality of devices to be inspected arranged on the semiconductor wafer in the high voltage inspection apparatus of the present invention are short-circuited to the GND potential.

  Further preferably, in the high voltage inspection apparatus of the present invention, the conductive outer periphery of the semiconductor wafer is electrically short-circuited to the GND potential, and the GND potential short-circuited between the plurality of devices to be inspected, and the semiconductor wafer By connecting the GND potential of the contact stage conductive layer to which the conductive outer peripheral portion is electrically connected and the GND potential of the ESD circuit as a common GND potential, connection processing to the GND terminals of the plurality of devices to be inspected is unnecessary. And

  Further, preferably, the connection processing for the plurality of devices to be inspected arranged on the semiconductor wafer in the high voltage inspection apparatus of the present invention is continuously performed using a prober.

  Still preferably, in a high voltage inspection apparatus according to the present invention, a computer system controls the vertical movement of the contact stage and the operation of the prober to display a wafer map indicating addresses of the plurality of devices to be inspected. Probing control is performed based on this.

  Further preferably, the high-voltage power supply in the high-voltage inspection apparatus of the present invention includes a positive power supply and a negative power supply with respect to the GND potential, and is configured to be able to switch between the positive power supply and the negative power supply. A forward bias and a reverse bias can be switched with respect to the target device.

  Further preferably, in the probe card of the high voltage inspection apparatus according to the present invention, the probe stand design criteria for a plurality of probes calculates the relationship of the discharge limit value with respect to the distance between the conductive members due to the vertical movement of the contact stage from the law of Passen. The line with the shortest distance connecting the theoretical value obtained in step 3 and the actual value obtained by actually performing the ESD test is used as the minimum design value of the distance between the conductive members, and the distance is equal to or larger than the semiconductor chip size. Is required, for example, one semiconductor chip is skipped or two or more semiconductor chips are skipped.

  Further preferably, in the probe card of the high-voltage inspection apparatus of the present invention, the semiconductor chip in the space area that is not probed by one contact is sequentially contact-processed by probing control mainly by the personal computer PC, and ESD is applied without fail. Execute.

  With the above configuration, the operation of the present invention will be described below.

  In the present invention, in a high-voltage inspection apparatus that inspects ESD tolerance for one or a plurality of devices to be inspected, the switch means is turned on / off by the up and down movement of the contact stage carrying the one or a plurality of devices to be inspected. Then, one or a plurality of devices to be inspected are charged / discharged with a high voltage of each high voltage capacity means corresponding to one-to-one, and the discharge of each high voltage capacity means causes the one or more devices to be inspected to Perform ESD inspection.

  As a result, the overall configuration can be simplified without using a high-voltage relay, and a high-voltage application test can be performed with a current waveform (or voltage waveform) conforming to the standard.

  As described above, according to the present invention, a high voltage application test can be performed with a current waveform (or voltage waveform) conforming to the standard by simplifying the overall configuration without using a high voltage relay.

It is a circuit diagram which shows the structural example of the ESD test apparatus in Embodiment 1 of this invention. 4 is a plan view schematically showing four adjacent vertical and horizontal semiconductor chips arranged in a matrix in a semiconductor wafer plane. FIG. It is a figure which shows the relationship of the discharge limit value with respect to the distance between electrodes which used the theoretical value and the actual measurement value as a parameter. It is a perspective view which shows typically the enlarged image of the contact state to the device in the ESD test apparatus of FIG. It is a perspective view which shows typically the example of a structure image at the time of ESD application in the ESD test apparatus of FIG. It is a top view which shows typically the example of installation image of the several ESD applicator in the ESD test apparatus of FIG. (A) is a top view which shows typically the example of another installation image of the several ESD applicator in the ESD test apparatus 1 of FIG. 1, (b) is an ESD applicator of (a), a probe card, and It is a longitudinal cross-sectional view of a prober. (A) is a perspective view which shows typically the ESD applicator of Fig.7 (a), (b) is a figure which shows the ESD applied voltage waveform used by an ESD test. FIG. 3 is a block diagram showing a wafer map and probing management mainly using a personal computer PC. It is a circuit diagram which shows the structural example of the ESD test apparatus in Embodiment 2 of this invention. FIG. 11 is a schematic diagram when an ESD withstand voltage test is performed on a large number of devices to be inspected arranged in a matrix on a semiconductor wafer using the ESD test apparatus of FIG. 10. It is a schematic diagram in the case of setting the state of a reverse bias with a plus power supply using the ESD test apparatus of FIG. FIG. 11 is a plan view for explaining probe arrangement at each terminal of a semiconductor chip as an example of probing when a plurality of devices are subjected to ESD application in the ESD test apparatus of FIG. 10. It is a figure which shows typically the connection of the test object device in the case of abbreviate | omitting the probe by the side of GND. It is a longitudinal cross-sectional view which shows typically the case where a contact stage is an upper position in the ESD test apparatus in Embodiment 3 of this invention. FIG. 16 is a longitudinal sectional view schematically showing a case where the contact stage is in a lower position in the ESD test apparatus of FIG. 15. FIG. 16 shows a gap between the contacts of the switch of FIG. 15, in which a dotted line indicates a lower position of the contact stage and a solid line indicates an upper position of the contact stage. It is a longitudinal cross-sectional view which shows the other structural example of the ESD test apparatus in Embodiment 3 of this invention. It is a longitudinal cross-sectional view which shows the further another structural example of the ESD test apparatus in Embodiment 3 of this invention. It is a longitudinal cross-sectional view which shows another structural example of the ESD test apparatus in Embodiment 3 of this invention. It is a circuit diagram which shows typically the structural example of the conventional ESD test apparatus currently disclosed by patent document 1. FIG.

  Hereinafter, a case where the present invention is applied to an ESD test apparatus as Embodiment 3 of the high voltage inspection apparatus of the present invention will be described in detail with reference to the drawings. The first and second embodiments are used as a reference example of the third embodiment. That is, instead of the high-voltage relay 3 of the first embodiment and its driving power source and the ESD controller, the vertical movement mechanism of the switch 52 and the contact stage 53 of the third embodiment and its peripheral control circuit are used, so that mercury is used. The reference example of the first embodiment can be applied to the third embodiment without using the high withstand voltage relay 3. In addition, each thickness, length, etc. of the structural member in each figure are not limited to the structure to illustrate from a viewpoint on drawing preparation.

(Embodiment 1)
FIG. 1 is a circuit diagram showing a configuration example of an ESD test apparatus according to Embodiment 1 of the present invention.

  In FIG. 1, an ESD test apparatus 1 as a high voltage inspection apparatus according to the first embodiment includes a high voltage power supply 2 that outputs a predetermined high voltage, and a plurality of devices to be inspected with a predetermined high voltage from the high voltage power supply 2. 6 and an ESD circuit 10 that applies simultaneously to the plurality of devices 6, and inspects a plurality of devices to be inspected for ESD resistance.

  The ESD circuit 10 includes a plurality of high voltage capacitors 4 as high voltage capacity means for storing a predetermined high voltage from the high voltage power supply 2 and a predetermined high voltage applied from the plurality of high voltage capacitors 4 to the application resistors 5. A plurality of high-voltage output units that output through and a predetermined high voltage from the high-voltage power supply 2 is connected to the high-voltage capacitor 4 side, or a predetermined high voltage from the high-voltage capacitor 4 is connected to the high-voltage output unit side A high voltage relay 3 as a plurality of switching means for switching, and as a single circuit configuration, a circuit extending from the high voltage capacitor 4 to the high voltage output unit 3 through the high voltage relay 3 and the application resistor 5 is independently and collectively applied. As many as the plurality of devices to be inspected 6 to be processed are provided in parallel.

  The ESD test apparatus 1 is configured such that one terminal of a high voltage power supply 2 is connected to each electrode of a plurality of (here, eight) high voltage capacitors 4 via each contact of a high voltage relay 3 having multiple contacts (here, eight contacts). The other electrodes of the plurality (eight in this case) of the high-voltage capacitors 4 are connected to the other terminal of the high-voltage power supply 2 and grounded. Each one electrode of the multiple (eight here) high-voltage capacitors 4 is inspected from the high-voltage output section through each applied resistor 5 from each contact of the multi-contact (here, eight contacts) high-voltage relay 3. Each of the target devices 6 is connected to one terminal. The other terminal of each device 6 is connected to the other terminal of the high voltage power supply 2 from the GND voltage output section and grounded. Although not shown here, there is provided an ESD controller 9 to be described later for controlling simultaneous connection switching of the multi-contact (here, 8 contacts) high-voltage relay 3 at a predetermined timing. A separate power source is required to drive the multi-contact (here, 8 contacts) high voltage relay 3.

  The high-voltage power supply 2 is selected and used in accordance with the capacity of the number of high-voltage capacitors 4 to be collectively processed.

  As the high voltage relay 3, a mercury relay having directionality is used. Here, eight relays may be used, but four contacts may be two or two contacts may be four. . Instead of the eight-contact high-voltage relay 3, eight one-contact high-voltage relays 3 may be provided. The high-voltage relay 3 is switched between the high-voltage power supply 2 side and the device 6 side around the high-voltage capacitor 4 side at the same time by the ESD controller 9 (not shown) with respect to the high-voltage capacitor 4. The control signal to the high withstand voltage relay 3 is a single simultaneous control with respect to the independent high-voltage collective application from the eight high voltage capacitors 4 to the eight devices 6. If the high voltage relays 3 are stacked, the high voltage relay 3 is a component that operates by a coil magnetic field, which may cause a malfunction.

  Further, as shown in FIG. 21 to be described later, an independent high-voltage relay configuration such as a high-voltage relay 102 for charging and a high-voltage relay 103 for discharging may be used.

  Here, eight high-voltage capacitors 4 are used, and those having tolerances suitable for the test voltage are selected. In selecting the capacity, those determined for each test model so as to meet the ESD test standard are selected. Select. For example, 100 pF for the HBM standard and 200 pF for the MM standard.

  Eight applied resistors 5 are used here, for example, about 1.5 KΩ for the HBM standard, and 0 KΩ (no resistance) for the MM standard. These high-voltage capacitors 4 and applied resistors 5 are mounted in a state where the number of devices 6 to be collectively processed is electrically independent.

  The device 6 is, for example, a light emitting element such as an LSI element, an LED element, or a laser element.

  With the above configuration, first, eight contacts of the high-voltage relay 3 are turned on to the high-voltage power source 2 side by the ESD controller 9 (not shown), branching from the high-voltage power source 2 to eight, and current flows into each high-voltage capacitor 4. Thus, the high voltage of the high voltage power supply 2 is uniformly accumulated. At this time, the eight contacts on the device 6 side of the high-voltage relay 3 are turned off by the ESD controller 9.

  Next, after the eight contacts on the high-voltage power supply 2 side of the high-voltage relay 3 are turned off by the ESD controller 9, the control is performed so that the eight contacts on the device 6 side of the high-voltage relay 3 are turned on. . As a result, the high voltage accumulated in the high-voltage capacitor 4 is applied to one terminal of each device 6 to be inspected from the eight contacts of the high-voltage relay 3 through the application resistors 5. In this case, each high-voltage capacitor 4 and each device 6 to be inspected have a one-to-one correspondence, and a clear and accurate ESD inspection is performed greatly efficiently.

  In this way, the eight contacts of these high voltage relays 3 are switched by the ESD controller 9 from the high voltage power supply 2 side to each device 6 to be inspected, and the eight high voltage capacitors 4 are charged or discharged. A predetermined clear and accurate high voltage can be applied to each device 6 to be inspected from each of the eight high voltage capacitors 4 from each high voltage output section. The switching operation of the eight contacts of the high withstand voltage relay 3 is simultaneously performed by the ESD controller 9 at a specified timing. In the ESD test, several types of application models and standards are defined for each of them, and conformity is determined by an ESD current waveform (or ESD voltage waveform) applied to each device 6 to be inspected.

  The ESD test includes an ESD application circuit in which eight series circuits of a high-voltage capacitor 4 and an application resistor 5 are connected in parallel through eight contacts of a high-voltage relay 3 from a high-voltage power supply 2, and in addition to a socket, A high voltage is applied to each device 6 to be inspected via a contact jig as a contact means such as a manipulator having a plurality of probes (contact members) fixed to the arm, a probe card having a plurality of probes (contact members) fixed thereto, etc. Applied. Eight high voltages are simultaneously applied to each device 6 to be inspected by bringing a high-voltage supply-side terminal (one) and a GND-side terminal (one) into contact with each terminal of the device 6 to be inspected. . In this case, eight high voltage application processes are simultaneously performed on each device 6 to be inspected.

  FIG. 2 is a plan view schematically showing four adjacent vertical and horizontal semiconductor chips arranged in a matrix in a semiconductor wafer plane.

  In FIG. 2, terminals 12 facing each side of a semiconductor chip 11 as a device 6 to be inspected arranged in a matrix in a semiconductor wafer plane are provided. Thus, two terminals 12 are provided for each semiconductor chip 11, for example, when the probe 13 as a contact member for applying a high voltage indicated by an arrow is contacted in the opposite direction (triangle Δ) of the terminal 12, In some cases, the probe 13 for applying a high voltage indicated by an arrow is brought into contact with the adjacent direction (cross X) of the terminal 12.

  FIG. 3 is a diagram showing the relationship of the discharge limit value with respect to the interelectrode distance using the theoretical value and the actually measured value as parameters.

  The measured values between the opposing terminals indicated by the triangle plot Δ in FIG. 3 are the observation results when the high voltage application probe 13 indicated by the arrow is in contact with the opposing direction (triangle Δ) of the terminal 12 as shown in FIG. is there. In addition, the measured value between adjacent terminals indicated by the cross plot X in FIG. 3 is an observation when the high voltage applying probe 13 indicated by the arrow is in contact with the adjacent direction (triangle X) of the terminal 12 as shown in FIG. It is a result.

  Fig. 3 shows the relationship of the discharge limit value with respect to the distance between the electrodes, but the square plot ■ indicates Passen's law (how far the distance is reduced when high voltage is applied between the terminals and the discharge is reduced). The triangular plot Δ and the cross plot X are actually measured values obtained in the state where the ESD test was actually performed. It is an observation result when an ESD applied voltage waveform is applied between terminals suddenly and instantaneously. A triangular plot Δ is an actual measurement value between opposing terminals (discharge distance when a high voltage is applied between two opposing terminals of the semiconductor chip 11), and a cross plot X is an actual measurement value between adjacent terminals (between adjacent semiconductor chips 11). The discharge distance when a high voltage is applied between adjacent terminals. When the high voltage accumulated in the high-voltage capacitor 4 from the high-voltage power supply 2 is 1500 V, for example, the discharge start voltage is 1500 V, and the theoretical value of the square plot ■ indicates that the distance between the electrodes of the discharge limit value is about 140 μm. In the measured value between the opposing terminals in the plot Δ, the distance between the electrodes of the discharge limit value is about 50 μm, whereas in the measured value between the adjacent terminals in the cross plot X, the distance between the electrodes of the discharge limit value is about 95 μm. It is. Therefore, it can be seen that the measured value between the opposing terminals is shorter in the discharge limit value than the measured value between the adjacent terminals.

  The shortest distance line connecting these measured values and theoretical values can be used as the relationship of the discharge limit value to the design values of the ESD circuit 10, the interelectrode distance, and the interprobe distance. In this case, in the theoretical value line, when the distance between the terminals is 150 μm to 200 μm, the line shifts to the actual value line (cross plot X is the actual value line between adjacent terminals). Therefore, regarding the interelectrode distance of the discharge limit value with respect to the high voltage to be applied, the theoretical value line is used on the low voltage value side of the high voltage, and the actually measured value line is used on the high voltage value side. Therefore, when the high voltage stored in the high voltage capacitor 4 from the high voltage power supply 2 is, for example, 1500 V on the low voltage side, if the discharge start voltage is 1500 V, a distance between the electrodes exceeding the theoretical value of 140 μm is required.

  FIG. 4 is a perspective view schematically showing an enlarged image of a contact state with the device 6 in the ESD test apparatus 1 of FIG. FIG. 5 is a perspective view schematically showing an example of a configuration image when ESD is applied in the ESD test apparatus 1 of FIG.

  4 and 5, in the ESD test apparatus 1 of FIG. 1, one high-voltage power source 2, eight-contact high-voltage relay 3, eight high-voltage capacitors 4, eight applied resistors 5, and other additions An ESD board for 8 channels having a wiring output portion 21a for 8 circuits of a series circuit from the high voltage capacitor 4 to the applied resistance 5 through a contact of the high voltage relay 3 is accommodated in a housing for safety. The substrate box 21 and each wiring 23 from the wiring output portion 21a of the ESD substrate box 21 are connected to 8 sets of probes 22a and 22b on the lower surface side via connectors 24 provided on the upper surface, respectively. The wafer stage 7 includes a probe card 22 provided with eight sets of probes 22a and 22b protruding from the lower surface so as to correspond to the terminals 6a and 6b on a one-to-one basis. A pair of terminals 6a and 6b of each of the eight devices 6 to be inspected provided in a matrix on the semiconductor wafer 8 and eight sets of probes 22a and 22b connected to the high-voltage capacitors 4 respectively. 1 so as to correspond to 1.

  As the wiring length from the wiring output part 21a of the ESD board box 21 to the probe card 22 changes, the ESD applied voltage waveform changes. Accordingly, the wiring lengths from the high voltage capacitor 4 to the terminals 6a and 6b of the device 6 are all the same, and the ESD voltage waveforms applied to the terminals 6a and 6b of the device 6 are the same. The ESD substrate may have a socket part for component replacement.

  FIG. 6 is a plan view schematically showing an installation image example of a plurality of ESD applicators in the ESD test apparatus 1 of FIG.

  As shown in FIG. 6, the ESD test apparatus 1A includes a plurality of ESD substrates 31 as a plurality of ESD applicators, arranged in a radial manner with the central circular portion 32 standing around the periphery, and the plurality of ESD substrates 31. The plurality of output terminals having the same circuit configuration are provided toward the central circular portion 32 side. Each of a plurality of high voltage output units from a plurality of output terminals of the same circuit configuration can be electrically connected to each terminal of a plurality of devices 6 to be inspected provided below the central circular portion 32. Has been. The distances including the independent wiring for the number of devices to be collectively applied from the plurality of output terminals of the same circuit configuration to the plurality of devices 6 to be inspected through the high voltage output units are all the same distance. The same ESD applied voltage waveform from the voltage power supply 2 is configured to be clearly and reliably applied to each terminal of the plurality of devices to be inspected 6 simultaneously.

  As the ESD test apparatus 1A, a plurality of ESD substrates 31 on which a plurality of high-voltage relays 3, a plurality of high-voltage capacitors 4 and a plurality of applied resistors 5 are mounted in an ESD circuit 10 have a donut shape excluding a central circular portion 32. A plurality of radial shapes (radial with respect to the center of the central circular portion 32) are arranged. The thickness of the high withstand voltage relay 3 is about 15 mm for a general purpose 4000V withstand voltage and about 30 mm for an 8000V withstand voltage. This thickness determines how many ESD substrates 31 can be arranged. When the high withstand voltage relay 3 has a thickness of 15 mm for a withstand voltage of 4000 V and the inner peripheral diameter of the central circular portion 32 is 40 cm, 64 ESD substrates 31 can be arranged.

  Further, since the thickness of the ESD substrate 31 is determined by the thickness of the high voltage relay 3, it is preferable to use a high voltage relay 3 having a small thickness. For example, when one ESD substrate 31 is 4ch and eight high-voltage relays 3 with one contact are mounted, the thickness of the high-voltage relay 3 is 4000V withstand voltage of 13.5 mm and 83 ESD substrates 31. Can be mounted radially and has a capacity of 332 channels in total (332 devices 6 can simultaneously perform an ESD test). In this case, the outer diameter of the ESD substrate 31 is about 50 cm.

  A plurality of sets of probes 22 a and 22 b provided on the lower surface of the probe card 22 are sucked onto the wafer stage 7 by drawing the wiring 23 from the inner peripheral side of the plurality of ESD substrates 31 and connecting to the connector 24 of the probe card 22. An ESD test is performed by connecting the terminals 6a and 6b of each device 6 to be inspected provided in a matrix on the semiconductor wafer 8 in a one-to-one correspondence. The positional relationship between the probes 22a and 22b and the terminals 6a and 6b of the device 6 can be accurately determined by image recognition while accurately moving the wafer stage 7 side constituting the prober of the automatic transfer apparatus. Here, an ESD test is performed in a row of 64 semiconductor chips 11 each having a size of 400 μm × 200 μm, and this is repeated, so that all the chips on the wafer (for example, 100,000 chips) can be automatically and sequentially performed. Since it is difficult to place the probes 22a and 22b in the adjacent rows, it is less likely that contact mistakes occur in one row than in the ESD test in two or more rows.

  In probe card needle holder design, the theoretical value obtained by calculating the relationship between the discharge limit value and the distance between the conductive members from the Passen's law and the actual value obtained by actually performing the ESD test are connected to each other. When the distance is required to be equal to or larger than the semiconductor chip size, for example, the design is such that one or two semiconductor chips are skipped, and a spatial distance of at least two is skipped to avoid discharge between adjacent probes. A semiconductor chip in a space that is not probed by a single contact is sequentially contact-processed by probing control mainly using a personal computer PC described later, and ESD application can be executed without any problem.

  The wiring length from the ESD substrate 31 to the device 6 is desirably 20 cm or less in order to maintain the standard of the ESD applied voltage waveform in FIG. The wiring length from each ESD substrate 31 to each terminal of the eight devices 6 is set to the same wiring length, and the ESD voltage waveform of FIG. 8B applied to each terminal of the device 6 is made the same. This makes the ESD test uniform.

  7A is a plan view schematically showing another installation image example of a plurality of ESD applicators in the ESD test apparatus 1 of FIG. 1, and FIG. 7B is an ESD diagram of FIG. 7A. It is a longitudinal cross-sectional view of an applicator, a probe card, and a prober. FIG. 8A is a perspective view schematically showing the ESD applicator of FIG. 7A, and FIG. 8B is a diagram showing an ESD applied voltage waveform used in the ESD test.

  7 (a), 7 (b), and 8 (a), the ESD test apparatus 1B includes a plurality of ESD board boxes 21 that are a plurality of cases, with a central circular portion 25 spaced radially around it. Has been placed. Each output terminal in a plurality of the same circuit configurations of the plurality of ESD substrates 31 accommodated in the plurality of ESD substrate boxes 21 is provided toward the central circular portion 25 side. Each of the plurality of high voltage output units is electrically connected to each terminal 6a, 6b of the plurality of devices 6 to be inspected provided below the central circular portion 25 from each of the plurality of output terminals having the same circuit configuration. It is configured to be possible. The distances including the independent wires 23 for the number of devices to be collectively applied from the plurality of output terminals of the same circuit configuration to the plurality of devices 6 to be inspected through the high voltage output units are all the same distance. The same ESD applied voltage waveform from the voltage power supply 2 is configured to be simultaneously applied to the plurality of devices to be inspected 6. The high voltage output unit may be an output terminal having the same circuit configuration, or may include the probes 22a and 22b of the probe card 22 through the wiring from the output terminal.

  As the ESD test apparatus 1B, a plurality of ESD boards 31 mounted with one high-voltage power source 2, eight-contact high-voltage relay 3, eight high-voltage capacitors 4, eight applied resistors 5, and other additional circuits are provided. Eight ESD channel boxes 21 for 8 channels having wiring output portions 21 a for 8 circuits in series connected from the high-voltage capacitor 4 to the applied resistor 5 through the contact of the high-voltage capacitor 3 from the high-voltage capacitor 4 are radially arranged. ing. The wiring 23 is drawn out from the inner peripheral side of the eight ESD substrate boxes 21 and connected to the connector 24 of the probe card 22, and eight sets of probes 22a and 22b provided on the lower surface of the probe card 22 are connected to the automatic transfer device. Of the many devices 6 provided in a matrix on the semiconductor wafer 8 on the wafer stage 7 constituting the prober, there is a one-to-one correspondence with the terminals 6a and 6b of the eight devices 6 to be inspected. Thus, an ESD test is performed and this is repeated.

  The wiring length from the wiring output portion 21a of the 8-channel ESD board box 21 to each device 6 is desirably 20 cm or less in order to maintain the standard of the ESD applied voltage waveform in FIG. The ESD voltage shown in FIG. 8B is applied to each terminal of each device 6 with the same wiring length from each wiring output portion 21a of each ESD board box 21 to each terminal of each of the eight devices 6. The waveforms are the same. This makes the ESD test uniform.

  FIG. 9 is a block diagram showing a wafer map and probing management mainly for the personal computer PC.

  In FIG. 9, an ESD test apparatus 1 according to the first embodiment includes a personal computer PC that performs probing management, one high-voltage power supply 2, an ESD controller 9 that is driven in response to an instruction from the personal computer PC, and an ESD The controller 9 simultaneously switches the eight contacts of the high-voltage relay 3 to the high-voltage power supply 2 side to accumulate the high voltage from the high-voltage power supply 2 in the eight high-voltage capacitors 4, and then the high-voltage relay 3 at a predetermined timing. The ESD circuit 10 composed of eight parallel circuits that simultaneously switch the eight contacts of the eight applied resistors 5, and the ESD applied voltage from the ESD circuit 10 through the eight applied resistors 5, respectively, to the wafer stage 7 semiconductor wafers 8 are moved and then raised, and the probes of the probe card 22 are connected to the terminals 6a and 6b of the eight devices 6, respectively. 2a, and has the probe 22a is brought into contact respectively with 8 sets of 22b, the respective terminals 6a by 8 sets 22b, and a prober 20 for application to 6b. When performing an ESD test on as many as 100,000 chips on the semiconductor wafer 8 sequentially, probing is performed continuously using an automatic transfer device such as the prober 20.

  The probing management is based on a personal computer PC and a wafer map on the semiconductor wafer 8, that is, an address indicating the positions of a large number (for example, 100,000) of semiconductor chips 11 arranged in a matrix on the semiconductor wafer 8. Thus, it is possible to store which address range of the semiconductor chip 11 is subjected to the ESD test and which address of the semiconductor chip 11 is defective in ESD withstand voltage. The ESD withstand voltage failure is measured by a measuring instrument when the leakage current due to the reverse voltage of the diode structure of the semiconductor chip 11 exceeds a predetermined value and is recognized as a failure, and the address of the semiconductor chip 11 is assigned to the personal computer PC. Remember.

  The ESD controller 9 operates not only in accordance with the operation control of the high-voltage relay 3 of the ESD circuit but also in accordance with a sequence in which the setting of the voltage level to be applied, the number of times of application, and the polarity condition to be applied are set in advance by a program or the like.

  As described above, according to the first embodiment, the high voltage application test is performed clearly and accurately on the plurality of devices 6 to be inspected collectively with the ESD applied voltage waveform conforming to the standard at the time of mass production. The high voltage inspection can be performed greatly efficiently.

  Although not described in detail in the first embodiment, each semiconductor chip 11 as a large number of devices 6 before singulation (before cutting) arranged in a matrix on the semiconductor wafer 8 is described. In addition to performing the ESD test, the ESD test is performed on each semiconductor chip 11 after separation (after cutting) and with a holding tape (the semiconductor chips 11 are arranged in a matrix). It can be carried out.

  Although not particularly described in the first embodiment, the high-voltage power supply 2 includes a positive power supply and a negative power supply with respect to the GND potential, and is configured to be able to switch between the positive power supply and the negative power supply. The target device 6 may be configured to be able to switch between a forward bias and a reverse bias.

(Embodiment 2)
In the first embodiment, a case has been described in which a predetermined high voltage from the high voltage power supply 2 is applied to a plurality of devices 6 to be inspected accurately and simultaneously with the same ESD application voltage waveform. 2, in addition to this, when each terminal 12 b on the GND side of the semiconductor chip 11 is an electrically short-circuited semiconductor wafer, the ESD withstand voltages of a large number of devices 6 to be inspected arranged in a matrix on the semiconductor wafer. A case where the inspection is performed stably will be described.

  In addition, the ESD test has two application methods for the device operating polarity: forward bias application and reverse bias application. In general, it is known that performing a test with reverse bias can guarantee high reliability. Here, in particular, in accordance with the device configuration for maintaining the ESD standard at the time of reverse bias and the shipping specification of the device. The configuration of a device capable of bidirectional bias application will be described.

  FIG. 10 is a circuit diagram illustrating a configuration example of the ESD test apparatus according to the second embodiment of the present invention.

  In FIG. 10, an ESD test apparatus 1C as a high voltage inspection apparatus according to the second embodiment includes a high voltage power supply 2C that outputs a predetermined negative high voltage, and a predetermined negative high voltage from the high voltage power supply 2C. An ESD circuit 10 </ b> C that applies simultaneously to a predetermined number of inspection target devices 6 among a large number of inspection target devices 6 arranged in a matrix on the semiconductor wafer 8, The ESD resistance of the device 6 to be inspected is inspected.

  The ESD circuit 10C includes a plurality of high voltage capacitors 4 as a plurality of high voltage capacity means for storing a predetermined negative high voltage from the high voltage power source 2, and each predetermined negative high voltage from the plurality of high voltage capacitors 4. Are connected to the high-voltage capacitor 4 side by a predetermined negative high voltage from the plurality of high-voltage power supplies 2C, or a predetermined voltage from the high-voltage capacitor 4 is output. One or a plurality of high withstand voltage relays 3 as a plurality of switching means for switching so as to connect the high voltage to the high voltage output unit side, and the same circuit configuration, from the high voltage capacitor 4 to the high withstand voltage relay 3 and the applied resistance 5 As many circuits as the plurality of devices to be inspected 6 to be batch-applied are provided in parallel.

  The ESD circuit 10C causes the ESD controller 9 to simultaneously switch the eight contacts of the high voltage relay 3 to the high voltage power supply 2C side and accumulate the negative high voltage from the high voltage power supply 2C in the eight high voltage capacitors 4, and then At the predetermined timing, the eight contacts of the high voltage relay 3 are simultaneously switched to the eight applied resistances 5 side, and the negative high voltage from the eight high voltage capacitors 4 is transmitted through the eight contacts of the high voltage relay 3 respectively. Each of the applied resistors 5 is composed of eight parallel circuits.

  In this case, the device 6 to be inspected is a light emitting element such as an LRD element or a laser element having a diode structure therein. A high voltage capacitor 4 stored in the high voltage power supply 2C applies a negative high voltage so as to be reverse biased to the diode structures of the plurality of devices 6 to be inspected arranged in a matrix on the semiconductor wafer 8.

  The ESD test apparatus 1C has a plurality of (eight in this case) high voltage via each contact of the high voltage relay 3 with one terminal of the high voltage power supply 2C that outputs a negative high voltage having multiple contacts (here, eight contacts). The other electrodes of the plurality of (eight in this case) high-voltage capacitors 4 are connected to the other electrode of the capacitor 4 and are connected to the other terminal of the high-voltage power source 2C and grounded. Each one electrode of the multiple (eight here) high-voltage capacitors 4 is inspected from the high-voltage output section through each applied resistor 5 from each contact of the multi-contact (here, eight contacts) high-voltage relay 3. Each of the target devices 6 is connected to one terminal. The other terminal of each device 6 is connected to the other terminal of the high voltage power source 2C from the GND voltage output section and grounded. Although not shown here, there is provided an ESD controller 9 to be described later for controlling simultaneous connection switching of the multi-contact (here, 8 contacts) high-voltage relay 3 at a predetermined timing. A separate power source is required to drive the multi-contact (here, 8 contacts) high voltage relay 3.

  FIG. 11 is a schematic diagram when an ESD withstand voltage test is performed on a large number of devices 6 to be inspected arranged in a matrix on the semiconductor wafer 8 using the ESD test apparatus 1C of FIG.

  In FIG. 11, the high voltage capacitor 4 in the ESD test apparatus 1C is charged with a negative high voltage. For example, −1500 V is applied to the anode terminal of each device 6 to be inspected, and 0 V is applied to the cathode terminal. Thus, since a negative high voltage of −1500 V is applied to the anode terminal of each device 6 and 0 V is applied to the cathode terminal, an ESD reverse voltage is applied to the diode structure to perform an ESD test. In this case, the high voltage power source 2C is set as a negative power source. The voltage supply source side and the GND side of the ESD 10C are reversed. Since the charge regulation amount (for example, 100 pF) of the high-voltage capacitor 4 is sucked from the n-GaN substrate through the anode terminal, the amount of charge passing through the anode terminal is constant. Since the anode electrode is independent for each device, there is no problem as an ESD condition. Therefore, it is possible to reliably ensure the application of the charge regulation amount (for example, 100 pF) of the high-voltage capacitor 4 to each device 6. Furthermore, if the high voltage power supply 2C is a + power supply, a forward bias can be realized.

  On the other hand, as shown in FIG. 12, when the reverse bias state is set by reversing the polarity of the application circuit (GND) using a positive power source, the cathode terminal of the device 6 is switched to the anode terminal of the adjacent device 6. When the short circuit occurs, the applied charge amount is dispersed in the n-GaN substrate, and the charge amount passing through the anode terminal from the cathode terminal of the same device 6 becomes indefinite. In this way, when short-circuit defects are present, the charge penetrating through the short-circuited portion concentrates, and thus deviates from the ESD regulations. This can be solved by the ESD test apparatus 1C of FIG. 11 with a negative high voltage.

  FIG. 13 is a plan view for explaining probe arrangement at each terminal of the semiconductor chip 11 as an example of probing when a plurality of devices are subjected to ESD application in the ESD test apparatus 1C of FIG.

  As shown in FIG. 13, the contact to each terminal 12a of the probe 22a which is an ESD charge supply source is performed independently for each device (each semiconductor chip 11), and the application circuit (the ESD circuit 10C and the high voltage output unit are connected). (Including circuit) mounting and probe contact. As described above, the probe 22a to each terminal 12a of the semiconductor chip 11 to which the ESD voltage waveform of FIG. 8B is applied is provided independently for each semiconductor chip 11, but each of the semiconductor chips 11 which are GND side terminals is provided. The probe 22b to the terminal 12b is one point (or a plurality of the semiconductor chips 11) for the ESD voltage waveform application processing when each terminal 12b on the GND side of the semiconductor chip 11 is an electrically shorted semiconductor wafer. Each element) may be a contact target. In the probe 22b connected to the GND (COM) of the ESD circuit 10C, since the terminals 12b on the GND side of the plurality of devices are both electrically short-circuited in the wafer 8, of the plurality of terminals 12b on the GND side. By contacting at least one point, the same state as that in which all devices are contacted is obtained. As a result, at least one contact probe on the GND side can be left out and the other can be made unnecessary.

  FIG. 14 is a diagram schematically showing connection to the device 6 to be inspected when the probe on the GND side is omitted.

  In FIG. 14, a grounded wafer stage conductive layer 42 is provided on the surface side of the wafer stage insulating layer 41, and the semiconductor wafer 8 is mounted on the wafer stage conductive layer 42. The plurality of inspection target devices 6 arranged in a matrix on the semiconductor wafer 8 are positively subjected to a shorting process so as to be short-circuited on the GND side between the plurality of inspection target devices 6 in the manufacturing process. Further, a conductive film is formed on the edge side surface of the semiconductor wafer 8, and the wafer stage conductive layer 42 is electrically connected from each terminal 12 b that is a ground terminal (GND terminal) of the device 6 to be inspected through the conductive film on the side surface of the wafer edge. Connect. Each wiring 23 from the wiring output unit 21 a is connected to the probe 22 a on the lower surface side of the probe card 22 via a connector 24 provided on the upper surface of the probe card 22 so as to correspond to each device 6 on a one-to-one basis. Probes 22a are provided so as to protrude from the lower surface.

  By connecting the GND that is short-circuited between the devices 6, the GND of the wafer stage conductive layer 42, and the GND of the ESD circuit 10 </ b> C as a common GND, probing the GND terminal of each device 6 may be completely unnecessary. it can.

  As described above, according to the second embodiment, a plurality of devices 6 to be inspected are collectively subjected to a high voltage application test clearly and accurately with an ESD application voltage waveform conforming to the standard. The inspection can be performed greatly efficiently. In addition to this, when a plurality of devices 6 to be inspected arranged in a matrix on the semiconductor wafer 8 are short-circuited on the GND side or when a wafer in which the devices 6 are short-circuited on the GND side is used. The withstand voltage inspection can be performed accurately and stably and greatly efficiently.

  Although not particularly described in the first and second embodiments, the substrate of the probe card 22 is not a multilayer wiring substrate but a surface wiring substrate for avoiding discharge. When a multilayer wiring board is used as the board of the probe card 22, since it is a high voltage of several thousand volts, the dielectric constant (discharge avoidance characteristics) between the wirings and the distance / voltage are taken into consideration. The probe may be made of an indium or tungsten material that is resistant to discharge heat. The probe maintains a distance between probes for avoiding discharge. As means for monitoring the ESD applied voltage waveform, it is desirable that a round pin connector is provided at the base of the probes 22a and 22b of the substrate of the probe card 22.

(Embodiment 3)
In the third embodiment, a case where an ESD test is performed without using a mercury relay as the high-voltage relay 3 will be described.

  FIG. 15 is a longitudinal sectional view schematically showing a case where the contact stage is in the upper position in the ESD test apparatus according to Embodiment 3 of the present invention. FIG. 16 is a longitudinal sectional view schematically showing the case where the contact stage is in the lower position in the ESD test apparatus of FIG.

  In FIG. 15, in the ESD test apparatus 1D of the third embodiment that inspects ESD tolerance for one or a plurality of devices to be inspected, the switch is operated by the vertical movement of the contact stage 53 on which the one or a plurality of devices to be inspected 54 are mounted. The switch 52 as the means is turned on / off to charge / discharge the high voltage of the high voltage capacitor 56 as the high voltage capacity means corresponding to one or a plurality of devices to be inspected one-to-one. The ESD inspection of one or a plurality of devices to be inspected 54 is performed by the discharge from.

  The ESD test apparatus 1D of the third embodiment includes a high voltage power supply 55 that outputs a predetermined high voltage, one or more high-voltage capacitors 56 that store a predetermined high voltage from the high voltage power supply 55, and one or more It has probes 57a and 57b of a probe card 57 as one or a plurality of high voltage output units that output a predetermined high voltage from the high voltage capacitor 56, and the probes 57a and 57b of the probe card 57 and one or a plurality of inspection objects. The first operation of separating the terminals 54 a and 54 b of the device 54 and connecting the one or more high-voltage capacitors 56 to the high-voltage power supply 55 side by the switch 52, and the one or more high-voltage capacitors 56 and the high voltage by the switch 52 The power supply 55 is shut off and one or more probes are passed through the probes 57a and 57b of the probe card 57. Each terminal 54a of 査 target device 54, the second operation and to connect respectively to 54b, switched by vertical movement of the contact stage 53.

  Further details will be described. One contact 52 a of the switch 52 is fixed on the base 51, and the other contact 52 b of the switch 52 is fixed immediately below the one contact 52 a of the switch 52 on the lower surface of the contact stage 53. A device 54 to be inspected is fixed on the contact stage 53, and the contact stage 53 is configured to be movable up and down at a predetermined interval. Although only one device 54 to be inspected is shown here, a plurality of devices 54 to be inspected are provided in the front-rear direction.

  One contact 52 a of the switch 52 is connected to a high voltage power supply 55, and the other contact 52 b of the switch 52 is grounded via a high voltage capacitor 56. The high voltage capacitor 56 is connected to the high voltage side of the probe card 57, and the GND side of the probe card 57 is grounded.

  Probes 57 a and 57 b are provided to protrude from the lower surface of the probe card 57 so as to correspond to the two terminals 54 a and 54 b of each device 54 on a one-to-one basis. The terminals 54a and 54b of each device 54 and the probes 57a and 57b of the probe card 57 respectively connected to the high-voltage capacitor 56 are arranged in a one-to-one correspondence.

  As the high-voltage power supply 55, one having a charge processing capability corresponding to a plurality of high-voltage capacitors 56 corresponding to the number of devices to be collectively applied is selected.

  The high voltage output unit and the GND voltage output unit connected to the GND voltage source are each a plurality of contact members that can be electrically connected to the terminals 54a and 54b of one or a plurality of test target devices 54. Has contact means arranged. This contact means is either a manipulator having a plurality of contact members fixed to the arm or a probe card 57 having a plurality of contact members fixed thereto. As the contact member, a discharge heat resistant indium or tungsten material is used. Here, a probe card 57 is used as a contact means, and probes 57a and 57b are used as a plurality of contact members. Since a high voltage is applied to the substrate of the probe card 57, it is not a multilayer wiring substrate but a surface wiring substrate for avoiding discharge.

  With the above configuration, in FIG. 15, the contact stage 53 is in the upper position, and the high voltage from the high voltage capacitor 56 is applied to the terminal 54 a of each device 54 via the probe 57 a on the high voltage side of the probe card 57. An ESD test is performed. That is, when the contact stage 53 is in the upper position, the high voltage power supply 55 is cut off from the high voltage capacitor 56, and the same ESD applied voltage waveform from each high voltage capacitor 56 is transmitted from each probe 57a to the terminal 54a of each device 54. To be applied. At this time, the terminal 54b of each device 54 is grounded via the probe 57b.

  In FIG. 16, the contact stage 53 is in the lower position, and the high voltage from the high voltage power supply 55 is charged to the high voltage capacitor 56 via the switch 52. That is, when the contact stage 53 is in the lower position, the probes 57a and 57b and the terminals 54a and 54b of the device 54 are separated from each other, and the high voltage power supply 55 is connected to the high voltage capacitor 56 and charged.

  FIG. 17 shows the gap between the contacts of the switch 52 of FIG. 15, where the dotted line is the lower position of the contact stage 53 and the solid line is the upper position of the contact stage 53.

  In FIG. 17, the gap length A is the contact height of the probes 57a and 57b, and the gap length B is the contact height of the contacts 52a and 52b of the switch 52. The probes 57a and 57b are urged with a constant urging force by a spring, an elastic body or the like within a predetermined stroke range, and come into contact with the terminals 54a and 54b of the device 54. Further, the contacts 52a and 52b of the switch 52 are also urged with a constant urging force by a spring, an elastic body, or the like within a predetermined stroke range and are connected to each other.

  The relationship between the discharge limit value with respect to the distance between the conductive members (the distance between the probes 57a and 57b and the terminals 54a and 54b of the device 54 and the distance between the contacts of the switch 52) due to the vertical movement of the contact stage 53 is calculated from the law of Passen. The line with the shortest distance connecting the theoretical value and the actually measured value obtained by actually conducting the ESD test is used as the design value of the distance between the conductive members.

  The contact stage 53 constituting the prober of the automatic transfer apparatus for the semiconductor wafer 8 originally adsorbs a plurality of devices 54 (or the semiconductor wafer 8) to be inspected and moves up and down, but also performs the following plurality of inspections. In order to perform the ESD inspection of the target device 54, the plane is horizontally moved and vertically moved. The up / down operation (vertical movement) of the contact stage 53 corresponds to the operation of a high voltage relay (mercury relay) necessary for the ESD circuit, and is replaced with an electric circuit operation.

  As described above, according to the third embodiment, the switch 52 is turned on / off by the vertical movement of the contact stage 53 to charge / discharge the high-voltage capacitor 56 and perform the ESD inspection of the device 54 to be inspected. The more devices 54, the more high-voltage relays (mercury relays) can be made unnecessary, and the power source and the ESD controller for driving them can be made unnecessary.

  Also in the third embodiment, as in the first and second embodiments, at the time of mass production, a plurality of devices 6 to be inspected are collectively and clearly and accurately applied with an ESD applied voltage waveform conforming to the standard. By performing a high voltage application test, a high voltage test can be performed significantly more efficiently.

  In the third embodiment, the probes 57a and 57b and the terminals 54a and 54b of the device 54 are in a one-to-one correspondence with one high-voltage capacitor 56. The number of high-voltage capacitors 56 is provided so as to correspond to this one by one.

  In the third embodiment, the charging / discharging of the high-voltage capacitor 56 is controlled by turning the switch 52 on and off by the vertical movement of the contact stage 53. However, the present invention is not limited to this, and instead of the switch 52 in the ESD test apparatus 1E. Thus, the insulating gas filling switch 61 in FIG. 18 may be used. Since the insulating gas filling switch 61 has a high voltage, even if an arc is drawn between the contacts in the sealed space in which the switch contacts are accommodated, the insulating space filling gas is filled in the sealed space with a long insulation life. .

  When the switch 52 (or between contact probes) is electrically opened and closed with a high voltage difference, a discharge phenomenon that emits light or heat can be confirmed. When a discharge occurs in the switch 52 (or between the contact probes), heat generated by air discharge occurs at the contact point of the switch 52. Therefore, the contact surface is oxidized by this discharge heat, and electrical contact itself becomes difficult. The ESD application according to the standard cannot be continued due to the change in the contact resistance of the switch 52.

  The high-voltage discharge threshold varies depending on the applied voltage, the distance between contact points of the switch, temperature and humidity, and the like. As a current technology, it is known to use a gas having high insulation used as an insulation medium or arc extinguishing medium for power equipment such as an insulation switchgear in a high voltage facility. By sealing and filling with an insulating gas, a measure for protecting the switch, such as the insulating gas filling switch 61, can be realized.

  To protect the contact probe portion, against the increase in contact resistance due to the surface oxidation of the probe, the ESD application based on the standard is continued by monitoring the needle tip and periodically polishing. Alternatively, if the gas is not harmful, it is also an effective means to always blow this gas on the contact portion.

  In the third embodiment, charging / discharging of the high-voltage capacitor 56 is controlled by turning on / off the switch 52 by the vertical movement of the contact stage 53 (wafer prober). In the apparatus 1F, instead of the switch 52, a shaft 71 as a drive source for moving the contact stage 53 up and down, a rack and a pinion 72 for driving the contact stage 53 up and down are provided, and a switch 73 is provided at the tip (lower end surface) of the shaft 71. May be provided. That is, the switch 73 may be provided on the lower end surface of the shaft (axis 71) that moves up and down the contact stage 53 with the semiconductor wafer 58 fixed on the upper surface. When the contact stage 53 moves downward together with the shaft 71, the switch 73 is turned on and the high voltage power supply 55 charges the high voltage capacitor 56. Further, when the contact stage 53 moves upward together with the shaft 71, the switch 73 is turned off, the high voltage power supply 55 and the high voltage capacitor 56 are shut off, and the ESD test is executed.

  In the third embodiment, the charging / discharging of the high-voltage capacitor 56 is controlled by turning on / off the switch 52 by the up / down operation of the contact stage 53 (wafer prober). In the apparatus 1G, the contact 52a of the switch 52 on the base 51 is grounded, a voltage source of about 5V is connected to the contact 52b of the switch 52 on the contact stage 53 side, and the low voltage source 82 of about 5V has a high withstand voltage. The high-voltage power supply 55 is connected to the high-voltage capacitor 56 through the high-breakdown-voltage transistor 81 and is connected to the control terminal of the transistor 81 (insulated gate bipolar transistor IGBT). When the switch 52 is turned on, the low voltage source 82 of about 5V functions, the high breakdown voltage transistor 81 (insulated gate bipolar transistor IGBT) is turned on, and the high voltage from the high voltage power supply 55 is charged in the high voltage capacitor 56. . When the switch 52 is turned off, the high voltage charged in the high voltage capacitor 56 is applied to each terminal 54a of each device 54 as an ESD applied voltage waveform. At this time, the low voltage source 82 does not function, whereby the high voltage transistor 81 (insulated gate bipolar transistor IGBT) is turned off, and the high voltage power supply 55 is cut off from the high voltage capacitor 56. Compared to the case of FIG. 17, this merit is that a high voltage of several thousand volts is not directly applied to the mechanical switch 52 and is safe and has a long life.

  Although not specifically described in the third embodiment, the reference example of the second embodiment can be applied. That is, the high voltage power supply 55 has a semiconductor wafer mounted on the contact stage 53 (wafer prober) and is negatively biased so as to be reversely biased with respect to the diode structures of the plurality of devices to be inspected 54 arranged on the semiconductor wafer. Apply high voltage. In this case, the plurality of inspection target devices arranged on the semiconductor wafer are short-circuited to the GND potential. Further, the conductive outer peripheral portion of the semiconductor wafer is electrically short-circuited to the GND potential, and the GND potential short-circuited between the plurality of devices to be inspected 54 is electrically connected to the conductive outer peripheral portion of the semiconductor wafer. By connecting the GND potential of the upper surface conductive layer and the GND potential of the ESD circuit composed of the high-voltage capacitor 56 and the high-voltage output unit as a common GND potential, connection processing to the GND terminals of the plurality of devices to be inspected 54 becomes unnecessary. You may make it do.

  Although not specifically described in the third embodiment, the reference example of the first embodiment can be applied. Mercury was used by using the switch 52 and contact stage 53 vertical movement mechanism and its peripheral control circuit in place of the high withstand voltage relay 3 and its drive power supply and ESD controller 9 of the first embodiment. The reference example of the first embodiment can be applied without using the high voltage relay 3. That is, a semiconductor wafer is mounted on the contact stage 53 (wafer prober), and the connection processing for the plurality of devices to be inspected 54 arranged on the semiconductor wafer is continuously performed using the prober. The computer system controls the vertical movement of the contact stage 53 and the operation of the prober to perform the probing control based on the wafer map indicating the addresses of the plurality of inspection target devices 54. The high voltage power supply 55 includes a positive power supply and a negative power supply with respect to the GND potential, and can be switched between a positive power supply and a negative power supply, and a forward bias and a reverse bias are applied to a plurality of devices to be inspected 54. It is configured to be switchable.

  Although not described in detail in the third embodiment, in an apparatus having a contact stage 53 that swings in a vertical direction and a horizontal direction of a semiconductor test apparatus, this amplitude operation is an electrical function necessary for ESD application. Substitutes for circuit operation. The amplitude mechanism of the contact stage 53 is a switching mechanism necessary for the ESD application circuit. The high withstand voltage relay 3, the ESD controller 9 which is a timing controller necessary for this operation, and the high withstand voltage relay drive power supply are not required. By sharing the switch 52 and increasing the number of wirings and high-voltage capacitors 56 for applying ESD to the device 54, it is possible to realize a batch processing of a large number of devices. The switch 52 is uniformly controlled for a plurality of application targets. The high voltage output unit is configured as a probe card 57, and the device 54 is processed in a wafer state. As described above, the switch mechanism is provided on the end surface of the shaft that drives the contact stage 53. This is a function of charging the high voltage capacitor 56 from the high voltage power supply 55 by the amplitude operation of the contact stage 53. Due to the amplitude operation of the contact stage 53, the charge charged in the high voltage capacitor 56 is passed through the device 54. The vertical movement itself of the device contact 53 is an ESD application switching mechanism. The contact length of the switch 52 and the gap length between the probes 57 a and 57 b and the terminals 54 a and 54 b are determined by the amplitude distance of the contact stage 53. The contact length of the switch 52 and the gap length between the probes 57a and 57b and the terminals 54a and 54b are determined from the calculated values according to the passenger as a reference for avoiding high voltage discharge. The switch 52 may be installed in a sealed state filled with a gas having high insulation resistance.

  As mentioned above, although this invention has been illustrated using preferable Embodiment 1-3 of this invention, this invention should not be limited and limited to this Embodiment 1-3. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments 1 to 3 of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention is in the field of a high-voltage inspection apparatus that performs high-voltage application inspection using an ESD test apparatus that inspects ESD resistance for inspection target devices such as LSI elements, light-emitting elements such as LED elements and laser elements, for example. Execute high-voltage inspection significantly and efficiently by performing a clear and accurate high-voltage application test with a current waveform (or voltage waveform) conforming to the standard for multiple devices to be inspected. Can do.

DESCRIPTION OF SYMBOLS 1, 1A-1G ESD test apparatus 2,2C High voltage power supply 3 High voltage relay 4 High voltage capacitor 5 Applied resistance 6 Device 6a, 6b Terminal 7 Wafer stage 8 Semiconductor wafer 9 ESD controller 10, 10C ESD circuit 11 Semiconductor chip 12 , 12a, 12b Terminal 13 Probe 20 Prober (automatic transfer device)
21 ESD board box 21a Wiring output part 22 Probe card (contact means)
22a, 22b Probe (contact member)
23 Wiring 24 Connector 25 Central Circular Portion 31 ESD Substrate 32 Central Circular Portion 41 Wafer Stage Insulating Layer 42 Wafer Stage Conductive Layer 51 Base 52 Switch 52a One Contact 52b Other Contact 53 Contact Stage 54a, 54b Terminal 54 Inspected Device 55 High Voltage Power supply 56 High-voltage capacitor 57 Probe card 57a, 57b Probe 58 Semiconductor wafer 61 Insulating gas filling switch 71 Bearing 72 Rack pinion 73 Switch 81 High voltage transistor (insulated gate bipolar transistor IGBT)
82 Low Voltage Source 100 Conventional ESD Test Device 101 High Voltage Power Supply 102 High Voltage Relay for Charging 103 High Voltage Relay for Discharge 104 Applied Resistance 105 Device to be Tested 106 High Voltage Capacitor 107 Timing Controller 200 Electrostatic Discharge Test Jig 206 Gun Holder 201 Electronic Component 202 Printed Wiring Board 202a Wiring Pattern 203 Conductive Plate 204 Printed Board Supporting Tool 205 Static Electricity Generation Gun PC Personal Computer

Claims (16)

A high-voltage testing device for simultaneously testing the ESD resistance to more device under test, the vertical movement of the contact stages equipped with the plurality of device under test, switch means is turned on / off, the plurality of A high voltage inspection apparatus that charges / discharges a high voltage of each high voltage capacity unit corresponding to the inspection target device on a one-to-one basis, and performs ESD inspection of the plurality of inspection target devices by discharging from the high voltage capacity unit. The high voltage inspection apparatus according to claim 1,
And outputs a high voltage power supply that outputs a predetermined high voltage, a plurality of high voltage capacitive means for storing a predetermined high voltage from the high voltage power source, a predetermined high voltage from said plurality of high voltage capacitive means and a plurality of high-voltage output unit, with to separate the respective terminals of the with the plurality of high voltage output unit a plurality of device under test, the high voltage side of said plurality of high voltage capacitive means by said switching means first operation and to connect to, along with blocking the high voltage capacitive means and the high voltage power supply of said plurality of the said switch means, second connecting said plurality of high voltage output unit to the terminals of said plurality of device under test A high-voltage inspection apparatus that switches between two operations by an up-and-down operation of the contact stage. The high voltage inspection apparatus according to claim 2,
A high-voltage inspection apparatus that selects a high-voltage power supply that has a charge processing capability corresponding to the plurality of high-voltage capacity means for the number of devices to be collectively applied. The high voltage inspection apparatus according to claim 2,
Each of the high voltage output unit and the GND voltage output unit connected to the GND voltage source is provided with a plurality of contact members that can be electrically connected to the terminals of the plurality of devices to be inspected. High voltage inspection apparatus having contact means. The high voltage inspection apparatus according to claim 4,
The contact means is a high voltage inspection apparatus which is either a manipulator having a plurality of contact members fixed to an arm or a probe card having a plurality of contact members fixed thereto. The high voltage inspection apparatus according to claim 4,
The contact member is a high-voltage inspection device using a discharge heat resistant indium or tungsten material. In the high voltage inspection apparatus according to claim 5,
The probe card substrate is a high-voltage inspection device which is a surface wiring substrate for avoiding discharge. The high voltage inspection apparatus according to claim 1,
A line with the shortest distance connecting the theoretical value obtained by calculation from the Passen's law and the actual measurement value obtained by actually performing the ESD test on the relationship between the discharge limit value and the distance between the conductive members due to the vertical movement of the contact stage. A high voltage inspection device used for the minimum design value of the distance between the conductive members. The high voltage inspection apparatus according to claim 2,
The high voltage power supply is a high voltage inspection apparatus that applies a negative high voltage so as to be reverse-biased with respect to a diode structure of a plurality of devices to be inspected disposed on a semiconductor wafer. The high voltage inspection apparatus according to claim 9,
A high-voltage inspection apparatus in which a plurality of inspection target devices arranged on the semiconductor wafer are short-circuited to a GND potential. The high voltage inspection apparatus according to claim 10,
A contact stage in which the conductive outer peripheral portion of the semiconductor wafer is electrically short-circuited to the GND potential, and the GND potential short-circuited between the plurality of devices to be inspected is electrically connected to the conductive outer peripheral portion of the semiconductor wafer. A high-voltage inspection apparatus that eliminates connection processing to the GND terminals of the plurality of devices to be inspected by connecting the GND potential of the conductive layer and the GND potential of the ESD circuit as a common GND potential. The high voltage inspection apparatus according to claim 1,
A high-voltage inspection apparatus in which connection processing for a plurality of inspection target devices arranged on a semiconductor wafer is continuously performed using a prober. The high voltage inspection apparatus according to claim 12,
A high-voltage inspection apparatus in which a computer system controls probing of the contact stage and also controls the operation of the prober to perform probing control based on a wafer map indicating addresses of the plurality of devices to be inspected. The high voltage inspection apparatus according to claim 2,
The high-voltage power source includes a positive power source and a negative power source with respect to a GND potential, and is configured to be switchable between the positive power source and the negative power source, and forward bias and reverse bias for the plurality of devices to be inspected. A high-voltage inspection device that can be switched between. In the high voltage inspection apparatus according to claim 5,
In the probe card,
The probe stand design criteria for a plurality of probes are the theoretical values obtained by calculating from the Passen's law the relationship between the discharge limit value and the distance between the conductive members due to the vertical movement of the contact stage, and the actual measurement obtained by conducting an ESD test. The line with the shortest distance connecting the values is used as the minimum design value of the distance between the conductive members. When a distance larger than the semiconductor chip size is required, for example, one or two semiconductor chips are skipped. High-voltage inspection device designed to maintain a large spatial distance. The high voltage inspection apparatus according to claim 15,
In the probe card,
A semiconductor chip in a spatial region that is not probed by a single contact is a high-voltage inspection apparatus that is subjected to contact processing sequentially by probing control, mainly using a personal computer PC, and executes ESD application.