JP7417835B2 - Continuity testing equipment, prober - Google Patents

Description

The present invention relates to a continuity test device, a prober, and a static eliminator used in a wafer test system that tests the electrical characteristics of a plurality of semiconductor chips formed on a wafer.

A plurality of semiconductor chips having the same electric element circuit are formed on the surface of a wafer (also referred to as a semiconductor wafer). Before the wafer is individually cut into semiconductor chips by a dicer, the electrical characteristics of each semiconductor chip are tested by a wafer test system (see Patent Document 1 and Patent Document 2). This wafer test system includes a prober and a tester.

A prober applies probes to the electrodes (also called electrode pads) of each semiconductor chip by moving the wafer chuck and a probe card having probes (also called probe needles) relative to each other while the wafer is fixed on the wafer chuck. Make electrical contact. The tester supplies various test signals to the electrodes of each semiconductor chip through the terminals connected to the probe, and receives and analyzes the signals output from the electrodes in response to the supply of the test signals. Inspect the electrical characteristics of each semiconductor chip (whether it operates normally, etc.).

Semiconductor chips such as power transistors, field effect transistors, IGBTs (Insulated Gate Bipolar Transistors), LEDs (light emitting diodes), and semiconductor lasers have electrodes formed on their front surfaces, as well as electrodes on their back surfaces. An electrode (back electrode) is formed. For example, a gate electrode and an emitter electrode are formed on the front surface of an IGBT, and a collector electrode is formed on the back surface thereof.

The wafer chuck of a wafer test system that is compatible with the inspection of such semiconductor chips includes a support surface that supports the wafer in contact with the back surface of the wafer, and a conductive support surface that acts as a measurement electrode for the tester. A wafer mounting surface) is provided (see Patent Document 3). This support surface is electrically connected to the tester via chuck lead wires (wiring) drawn out from the wafer chuck. When inspecting a semiconductor chip, the wafer is held in a wafer chuck, and various measurements are performed with a probe in contact with a surface electrode of the semiconductor chip formed on the surface of the wafer. At this time, depending on the measurement conditions, voltage, current, etc. are applied from the tester to the back electrode of the semiconductor chip described above, or the back electrode is grounded.

Patent No. 4068127 Japanese Patent Application Publication No. 2003-218175 Patent No. 2970893

By the way, as the wafer chuck moves around, the temperature becomes high, so the chuck lead wires described above tend to be exposed to severe mechanical and thermal conditions and tend to break. If this chuck lead wire breaks, it becomes impossible to apply voltage and current to the support surface of the wafer chuck, that is, the back electrode of the semiconductor chip of the wafer, or it becomes impossible to detect signals from the back electrode. Accurate inspection of semiconductor chips becomes impossible.

For this reason, in the past, personnel in charge regularly checked the continuity of the chuck lead wire using a handy tester during periodic inspections, etc., but until the periodic inspection, it was not known that the chuck lead wire was broken. , there is a risk that the wafer will be inspected with the chuck lead wire broken.

Therefore, as described in Patent Document 3, for example, a test power source that applies a test voltage to the chuck lead wire, a conversion transformer that extracts an output waveform from the current flowing through the chuck lead wire, and an output waveform and a reference from the conversion transformer. A possible method is to provide the wafer test system with a determination unit that compares the waveform with the waveform and determines whether there is continuity (disconnection) in the chuck lead wire.

However, according to the method described in Patent Document 3, although the presence or absence of continuity of the chuck lead wire can be automatically inspected, the device configuration becomes large-scale. For this reason, there is a strong desire to automatically and easily inspect the presence or absence of continuity of the chuck lead wire.

Note that the wafer chuck is charged with an electric charge (static electricity), and the wafer on the wafer chuck is also charged with electric charge. There is a risk that an arc will occur due to discharge between the chip and the probe, damaging the semiconductor chip. For this reason, for example, as described in Patent Document 2, by connecting a resistor (high resistance) to a connection line electrically connected to the wafer chuck, and further connecting a grounded relay to this resistor, One possible method is to remove static electricity from the wafer chuck.

However, in order to accurately inspect each semiconductor chip, it is necessary for the wafer chuck to be in a highly insulating state (a state that is not affected by external leakage current, etc.), which is described in Patent Document 2 above. In this method, a resistor is placed between the wafer chuck and the relay. Therefore, even after the relay is switched from on to off after static electricity is removed from the wafer chuck, the state of connection between the wafer chuck and the resistor is maintained. As a result, the leakage current generated from the resistor may affect the inspection of each semiconductor chip or may adversely affect the semiconductor chips.

The present invention has been made in view of the above circumstances, and a first object thereof is to provide a continuity testing device and a prober that can automatically and easily test whether or not there is continuity in a chuck lead wire. A second object of the present invention is to provide a static eliminator that can minimize the occurrence of leakage current.

A continuity testing device for achieving the first object of the present invention includes: a wafer chuck that holds a wafer on which a plurality of semiconductor chips are formed; a probe that contacts a surface electrode of the semiconductor chip formed on the surface of the wafer; A wafer support surface provided on a wafer chuck of a prober equipped with a conductive support surface that is in contact with a back electrode of a semiconductor chip formed on the back surface of the wafer. In the continuity testing device, a first component, which is one of a first relay and a first resistor, is connected to the other end opposite to one end of the wiring connected to the support surface; a second component that is the other of the first relay and the first resistor that are grounded; additional wiring connected to the support surface; and a current loop forming part connected to the additional wiring, the second component being provided with at least a power source and the wiring. , a current loop forming section that forms a current loop that includes at least an additional wiring, a first component, a second component, and a power source, and a determining section that determines whether or not a current from the power source flows through the current loop. .

According to this continuity testing device, it is possible to determine whether or not there is continuity in the wiring by determining whether or not current flows through the current loop.

In the continuity testing device according to another aspect of the present invention, the current loop forming section includes a second relay and a second resistor connected to the other end of the additional wiring connected to the support surface on the opposite side from one end of the additional wiring. a third component on one side; a fourth component on the other side of the second relay and second resistor connected to the third component; and a power source connected to the fourth component and grounded; The determination unit makes a determination based on the detection result of the voltage detection unit. Thereby, it is possible to determine whether or not current flows through the current loop based on the voltage detection result of the second resistor by the voltage detection section.

A continuity testing device according to another aspect of the present invention includes a relay control unit that individually switches both the first relay and the second relay between a closed state and an open state, and the determination unit controls the relay control unit to The determination is made based on the detection result of the voltage detection unit in a state where both the first relay and the second relay are switched to the closed state. Thereby, it is possible to determine whether or not current flows through the current loop based on the voltage detection result of the second resistor by the voltage detection section.

In a continuity testing device according to another aspect of the present invention, the first component is a first relay, and the second component is a first resistor. Thereby, by turning off the first relay, the first resistor can be separated from the support surface in the shortest possible time, so that leakage current can be suppressed to a minimum.

In the continuity testing device according to another aspect of the present invention, the connector is provided at the other end of the wiring and is connected to both the tester for testing the electrical characteristics of the semiconductor chip and the first component. Equipped with.

A prober for achieving the first object of the present invention is a wafer chuck that holds a wafer on which a plurality of semiconductor chips are formed, and a conductive chuck that is in contact with the back electrode of the semiconductor chip formed on the back surface of the wafer. The present invention includes a wafer chuck having a support surface, a probe that contacts a surface electrode of a semiconductor chip formed on a surface of a wafer, and the above-described continuity testing device.

A static eliminator for achieving the second object of the present invention includes a wafer chuck that holds a wafer on which a plurality of semiconductor chips are formed, and a probe that contacts a surface electrode of the semiconductor chip formed on the surface of the wafer. Wiring that is electrically connected to the conductive supporting surface that is provided on the wafer chuck of the prober and that contacts the backside electrode of the semiconductor chip formed on the backside of the wafer, and the wiring that is connected to the wiring. and a first resistor connected to the first relay and grounded.

According to this static eliminator, the first resistor can be separated from the support surface in the shortest possible time by turning off the first relay, so that leakage current can be suppressed to a minimum.

The continuity testing device and prober of the present invention can automatically and easily test whether or not the chuck lead wire has continuity. Furthermore, the static eliminator of the present invention can minimize the occurrence of leakage current.

FIG. 1 is a schematic diagram of a wafer test system. It is an explanatory view for explaining a chuck lead wire and an additional circuit. It is a schematic diagram of the static elimination circuit of a comparative example. It is an explanatory diagram for explaining a current loop and a power supply. FIG. 3 is a functional block diagram of an overall control section of the prober. 7 is a flowchart showing the process flow of static elimination of the wafer chuck, continuity test of the chuck lead wire, and self-diagnosis of each relay using an additional circuit.

[Wafer test system configuration]
FIG. 1 is a schematic diagram of a wafer test system 9. As shown in FIG. Hereinafter, the upper and upper surfaces in the Z-axis direction, which is the vertical direction in the figure, will be referred to as "upper" and "upper surface", and the lower and lower surfaces in the Z-axis direction will be referred to as "lower" and "lower surface", as appropriate.

The wafer test system 9 tests the electrical characteristics of each of a plurality of semiconductor chips (not shown) formed on a wafer W, each of which has electrodes (not shown) formed on both surfaces. This wafer test system 9 includes a prober 10 and a tester 30.

The prober 10 brings the probe 25 into contact with a front surface electrode (not shown) formed on the surface of each semiconductor chip (not shown) on the wafer W, and also contacts a back surface electrode (not shown) formed on the back surface of each semiconductor chip. (illustrated) is brought into contact with a conductive support surface 16a of a wafer chuck 16, which will be described later. The tester 30 is electrically connected to the probe 25 and the support surface 16a, and tests the electrical characteristics of each semiconductor chip.

The prober 10 includes a base 11, a base 12, a Y stage 13, an X stage 14, a Zθ stage 15, a wafer chuck 16, a probe position detection camera 18, a probe height detector 20, and a height It includes adjustment mechanisms 21 and 27, a wafer alignment camera 19, a head stage 22, a card holder 23, a probe card 24, and a probe 25.

A substantially flat base 12 is fixed to the upper surface of the base 11. Note that a leg member may be used instead of the base 11, or the base 11 may be omitted.

A substantially flat Y stage 13 is supported on the upper surface of the base 12 via a Y moving section (not shown) so as to be movable in the Y-axis direction. The Y moving unit includes a guide rail provided on the upper surface of the base 12 and parallel to the Y axis, a slider provided on the lower surface of the Y stage 13 and engaged with the guide rail, and moves the Y stage 13 in the Y axis direction. A drive mechanism such as a motor is provided. By driving this Y moving unit, the Y stage 13, the X stage 14, the Zθ stage 15, etc., which will be described later, are integrally moved in the Y axis direction on the base 12.

A substantially flat X stage 14 is supported on the upper surface of the Y stage 13 via an X moving section (not shown) so as to be movable in the X-axis direction. The X moving unit includes a guide rail provided on the top surface of the Y stage 13 and parallel to the X axis, a slider provided on the bottom surface of the X stage 14 and engaged with the guide rail, and moves the X stage 14 in the X axis direction. and a drive mechanism such as a motor. By driving this X moving section, the X stage 14, the Zθ stage 15 (described later), etc. are integrally moved in the X-axis direction on the Y stage 13.

A Zθ stage 15 and height adjustment mechanisms 21 and 27 are provided on the upper surface of the X stage 14. Inside the Zθ stage 15, a Zθ moving section (not shown) is provided. Further, a wafer chuck 16 is held on the upper surface of the Zθ stage 15 via a Zθ moving section (not shown). The Zθ moving unit includes, for example, an elevating mechanism that can move the upper surface of the Zθ stage 15 in the Z-axis direction, and a rotation mechanism that rotates the upper surface around the Z-axis. Therefore, the Zθ moving unit moves the wafer chuck 16 held on the upper surface of the Zθ stage 15 in the Z-axis direction and rotates it around the Z-axis.

The wafer chuck 16 holds the wafer W from its back side. The wafer chuck 16 is supported by the Y stage 13, the X stage 14, and the Zθ stage 15, which have already been described, to be movable in the X, Y, and Z axes relative to the base 12, and is also rotatable around the Z axis. Supported. Thereby, the wafer W held by the wafer chuck 16 and the probe 25, which will be described later, can be moved relative to each other.

The support surface 16a of the wafer W, which is the upper surface of the wafer chuck 16, is plated with various metals such as aluminum plating or gold plating, and has electrical conductivity. This support surface 16a contacts the back electrode (not shown) of each semiconductor chip of the wafer W. This support surface 16a is connected to a tester 30 via a chuck lead wire 40 (see FIG. 2), which will be described later, and acts as a measurement electrode for this tester 30. As a result, depending on various measurement conditions during testing of each semiconductor chip (not shown) on the wafer W, voltage, current, etc. are applied to the back electrode of each semiconductor chip from the tester 30 via the support surface 16a, or Or it may be grounded.

The height adjustment mechanism 21 raises and lowers the probe position detection camera 18, which will be described later, in the Z-axis direction. Further, the height adjustment mechanism 27 raises and lowers the probe height detector 20, which will be described later, in the Z-axis direction. The height adjustment mechanisms 21 and 27 may be any known linear movement mechanism, such as a linear guide mechanism, a ball screw mechanism, or the like.

The head stage 22 constitutes, for example, a top plate of a housing (not shown) of the prober 10, and is supported above the wafer chuck 16 (wafer W) by a support (not shown) or the like. The head stage 22 is formed in a substantially annular shape, and a substantially annular card holder 23 that holds a probe card 24 is provided at the center thereof. That is, the head stage 22 holds the probe card 24 via the card holder 23.

The probe card 24 has a plurality of probes 25. These probes 25 are arranged on the probe card 24 in a pattern corresponding to the arrangement pattern of surface electrodes of each semiconductor chip (not shown) of the wafer W to be inspected.

The probe position detection camera 18 is attached to the height adjustment mechanism 21. The probe position detection camera 18 is, for example, a camera equipped with a needle alignment microscope, and photographs the probes 25 of the probe card 24 from below. Based on the image of the probe 25 taken by the probe position detection camera 18, the position of the probe 25 can be detected. Specifically, the XY coordinates of the tip position of the probe 25 are detected from the position coordinates of the probe position detection camera 18, and the Z coordinates of the tip position of the probe 25 are detected from the focal position of the probe position detection camera 18.

The wafer alignment camera 19 is supported by a support (not shown) provided on the base 12 and photographs a semiconductor chip (not shown) of the wafer W held by the wafer chuck 16 from above. Based on the image of the semiconductor chip taken by this wafer alignment camera 19, the positions of the electrodes of the semiconductor chip can be detected. Thereby, based on the information obtained by the wafer alignment camera 19 and the position information of the tip of the probe 25 obtained by the probe position detection camera 18, the distance between the probe 25 and the electrode of the semiconductor chip of the wafer W in the XY plane is determined. Dimensional alignment can be performed.

The probe height detector 20 is attached to the previously described height adjustment mechanism 27 on the X stage 14. The probe height detector 20 detects the height of the tip of the probe 25 from a reference plane that serves as a reference for the height of the probe position detection camera 18. The probe height detector 20 is a contact type detector, and detects the height of the tip of the probe 25 by physically touching the tip of the probe 25. Here, the reference plane is a plane that serves as a height reference for the entire prober 10, and is set arbitrarily (eg, the top surface of the X stage 14).

The height adjustment mechanism 21 described above adjusts the probe position detection camera 18 to a height that is a working distance away from the tip of the probe 25 based on the detection result of the height of the tip of the probe 25. This prevents the probe position detection camera 18 from being raised too high and colliding with the tip of the probe 25.

The tester 30 includes a tester main body 31 and a contact ring 32 provided on the tester main body 31. The probe card 24 is provided with terminals connected to each probe 25. The contact ring 32 has spring probes arranged in an arrangement pattern that allows contact with each terminal of the probe card 24.

The tester main body 31 is held relative to the prober 10 by a support mechanism (not shown). The tester main body 31 is electrically connected to a surface electrode of a semiconductor chip (not shown) via a probe card 24, a probe 25, etc., and is also electrically connected to a surface electrode of a semiconductor chip (not shown) via a chuck lead wire 40 (see FIG. 2), a support surface 16a, etc. It is electrically connected to the back electrode of the illustrated semiconductor chip. The tester main body 31 then tests the electrical characteristics of the semiconductor chip by applying current, voltage, or the like to the semiconductor chip.

[Chuck lead wire and additional circuit]
FIG. 2 is an explanatory diagram for explaining the chuck lead wire 40 and the additional circuit 42. As shown in FIG. 2, the chuck lead wire 40 corresponds to the wiring of the present invention, and electrically connects the support surface 16a and the tester 30 (tester main body 31). The chuck lead wire 40 has one end 40a that is electrically connected to the support surface 16a, and the other end 40b that is opposite to the one end 40a and that is electrically connected to a connector 44 that will be described later. It has an end portion 40b. Note that the type of chuck lead wire 40 (wiring) is not particularly limited.

The additional circuit 42 functions entirely as a continuity testing device of the present invention, and a portion thereof functions as a static eliminator of the present invention, and performs a continuity test (disconnection test) of the chuck lead wire 40, and also performs a continuity test (disconnection test) of the chuck lead wire 40. 16 static elimination (discharge) is performed. This additional circuit 42 includes a connector 44, a static elimination circuit 50 (a first relay 46 and a first resistor 48), an additional lead wire 52, a second relay 54, a second resistor 56, a power supply 58, and a detection circuit. 60.

The connector 44 is electrically connected to the other end 40b of the chuck lead wire 40, as described above. In addition to the other end 40b, the connector 44 is individually connected to the tester 30 and a first relay 46 that constitutes a static elimination circuit 50. Thereby, the support surface 16a and the tester 30 are electrically connected via the chuck lead wire 40 and the connector 44, and the support surface 16a and the static elimination circuit 50 (first relay 46) are electrically connected. .

The static elimination circuit 50 corresponds to the static elimination device of the present invention, and includes a first relay 46 electrically connected to the connector 44 (that is, the other end 40b), and a first relay 46 that is connected to the first relay 46 and grounded. A first resistor 48 is provided. In this embodiment, one first relay 46 of the static elimination circuit 50 corresponds to the first component of the present invention, and the other first resistor 48 corresponds to the second component of the present invention. As described above, the wafer chuck 16 is charged with electric charge (static electricity), and as a result, the wafer W on the wafer chuck 16 is also charged with electric charge. Therefore, the static elimination circuit 50 eliminates the charge (static electricity) charged on the wafer chuck 16.

The first relay 46 is in a closed state (connected state) in which the chuck lead wire 40 and the support surface 16a (hereinafter abbreviated as support surface 16a, etc.) and the first resistor 48 are electrically connected to each other. and an open state (non-connected state) in which the electrical connection between the two is released. Note that the type of first relay 46 is not particularly limited. Further, in this specification, switching the first relay 46 to the closed state is defined as "on", and conversely, switching to the open state is defined as "off". The on/off switching of the first relay 46 is controlled by a general control unit 62, which will be described later.

The first relay 46 is turned on when static electricity is removed from the wafer chuck 16 and during a continuity test of the chuck lead wire 40, which will be described later, and electrically connects the support surface 16a and the like to the first resistor 48. Further, the first relay 46 is turned off when testing the electrical characteristics of each semiconductor chip (not shown), and the electrical connection between the support surface 16a and the like and the first resistor 48 is released.

The first resistor 48 is a current limiting resistor that prevents the charge (static electricity) charged on the wafer chuck 16 from flowing all at once toward the ground side when the first relay 46 is turned on during static electricity removal from the wafer chuck 16. Yes, high resistance material is used. As a result, when the first relay 46 is turned on when static electricity is removed from the wafer chuck 16, the electric charge charged on the wafer chuck 16 can be gradually discharged to the ground side via the first resistor 48, and as a result, , the wafer chuck 16 is neutralized.

Next, the effects of the static elimination circuit 50 of this embodiment will be described in more detail by comparing the static elimination circuit 50 of this embodiment with the static elimination circuit 200 of a comparative example (see FIG. 3). Note that the present invention is not limited to the explanation of the following effects.

FIG. 3 is a schematic diagram of a static elimination circuit 200 of a comparative example. In addition, in the comparative example shown in FIG. 3, the same reference numerals are given to the same components as in the present embodiment in function or configuration, and the explanation thereof will be omitted. As shown in FIG. 3, in the static elimination circuit 200 of the comparative example, the first resistor 48 is first electrically connected to the connector 44, as disclosed in Japanese Patent Laid-Open No. 2003-218175 (Patent Document 2 above). A first relay 46 connected to the first resistor 48 and grounded is connected to the first resistor 48 .

In the static eliminator circuit 200 of the comparative example as well, by turning on the first relay 46, the charges accumulated on the wafer chuck 16 are grounded via the first resistor 48, similarly to the static eliminator circuit 50 of the present embodiment. It can be discharged gradually to the side.

However, in the static elimination circuit 200 of the comparative example, since the first resistor 48 is disposed between the wafer chuck 16 and the first relay 46, even when the first relay 46 is turned off, the support surface 16a etc. The connection with the first resistor 48 is maintained. On the other hand, since the first resistor 48 is a high-resistance element, leakage current may occur when the first relay 46 is turned off. When a leakage current is generated from the first resistor 48, this leakage current is mixed into the signal output from the back electrode (not shown) during the inspection of each semiconductor chip (not shown) on the wafer W, so that each semiconductor chip There is a risk that the test may be affected or each semiconductor chip may be adversely affected. Therefore, in order to accurately test each semiconductor chip, it is necessary for the wafer chuck 16 to be in a highly insulated state (not affected by external leakage current, etc.), and the wafer chuck 16 must have an extra Connecting parts is undesirable.

In contrast to the static elimination circuit 200 of the comparative example, in the static elimination circuit 50 of the present embodiment, as shown in FIG. A grounded first resistor 48 is electrically connected to the first relay 46 . Thereby, by turning off the first relay 46 when testing each semiconductor chip, the first resistor 48 can be separated from the support surface 16a and the like in the shortest possible time. As a result, leakage current caused by the static elimination circuit 50 added for static elimination can be minimized.

Returning to FIG. 2, the additional lead wire 52 corresponds to the additional wiring of the present invention, and one end portion 52a thereof is connected to the support surface 16a. Thereby, the chuck lead wire 40 and the additional lead wire 52 are electrically connected via the support surface 16a. Further, a second relay 54 is electrically connected to one end 52a of the additional lead wire 52 and the other end 52b on the opposite side. Note that the type of additional lead wire 52 (wiring) is not particularly limited. Further, in this embodiment, a portion of both the chuck lead wire 40 and the additional lead wire 52 are housed within the cable (registered trademark) bearer 64.

The second relay 54 corresponds to the third component of the present invention, and is in a closed state to electrically connect both a second resistor 56 and a power source 58, which will be described later, and the additional lead wire 52. (connected state) and an open state (non-connected state) in which the electrical connection between the two is released. Note that the type of second relay 54 is not particularly limited either. Further, in this specification, switching to the closed state of the second relay 54 is defined as "on", and conversely, switching to the open state is defined as "off". The on/off switching of the second relay 54 is controlled by a general control unit 62, which will be described later, similarly to the first relay 46.

The second relay 54 is turned on during a continuity test of the chuck lead wire 40, which will be described later, and electrically connects the second resistor 56 and power source 58 to the additional lead wire 52. Further, the second relay 54 is turned off when static electricity is removed from the wafer chuck 16 and when inspecting the electrical characteristics of each semiconductor chip (not shown), and the second relay 54 is turned off to connect the second resistor 56 and power source 58 to the additional lead wire 52. Disconnect.

The second resistor 56 corresponds to the fourth component of the present invention and is electrically connected to the second relay 54. This second resistor 56 is a current limiting resistor similar to the first resistor 48, and is made of a high resistance material. As will be described in detail later, the voltage (both-end voltage, potential difference) of the second resistor 56 is used to determine whether or not the chuck lead wire 40 is electrically connected (broken).

FIG. 4 is an explanatory diagram for explaining the current loop CR and the power supply 58. As shown in FIGS. 2 and 4, the power source 58 is connected to the second resistor 56 and grounded. Note that the power source 58 and the first resistor 48 described above are connected to the so-called frame ground (for example, connected to a ground electrode or a metal casing), so the power source 58 and the first resistor 48 are not electrically connected. There is. Therefore, the chuck lead wire 40, the first relay 46, the first resistor 48, the additional lead wire 52, the second relay 54, the second resistor 56, and the power source 58 constitute a current loop CR. Therefore, the second relay 54, the second resistor 56, and the power source 58 function as a current loop forming section of the present invention.

The power supply 58 supplies current (applies voltage) to the current loop CR during a continuity test of the chuck lead wire 40, which will be described later, that is, when both the first relay 46 and the second relay 54 are turned on. . As a result, when the chuck lead wire 40 is conductive (not disconnected), that is, when the current loop CR is configured, a current Is (minor current) flows through the current loop CR.

The detection circuit 60 corresponds to the voltage detection section of the present invention, and is a voltmeter that detects the voltage (both-end voltage, potential difference) of the second resistor 56. When both the first relay 46 and the second relay 54 are turned on and the chuck lead wire 40 is conductive, a current Is flows through the current loop CR described above. In this case, if the voltage V applied to the current loop CR by the power source 58, the resistance value of the first resistor 48 is R1, and the resistance value of the second resistor 56 is R2, then the second resistor 56 detected by the detection circuit 60 The detected voltage is “V×(R2/(R1+R2))”. Therefore, for example, when R1=R2, the detected voltage of the second resistor 56 is "V/2". Hereinafter, in order to prevent the explanation from becoming complicated, the explanation will be made assuming that "R1=R2".

On the other hand, even if both the first relay 46 and the second relay 54 are turned on, if the chuck lead wire 40 is disconnected, the current Is from the power source 58 will not flow through the current loop CR. . Therefore, in this case, the voltage detected by the detection circuit 60 is "V".

By referring to the voltage detected by the detection circuit 60 in this manner, it is possible to determine whether or not the current Is is flowing through the current loop CR, that is, whether or not the chuck lead wire 40 is electrically connected (whether there is any disconnection or not). The detection circuit 60 then outputs the voltage detection result of the second resistor 56 to the overall control section 62.

Conversely, when the conductivity of the chuck lead wire 40 is confirmed, the voltage detection result of the second resistor 56 by the detection circuit 60 can be used for self-diagnosis of the first relay 46 and the second relay 54.

For example, if the voltage detected by the detection circuit 60 is "V/2" when both the first relay 46 and the second relay 54 are turned on, both the first relay 46 and the second relay 54 are normal. It can be determined that there is. On the other hand, if the voltage detected by the detection circuit 60 is "V" when both the first relay 46 and the second relay 54 are turned on, at least one of the first relay 46 and the second relay 54 is actually turned on. is not turned on, that is, it can be determined that at least one of them is abnormal. Further, if the voltage detected by the detection circuit 60 is "V/2" when at least one of the first relay 46 and the second relay 54 is turned off, both the first relay 46 and the second relay 54 are turned off. Since it is actually turned on, it can be determined that at least one of the first relay 46 and the second relay 54 is abnormal.

FIG. 5 is a functional block diagram of the overall control unit 62 of the prober 10 (or the wafer test system 9, the same applies hereinafter). The overall control unit 62 is composed of various arithmetic units, processing units, memory, etc., including, for example, a CPU (Central Processing Unit) or an FPGA (field-programmable gate array), and controls the operation of each unit of the prober 10 in an integrated manner. In addition, in FIG. 5, among the plurality of functions of the overall control unit 62, only the functions related to static elimination of the wafer chuck 16 by the additional circuit 42, continuity test of the chuck lead wire 40, and self-diagnosis of each relay 46, 54 are shown. The functions shown in the figure and related to other control of the prober 10 such as inspection of the wafer W are well-known techniques and are therefore omitted from the figure.

The overall control unit 62 is connected to an operation unit 70 that receives various operation inputs, a display unit 72 that displays various displays, the aforementioned relays 46 and 54, a power supply 58, a detection circuit 60, and other parts of the prober 10. has been done. The overall control section 62 functions as an additional circuit control section 76, a determination section 80, and a self-diagnosis section 82 by executing a predetermined control program.

The additional circuit control unit 76 turns each relay 46, 54 on and off when the additional circuit 42 starts static electricity removal from the wafer chuck 16, conduction test of the chuck lead wire 40, and self-diagnosis of each relay 46, 54. Controls on/off of the power source 58. That is, the additional circuit control section 76 functions as a relay control section of the present invention.

Note that the static elimination, continuity test, and self-diagnosis by the additional circuit 42 are performed at an arbitrary timing when each semiconductor chip (not shown) is not being tested, that is, at a timing when the probe 25 is separated from the wafer W. Examples include the timing when the wafer chuck 16 is retracted downward by the Zθ stage 15, the timing when the wafer W is loaded or unloaded onto the wafer chuck 16, and the timing when the semiconductor chip is indexed. Note that static elimination, continuity testing, and self-diagnosis may be started in response to a start operation on the operation unit 70.

The additional circuit control unit 76 turns on only the first relay 46 at an arbitrary timing to perform static elimination or upon receiving an input of a static elimination start operation to the operation unit 70. Further, the additional circuit control unit 76 turns on both the relays 46 and 54 and turns on the power supply 58 at any timing when performing a continuity test or upon receiving an input of a continuity test start operation to the operation unit 70. let Further, the additional circuit control unit 76 turns each relay 46 and 54 on and off individually one or more times at the timing of executing a self-diagnosis or upon receiving an input of a self-diagnosis start operation to the operation unit 70, and turns on the power supply 58. let

When the continuity test is started, that is, when both the first relay 46 and the second relay 54 are turned on and the power supply 58 is turned on, the determination unit 80 determines whether the second resistor 56 is Based on the voltage detection result, it is determined whether the current Is is flowing through the current loop CR. As a result, the determination unit 80 can determine whether or not the chuck lead wire 40 is electrically connected. As described above, when the voltage of the second resistor 56 is "V/2", the determination unit 80 determines that the current Is is flowing through the current loop CR, and the chuck lead wire 40 is conductive. It is determined that the On the other hand, when the voltage of the second resistor 56 is "V", the determination unit 80 determines that the current Is is not flowing through the current loop CR, and determines that the chuck lead wire 40 is disconnected. .

Then, the determination section 80 outputs to the display section 72 whether or not the chuck lead wire 40 is electrically conductive. As a result, the display unit 72 displays whether or not the chuck lead wire 40 is electrically connected (whether or not it is disconnected). Note that the display unit 72 includes, in addition to a monitor that displays a screen (image display), a speaker that displays audio (audio output) and the like.

The self-diagnosis section 82 uses the voltage detection result of the second resistor 56 inputted from the detection circuit 60 when the self-diagnosis is being executed, that is, when the relays 46 and 54 are turned on and off and the power supply 58 is turned on. Based on this, self-diagnosis of each relay 46, 54 is performed. As described above, the self-diagnosis unit 82 detects whether both the relays 46 and 54 are turned on if the voltage detected by the detection circuit 60 is "V/2" when both the relays 46 and 54 are turned on. is determined to be normal, and if the detected voltage is "V", it is determined that at least one of the relays 46 and 54 is abnormal. Furthermore, if the voltage detected by the detection circuit 60 is "V/2" when at least one of the relays 46 and 54 is turned off, the self-diagnosis unit 82 determines that at least one of the relays 46 and 54 is abnormal. It is determined that

Then, the self-diagnosis section 82 outputs the self-diagnosis results of each relay 46 and 54 to the display section 72. As a result, the self-diagnosis results of each relay 46, 54 are displayed on the display section 72.

[Operation of additional circuit of this embodiment]
FIG. 6 is a flowchart illustrating the process of eliminating electricity from the wafer chuck 16, testing the continuity of the chuck lead wire 40, and self-diagnosing each relay 46, 54 by the additional circuit 42 configured as described above.

<Continuity test>
As shown in FIG. 6, the additional circuit control unit 76 controls each relay 46, 54 at an arbitrary timing to perform a continuity test or upon receiving an input of a continuity test start operation to the operation unit 70 (YES in step S1). (step S2), and the power source 58 is turned on (step S3). On the other hand, the detection circuit 60 starts detecting the voltage of the second resistor 56 when the power supply 58 is turned on, and outputs the voltage detection result of the second resistor 56 to the determination unit 80 (step S4).

When the voltage of the second resistor 56 is "V/2", the determination unit 80 determines that the current Is is flowing through the current loop CR, that is, determines that the chuck lead wire 40 is conductive ( Step S5). On the other hand, when the voltage of the second resistor 56 is "V", the determination unit 80 determines that the current Is is not flowing through the current loop CR, that is, determines that the chuck lead wire 40 is disconnected ( Step S5). The determination unit 80 then outputs the determination result to the display unit 72. As a result, the display unit 72 displays the determination result as to whether or not the chuck lead wire 40 is electrically conductive (step S6).

<Static electricity removal>
The additional circuit control unit 76 turns on the first relay 46 at an arbitrary timing to perform static elimination or upon receiving an input of a static elimination start operation to the operation unit 70 (NO in step S1, YES in step S7). S8). As a result, the charge on the wafer chuck 16 is discharged to the ground side via the first resistor 48, so that the wafer chuck 16 is neutralized.

<Self-diagnosis>
The additional circuit control unit 76 turns on the power supply at any timing when executing the self-diagnosis of each relay 46, 54, or upon receiving an input of a self-diagnosis start operation to the operation unit 70 (NO in both step S1 and step S7). 58 is turned on (step S9). Further, when the power supply 58 is turned on, the detection circuit 60 starts detecting the voltage of the second resistor 56, and outputs the voltage detection result to the self-diagnosis section 82 (step S10).

Next, the additional circuit control unit 76 individually turns on and off each relay 46, 54 one or more times (step S11). Then, while each relay 46, 54 is being turned on/off, the self-diagnosis unit 82 detects the voltage of each relay 46, 54 based on the voltage detection result of the second resistor 56 inputted from the detection circuit 60. A self-diagnosis is performed and the diagnosis result is output to the display section 72 (step S12). As a result, the self-diagnosis results of each relay 46, 54 are displayed on the display section 72 (step S13).

[Effects of this embodiment]
As described above, according to the additional circuit 42 of this embodiment, a current loop CR is formed by the additional lead wire 52 and the like, and whether or not the current Is flows through this current loop CR is determined by the second resistor 56 by the detection circuit 60. It is possible to determine whether or not the chuck lead wire 40 is electrically connected by simply detecting whether the voltage detection result is "V/2". This additional circuit 42 can be easily constructed by simply combining known relays 46, 54, resistors 48, 56, power supply 58, and detection circuit 60 (voltmeter, etc.). As a result, the presence or absence of continuity of the chuck lead wire 40 can be automatically and easily tested.

Further, in the static elimination circuit 50 of this embodiment, the first relay 46 is first electrically connected to the connector 44, and the first resistor 48, which is grounded, is electrically connected to the first relay 46. Therefore, by turning off the first relay 46 when testing each semiconductor chip, the first resistor 48 can be separated from the chuck lead wire 40 and the like in the shortest possible time. As a result, the leakage current caused by the static elimination circuit 50 can be suppressed to a minimum, so that the leakage current does not affect the inspection of each semiconductor chip (not shown) on the wafer W or adversely affect each semiconductor chip. This prevents

[others]
In the above embodiment, the second relay 54, the second resistor 56, and the power source 58 are connected in this order to the additional lead wire 52 (the other end 52b), but depending on whether the second relay 54 is turned on or off, As long as the supply of the current Is to the current loop CR can be turned on and off, the order is not particularly limited. Further, in the above embodiment, in order to minimize the leakage current caused by the static elimination circuit 50, the first relay 46 and the first resistor 48 are connected to the connector 44 in this order, but it is necessary to take leakage current into consideration. If not, the first resistor 48 and the first relay 46 may be connected to the connector 44 in this order.

In the above embodiment, each of the first resistor 48 and the second resistor 56 is a single resistor. (including electronic components other than resistors).

In the embodiment described above, the voltage of the second resistor 56 is detected by the detection circuit 60, but the voltage of the first resistor 48 is detected by the detection circuit 60, and the determination unit 80 makes a determination and self-diagnosis based on this voltage detection result. Diagnosis by the unit 82 may also be performed.

In the embodiment described above, the power source 58 is connected to the additional lead wire 52 side, but the power source 58 may be connected to the static elimination circuit 50.

In the above embodiment, the case where the tester 30 is connected to the connector 44 (the other end 40b of the chuck lead wire 40) in addition to the static elimination circuit 50 has been described as an example. Alternatively, the present invention can also be applied when a measuring device or the like is connected. Further, when the purpose is only to eliminate static electricity from the wafer chuck 16, only the static elimination circuit 50 may be connected to the connector 44.

9...Wafer test system,
10...Prober,
16...Wafer chuck,
16a...support surface,
30...Tester,
40...Chuck lead wire,
42...Additional circuit,
44...Connector,
46...first relay,
48...first resistor,
50... Static elimination circuit,
52...Additional lead wire,
54...Second relay,
56...Second resistance,
58...Power supply,
60...detection circuit,
62...General control unit,
80...judgment section,
82...Self-diagnosis section

Claims (2)

In a continuity testing device for wiring that is electrically connected to a conductive support surface of a wafer chuck of a prober that contacts a back electrode of a semiconductor chip formed on the back surface of a wafer,
a relay connected to the other end opposite to one end of the wiring connected to the support surface and grounded;
additional wiring connected to the support surface;
a current loop forming unit connected to the additional wiring, which is provided with at least a power source and forms a current loop including at least the wiring, the additional wiring, the relay, and the power source;
a determination unit that determines whether or not a current from the power source flows through the current loop;
A continuity testing device comprising: A wafer chuck that holds a wafer on which a plurality of semiconductor chips are formed, the wafer chuck having a conductive support surface that contacts a back electrode of the semiconductor chip formed on the back surface of the wafer;
a probe that contacts a surface electrode of the semiconductor chip formed on the surface of the wafer;
A continuity testing device according to claim 1;
A prober equipped with.

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