201244061 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種金氧半場效電晶體佈局結構，特 別關於一種具有較高有效通道寬度及較高元件密度之 金氧半場效電晶體佈局結構，可提升傳統佈局電路之元 件密度及提升其有效通道寬度，達到降低成本及更高功 率操作之目的。 【先前技術】 近年來’金氧半場效電晶體（Metal 〇xide Semiconductor，MOS)都是以元件尺寸縮小來達到增加 凡件速度及驅動電流的目的，但是根據ITRS r〇admap， 利用元件尺寸縮小以提升元件操作速度的方法趨近極 限。因此，藉由元件尺寸縮小來達到性能的改善，顯的 越來越不容易。 此外，具有大線寬的金氧半場效電晶體（P〇werM〇s) 也廣泛地被應用作為電源管理應用的電源開關。不過， 此類金氧半場效電晶體的源極與沒極的過長連接導線 會導致一些缺陷或問題，例如連接導線的嚴重電壓降。 此外，由於考慮到積集度的因素，功率元件的晶胞間距 必須越小越好，因此金氧半場效電晶體的源極與汲極的 金屬連接導線寬度勢必受限。源極與汲極的金屬連接導 線的長度也因電致遷移（Electron Migration)的問題而受 限，尤其是在金屬連接導線寬度受限時。因此傳統高功 201244061 率金氧半場效電晶體很難兼具大電流功能與高積集度 佈局兩種性質。 參照美國專利公告號第7，132,717號’標題為具有低 輸出電阻與高電流限制的功率金屬氧化物半導體電晶 體佈局（Power Metal Oxide Semiconductor Transistor201244061 VI. Description of the Invention: [Technical Field] The present invention relates to a gold oxide half field effect transistor layout structure, in particular to a gold oxide half field effect transistor layout having a higher effective channel width and a higher component density. The structure can increase the component density of the traditional layout circuit and increase the effective channel width, thereby achieving the purpose of reducing cost and higher power operation. [Prior Art] In recent years, 'Metal 〇xide Semiconductor (MOS) has been designed to reduce the speed of parts and drive current by reducing the size of components, but according to ITRS r〇admap, the size of components is reduced. The method of increasing the operating speed of the component approaches the limit. Therefore, it is becoming less and less difficult to achieve performance improvement by reducing the size of components. In addition, gold oxide half field effect transistors (P〇werM〇s) with large linewidths are also widely used as power switches for power management applications. However, the source of this type of MOS field-effect transistor and the extremely long connecting wires of the poles cause some defects or problems, such as a severe voltage drop of the connecting wires. In addition, since the cell pitch of the power element must be as small as possible in consideration of the degree of integration, the metal connection wire width of the source and the drain of the gold oxide half field effect transistor is bound to be limited. The length of the metal-to-drain metal connection wires is also limited by the problem of Electron Migration, especially when the width of the metal connection wires is limited. Therefore, the traditional high-power 201244061 rate gold-oxygen half-field effect transistor is difficult to combine both high-current function and high-accumulation layout. Refer to U.S. Patent Publication No. 7,132,717, entitled Power Metal Oxide Semiconductor Arrays with Low Output Resistance and High Current Limit (Power Metal Oxide Semiconductor Transistor)
Layout with Lower Output Resistance and High Current Limit)，其主要揭示一種功率金屬氧化物半導體電晶體 佈局，特別關於一種使用網狀連接導線或一平面化連接 導線，然而該案於源極/汲極導線連接時，並未清楚揭示 其靜電防護（Electrostatic Discharge，ESD)佈局規則。 現請參考第1(A)圖，其顯示習之技術之金氧半場效 電晶體佈局結構100，其係以金氧半場效電晶體佈局陣 列110所組成’其中更包含：源極12〇、汲極13〇、閘極 140、電aa體150、連接源極導線16〇及連接及極導線 170。 現凊參考第1 (B)圖，其顯示習之技術之金氧半場效 電晶體佈局結構之汲極與源極連接圖。其中連接源極導 線160與連接汲極導線17〇之連接方式皆採取斜線連 接。一般而言’其具有（1)於源極120、汲極130之角落 是否順利連接（2)連線電路不對稱之問題。 因此，有必要提出一種具有較高有效通道寬度及較高 元件密度之金氧半場效電晶體佈局結構以解決上述所 201244061 提及之問題。 【發明内容】 本發明之主要目的在於提供一種金氧半場效電晶體 佈局結構，可詩CMQS製財，以具有較高有效通道 寬度及較高元件密度。 為達^述目的，本發明提供一種具有較高有效通道寬 度及較同7C件密度之金氧半場效電晶體佈局結構，其包 S·—基板；一具有正十字圖案之共汲極區；複數個具 有格子圖案之共源極區；—具有正十字圖案之共源極 區，複數個具有格子®案之共沒極區；以及複數個共閘 極區該具有正十字圖案之共沒極區，形成於該基板 上，忒複數個具有格子圖案之共源極區，係配置於該具 有正十字圖案之共汲極區之四個角落，形成於該基板 上，。亥具有正十字圖案之共源極區，形成於該基板上； 該複數個具有格子圖案之共汲極區，係配置於該具有正 十子圖案之共汲極區之四個角落，形成於該基板上；以 及"亥複數個共閘極區，係配置於該具有正十字圖案之共 汲極區與複數個具有格子圖案之共源極區、該具有正十 字圖案之共源極區與該複數個具有格子圖案之共汲極 區以及該複數個具有格子圖案之共汲極區與該複數個 具有格子圖案之共源極區之間，形成於該基板上。 本發明所揭示之具有較高有效通道寬度及較高元件 201244061 '密度之金氧半場效電晶體佈局結構將具有以下之功效: 1.利用具有正十字圖案之共汲極區與複數個具有 格子圖案之共汲極區、具有正十字圖案之共源極 區與稷數個具有格子圖案之共源極區所形成之 具有正十字圖案共沒極區與正十字圖案共源極 之混成式陣列，其可提升傳統饰局電路之元件密 度及提升其有效通道寬度，以達降低成本及更高 功率操作之目的。 2·與傳統佈局電路比較，於相同面積下，其可提升 約一倍之電晶體數量。 為讓本發明之上述和其他目的、特徵、和優點能更 :月顯易懂，下文特舉數個較佳實施例，並配合所附圖 式，作詳細說明如下。 【實施方式】 雖然本發明可表現為不同形式之實施例，但附圖所 :及於下文中說明者料本發明可之較佳實施例，並 =解本文所揭示者係考量為本發明之—範例，且並非 =用以將本發明限制於_及/或所描述之特定實施 7 201244061 構示意圖。其包含：一基板；一具有正十字圖案之共汲 極& 220，複數個具有格子圖案之共源極區231 ; 一且 有正十字圖案之共源極區230 ;複數個具有格子圖案之 共及極區221，以及複數個共閘極區240。具有正十字 圖案之共汲極區220，形成於該基板上；複數個具有格 子圖案之共源極區231，係配置於該具有正十字圖案之 共汲極區220之四個角落，形成於該基板上；具有正十 子圖案之共源極區230 ’形成於該基板上；複數個具有 格子圖案之共汲極區221，係配置於該具有正十字圖案 之共汲極區221之四個角落，形成於該基板上；以及該 複數個共閘極區240，係配置於該具有正十字圖案之共 汲極區220與複數個具有格子圖案之共源極區231、具 有正十字圖案之共源極區230與複數個具有格子圖案之 八/及極區221以及複數個具有格子圖案之共沒極區工 與複數個具有格子圖案之共源極區之間23丨，形成於該 基板上。其格子圖案可為矩形、正方形及菱形之一。 需注意的是，其中具有正十字圖案之共汲極區 22〇、複數個具有格子圖案之共源極區23丨與複數個共 閘極區240可形成具有正十字圖案共汲極區之網格 八有正十子圖案之共源極區2 3 〇、複數個具有格子 圖案之共汲極區221與複數個共閘極區24〇可形成具有 正十字圖案共源極區之網格29〇。而具有正十字圖案共 201244061 汲極區之網格280係配置於任兩個相鄰之具有正十字圖 案共源極區之網格290之間1而形成具有正十字圖案 共汲極區與正十㈣案共源極之混成式陣歹U 2ι〇。此 外，具有正十字圖案共汲極區之網格28〇與具有正十字 圖案共源極區之網格29〇之間為複數個共間極區24〇。 般而δ，本發明之之具有較高有效通道寬度及較 高元件密度之金氧半場效電晶體佈局結構2〇〇，其可實 現於藍寶石基板、㈣板、_化鎵基板、絕緣層上覆石夕 基板、矽鍺基板及玻璃基板上。而具有正十字圖案共汲 極區與正十字圖案共源極之混成式陣列21〇可被實現於 〇.35μηι、〇.25卿、〇.18μιη、〇13_、9〇請、45nm 或更 先進之製程中。 現靖參考第2(B)圖，其顯示本發明之金氧半場效電 晶體佈局結構之汲極連接圖。其中，任兩個相鄰之具有 正十字圖案共汲極區之網格280與具有正十字圖案共源 極區之網格29G分別包含之具有正十字圖案之共沒極區 220與複數個具有格子圖案之共汲極區221、複數個具 有格子圖案之共汲極區221 <間係以一第一網狀導線 260連接。 見明 > 考第2(C)圖，其顯示本發明之金氧半場效電 晶體佈局結構之源極連接圖。其中，任兩個相鄰之具有 正十字圖案共源極區之網格29〇與具有正十字圖案共汲 9 201244061 極區之網格280分別包含之該具有正十字圖案之共源極 區230與複數個具有格子圖案之共源極區231、複數個 具有格子圖案之共源極區231之間係以—帛二網狀_ 270連接。一般而言’此處所使用第-網狀導線260與 第二網狀導線270為銅金屬。亦即，本發明之具有較高 有效通道寬度及較高元件密度之金氧半場效電晶體皆 為採用並聯之排列方式。 現請再次參考第KA)圖與第2(A)圖，其電晶體15〇 與電晶體250之數量，於單位面積下，使用具有正十字 圖案共沒極區與正十字圖案共源極之混成式陣列21〇之 電晶體數量約可提升一倍。 —於一實施例中具有正十字圖案共汲極區與正 十子圖案共源極之混成式陣列21〇為3χ3陣列，亦即 八中I έ 5組具有正十字圖案共源極區之網格“ο及4 組具有正十字圖案共沒極區之網格28G。本發明之金氧 半場效電晶體數量可達72顆電晶體。 上f上所述，本發明之一種具有較高有效通道寬度 及孝乂问7G件密度之金氧半場效電晶體佈局結構將具有 以下之功效： 用/、有正十子圖案之共汲極區與複數個具有 格子圖案之共沒極區、具有正十字圖案之共源極 區與複數個具有格子圖案之共源極區形成之呈 J0 201244061 有正十字圖案共沒極區與正十字圖案共源極之 混成式陣列，其可提升傳統佈局電路之元件密度 及提升其有效通道寬度，以達降低成本及更高功 率操作之目的。 2.與傳統佈局電路比較，於相同面積下，其可提升 約一倍之電晶體數量。 雖然本發明已以前述較佳實施例揭示，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發 明之精神和範圍内，當可作各種之更動與修改。如上 述的解釋，都可以作各型式的修正與變化，而不會破 壞此創作的精神。因此本發明之保護範圍當視後附之 申請專利範圍所界定者為準。 【圖式簡單說明】 第1 (A)圖係為習之技術之金氧半場效電晶體佈局結構； 第1(B)圖係為習之技術之金氧半場效電晶體佈局結構 之没極與源極連接圖； 第2(A)圖係為本發明之具有較高有效通道寬度及較高 元件也度之金氧半場效電晶體佈局結構示意圖； 第2(B)圖係為本發明之金氧半場效電晶體佈局結構之 沒極連接圖；以及 第2(C)圖係為本發明之金氧半場效電晶體佈局結構之 201244061 汲極連接圖。 【主要元件符號說明】 1 〇〇金氧半場效電晶體佈局結構 110金氧半場效電晶體佈局陣列 12 0源極 14 0間極 150電晶體 160連接源極導線 170連接汲極導線 200具有較高有效通道寬度及較高元件密度之金氧 半場效電晶體佈局結構 210具有正十字圖案共汲極區與正十字圖案共源極 之混成式陣列 220具有正十字圖案之共汲極區 221複數個具有格子圖案之共汲極區 230具有正十字圖案之共源極區 231複數個具有格子圖案之共源極區 240複數個共閘極區 250電晶體 260第一網狀導線 270第二網狀導線 12 201244061 _ 280具有正十字圖案共汲極區之網格 290具有正十字圖案共源極區之網格 13Layout with Lower Output Resistance and High Current Limit), which mainly discloses a power metal oxide semiconductor transistor layout, in particular, a use of a mesh connecting wire or a planar connecting wire, but the case is connected to the source/drain wire At the time, the Electrostatic Discharge (ESD) layout rules were not clearly revealed. Please refer to FIG. 1(A), which shows a gold-oxygen half-field effect transistor layout structure 100 of the prior art, which is composed of a gold-oxygen half-field effect transistor layout array 110, which further includes: a source of 12 〇, The drain 13 〇, the gate 140, the electrical aa body 150, the connection source lead 16 〇 and the connection and pole lead 170. Referring now to Figure 1 (B), it shows the connection diagram of the drain and source of the gold-oxygen half-field transistor layout structure of the technology. The connection mode between the connection source wire 160 and the connection drain wire 17〇 is slanted. In general, it has the problem of (1) whether the corners of the source 120 and the drain 130 are smoothly connected, and (2) the asymmetry of the wiring circuit. Therefore, it is necessary to propose a gold oxide half field effect transistor layout structure having a higher effective channel width and a higher element density to solve the above-mentioned problems mentioned in 201244061. SUMMARY OF THE INVENTION The main object of the present invention is to provide a gold oxide half field effect transistor layout structure, which can be made by poetry CMQS to have a higher effective channel width and a higher component density. For the purpose of the present invention, the present invention provides a gold oxide half field effect transistor layout structure having a higher effective channel width and a density of the same 7C member, which comprises a S·-substrate; a common drain region having a positive cross pattern; a plurality of common source regions having a lattice pattern; a common source region having a positive cross pattern, a plurality of common pole regions having a lattice pattern; and a plurality of common gate regions having a common cross pattern The region is formed on the substrate, and a plurality of common source regions having a lattice pattern are disposed on the substrate at four corners of the common drain region having the positive cross pattern. a common source region having a positive cross pattern formed on the substrate; the plurality of common drain regions having a lattice pattern disposed in the four corners of the common drain region having the positive ten sub-pattern, formed in And a plurality of common gate regions arranged in the common cross region having a positive cross pattern and a plurality of common source regions having a lattice pattern, the common source regions having a positive cross pattern And forming a plurality of common drain regions having a lattice pattern and the plurality of common drain regions having a lattice pattern and the plurality of common source regions having a lattice pattern formed on the substrate. The gold oxide half field effect transistor layout structure with higher effective channel width and higher element 201244061 'density disclosed by the invention has the following effects: 1. Using a common drain region with a positive cross pattern and a plurality of lattices a common ytterbium region of a pattern, a common source region having a positive cross pattern, and a plurality of fused arrays having a positive cross pattern common dipole region and a positive cross pattern common source formed by a plurality of common source regions having a lattice pattern It can improve the component density of traditional decorative circuits and increase the effective channel width for the purpose of reducing cost and higher power operation. 2. Compared with the traditional layout circuit, it can increase the number of transistors by about twice in the same area. The above and other objects, features, and advantages of the present invention will become more apparent from the accompanying drawings. The present invention may be embodied in various forms, and the drawings and the following description of the preferred embodiments of the present invention are intended to be considered as - Examples, and not = to limit the invention to _ and/or to the specific implementation described in the 2012. The method comprises: a substrate; a common dipole & 220 having a positive cross pattern; a plurality of common source regions 231 having a lattice pattern; a common source region 230 having a positive cross pattern; and a plurality of lattice patterns The common pole region 221 and the plurality of common gate regions 240. A common drain region 220 having a positive cross pattern is formed on the substrate; a plurality of common source regions 231 having a lattice pattern are disposed in the four corners of the common drain region 220 having the positive cross pattern, and are formed on On the substrate, a common source region 230 ′ having a positive ten sub-pattern is formed on the substrate; a plurality of common drain regions 221 having a lattice pattern are disposed on the common buck region 221 having the positive cross pattern a plurality of corners formed on the substrate; and the plurality of common gate regions 240 are disposed in the common drain region 220 having a positive cross pattern and a plurality of common source regions 231 having a lattice pattern, having a positive cross pattern The common source region 230 is formed between the plurality of octapole/pole regions 221 having a lattice pattern and a plurality of common immersion regions having a lattice pattern and a plurality of common source regions having a lattice pattern. On the substrate. The lattice pattern may be one of a rectangle, a square, and a diamond. It should be noted that a common drain region 22 正 having a positive cross pattern, a plurality of common source regions 23 具有 having a lattice pattern, and a plurality of common gate regions 240 may form a network having a positive cross pattern and a common drain region. Grid eight has a common source region of the positive ten sub-pattern 2 3 〇, a plurality of conjugated pole regions 221 with a grid pattern and a plurality of common gate regions 24 〇 can form a grid with a common cross pattern common source region 29 Hey. A grid 280 having a positive cross pattern of a total of 201244061 bungee regions is disposed between any two adjacent grids 290 having a positive cross pattern common source region 1 to form a positive cross pattern with a common drain region and positive The ten (four) case has a common source of mixed-type U 2ι〇. In addition, a grid 28〇 having a positive cross pattern common drain region and a grid 29〇 having a positive cross pattern common source region are a plurality of common interpole regions 24〇. Generally, δ, the present invention has a higher effective channel width and a higher element density of the metal oxide half field effect transistor layout structure 2, which can be realized on a sapphire substrate, a (four) plate, a gallium substrate, an insulating layer On the stone-covered substrate, the ruthenium substrate and the glass substrate. The hybrid array 21 with a positive cross pattern and a positive cross pattern can be realized in 〇.35μηι, 〇.25 〇, 〇.18μιη, 〇13_, 〇 〇, 45nm or more advanced In the process. Reference is made to Fig. 2(B) which shows a diagram of the connection of the gate of the gold oxide half field effect transistor layout structure of the present invention. Wherein, any two adjacent grids 280 having a positive cross pattern common drain region and a grid 29G having a positive cross pattern common source region respectively include a common non-polar region 220 having a positive cross pattern and a plurality of The common drain region 221 of the lattice pattern and the plurality of common drain regions 221 < with a lattice pattern are connected by a first mesh wire 260. See Fig. 2(C), which shows the source connection diagram of the gold oxide half field effect transistor layout structure of the present invention. Wherein, any two adjacent grids 29 具有 having a positive cross pattern common source region and a grid 280 having a positive cross pattern 汲 9 201244061 polar regions respectively include the common source region 230 having a positive cross pattern A plurality of common source regions 231 having a lattice pattern and a plurality of common source regions 231 having a lattice pattern are connected by a network _ 270. Generally, the first mesh wire 260 and the second mesh wire 270 used herein are copper metal. That is, the gold oxide half field effect transistors of the present invention having a higher effective channel width and a higher element density are arranged in parallel. Please refer again to the KA) and 2(A) diagrams, the number of the transistor 15〇 and the transistor 250, and the unit area, using a common cross pattern with a positive cross pattern and a positive cross pattern The number of transistors in the hybrid array 21 can be doubled. In an embodiment, the hybrid array 21 having a positive cross pattern and a common source of the positive tenth pattern is a 3χ3 array, that is, a group of eight middle I έ 5 groups having a positive cross pattern common source region The grid "G" and "4" have a grid 28G with a positive cross pattern and a total immersion region. The number of the gold oxide half field effect transistors of the present invention can reach 72 transistors. As described above, one of the present invention is more effective. The width of the channel and the layout of the gold-oxygen half-field effect transistor of the 7G piece density will have the following effects: With /, the common X-pole region with a positive ten-sub-pattern and a plurality of common non-polar regions with a lattice pattern, The common source region of the positive cross pattern and the plurality of common source regions having the lattice pattern are formed by J0 201244061. A hybrid array having a positive cross pattern and a common cross source common source, which can enhance the conventional layout circuit. The component density and the effective channel width are increased to achieve cost reduction and higher power operation. 2. Compared with the conventional layout circuit, it can increase the number of transistors by about twice in the same area. before The preferred embodiments are not intended to limit the invention, and various modifications and changes can be made without departing from the spirit and scope of the invention. Modifications and changes of the type without damaging the spirit of the creation. Therefore, the scope of protection of the present invention is defined by the scope of the appended patent application. [Simplified illustration] The first (A) diagram is a habit. The gold-oxygen half-field effect transistor layout structure of the technology; the first (B) diagram is the connection diagram of the dipole and source of the gold-oxygen half-field effect transistor layout structure of the technology; the second (A) diagram is The schematic diagram of the gold oxide half field effect transistor layout structure with higher effective channel width and higher component degree; the second (B) diagram is the electrodeless connection diagram of the gold oxide half field effect transistor layout structure of the invention; And the second (C) diagram is the 201244061 dipole connection diagram of the gold oxide half field effect transistor layout structure of the present invention. [Main component symbol description] 1 〇〇 gold oxygen half field effect transistor layout structure 110 gold oxygen half field effect electricity Crystal layout array 12 0 source 14 0 pole 150 transistor 160 is connected to the source wire 170 to connect the drain wire 200. The gold oxide half field effect transistor layout structure 210 having a higher effective channel width and a higher component density has a positive cross pattern and a positive cross region and a positive cross. The patterned common source hybrid array 220 has a positive cross pattern of the common drain region 221, a plurality of common drain regions 230 having a lattice pattern, a common source region 231 having a positive cross pattern, and a plurality of common source regions having a lattice pattern. 240 a plurality of common gate regions 250 transistors 260 first mesh wires 270 second mesh wires 12 201244061 _ 280 grids with positive cross pattern common drain regions 290 with positive cross pattern common source regions 13