TWI682544B - Semiconductor element structure - Google Patents

Abstract

The invention provides a semiconductor device structure including a substrate having a source region, a channel region, a drift region and a drain region, the channel region is located between the source region and the drift region, so as to separate the source region and drift by the channel region Region, the drain region is located on the other side of the drift region, the first gate is located on the substrate, and is located on the source region, the channel region and the drift region, used to connect the source region and the drift region, auxiliary gate The pole is located on the substrate and on the drift region to increase the withstand voltage of the drift region. The structure of the present invention can reduce the length of the drift region of the device and improve the breakdown voltage of the device.

Description

Semiconductor element structure

The invention relates to a semiconductor element structure, especially a semiconductor element structure with auxiliary gate.

Semiconductor devices have been widely used in applications of various electronic products, such as personal computers, tablet computers, smart phones, digital cameras, or other various electronic devices. The structure of semiconductor devices is usually deposited by sequential deposition on a substrate The insulating layer or dielectric layer material, the conductive layer material, the semiconductor layer material, etc., and then using the lithography process to pattern the various material layers formed to form semiconductor circuit parts and components on the substrate.

For example, referring to the first figure, a semiconductor device structure 10 includes a substrate 12 having a source region 14, a drain region 16, a channel region 18, and a drift region 20 having an insulating layer 21 thereon, and A gate electrode 22 is provided on the insulating layer 21 of the channel region 18 to connect the source region 14 and the drift region 20. When the gate 22 is very short, or even the voltage of the drain region 16 is too large, current will easily flow from the drain region 16 to the source region through the substrate 12 that is not controlled by the channel region 18 or the gate 22 14. Leakage is formed to reduce the breakdown voltage of the device, and it is easy to form a short channel effect, and the empty regions of the source region 14 and the drift region 20 are easily connected together to become a leakable channel. In addition, the drift region 20 is used to reduce the electric field intensity flowing from the drain region 16 to the source region 14 to reduce the voltage that the channel region 18 is subjected to.

Therefore, in the design of semiconductor device structures, in order to improve the problem of structural design, many different semiconductor device structures have been introduced, such as FinField-Effect Transistor (FinFET), which is a complementary metal oxide semiconductor The gate length of the crystal can be less than 25 nanometers, and it is expected to be further reduced in the future. As a result, the future chip design can design the supercomputer to be the size of a nail. In the traditional transistor structure, the gate that controls the current flow can only be at the gate. One side of the electrode controls the turning on and off of the transistor channel. In the FinFET architecture, the gate is a fin-like structure, which can control the turning on and off of the channel on both sides of the transistor channel. Improve the control ability of the transistor channel and reduce the leakage current, at the same time can also greatly shorten the gate length of the transistor.

However, the inventor of the present invention is different from the conventional semiconductor device structure. After careful R&D and design, a device structure that is different from the past and has the ability to solve problems is also introduced.

The main object of the present invention is to provide a semiconductor device structure. The semiconductor device structure using an auxiliary gate can shorten the length of the drift region of the device and can effectively improve the breakdown voltage of the device.

Another object of the present invention is to provide a semiconductor device structure. When the effective width of the drain (including the drift region) is sufficiently narrow, it can be covered by the auxiliary gate, so that the drift region of the drain can be completely depleted. There will be leakage, and the breakdown voltage can be improved.

In order to achieve the above object, the present invention provides a semiconductor device structure including a substrate having a source region, a channel region, a drift region and a drain region, the channel region is located between the source region and the drift region, The channel region separates the source region and the drift region, the drain region is located on the other side of the drift region, a gate is located on the substrate and is located on the source region, the channel region and the drift region for connecting the source In the pole region and the drift region, an auxiliary gate is located on the substrate and on the drift region, to increase the withstand voltage of the drift region.

In the present invention, the drift region is N-type well doped with N-type impurities or has a low N-type doping concentration.

In the present invention, the source region and the drain region are doped with N+ impurities.

In the present invention, the length of the drift region may be 3 microns.

In the present invention, the length of the auxiliary gate may be 0.5 microns.

In the present invention, when the voltage of the drift region and the channel region is less than 60 volts, the length of the drift region is 0.5-6 microns, and the length of the channel region is 0.3-1.2 microns; the drift region and the channel region drift when the voltage is less than 600 volts The length of the area is 6~40 microns, and the length of the channel area is 1~5 microns; when the voltage of the drift area and the channel area is greater than 600 volts, the length of the drift area is greater than 40 microns, and the length of the channel area is greater than 5 microns.

The following detailed description will be made with specific embodiments and accompanying drawings to make it easier to understand the purpose, technical content, features, and effects of the present invention.

The present invention is different from the conventional semiconductor device structure. A semiconductor device structure with an auxiliary gate is introduced. A gate is mainly added to the drift region, thereby reducing the length of the drift region and effectively improving the breakdown voltage.

First, please refer to the second figure of the present invention, a semiconductor device structure 30 includes a substrate 32, a first gate 34 and an auxiliary gate 36, the substrate 32 has a source region 322, a channel region 324, A drift region 326 and a drain region 328, the channel region 324 is located between the source region 322 and the drift region 326, and the drain region 328 is located in the drift region by the channel region 324 separating the source region 322 and the drift region 326 The other side of 326; the first gate 34 is located on the substrate 32, and is located on the source region 322, the channel region 324 and the drift region 326, for connecting the source region 322 and the drift region 326, and the first gate There is also a first insulating layer 35 between the electrode 34 and the source region 322, the channel region 324 and the drift region 326; the auxiliary gate 36 is located on the substrate 32, and is located on the drift region 326, the auxiliary gate 36 and the drift region There is also a second insulating layer 37 between 326.

Following the upper stage, in this embodiment, the drift region 326 is an N-well doped with N-type impurities (N-Well) or a low N-type doping concentration, and the source region 322 and the drain region 328 are doped with N+ impurities The length of the drift region 326 is 3 microns (μm), and the length of the auxiliary gate 36 is 0.5 microns, but the invention is not limited thereto. In addition, the concentration of N+ impurities can be 1.0 × 10 ²⁰ m ^-3 , the concentration of N-type impurities can be 3.0 × 10 ¹⁶ m ^-3 , and the substrate 32 can be doped with P-type impurities, the concentration of which is 1.0 × 10 ¹⁶ m ^-3 , a P-well with a concentration of 1.0 × 10 ¹⁷ m ^-3 can be doped in the source region 322.

After describing the structure of the semiconductor device of the present invention, the operation mode of the present invention will be described successively. Please also refer to the third diagram of the present invention. The first voltage V1 can enter through the drain region 328. The first voltage in this embodiment V1 is a voltage of 5 volts (V). The first gate 34 can be used as a control switch via a pressurized voltage. When a positive voltage is applied to the first gate 34, the channel region 324 can be turned on to make the first voltage V1 reaches the source region 322 from the drift region 326 under the first gate 34 via the channel region 324. At this time, the first voltage V1 will be affected by the resistance in the drift region 326, causing the voltage value to drop. The drift region 326 below the first gate 34 forms the second voltage V2. In this embodiment, the second voltage V2 is It is 3 volts, so a voltage drop of about 2 volts will form through the drift region 326. If the auxiliary gate 36 on the drift region 326 is grounded, and the presence of the auxiliary gate 36 further generates a fully depletion region in the drift region 326 under the auxiliary gate 36, then this region can withstand more Because of the voltage drop, the length of the shorter drift region 326 can be used to withstand the same voltage drop or maintain the same length, but can withstand a higher breakdown voltage. In other words, the meaning is the drift region 326 of the present invention. Because the auxiliary gate 36 is provided thereon, the space for processing the voltage drop will be much shorter than the conventional drift region length. After the stepped-down second voltage V2 is formed, it will again reach the source region 322 from the channel region 324, thereby improving the breakdown voltage.

In addition, please refer to the fourth and fourth b diagrams of the present invention. The fourth a diagram is a tested electric field intensity distribution diagram of a conventional semiconductor device structure, and the fourth b diagram is the invention The electric field strength distribution diagram, as can be clearly seen from the fourth a and the fourth b diagrams, the electric field strength distribution of the present invention is also superior to the conventional technology. The present invention thus reduces the electric field strength in the drift region, making the drift region The setting can be significantly shorter than the conventional drift area.

The present invention is mainly to add an auxiliary gate to the drift region. In addition to improving the length of the drift region, it can also improve the breakdown voltage value of the semiconductor device structure. Please refer to the fifth and fifth figures of the present invention. Show. Figure 5a is a conventional semiconductor device structure with only one gate, and Figure 5b is the semiconductor device structure of the present invention, which adds an additional gate in the drift region. Through electrical simulation, when the drain current is 5e-13 ampere/micrometer (A/μm) at the same time, it can be converted that the breakdown voltage of the conventional semiconductor device structure is 28.7 volts, and the breakdown voltage of the present invention It is 62.0 volts, which makes the breakdown voltage of the present invention significantly better than the conventional breakdown voltage.

The present invention effectively improves the length of the drift region and the breakdown voltage. When the effective width of the drain region of this device structure is narrow enough, for example, the drift region and channel region of the present invention can have a length of the drift region when the voltage is less than 60 volts 0.5~6 microns, the length of the channel area can be 0.3~1.2 microns; when the voltage of the drift area and the channel area is less than 600 volts, the length of the drift area can be 6~40 microns, and the length of the channel area can be 1~5 microns; When the voltage of the drift region and the channel region is greater than 600 volts, the length of the drift region is greater than 40 microns, and the length of the channel region is greater than 5 microns. For example, the effective width of the drift region is less than or equal to 30 nanometers (nm), and has a high When the voltage is higher than Vcc, it can be covered by the auxiliary gate of the present invention, so that the extended region of the drain region, that is, the drift region under the auxiliary gate, can form a fully depletion region to reduce leakage. Occurs, and the breakdown voltage is increased, the concept of the present invention can also be applied to PMOS on N-type substrates, the source region and the drain region are doped with P+ impurities, and the drift region is doped with P-type impurities (P-Well ) Or low P-type doping concentration.

The above-mentioned embodiments are only to illustrate the technical ideas and characteristics of the present invention, and the purpose is to make those skilled in the art sufficiently understand the content of the present invention and implement it accordingly, but cannot limit the patent scope of the present invention , That is, any equivalent changes or modifications made in accordance with the spirit disclosed by the present invention should still be covered by the patent scope of the present invention.

10‧‧‧Semiconductor structure

12‧‧‧ substrate

14‧‧‧Source region

16‧‧‧ Drainage area

18‧‧‧Channel area

20‧‧‧Drift area

21‧‧‧Insulation

22‧‧‧Gate

30‧‧‧Semiconductor structure

32‧‧‧substrate

322‧‧‧Source region

324‧‧‧Channel area

326‧‧‧Drift area

328‧‧‧Drainage area

34‧‧‧ First gate

35‧‧‧First insulation layer

36‧‧‧ auxiliary gate

37‧‧‧Second insulation layer

V1‧‧‧ First voltage

V2‧‧‧Second voltage

The first figure is a structural schematic diagram of a conventional semiconductor device structure. The second figure is a schematic diagram of the present invention. The third figure is a schematic diagram of the turn-on voltage of the present invention. Figure 4a is a schematic diagram of the electric field strength of a conventional semiconductor device structure. Figure 4b is a schematic diagram of the electric field strength of the present invention. Fig. 5a is a schematic diagram of a breakdown voltage formed by a conventional semiconductor device structure. Figure 5b is a schematic diagram of the present invention forming a breakdown voltage.

30‧‧‧Semiconductor structure

32‧‧‧substrate

322‧‧‧Source region

324‧‧‧Channel area

326‧‧‧Drift area

328‧‧‧Drainage area

34‧‧‧ First gate

35‧‧‧First insulation layer

36‧‧‧ auxiliary gate

37‧‧‧Second insulation layer

Claims (9)

A semiconductor device structure includes: a substrate having a source region, a channel region, a drift region, and a drain region, the channel region is located between the source region and the drift region, through the channel region Separate the source region and the drift region, the drain region is located on the other side of the drift region; a first gate is located on the substrate, and is located in the source region, the channel region and the The drift region is used to connect the source region and the drift region; and an auxiliary gate is located on the substrate and is located on the drift region to increase the withstand voltage of the drift region when the drain region When there is a high voltage, it can be covered by the auxiliary gate, so that the extension of the drain region, that is, the drift region under the auxiliary gate can form a fully depletion region (fully depletion region), reducing the occurrence of leakage, And can increase the breakdown voltage. The semiconductor device structure according to claim 1, wherein the drift region is an N-well (N-Well) doped with N-type impurities or has a low N-type doping concentration. The semiconductor device structure according to claim 2, wherein the source region and the drain region are doped with N+ impurities. The semiconductor device structure according to claim 1, wherein a first insulating layer is further provided between the first gate and the source region, the channel region, and the drift region. The semiconductor device structure according to claim 1, wherein a second insulating layer is further provided between the auxiliary gate and the drift region. The semiconductor device structure according to claim 1, wherein the effective width of the drain region and the drift region is less than or equal to 30 nanometers (nm). The semiconductor device structure according to claim 1, wherein the drift region and the channel region are When the voltage is less than 60 volts (V), the length of the drift region is 0.5 to 6 microns (μm), and the length of the channel region is 0.3 to 1.2 microns. The semiconductor device structure according to claim 1, wherein when the voltage is less than 600 volts in the drift region and the channel region, the drift region length is 6-40 microns, and the channel region length is 1-5 microns. The semiconductor device structure of claim 1, wherein when the voltage is greater than 600 volts in the drift region and the channel region, the drift region length is greater than 40 microns, and the channel region length is greater than 5 microns.

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