CN102760766A - Metal oxide semiconductor field effect transistor layout structure - Google Patents
Metal oxide semiconductor field effect transistor layout structure Download PDFInfo
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- CN102760766A CN102760766A CN2011101948169A CN201110194816A CN102760766A CN 102760766 A CN102760766 A CN 102760766A CN 2011101948169 A CN2011101948169 A CN 2011101948169A CN 201110194816 A CN201110194816 A CN 201110194816A CN 102760766 A CN102760766 A CN 102760766A
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- cross pattern
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- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 42
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 42
- 230000005669 field effect Effects 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title abstract description 4
- 239000000758 substrate Substances 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000012545 processing Methods 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 229910052594 sapphire Inorganic materials 0.000 claims description 2
- 239000010980 sapphire Substances 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 3
- 239000004020 conductor Substances 0.000 description 6
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a metal oxide semiconductor field effect transistor layout structure. The layout structure uses a mixed array of the common drain region with the cross pattern and at least two common drain regions with the grid pattern, the common source region with the cross pattern and at least two common source regions with the grid pattern, so that the device density of the traditional layout circuit can be improved, the effective channel width of the traditional layout circuit can be improved, and the effects of reducing the cost and operating with higher power can be achieved.
Description
Technical field
The present invention relates to a kind of metal-oxide half field effect transistor layout structure; Be particularly related to a kind of metal-oxide half field effect transistor layout structure with higher efficient channel width and higher component density; Can promote the component density of conventional in layout circuit and promote its efficient channel width, reach and reduce cost and the purpose of high power operation more.
Background technology
In recent years; Metal-oxide half field effect transistor (Metal Oxide Semiconductor; MOS) all be to dwindle with size of components to reach the purpose that increases component speed and drive current, but, utilize size of components to dwindle the method convergence limit with the lifting subassembly service speed according to ITRS roadmap.Therefore, utilize size of components to dwindle to reach the improvement of performance, apparent more and more is not easy.
In addition, the metal-oxide half field effect transistor (Power MOS) that has a big live width also is employed the mains switch as power management applications widely.But, the source electrode of this type of metal-oxide half field effect transistor can cause some defectives or problem with the long lead that is connected of drain electrode, for example connects the serious voltage drop of lead.In addition, owing to consider the factor of integration, the cell pitch of (PCC) power must be more little good more, thus the source electrode of metal-oxide half field effect transistor be connected conductor width with the metal of drain electrode certainly will be limited.Source electrode is connected the length of lead with the metal of drain electrode also limited because of the problem of electromigration (Electron Migration), especially connects conductor width when limited at metal.Therefore traditional high power metal-oxide half field effect transistor is difficult to have concurrently big function of current and two kinds of character of high integration layout.
With reference to United States Patent (USP) notification number the 7th; 132; No. 717, title is the power MOS transistor layout (Power Metal Oxide Semiconductor Transistor Layout with Lower Output Resistance and High Current Limit) with low output resistance and the restriction of high electric current, discloses a kind of power MOS transistor layout; Connect lead especially in regard to a netted connection lead of a kind of use or a complanation; When yet this case connects in the source/drain polar conductor, unclear its electrostatic defending (ElectroStatic Discharge, ESD) placement rule of disclosing.
Please refer to Figure 1A, it shows prior art metal-oxide half field effect transistor layout structure 100 at present, and it is made up of metal-oxide half field effect transistor layout array 110.Metal-oxide half field effect transistor layout array 110 comprises: source electrode 120, drain electrode 130, grid 140, transistor 150, connection source electrode lead 160 and connection drain conductors 170.
Please refer to Figure 1B, it shows the drain electrode and the source electrode connection layout of the metal-oxide half field effect transistor layout structure of prior art at present.Wherein connecting source electrode lead 160 all takes oblique line to connect with the connected mode that is connected drain conductors 170.Generally speaking, it has (1) and whether connects the asymmetric problem of (2) online circuit smoothly in source electrode 120, drain electrode 130 corner.
Therefore, be necessary to propose a kind of metal-oxide half field effect transistor layout structure to solve above-mentioned mentioned problem with higher efficient channel width and higher component density.
Summary of the invention
Main purpose of the present invention is to provide a kind of metal-oxide half field effect transistor layout structure, can be used in the CMOS processing procedure, to have higher efficient channel width and higher component density.
For reaching above-mentioned purpose, the present invention provides a kind of metal-oxide half field effect transistor layout structure, and it comprises: a substrate; One has the common drain district of positive cross pattern; At least two common source polar regions with grid pattern; One has the common source polar region of positive cross pattern; At least two common drain districts with grid pattern; And at least two common gate districts.The common drain district that this has positive cross pattern is formed on this substrate; These at least two the common source polar regions with grid pattern are disposed at four corners in this common drain district with positive cross pattern, are formed on this substrate; The common source polar region that this has positive cross pattern is formed on this substrate; These at least two the common drain districts with grid pattern are disposed at four corners in this common drain district with positive cross pattern, are formed on this substrate; And these at least two common gate districts; Be disposed at this common drain district and at least two common source polar regions, this common source polar region and these at least two and have between common drain district and these at least two the common drain districts and these at least two common source polar regions of grid pattern, be formed on this substrate with grid pattern with grid pattern with positive cross pattern with grid pattern with positive cross pattern.
Metal-oxide half field effect transistor layout structure of the present invention has following effect:
Common drain district and at least two the common drain districts with grid pattern, the common source polar region with positive cross pattern and at least two common source polar regions with grid pattern that utilization has positive cross pattern form the hybrid-type array with positive cross pattern common drain district and positive cross pattern common source; It can promote the component density of conventional in layout circuit and promote its efficient channel width, reduces cost and the purpose of high power operation more to reach.
Compare with the conventional in layout circuit, under equal area, it can promote about one times number of transistors.
For letting above-mentioned and other purposes of the present invention, characteristic and the advantage can be more obviously understandable, hereinafter is special lifts several preferred embodiments, and cooperates appended graphicly, elaborates as follows.
Description of drawings
Figure 1A is a prior art metal-oxide half field effect transistor layout structure sketch map;
Figure 1B is the drain electrode and the source electrode connection layout of prior art metal-oxide half field effect transistor layout structure;
The metal-oxide half field effect transistor layout structure sketch map of Fig. 2 A higher efficient channel width and higher component density for the present invention has;
Fig. 2 B is the drain electrode connection layout of metal-oxide half field effect transistor layout structure of the present invention; Fig. 2 C is the drain electrode connection layout of metal-oxide half field effect transistor layout structure of the present invention.
The primary clustering symbol description
100 metal-oxide half field effect transistors, 110 MOSFET crystal, 120 source electrodes
Layout structure pipe layout array
130 drain electrodes, 140 grids, 150 transistors
It is wide that 160 connection source electrode leads, 170 connection drain conductors 200 have higher efficient channel
Degree and higher component density
Metal-oxide half field effect transistor cloth
Office's structure
210 have positive cross pattern totally 220 has 221 at least two of positive cross patterns and has trellis diagram
The common drain district of the common drain district case of drain region and positive cross figure
The hybrid-type of case common source
Array
230 with positive cross pattern 231 at least two have 240 at least two common gate districts of lattice
The common source of common source polar region sub patterns
The district
250 transistors, 260 first netted lead 270 second netted leads
280 have positive cross pattern totally 290 has positive cross pattern
The grid of the grid common source polar region of drain region
Embodiment
Though the present invention can show as multi-form embodiment; But person shown in the accompanying drawing and in the system of expositor hereinafter for the present invention can preferred embodiment; And please understand person disclosed herein system and be thought of as one of the present invention example, and be not that intention is in order in the specific embodiment that the present invention is limited to diagram and/or is described.
Please refer to Fig. 2 A, it shows the metal-oxide half field effect transistor layout structure sketch map that the present invention has higher efficient channel width and higher component density at present.It comprises: a substrate; One has the common drain district 220 of positive cross pattern; At least two common source polar regions 231 with grid pattern; One has the common source polar region 230 of positive cross pattern; At least two common drain districts 221 with grid pattern; And at least two common gate districts 240.Common drain district 220 with positive cross pattern is formed on this substrate; At least two common source polar regions 231 with grid pattern are disposed at four corners in this common drain district 220 with positive cross pattern, are formed on this substrate; Common source polar region 230 with positive cross pattern is formed on this substrate; At least two common drain districts 221 with grid pattern are disposed at four corners in this common drain district 221 with positive cross pattern, are formed on this substrate; And these at least two common gate districts 240; Be disposed between this common drain district 220 and at least two common source polar regions 231, common source polar region 230 and at least two common drain districts 221 and at least two common drain districts 221 and at least two the common source polar regions 231, be formed on this substrate with grid pattern with grid pattern with grid pattern with positive cross pattern with grid pattern with positive cross pattern.Its grid pattern can be one of rectangle, square and rhombus.
Be noted that wherein have the common drain district 220 of positive cross pattern, at least two common source polar regions 231 with grid pattern can form the grid 280 with positive cross pattern common drain district with at least two common gate districts 240.Have the common source polar region 230 of positive cross pattern, at least two common drain districts 221 with grid pattern can form the grid 290 with positive cross pattern common source polar region with at least two common gate districts 240.And the grid 280 with positive cross pattern common drain district is disposed between any two adjacent grids 290 with positive cross pattern common source polar region, and then forms the hybrid-type array 210 with positive cross pattern common drain district and positive cross pattern common source.In addition, has the grid 280 in positive cross pattern common drain district and have between the grid 290 of positive cross pattern common source polar region and be at least two common gate districts 240.
Generally speaking; The present invention has the metal-oxide half field effect transistor layout structure 200 of higher efficient channel width and higher component density, and it can be implemented on sapphire substrate, silicon substrate, GaAs substrate, coated insulating layer silicon substrate, sige substrate and the glass substrate.And the hybrid-type array 210 with positive cross pattern common drain district and positive cross pattern common source can be implemented in 0.35 μ m, 0.25 μ m, 0.18 μ m, 0.13 μ m, 90nm, 45nm or the more advanced processing procedure.
Please refer to Fig. 2 B, it shows the drain electrode connection layout of metal-oxide half field effect transistor layout structure of the present invention at present.Wherein, the grid 280 with positive cross pattern common drain district that any two are adjacent and the grid 290 with positive cross pattern common source polar region comprise respectively between common drain district 220 with positive cross pattern and two common drain districts with grid pattern 221, two common drain districts 221 with grid pattern be connected with one first netted lead 260 at least at least.
Please refer to Fig. 2 C, it shows the source electrode connection layout of metal-oxide half field effect transistor layout structure of the present invention at present.Wherein, the grid 290 with positive cross pattern common source polar region that any two are adjacent and the grid 280 with positive cross pattern common drain district comprise respectively between this common source polar region 230 with positive cross pattern and two common source polar regions with grid pattern 231, two common source polar regions 231 with grid pattern be connected with one second netted lead 270 at least at least.Generally speaking, this place uses the first netted lead 260 and the second netted lead 270 to be the copper metal.That is the present invention has higher efficient channel width and higher component density metal-oxide half field effect transistor is all the arrangement mode that adopts parallel connection.
Please refer again to Figure 1A and Fig. 2 A, the quantity of its transistor 150 and transistor 250 under unit are, uses the number of transistors of the hybrid-type array 210 with positive cross pattern common drain district and positive cross pattern common source can promote one times approximately at present.
In an embodiment; If having the hybrid-type array 210 of positive cross pattern common drain district and positive cross pattern common source is 3 * 3 arrays, that is wherein comprises 5 groups of grid 290 and 4 groups of grids 280 with positive cross pattern common drain district with positive cross pattern common source polar region.Metal-oxide half field effect transistor quantity of the present invention can reach 72 transistors.
In sum, the metal-oxide half field effect transistor layout structure of the present invention with higher efficient channel width and higher component density has following effect:
Common drain district and at least two the common drain districts with grid pattern, the common source polar region with positive cross pattern and at least two common source polar regions with grid pattern that utilization has positive cross pattern form the hybrid-type array with positive cross pattern common drain district and positive cross pattern common source; It can promote the component density of conventional in layout circuit and promote its efficient channel width, reduces cost and the purpose of high power operation more to reach.
Compare with the conventional in layout circuit, under equal area, it can promote about one times number of transistors.
Though the present invention discloses with aforementioned preferred embodiment, so it is not in order to limiting the present invention, anyly has the knack of this art, in spirit that does not break away from the present invention and scope, when doing various changes and modification.Like above-mentioned explanation, can do the correction and the variation of each pattern, and can not destroy the spirit of this creation.So the claim person of defining that the present invention's protection range attaches after looking is as the criterion.
The above; Be merely embodiment of the present invention, but protection scope of the present invention is not limited thereto, any technical staff who is familiar with the present technique field is in the technical scope that the present invention discloses; Can expect easily changing or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion by said protection range with claim.
Claims (8)
1. a metal-oxide half field effect transistor layout structure is characterized in that, comprises:
One substrate;
One has the common drain district of positive cross pattern, is formed on this substrate;
At least two common source polar regions with grid pattern are disposed at four corners in this common drain district with positive cross pattern, are formed on this substrate;
One has the common source polar region of positive cross pattern, is formed on this substrate;
At least two common drain districts with grid pattern are disposed at four corners in this common drain district with positive cross pattern, are formed on this substrate; And
At least two common gate districts; Be disposed at this common drain district and at least two common source polar regions, this common source polar region and these at least two and have between common drain district and these at least two the common drain districts and these at least two common source polar regions of grid pattern, be formed on this substrate with grid pattern with grid pattern with positive cross pattern with grid pattern with positive cross pattern;
Wherein this have the common drain district of positive cross pattern, these at least two common source polar regions and this at least two common gate districts with grid pattern can form one have a positive cross pattern common drain district grid, and this have the common source polar region of positive cross pattern, these at least two common drain districts and this at least two common gate districts with grid pattern can form one have a positive cross pattern common source polar region grid.
2. metal-oxide half field effect transistor layout structure as claimed in claim 1 is characterized in that, this substrate is sapphire substrate, silicon substrate, GaAs substrate, coated insulating layer silicon substrate, sige substrate and glass substrate.
3. metal-oxide half field effect transistor layout structure as claimed in claim 1 is characterized in that, this grid pattern is rectangle, square and rhombus.
4. metal-oxide half field effect transistor layout structure as claimed in claim 1; It is characterized in that; This grid configuration with positive cross pattern common drain district has between the grid of positive cross pattern common source polar region in any two adjacent these, and then forms one and have the hybrid-type array of positive cross pattern common drain district and positive cross pattern common source.
5. metal-oxide half field effect transistor layout structure as claimed in claim 1 is characterized in that, this has between grid and this grid with positive cross pattern common source polar region in positive cross pattern common drain district and is these at least two common gate districts.
6. metal-oxide half field effect transistor layout structure as claimed in claim 5; It is characterized in that this hybrid-type array with positive cross pattern common drain district and positive cross pattern common source is implemented in 0.35 μ m, 0.25 μ m, 0.18 μ m, 0.13 μ m, 90nm, 45nm or the more advanced processing procedure.
7. metal-oxide half field effect transistor layout structure as claimed in claim 1; It is characterized in that the grid that any two adjacent these have a positive cross pattern common drain district and this grid with positive cross pattern common source polar region comprise this common drain district with positive cross pattern respectively to have between the common drain district of grid pattern, these two the common drain districts with grid pattern and be connected with one first netted lead with these at least two at least.
8. metal-oxide half field effect transistor layout structure as claimed in claim 1; It is characterized in that the grid that any two adjacent these have a positive cross pattern common source polar region and this grid with positive cross pattern common drain district comprise this common source polar region with positive cross pattern respectively to have between the common source polar region of grid pattern, these two the common source polar regions with grid pattern and be connected with one second netted lead with these at least two at least.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100114773A TW201244061A (en) | 2011-04-28 | 2011-04-28 | Metal oxide semiconductor transistor layout with higher effective channel width and higher component density |
| TW100114773 | 2011-04-28 |
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| Publication Number | Publication Date |
|---|---|
| CN102760766A true CN102760766A (en) | 2012-10-31 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2011101948169A Pending CN102760766A (en) | 2011-04-28 | 2011-07-12 | Metal oxide semiconductor field effect transistor layout structure |
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| TW (1) | TW201244061A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5714784A (en) * | 1995-10-19 | 1998-02-03 | Winbond Electronics Corporation | Electrostatic discharge protection device |
| CN101510559A (en) * | 2008-02-15 | 2009-08-19 | 联咏科技股份有限公司 | Element and layout of power metal-oxide-semiconductor transistor |
| US20090250751A1 (en) * | 2007-12-17 | 2009-10-08 | Sehat Sutardja | Mos device with low on-resistance |
-
2011
- 2011-04-28 TW TW100114773A patent/TW201244061A/en unknown
- 2011-07-12 CN CN2011101948169A patent/CN102760766A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5714784A (en) * | 1995-10-19 | 1998-02-03 | Winbond Electronics Corporation | Electrostatic discharge protection device |
| US20090250751A1 (en) * | 2007-12-17 | 2009-10-08 | Sehat Sutardja | Mos device with low on-resistance |
| CN101510559A (en) * | 2008-02-15 | 2009-08-19 | 联咏科技股份有限公司 | Element and layout of power metal-oxide-semiconductor transistor |
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| Publication number | Publication date |
|---|---|
| TW201244061A (en) | 2012-11-01 |
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Application publication date: 20121031 |