TW201238231A - Power supply apparatuses for preventing latch-up of charge pump and methods thereof - Google Patents

Abstract

A power supply apparatus and a power supply method are disclosed. The power supply apparatus may include an internal power supply including a first voltage generator configured to generate a first voltage based on a pulse width modulation control signal, a charge pump configured to receive the first voltage and generate a second voltage, and an inrush current controller configured to be connected between the charge pump and the internal power supply and configured to generate the pulse width modulation control signal based on a target signal and a selection reference voltage.

Description

201238231 41432pif VI. Description of the Invention: [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims the priority of the Korean Patent Application No. 10-2011-0 (No. 4, 425, and No. 10-2011-002825, respectively. Approved to the Korean Intellectual Property Office on February 17, 2011 and March 29, 2011, the entire contents of which are incorporated herein by reference. A power supply, and particularly a power supply device including a charge pump, and a method therefor. [Prior Art] An electrical device or an electronic device usually uses a direct current DC power supply, which is an alternating current ( Aiternate current, AC) The power is converted to a DC voltage to drive the device. A switching mode power supply (SMPS) is used as a DC power supply. The DC power supplied by the switching power supply is applied to the electronic device. Each part is because the power supply supplied by the switching power supply is 5 v, 3.3 V or 12 V' electronic devices also include charge The self-switching power supply receives the DC voltage and boosts the DC voltage to the level of each part of the electronic device (such as the chipset and the memory). However, 'because of environmental conditions, such as design errors and ambient temperature errors (for example) 'Parts may be affected when the current is not evenly distributed due to the pinch-cooling current. In the case of the flash-lock effect, currents exceeding several hundred milliamps (mA) 201238231 41432pif flow in the circuit And interrupt or destroy the circuit. For example, the parasitic PNPN structure (also known as the thyristor structure) is in the N-type metal oxide semiconductor (NMOS) and the P-type gold oxide half (P- The type metal oxide semiconductor (PMOS) is triggered, and the inrush current may flow into the thyristor structure; the N-type gold oxide half and the P-type gold oxide half are in the complementary metal oxide semiconductor (CMOS) structure. Neighbor. Because the input/output voltage exceeds the rated voltage, the inrush current (or leakage current) flows into the internal device, or because the power supply is powered. When the internal voltage exceeds the rated voltage and the internal equipment fails, a large amount of current may affect the equipment. To prevent this latch-up effect, an external Schottky diode is usually used, or an internal Schottky can be provided in the integrated circuit. Diode. However, when using an external Schottky diode, the manufacturing price of the module rises. Internal Schottky diodes increase wafer size. SUMMARY OF THE INVENTION According to some exemplary embodiments, a power supply device is provided that includes an internal power supply, a charge pump, and an inrush current controller. The internal power supply includes a first voltage generator that generates a first voltage according to a pulse width modulation control signal; the charge pump receives the first voltage and generates a second voltage; and the inrush current The controller is connected between the charge pump and the internal power supply, and generates a pulse width modulation control signal according to the target signal and the selected test voltage. The thirsty current controller can include a first sampling circuit, a reference voltage generator, and a first comparator. The first sampling circuit is responsive to the first enabling signal 201238231 41432pif to divide the first voltage ' and output a target signal according to the divided voltage; the reference voltage generating reference voltage reference signal is outputted to select the reference voltage; and the first comparison The device compares the target signal with the selection reference voltage and outputs a pulse width modulation control signal. In some exemplary embodiments, the first voltage generator generates a feedback signal and the internal power supply includes a pulse generator that generates a pulse wave based on the feedback signal. The pulse generator can include a sawtooth pulse generator, a sawtooth pulse comparison signal generator, and a second comparator. The sawtooth pulse generator generates a sawtooth pulse wave having a slope, and the sawtooth pulse wave is a meal according to a pulse width: controlling the sfL number and the first enable signal; the ore tooth pulse wave comparison signal generating state responds to the second The target signal or the feedback signal is outputted as a sawtooth pulse comparison signal, and the second comparator compares the sawtooth pulse with the sawtooth pulse to generate a switching pulse. The sawtooth pulse generator can include a second generation circuit, a first waveform generator, and a second waveform generator. The second generating circuit divides the supply voltage by using a plurality of resistors, and generates a plurality of secondary reference voltages according to the divided voltage; the first waveform generator is connected to the second generating circuit and the sawtooth pulse wave output Between the terminals, the voltage is selected from the secondary reference voltage according to the second enable signal, and the ground voltage is pulled up by responding to the voltage selected from the secondary reference voltage to generate the first waveform; The second waveform generation is connected between the second generating circuit and the sawtooth pulse output end, and pulls down the voltage of the sawtooth pulse wave output to generate a second waveform by responding to the falling signal, wherein the falling signal is in the second waveform generator Generated, and according to the sampling supply voltage, the sampling voltage is sampled according to the internal power supply time of the 201232831 41432pif pulse signal. The first waveform generator can include a bias circuit, a pull up circuit, and a buffer. The bias circuit responds to the pulse width modulation control signal and the voltage of the wheel voltage is used as a soft bias signal, or responds to the second signal to output a maximum bias signal as a sawtooth pulse basic signal; The circuit responds to the voltage of the output of the pulse wave; the memory is connected between the output end of the sawtooth pulse wave and the ground terminal, and is used for storing the pull-up signal and generating the first waveform. According to other exemplary embodiments, a power supply method performed by a power supply is provided, the power supply including an internal power supply and a charge pump. The power supply method comprises: generating a target signal according to a first voltage generated by the internal power supply in response to the first enable signal, generating a selection reference voltage from the supply voltage, and generating a pulse width modulation control according to the target signal and the selected reference voltage. The signal controls the pulse width of the switching pulse wave according to the pulse width modulation control signal, controls the amount of inrush current of the input charge pump according to the switching pulse wave, and uses the charge pump to generate the second voltage. At least another exemplary embodiment discloses a power supply that includes a charge pump and an internal power supply. The charge pump receives a first voltage and generates a second voltage according to the first voltage; and the internal power supply generates a first voltage according to a pulse width of the switching pulse wave, and includes a pulse wave generator, The pulse wave generator generates a switching pulse according to the modulation control signal, and the modulation control signal is different from the second voltage, and the modulation control signal is compared according to the target signal and the selected reference voltage. The above and other features and advantages of the exemplary embodiments will be more apparent from the following description of the appended claims. The present invention will now be described more fully hereinafter with reference to the appended claims However, the illustrative embodiments may be embodied in many different forms and should not be construed as being limited to the illustrative embodiments set forth herein. Rather, these illustrative embodiments are provided so that this disclosure will be thorough and complete, and the scope of the exemplary embodiments will be fully conveyed by those of ordinary skill in the art. In the drawings, the dimensions and relative sizes of layers and regions can be exaggerated for clarity. Throughout the text, the same component symbols represent similar elements. It will be understood that when an element is "connected" or "coupled" to another element, the element can be directly connected or coupled to the other element or the intervening element can be present. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, the intervening element does not. The term "and/or" as used herein includes a combination of one or more of the associated listed items and may be abbreviated as "/". It should be understood that although terms such as "first" and "second" are used herein to describe various elements, these elements are not intended to be limited by these terms. These terms are only used to distinguish one element from another. For example, the first signal may be referred to as the first number, and the second signal may be referred to as the first signal, without departing from the teachings of the present disclosure. The terminology used herein is for the purpose of describing particular embodiments only, As used herein, unless the context, the main ^ 201238231 41432pif = then the singular forms "a" and "said" mean U together with the plural. It should be further understood that, when explicitly stated, the special micro, Μ杜, and ten use 4 ° ° ° including "Duffin / seven light six + ^ features ^, the whole, steps, operations, yuan 'but does not rule out the existence or addition One or more features, regions=numbers,, operations, components, components, and/or combinations thereof. "II: Another meaning" otherwise all the terms (including technical two: language) used herein have the same meaning as in the field of the exemplary embodiment. It should be further understood that the meaning of the term The interpretation of terms, such as those defined in the general dictionary, should be related to the relevant field and/or the meaning of the context, and unless explicitly defined in this article, it will not be interpreted in terms of ideology or over-formal meaning. 1 is a block diagram of a power supply 1 根据 according to some exemplary embodiments. The power supply 1 〇〇〇 includes an internal power supply 1 电荷, a charge pump 200, an inrush current controller 300, and timing The internal power supply 100 performs a switching operation in response to the clock signal SMPS_CK applied by the timing controller 400 and the pulse wave puii and the pulse wave Pul2, thereby controlling according to the widths of the pulse wave Pull and the pulse wave Pul2. The inrush current flows. The internal power supply 1 receives the supply voltage VDD as an input and generates a first voltage. The first voltage includes a positive voltage and a negative voltage. 'The first positive voltage is represented by VSP, and the first negative voltage is represented by VSN. In some exemplary embodiments, the internal power supply 1〇〇 may be a switching mode power supply (SMPS)' In other embodiments, the pulse width modulation can be used to implement. 201238231 41432pif The electric Hew200 200 alternately performs charging and discharging in response to the clock CP_CK applied by the timing controller 400, thereby boosting the first voltage and generating the first- The second voltage includes a positive voltage and a negative voltage. For the sake of clarity, the first positive money is represented by VGH, and the second negative voltage is represented by VGL. In different implementations, the charge pump can be implemented in different ways. The current controller 300 receives the first positive voltage vsp from the internal power supply 1 ,, compares the first positive voltage vsp with the selected reference voltage VREF_SEL' and outputs a pulse width modulation control signal Pul CON to the internal power supply temple. The timing controller 400 applies a plurality of preset pulse waves Pull and pulse waves pul2 having different widths to the internal power supply 1 〇〇. The internal power supply 1 〇〇 response pulse The width modulation control signal PuLC〇n uses the pulse pulse Pull or the pulse Pul2 as the switching pulse Lsw to control the amount of inrush current of the load pump 200. FIG. 2 is a diagram showing an example according to an exemplary embodiment. Detailed block diagram of the power supply 1000 in the middle. Referring to Fig. 2 '(10) The power supply (10) includes a first voltage generator 150 and a pulse generator 500. The first voltage generator 15 includes a first switch 101, an inductor The operation of the internal power supply 1 is described below, and the switching pulse LSW generated by the pulse generator 施加 is applied to the control terminal of the first switch ι1. When the first switching port 101 is turned on, energy from the supply voltage VDD is accumulated on the inductor 102. When the first switch 1〇1 is turned off, the energy accumulated on the inductor H 102 is released to the load circuit 1〇3. When this operation is repeated at a predetermined interval of 11 201238231 41432pif, the first voltage (VSP and VSN) is generated. The first voltage generator 150 divides the first voltage (VSP and VSN) and generates a feedback signal FB_VM. When the switching pulse LSW is generated, the feedback signal FB_VM is applied to the pulse generator 500 and reflected. The inrush current controller 300 includes a first sampling block 310, a reference voltage generator 320, and a first comparator 350. When the first enable signal REF_EN is not applied to the inrush current controller 3, the pulse generator 500 applies the switching pulse LSW to the feedback signal received from the first voltage generator 15A. The first voltage generator 15 is. However, when the first coincidence signal REF_EN is applied to the inrush current controller 3, the inrush current controller 300 generates the pulse width modulation control signal pui_c〇N. The pulse wave generator 500 selects the first pulse wave or the second pulse pul2 having different pulse widths in response to the pulse width modulation control signal Pul_c〇N, and by selecting the pulse wave Pulse or pulse Pul2 The pulse width modulation is performed on the upper to generate the switching pulse LSW. The switching pulse LSW controls the amount of inrush current supplied to the charge pump 200. The charge pump 200 boosts the first voltage (VSP and VSN) and turns on the two voltages (VGH and VGL), the first voltage being controlled by the controlled pulse in the internal power supply 1〇〇. The charge pump 200 is enabled and generates a second voltage before the first voltage reaches the preset maximum output due to the switching pulse. The structure and operation of the inrush current controller 3A will be described in detail below with reference to FIG. Figure 3 shows the inrush current controller 3〇〇 depicted in Figure 2. Referring to FIG. 3, the inrush current controller 300 includes a first sampling block.

12 201238231 41432pif 310, reference voltage generator 320, and first comparator 350. The first sampling block 310 responds to the first enable signal REF_EN, and divides the first voltage ' using a plurality of resistors connected between the first voltage and the ground to output a comparison target signal S_VSP. The first sampling block 310 is connected between the first voltage output terminal VSP or the output terminal VSN and the ground terminal GND. The first sampling block 310 includes a second switch 311 and a plurality of resistors. When the first enable signal REF_EN is applied to the control terminal of the second switch 311, the first sampling block 310 uses a resistor to divide the first voltage ' and outputs a comparison target signal S_VSP, the first voltage from The internal power supply 100 outputs 'and is input to the charge pump 200. The illustrative embodiment is not limited to FIG. For example, the first voltage VSP can be its original state as a comparison target signal, or in other embodiments, can be divided according to the level of the selection reference voltage VREF_SEL. The reference voltage generator 320 outputs a selection reference voltage VREF_SEL in response to the reference voltage selection signal SEL. The reference voltage generator 320 generates a plurality of primary reference voltages VREF_SEL_n to detect the first voltage, the reference voltage generator 320 and includes a first generation block 33〇 and a selection block 34〇. The first generating block 330 generates a plurality of main reference voltages VR£F_SEL-n by dividing the supply voltage by a plurality of resistors, the resistor being connected between the supply voltage terminal VDD and the ground terminal GND. For example, when a target reference value is used, the -th generation block 33G generates a first primary reference voltage VREF_SEL1 having a first target = a value and a second primary reference voltage VREF_SEL2 having a second privacy reference value. Two or more target reference values can be used at this time. 13 201238231 41432pif The selection block 340 outputs one of the plurality of primary reference voltages VREF_SEL_n as the selection reference voltage VRELSEL in response to the reference voltage selection signal SEL. The selection block 340 includes a plurality of switches SEL_SW1 and SEL_SW2, each of which is coupled to a reference voltage output. When the first generation block 330 generates at least two main reference voltages VREF_SEL_ii, the selection block 340 selectively outputs a selection reference voltage VREF_SEL in response to the reference voltage selection signal SEL. In Fig. 3, the first main reference voltage VREF_SEL1 or the second main reference voltage VREF_SEL2 is selected in response to the reference voltage selection signal SEL and output as the selection reference voltage VREF_SEL. The switch SEL_SW1 and the switch SEL_SW2 can be implemented in different ways. The first comparator 350 compares the comparison target signal S_VSP from the first sampling block 310 with the selection reference voltage VREF_SEL. When the comparison target signal S_VSP is lower than the selection reference voltage VREF_SEL, the first comparator 350 outputs the pulse width modulation control signal Pul_CON at the first logic level (e.g., low level). When the comparison target signal s_VSP is higher than the selection reference voltage VREF_SEL, the first comparator 350 outputs the pulse width modulation control signal Pul_c〇N at the second logic level (e.g., high level). 4 is a graph of voltage versus time illustrating the operation of the inrush current controller 300 illustrated in FIG. Referring to FIG. 4, when the comparison target signal s__vsp is lower than the selection reference voltage VREF_SEL, the first comparator 35 outputs a pulse width modulation (four) signal PuLc (10) at the first logic level. When the comparison target signal s vsp is higher than the selection reference voltage VREF-fox, the first comparator 35 outputs the pulse width modulation control signal pul_C〇N at the second logic level of 201238231 41432pif. For example, when the first main reference voltage VREF_SEL1 is input to the first comparator 350 as the selection reference voltage VREF_SEL, the first comparator 350 outputs the first pulse width modulation control signal Pul_c〇N as the second main reference voltage. When VREF_SEL2 is input to the first comparator 350 as the selection reference voltage VREF_SEL, the first comparator 350 outputs the second pulse width modulation control signal Pul_C〇N2. The pulse width modulation control signal Pul-CON1 or the pulse width modulation control signal Pul_CON2 is applied to the pulse generator 5A in the internal power supply 100. The pulse width modulation control signal Pul_CON is determined by the reference voltage selection signal SEL. When the pulse width modulation control signal Pul_C〇N is at a high level, the pulse generation benefit 500 applies the first pulse Pu1 to the switcher ιοί, and when the pulse width modulation control signal Pul_CON is at the low level, the width is Is the first pulse wave different from the second pulse? 1112 is applied to the switch ι〇1. Therefore, in the soft pulse period of the first pulse or the second pulse Pul2, the first voltage (VSP and VSN) of the internal power supply 1〇〇 is gradually generated, and in the soft pulse wave Before the end of the period, the clock signal CP_Sig is applied to the charge pump 2〇0 to prevent spike current generation. When the charge pump 200 is enabled in response to the clock signal Cp_Sig, the incoming current gradually flows into the charge pump period, and since the flash lock effect is prevented, the inrush current is normally converted into a voltage to generate a second. Voltage (VGH and VGL). At this time, the soft pulse period refers to an axis whose pulse width is lower than the preset maximum width. In other words, when the material supply 1 〇〇 generates the first-electric waste (vsp and VSN) and the charge f 〇〇 2 generates the second 15 201238231 41432pif voltage (VGH and VGL), the soft pulse period starts from the first voltage. It starts when it is generated and ends when the second voltage is stable. The control operation of the inrush current according to the pulse width modulation control will be described hereinafter with reference to FIG. FIG. 5 is a signal timing diagram illustrating operation of a power supply 1 根据, in accordance with some demonstrative embodiments. Referring to Fig. 5, the internal power supply 1 〇〇 and the charge pump 2 〇〇 from the timing controller 400 respectively receive clock signals smps CK and clock signals CP_CK having different frequencies. ~ ^ When the enable §fl number REF_EN is applied to the erase current controller 3 ,, the soup enters the current controller 300 to divide and sample the first voltage VSP output from the internal power supply 1 。. The inrush current controller 300 compares the selection reference voltage VREF_SEL with the comparison target signal s_VSP. The timing controller 4 generates a first pulse Pu1 and a second pulse pui2, respectively having preset different pulse widths. For example, the first pulse pull may have a soft pulse width of pwi and a maximum pulse width of PW_Max, and the second pulse Pul2 may have a soft pulse width of PW2 and a maximum pulse width of pW_Max. When the timing controller 400 applies the first pulse wave puii and the second pulse wave pui2 to the internal power supply 100, the pulse wave generator 500 selects the first pulse wave Pull or the first according to the pulse width modulation control signal Pul_CON. The second pulse Pul2' and the selected first pulse wave pui or second pulse wave pui2 are applied to the control terminal of the first switcher 101. The switching operation in the internal power supply 1 is controlled by the pulse width modulation control signal Pul_CON, so that when the internal power supply 100 generates the first voltage (VSP and VSN) in the soft pulse period, the charge pump 200 It is enabled, and the charge pump 2 is operated during the 201203231 41432pif Lotus pump operation period. In other words, before the pulse wave (ie, LSW) having the maximum pulse width of P \ V_M ax is applied to the first switch 101 in the internal power supply 100, the charge pump 2 starts the operation, and the current flows. The amount is gradually increased, thereby preventing a large amount of current from flowing instantaneously into the charge pump 200. Therefore the 'latch effect is prevented. When there are two reference voltages VREF_SEL1 and VREF_SEL2, two pulse width modulation control signals Pul_CON1 and Pul CON2 can be generated according to the two reference voltages VREF_SEL1 and VREF_SEL2, respectively. At this time, the two enable signals CP_Sigl and Cp_Sig2 can be used as the enable signal cp_sig when the charge pump =0 is operated. The pulse width, the number of reference voltages, and the level of the reference voltage are not limited to Fig. 5, and various changes can be made in other embodiments. FIG. 6 is a block diagram of a power supply 11A according to other exemplary embodiments. Referring to FIG. 6, the power supply 1100 includes an internal power supply =0, a charge pump 2, a immersive current controller lion, and a timing control state of 400°. The description of the power supply 1100 will focus on The difference from the power supply 1 绘 shown in FIGS. 2 and 3 . . The inrush current control is 300' different from the inrush current controller 300 depicted in Fig. 2, and the inrush current controller 3' can use the negative voltage VSN in the first voltage as the input shout. In other words, when the enable REF-EN is applied to the inrush current controller 3〇〇', the current controller doubles, and the internal power is used to supply the first negative voltage VSN generated by $1GG as an input signal. Sampling to generate a comparison target signal, inrush current controller 17 201238231 41432pif 300' and comparing comparison target signal S_VSN with selection reference voltage EF_SEL, and transmitting the comparison result to internal power supply wave generator 5〇〇, so that the flow The influx of the human charge pump is controlled. At this time, 'the current control (four) passes, the principle according to the operation is the same as the principle of the full current controller 300 shown in Fig. 3 . FIG. 7 is a block diagram of a power supply 12 according to other exemplary embodiments. Referring to Fig. 7, the power supply 1200 includes an internal power supply 1 电荷, a charge pump 200, an inrush current controller 3, and a timing controller 400'. The description of the power supply 12A will focus on its differences from the power supply 1000 illustrated in FIGS. 2 and 3. The inrush current controller 300'' compares the comparison target signal s_VSP with the selection reference voltage VREF_SEL and generates a pulse width modulation control signal Pul_CON. The pulse width modulation control signal Pul_c〇N is applied to the timing controller 400 instead of being applied to the pulse generator 500 in the exemplary embodiment illustrated in FIGS. 1 to 3, in addition to The principle that the inrush current controller 300" operates is the same as the principle of the inrush current controller 300 illustrated in Figure 3. The timing controller 400' stores at least two related information of a predetermined pulse width ' The pulse wave width corresponding to the pulse width modulation control signal Pul_CON is applied to the internal power supply 1 〇〇. Therefore, the pulse pulse Pul is input to the pulse generator 5 〇〇 and output as the internal power supply 100 The switching pulse LSW is such that the first voltage (VSP and VSN) is gradually formed. The clock signal or the charge pump enable signal CP_Sig is applied to the charge before the soft pulse period of the switching pulse lSW ends 8 201238231 41432pif Thereafter, the inrush current is gradually input to the charge pump to prevent the latch-up effect, causing the charge pump 200 to perform a normal boost operation to generate a second voltage. Fig. 8 is a power supply method according to some demonstrative embodiments. of Referring to Fig. 8, when the supply voltage VDD is applied to the internal power generator 1 使用 using pulse width modulation, the internal power generator 1 升压 boosts the supply voltage VDD and generates a first voltage VSP. The first voltage vsp is boosted by the charge pump 200 and generated as the second voltage VGH. At this time, the negative voltage GND, the negative voltage VSN, and the negative voltage VGL are incidentally generated. The internal power supply using the pulse width modulation 1〇 The switch can be a switched power supply (SMPS) 'but can be implemented in various ways. The charge pump 2 can also be implemented in various ways. In operation S10 'when the internal power generator 100 using the pulse width modulation is generated a voltage, and when the first voltage is input to the charge pump 2〇〇, the first voltage is split. In operation S11, the first voltage is sampled in response to the first enable signal REF JEN. At this time, the first voltage can be The original state is sampled' or may be generated after the partial voltage of the response selection reference voltage VREF_SEL is generated, but the exemplary embodiment is not limited thereto. The first voltage may be the first positive voltage VSp or the first negative voltage VSN. Fuck In S12, at least one main reference voltage VREF_SEL_n is generated from the supply voltage VDD. In operation S13, one of the at least one main reference voltage VREF_SEL_n is output as the selection reference voltage VREF_SEL in response to the reference voltage selection signal SEL. 201238231 41432pif In operation S14 The comparison target signal S_VSP or the comparison target signal S_VSN obtained by sampling is compared with the selection reference voltage VREF_SEL' and the pulse width modulation control signal pul_CON is output. At this time, when the comparison target signal S_VSP or the comparison target signal S_VSN is lower than the selection reference voltage VREF_SEL, the pulse width modulation control signal Pul_CON is output at the low level. When the comparison target signal s_VSP or the comparison target signal S_VSN is higher than the selection reference voltage VREF_SEL, the pulse width modulation control signal Pul_CON is output at a high level. The internal power supply 100 controls the pulse width in response to the pulse width modulation control signal Pul_CON in operation S15. At this time, when the pulse width modulation control signal Pul_CON is at the low level, the first pulse Pu1 generated by the timing controller 400 can be selected. When the pulse width modulation control signal Pul_CON is at a high level, the second pulse Pul2 generated by the timing controller 4〇〇 can be selected. Alternatively, when the pulse width modulation control signal Pul_C〇N is at the low level, the timing controller 400 may select the preset first pulse wave and apply the preset first pulse Pu1 to the internal Power supply 1〇〇. When the pulse width "Pulsing control condition number Pul_CON is at two punctual timings, the timing controller 4 〇〇, the preset second pulse PU12 can be selected, and the preset second pulse wave pul2 is applied to the internal power source. Provider 100. In operation S16, the amount of inrush current flowing into the charge pump 2 is controlled in accordance with the switching pulse wave LSW obtained by controlling the pulse width. Before the end of the soft pulse period, the charge can be signaled by the cp pump. In operation S17, the input (four) is in-current gradually

20 201238231 41432pif Latch-up effect due to the first voltage (VGH and VGL). The block diagram of the power supply 2〇00 of the exemplary embodiment which is generated without the occurrence of the peak current is referred to FIG. 9. The power supply contacts, the charge pump, the current controller, and the timer 4〇 Hey. The description of the power supply 2_ will be different from that of the power supply 1 绘 shown in FIG. The internal power supply 1 〇〇 responds to the pulse signal SMPS_CK applied by the timing controller 4 to perform a switching operation, and the ship width is used to control the flow of the shallow current. The internal power supply has just included the first voltage generator 150 and the pulse generator 5〇〇. The first voltage generator 150 receives the supply voltage VDD and generates a first voltage (VSP and VSN) and a feedback signal FB_VM. The first voltage includes a first positive voltage VSP and a first negative voltage VSN. The pulse generator 5A, the recovery signal FB_VM and the internal power supply clock signal SMPS_CK' generate the switching pulse LSW, and apply the switching pulse LSW to the first voltage generator 150. The first voltage (VSP) is output from the internal power supply, and is input to the charge pump 200. The inrush current controller 300 receives the first voltage (vsp) and the first enable signal REF-EN, compares the first voltage (vSp) with the selection reference voltage VREF_SEL and outputs a pulse wave to the internal power supply 1〇〇 The width modulation control signal Pul_CON is compared with the comparison target signal s VSP. At this time, the pulse width modulation control signal Pul_CON is used to select the soft bias signal associated with the square wave gradient and is applied to the pulse generator 500 to control the 21 201238231 41432pif pulse width. The charge pump 2 boosts the first voltage (VSP and VSN) and outputs a second voltage (VGH and VGL), which is controlled according to the controlled pulse wave in the internal power supply 100. This day, because of the switching pulse LSW, the f-load pump 200 is enabled and generates a second voltage before the first voltage reaches the preset maximum output. FIG. 10 is a detailed block diagram of the power supply 2〇〇〇 illustrated in FIG. 9. Referring to Fig. 10, the power supply 2000 includes an internal power supply 100', a charge pump 200, an inrush current controller 300, and a timing control pirate 400. The description of the power supply supply 2000 will focus on its differences from those described in FIG. The internal power supply 100' includes a first voltage generator 15A and a pulse generator 500. The first voltage generator 15A includes a first switcher 〇1, an inductor 102, and a load circuit 〇3. In the operation of the internal power supply 1', the switching pulse LSW generated by the pulse generator 500' is applied to the control terminal of the first switch 101. When the first switch 1〇1 is turned on, energy from the supply voltage VDD is accumulated on the inductor 1〇2. When the first switch 101 is turned off, the energy accumulated on the inductor 102 is discharged to the load circuit 103. When this operation is repeated at a preset interval, the first voltage (vsp and VSN) is generated. The first voltage generator 15 turns the first voltage (vSp and VSN) and generates a feedback signal FB_VM. The feedback signal FB_VM is applied to the pulse generator 5 〇 〇 and is reflected in the generation of the switching pulse L s W . The soup into current controller 300 includes a first sampling block 310, a reference voltage generator 320', and a first comparator 350. 22 8 201238231 41432pif When the first enable signal REF is not applied to the inrush current controller 300, the pulse generator 5 in the internal power supply 100, according to the received from the first voltage generator 150 The feedback signal FB_VM applies the switching pulse LSW to the first voltage generator 15A. However, when the first enable signal REF_EN is applied to the inrush current controller 3, the inrush current controller 300 generates the pulse width modulation control signal Pul_c〇N. Pulse Width The modulation control signal PU1_CON is used to select the soft = pressure signal associated with the slope of the square wave and is applied to the pulse generator 500 to control the pulse width. The soft bias signal Sigl is based on the second reference voltage signal VREF-1 SELECTION or VREF 2 SELECTION. The pulse generator 500' uses pulse width modulation to generate a switching pulse L S W to control the amount of inrush current supplied to the charge pump 2 〇 . The principle of operation of the pulse wave generator 500 will be described in detail below with reference to FIG. Figure 11 is a block diagram of the pulse wave generator 5A shown in Figure 10. Referring to Fig. 11, a pulse wave generator 500 includes a sawtooth pulse wave generator 550, a mineral tooth pulse wave comparison signal generator 56A, and a second comparator 5〇2. The sawtooth pulse generator 550 responds to the pulse width modulation control signal Pul_CON and the second enable signal MAX_pULSE_EN to generate a sawtooth pulse saw_pulse having an adjusted slope. At this time, the sawtooth pulse SAW_PULSE can be generated by using the clock signal SMPS_CK in the internal power supply 1', the internal reference voltage VREF_SMPS, and the supply voltage VDD. The sawtooth pulse comparison signal generator 56 outputs a comparison target signal s_vsp or a feedback signal 23 201238231 41432pif FB_VM as a sawtooth pulse comparison signal COMP_REF in response to the second enable signal MAX_PULSE_EN. The second comparator 502 receives the sawtooth pulse wave SAW-PULSE through the forward end (+), and receives the ore tooth pulse wave comparison signal COMP-REF through the negative end (-), which is higher than the car ore tooth wave SAW_PULSE and the mineral tooth pulse. Bobby passes the signal COMP_REF and outputs the comparison result COMP_OUT as the switching pulse LSW. The pulse generator 500' can include an inverter 501. The inverter 501 inverts the comparison result COMP_OUT of the second comparator 502, and outputs a switching pulse LSW suitable for the switching operation of the first voltage generator 150. The structure and operation of the pulse wave generator 500 will be described in detail below with reference to Figs. FIG. 12 is a schematic diagram showing the internal structure of a pulse wave generator 500' shown in the drawing in accordance with some exemplary embodiments. Referring to Fig. 12, the pulse generator 500' includes a sawtooth pulse generator 550, a sawtooth pulse wave comparison signal generator 560, and a second comparator 502. The mineral tooth wave generator 550 includes a second generating block 51A, a first waveform generator 520', and a second waveform generator 530. The second generation block 510 generates a plurality of secondary reference voltages by performing voltage division with a plurality of resistors connected between the internal reference voltage VREF-SMPS and the ground GND. At this time, the secondary reference voltage may include the basic signal VREFi of the soft bias signal Sigl and the basic signal VREF2, the maximum bias signal Sig2, and the sawtooth pulse reset SAW CMP REF. > The first waveform generator 520 includes a bias selection circuit 522, a pull-up circuit 524, and a memory 525. The first waveform generator 52 is coupled between the second 24 201238231 41432pif generation block 510 and the sawtooth pulse output 551. The first waveform generator 520 selects one of the soft bias signal Sigl and the maximum bias signal Sig2 as the sawtooth pulse basic signal SAW_REF in response to the second enable signal MAX_PULSE_EN, and responds to the bias signal according to the sawtooth pulse basic signal SAW_REF. The BIAS pulls up the ground voltage to generate a first waveform. The bias selection circuit 522 selects the soft bias signal Sigl selected from the secondary reference voltage in response to the pulse width modulation control signal Pul_CON, or selects the maximum bias signal Sig2 in response to the second enable signal MAX_PULSE_EN, and The selected signal output is the sawtooth pulse basic signal SAW_REF. For example, when the second enable signal MAX_PULSE_EN is at the low level (that is, when the maximum pulse width is not enabled), the soft bias signal Sigl is output as a sawtooth pulse. Wave basic signal SAW_REF. When the second enable signal MAX_PULSE_EN is at the high level (that is, when the maximum pulse width is enabled), the maximum bias signal Sig2 is output as the sawtooth pulse basic signal SAW_REF. The soft bias signal Sigl is one of the secondary reference voltage VREF1 and the secondary reference voltage VREF2 generated by the second generation block 510. The secondary reference voltage VREF1 and the secondary reference voltage VREF2 are response pulse width modulation control signals. pul_C〇N is selected. The maximum bias signal Sig2 may be one of the preset secondary reference voltages VREF1 and VREF2 generated by the second generating block 51A. The first waveform generator 520 may also include a stabilization circuit 523 for stabilizing the output of the bias signal bias. The stabilization circuit 523 can be a buffer that outputs the 25 201238231 41432pif orthodontic pulse signal SAW_REF as the bias signal BIAS, but can be implemented in various other ways. The pull-up circuit 524 is coupled between the supply voltage VDD and the sawtooth pulse output terminal X and pulls up the voltage of the sawtooth pulse output terminal in response to the bias signal BIAS. Pull-up circuit 524 can be a switch implemented by a P-type metal oxide half (PMOS) transistor, but can be implemented in different ways. The memory 525 is connected between the mineral pulse output terminal X and the ground. The memory 525 stores the pull-up signal and generates a first waveform. The first waveform can be a rising waveform of the tin-toothed pulse wave. The second waveform generator 530 includes a second sampling block and pull-down circuit 533. The first sampling block includes a comparator 531 and a latch circuit 532. The second sampling block is connected between the supply voltage VDD and the sawtooth pulse output terminal , to output a falling signal f_ s A w after resetting the latch circuit 532, and the falling signal f-SAW is responded to by the internal power supply 1 The pulse signal SMPS_CK sampling supply voltage VDD is called. The comparator 531 compares the sawtooth pulse s A w — p UL s E fed back by the spur pulse output terminal X with a preset sawtooth pulse reset reference SAW_CMP_REF and generates a reset signal. The pull-down circuit 533 is connected between the sawtooth pulse output terminal 接地 and the ground GND' and responds to the down signal f-SAW to pull down the voltage of the pulse output terminal χ. The pull-down circuit 533 can be a switch implemented by a gold-oxide half (nm(6) transistor, but can be implemented in different ways. The mine tooth pulse comparison signal generator responds to the second enable signal MAX_PULSE_EN 'in the soft pulse wave (when The second enable signal 8 201238231 41432pif When the MAX_PULSE-EN is not enabled, that is, at the low level, the comparison target signal S_VSP is output as the sawtooth pulse comparison signal c〇Mp—, and during the maximum greasy wave period (when the first When the binary enable signal max_pulse_en is enabled, that is, at the high level, the feedback signal FB_VM is output as the sawtooth pulse comparison signal COMP_REF. As described above, the second comparator 502 receives the sawtooth pulse SAW_PULSE through the forward end (+). Receiving the sawtooth pulse wave comparison signal COMP_REF through the negative end (1), comparing the sawtooth pulse wave SAW_PULSE with the sawtooth pulse wave comparison signal COMP_REF, and outputting the comparison result c〇MP_OUT as the switching pulse wave LSW. When the voltage signal Sigl is selected in response to the pulse width modulation control signal Pul_CON, the bias signal BIAS which determines the slope of the sawtooth pulse wave is output corresponding to the soft bias signal Sigl. When the bias signal BIAS rises, the slope of the first waveform also increases. When the slope of the first waveform increases, the comparison of the sawtooth pulse SAW_PULSE and the sawtooth pulse comparison signal COMP_REF produces a comparison result of the pulse width of the C0MP_0UT. As a result, since the comparison result COMP_OUT is reversed, the pulse width of the switching pulse LSW is decreased. Conversely, when the bias signal BIAS is decreased, the slope of the first waveform is also decreased. When the slope of the first waveform is decreased, the comparison is performed. The pulse width of the comparison result COMP_OUT generated by the tooth pulse wave SAW_PULSE and the sawtooth pulse wave comparison signal COMP_REF is also reduced. As a result, since the comparison result COMP_OUT is reversed, the pulse width of the switching pulse wave LSW is increased.

S 27 201238231 41432pif The pulse wave generator 500 generates a switching pulse wave LSW applied to the first switcher ι〇 in the internal power supply just by controlling the pulse width modulation ' according to the above principle. The amount of thirsty current flowing from the internal power supply 1〇〇 and flowing into the charge pump 200 is controlled according to the switching pulse Lsw to reduce the peak current. Therefore, the flash lock effect is prevented. FIG. 13B is a schematic diagram showing the internal structure of a pulse wave according to other exemplary embodiments. Referring to Fig. 13, the pulse generator 5A includes a sawtooth pulse generation 550□, a sawtooth pulse comparison signal generator 56A, and a second comparator 502. The description of FIG. 13 will focus on its differences from FIG. The first waveform generator 520□ includes a bias selection circuit 522, a pull-up circuit 524, and a memory 525. The first waveform generator 520□ is coupled between the second generation block 510 and the sawtooth pulse output 551. The first waveform generator 520 □ pulls up the ground voltage and generates a first waveform in response to the secondary reference voltage, the secondary reference voltage being selected from the plurality of secondary reference voltages in response to the second enable signal MAX_PULSE_EN. The bias selection circuit 522 outputs a soft bias signal Sigl or a maximum bias signal Sig2 as a bias signal BIAS in response to the second enable signal MAX_PULSE_EN. The soft bias signal Sigl is one of the secondary reference voltage VREF1 and the secondary reference voltage VREF2 generated by the second generating block 510. The secondary reference voltage VREF1 and the secondary reference voltage VREF2 are the response pulse width modulation control signals. pul_CON is selected. Different from the first waveform generator 520 shown in FIG. 12, the first waveform generator 520□ shown in FIG. 13 also includes generating a maximum bias signal. 8 201238231 41432pif

The second circuit 540 of Sig2. The second generation block 510 generates a secondary reference voltage in response to the level selection signal rEf_SEL. The second circuit 540 outputs a maximum bias signal Sig2 selected from the secondary reference voltage. The level selection signal reF_SEL is N bits in length, where N is a natural number of 2 or greater. The total voltage of the second generating block 510 can be divided into N voltages, and the level selection signal reF_SEL can select one of the N voltages. The second circuit 540 can include the decoder 541 and the level shifter 542' but can be implemented in a different manner. The first waveform generator 520□ may also include a stabilization circuit 523 for stabilizing the output of the bias signal BIAS. The stabilization circuit 523 can include a buffer. Therefore, the 'maximum bias signal Sig2' can be set in various ways depending on the characteristics of the first voltage (VSP) or the power supply 2000. In other words, the second circuit 540 and the pulse generator 500□□ including the second circuit 540 can control the slope of the sawtooth pulse wave according to a physical environment such as heat and temperature that may change with operation, and reset the maximum pulse width PW_Max. . 14A through 14C are signal timing diagrams illustrating the operation of a power supply in accordance with other exemplary embodiments. For clarity of description, assume that the secondary reference voltage VREF1 is higher than the secondary reference voltage VREF2. The operation shown in Fig. 14A of this §fL timing diagram is the operation when the secondary reference voltage VREF1 is selected as the sawtooth pulse fundamental signal SAW_REF in response to the pulse width modulation control signal Pul_c〇N. When the first enable signal max_pulse_en is in the soft pulse period of the low level, when the pulse width modulation control signal Pul_CON is at the low level, the second circuit 521 selects the secondary reference voltage VREF1. The secondary reference voltage VREF1 is supplied to the stabilization circuit 523 and outputted by the stabilization circuit 523 as the bias signal BIAS. The latch circuit 532 samples the supply voltage VDD in response to the clock signal SMPS_CK of the internal power supply 100, so that the down signal f_SAW is generated. Pull-up circuit 524 and memory 525 respond to bias signal BIAS to produce a first waveform (i.e., a rising waveform). The pull-down circuit 533 responds to the down signal f_SAW to generate a second waveform, i.e., a falling waveform, such that the first sawtooth pulse SAW__PULSE@VREF1 is generated in accordance with the secondary reference voltage VREF1. The first sawtooth pulse SAW_PULSE@VREF1 and the sawtooth pulse comparison signal COMP_REF are supplied to the forward terminal (+) and the negative terminal (-), respectively, and are compared by the second comparator 502. The second comparator 502 outputs the first comparison result COMP_OUT1. At this time, when the first sawtooth pulse SAW_PULSE@VREF1 is higher than the sawtooth pulse comparison signal COMP_REF, the first comparison result COMP_OUT1 is output at a high level, and when the first sawtooth pulse SAW_PULSE@VREF1 is lower than the sawtooth pulse comparison signal COMP_REF At the time, it is output at a low level. The first comparison result COMP_OUT1 is reversed by the inverter 501, and is output as the first switching pulse wave LSW. The operation shown in the signal timing diagram of FIG. 14B is the secondary reference voltage VREF2 responding to the pulse width modulation. The operation when the control signal Pul_c〇N is selected as the sawtooth pulse basic signal SAW_REF. The second sawtooth pulse SAW_PULSE@VREF2 is generated according to the same principles as described above with reference to Fig. 14A. However, since the secondary reference voltage VREF2 is lower than the secondary reference voltage VREF1, the slope of the second sawtooth pulse 201238231 41432pif SAW_PULSE@VREF2 is smaller than the slope of the first sawtooth pulse SAW_PULSE@VREF1. The second comparison result COMP_OUT2 and the second switching pulse LSW2 are generated according to the second sawtooth pulse SAW_PULSE@VREF2. 14C is a timing diagram showing that the secondary reference voltage VREF1 is selected as the mineral tooth pulse basic signal SAW_REF, and the secondary reference voltage VREF2 is selected as the sawtooth pulse basic signal SAW_REF. The difference between the two. Compared with when the secondary reference voltage VREF2 is selected, the sawtooth pulse basic signal SAW_REF is higher when the secondary reference voltage VREF1 is selected, so the slope of the first sawtooth pulse SAW_PULSE@VREF1 is greater than the second sawtooth pulse SAW_PULSE The slope of @VREF2. The first sawtooth pulse SAW_PULSE@VREF1 or the second sawtooth pulse SAW_PULSE@VREF2 is compared with the sawtooth pulse comparison signal c〇MP_REF to produce a comparison result COMP_OUT. In detail, when the first sawtooth pulse SAW_PULSE@VREF1 or the second sawtooth pulse SAW_PULSE@VREF2 is higher than the sawtooth pulse comparison signal COMP_REF, the comparison result COMP_OUT is output at a high level. When the first orthodontic pulse SAW_PULSE@VREF1 or the second sawtooth pulse SAW_PULSE@VREF2 is lower than the sawtooth pulse comparison signal COMP_REF, the comparison result COMP_OUT is output at the low level. Since the slope of the first orthodontic pulse wave SAW_PULSE@VREF1 is larger than the slope of the second sawtooth pulse wave SAW_PULSE@VREF2, the first sawtooth pulse wave 31 201238231 41432pif SAW_PULSE is used compared to when the second sawtooth pulse wave SAW_PULSE@VREF2 is used. When @VREF1, the pulse width of the comparison result COMP_OUT is large. The comparison result COMP_OUT is inverted by the inverter 501 and output as the switching pulse LSW. Therefore, the pulse width of the switching pulse LSW decreases as the slope of the sawtooth pulse SAW_PULSE increases. As described above, in the soft pulse period in which the second enable signal MAX_PULSE_EN is in the low level, the slope of the sawtooth pulse SAW_PULSE is controlled by the pulse width modulation control signal Pul_CON, so that the width of the switching pulse lsW is controlled. Fig. 15 is a timing chart showing the operation of the power supply according to other exemplary embodiments. Referring to FIG. 4 and FIG. 15 ', the clock signal SMPS-CK generated by the timing controller 400 has different frequencies from the clock signal CP_CK, and is applied to the internal power supply 1 and the charge pump 2, respectively. . When the comparison target signal S_VSP is lower than the selection reference voltage VREF_SEL, the first comparator 35 that is injected into the current controller 3A is at the low level output pulse width modulation control signal pul_c〇N, and when comparing the target When the signal S_VSP is higher than the selection reference voltage VREF_SEL, the pulse width modulation control signal pul_c〇N is output at the high level. For example, as shown in FIG. 4, when the first main reference voltage VREF_SEL1 is input to the first comparator 350 as the selection reference voltage VREF_SEL, the first comparator 350 outputs the first pulse width modulation control signal Pul_CON1. When the second main reference voltage VREF_SEL2 is input to the first comparator 350 as the selection reference voltage VREF_SEL, the first comparator 350 outputs the second pulse width modulation control signal Pul_c〇N2. The 8th 201238231 41432pif pulse width modulation control signal Pul_CON1 or the second pulse width modulation control signal Pul_CON2 is applied to the pulse generator 500 in the internal power supply 1〇〇. When the second enable signal MAX_PULSE_EN at the low level is input to the second circuit 522' and the first pulse width modulation control signal Pul_c〇N1 is input to the first circuit 521, if the first pulse width modulation control signal Pul_CONl At a low level, the pulse generator 5 selects the voltage VREF1 from the secondary reference voltage as the soft bias signal Sigl, and outputs the first switching pulse having the first pulse width pwi according to the soft bias signal Sigl. LSW1. Otherwise, if the first pulse width modulation control signal Pul_CON1 is at a high level, the pulse generator 5 selects the voltage VREF2 from the secondary reference voltage as the soft bias signal sigl and outputs it according to the soft bias signal Sigl. The second switching pulse wave LSW2 having the second pulse width pW2. When the second enable signal MAX_PULSE_EN at the high level is input to the second circuit 522, the pulse generator 5 〇〇 responds to the level selection signal REF_SEL and selects the maximum bias signal Sig2 from the secondary reference voltage, and according to the maximum bias The voltage signal Sig2 outputs a switching pulse LSW1 having a maximum pulse width pW_MAX or a switching pulse LSW2. The internal power supply 100 generates a first voltage (VSp and VSN) and an inrush current to be input to the charge pump 100 in accordance with the switching pulse wave LSW. When the inrush current is gradually supplied to the charge pump 200, the charge pump 200 is enabled before the switching pulse LSW having the maximum pulse width PW_MAX is generated, so that a large amount of current does not instantaneously input the charge pump 2〇〇. Therefore, the latch 33 201238231 41432pif lock effect is prevented. In the example, the 訾 丨 丨 丨 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 电压 电压 电压 电压 电压 电压 电压 电压 电压 电压 电压 电压 电压 电压 电压 电压 电压 电压 电压 电压 电压Limited to this. In the embodiment, the pulse width, the reference number of the soft bias signal, and the level of the reference voltage can be variously changed. Figure 16 is a block diagram of a power supply unit 2 according to other exemplary embodiments. Referring to the 'Fig. 16' power supply unit 2, including the internal power supply 100D□, the charge pump 200, and the timing controller 4〇〇. The description of the power supply 2000' shown in Fig. 16 will be focused on its difference from the power supply 2000 of Fig. 9. The power supply 2 is not shown in Fig. 16. Unlike the power supply 2000 shown in Fig. 9, the power supply 2' does not include the inrush current controller 300. The internal power supply 1〇〇□ includes a first voltage generator 15〇 and a pulse wave module 600. The pulse wave module 600 includes a pulse wave generator 5A and a control signal generator 650. The internal power supply 100□ applies a first voltage (VSP) to the pulse modulator 600 and the charge pump 200. The control signal generator 650 of the pulse wave module 600 generates a control signal SEL_Sig to control the pulse width modulation according to the first voltage (VSP). The pulse generator 500 generates a soft bias signal Sigl in response to the control signal SEL_Sig, and generates a switching pulse LSW whose pulse width corresponds to the soft bias signal Sigl. The control signal SEL_Sig can be two digits in length, but can be implemented in a variety of other ways. In other words, the power supply 2000' controls the amount of inrush current flowing into the charge pump 2〇〇 by the pulse width modulation according to the first voltage control within the 34 8 201238231 41432 pif portion power supply 1 , Use the inrush current controller 3〇〇. FIG. 17 is a flow chart of a power supply method according to other exemplary embodiments. Referring to Fig. 17', the power supply method is performed by a power supply (which includes an internal power supply 100 port for performing a switching operation) and a charge pump 200. In operation S100, when the first enable signal ^17_^1^ is applied to the erase current controller 300, the comparison target signal 8_乂3 is generated. In operation S11, the inrush current controller 3 generates a selection reference voltage VREF_SEL from the supply voltage VDD. In operation S120, the inrush current controller 300 compares the comparison target signal s_vsp with the selection reference voltage VREF_SEL' and generates a pulse width modulation control signal Pul_c〇N. In operation S130, the pulse width modulation control signal Pui_c〇N is applied to the internal power supply 1〇〇, and the pulse generator 500 in the internal power supply 1〇〇 is based on the second enable signal MAX_puLSE_EN and the pulse. The wave width modulation control signal Pul_c〇N uses the I pull operation I to generate a first waveform, that is, a rising waveform. At this time, the slope of the first waveform is changed according to the soft bias signal Sigl, and the soft bias signal Sigl is selected based on the pulse width modulation control signal Pul_CON. In operation sl4, the pulse generator 5 产生 generates a second waveform, that is, a falling waveform, and operates in si5〇 according to the clock signal SMPS_CK of the internal power supply II 1GG by pulling down the first waveform. A sawtooth pulse SAW__PULSE is generated that combines the first waveform with the second waveform. At the same time, in operation S16Q, for the micro-system; to enter 35 201238231 41432pif current, the pulse generator 500 responds to the second enable signal MAX_PULSE_EN and selects the comparison target signal S_V SP or the feedback signal FB_VM as the sawtooth pulse comparison signal COMP_REF . In operation S170, the pulse generator 500 compares the sawtooth pulse SAW_PULSE with the sawtooth pulse comparison signal COMP_REF and generates a switching pulse LSW. The width of the switching pulse LSW is controlled according to the slope of the sawtooth pulse SAW-PULSE. In operation S180, the internal power supply unit 1 generates a first voltage (VSP and VSN) and an inrush current in response to the switching brain wave LSW. In operation S190, the charge pump 2 generates a second voltage from the first voltage and the inrush current. Therefore, before the switching pulse wave LSW having the maximum pulse width pw - 产生 is generated, the operation of the charge pump is enabled in accordance with the amount of the (four) incoming current, so that the latch-up effect of the charge pump 200 is prevented. Figures 18A and ϋ18By are schematic diagrams of waveforms in green display 1000 and timing diagrams of input signals in the power supply face, in accordance with some exemplary embodiments. Referring to Fig. 18A and Fig. (10), in the temple, the ship's wave width axis is used to control the input data. The pulse width is the root of the pulse width. A voltage (VSP): the original supply benefit S-VSP is higher than the selection reference signal VREF SeI! _ the target signal is enabled and generates a second voltage (the energy stored in the VGH and -VGLf pump 102 passes through the control pulse width) :^谷[___Please" force open ==., by means of defense 8 36 201238231 41432pif Referring to FIG. 18B, the energy from the supply voltage VDD is limitedly supplied to the internal power supply according to the soft pulse width PW of the pulse wave. In the capacitor 102 in the device 1, the first voltage (VSP) is gradually increased in the soft pulse period a. When the first voltage (VSP) reaches at least the preset level, the internal power supply 10 0 causes the charge to help The PU 2 〇 is enabled and operates in the soft pulse period a due to the operation of the inrush current controller 300 or the pulse generator 500, and the internal power supply 1 〇〇 supplies the inrush current to the charge pump 200 Only when the energy of the capacitor 1〇2 reaches the preset maximum level, the internal The power supply 100 uses the maximum pulse width PW_MAX of the pulse wave during the maximum pulse period B to increase the inrush current supplied to the charge pump 2〇〇, so that the latch-up effect is prevented. At this time, in different embodiments The pulse width PW and the pulse width pw_MAX can be changed. Figure 19 is a diagram showing the output signal of the power supply according to some exemplary embodiments. °° Referring to Figure 19, when the first voltage (vsp and VSN) When the second voltage (VGH and VGL) is generated from the supply voltage VDD, no effect occurs. The comparison target signal S_VSP is obtained by sampling the first voltage, and the switching pulse LSW reflects the selection reference voltage vref_sel and the comparison target signal S. - comparison result of VSP; in detail, when the enable signal REF_EN is applied to the inrush current controller 300, the switching pulse LSW is applied to the internal power to supply the control terminal of the first switch 1G1 in the H 1GG, The first voltage (vsp) is gradually formed from the soft pulse start point. When the first voltage (vsp) reaches at least the preset level, the internal power supply contacts the soft pulse period 37 201238231 41432pif before the end of the charge The starting point enables the charge pump 200 so that the inrush current gradually flows into the charge pump 200. Therefore, in the case where the flash lock effect does not occur, the first voltage is normally boosted, and the second voltage (VGH) is generated. The VSN and the negative voltage VGL are generated according to the same principles as described above. Figure 20 is a block diagram of a display system 4000 including a power supply 1000, according to some exemplary embodiments. Referring to Figure 2, the display system 4 includes a panel 1 The source driver 3, the gate driver 2, the crying 4, and the power supply 1000. ^ j uses panel 1 to include a plurality of data lines, a plurality of gate lines, and a plurality of pixels connected to the data lines and the gate lines. The source driver 3 generates an analog voltage for driving the data line (or the source line) in the panel 回应 in response to the control signal output from the controller 4 and the voltage output from the power supply unit. The pole driver 2 responds to the control signal and the electric station and voltage outputted by the control & 4, and sequentially drives the interrogation line (or ϋ in the panel 1). 'The analog voltage output from the source driver 113 is supplied to 4 The power supply 1000 of the power supply 1000 is shown in Fig. 17 to provide a boost voltage (i.e., a second voltage) to the source drive D or the gate driver 2. The controller 4 generates a timing guard signal to The data connected to the source driver 2 is connected to the main controller ° " Closed-Motor 2 connection = timing' and control and Figure 21 is based on other exemplary examples. 4_' block diagram. Referring to Figure 2, the display system 38 201238231 41432pif 4000' includes a panel 1 and a display driver 5. The display driver 5 includes a source driver 3', a gate driver 2, a control state 4'', and a power supply. The display driver 5 can be implemented as a single wafer or in a package as illustrated in Figure 21, but the illustrative embodiments are not limited thereto. Figure 22 is an electronic device including a power supply, in accordance with some demonstrative embodiments. Block diagram of the device. 22, the electronic device 5000 includes a power supply 1000, a central processing unit (CPU) 5100, a memory device 5200, an input/output interface unit woo, and a bus bar 5400. The central processing unit 5100 can be controlled through the bus bar 5400. Data exchange between the power supply 1000, the memory device 5200, and the input/output interface unit. The memory device 5200 can be implemented as a non-volatile memory device. The non-volatile memory device can include a plurality of non-volatile memories. Each non-volatile memory cell can be implemented as an electronically erasable rewritable read-only δ ** (Electrically Erasable Programmable Read-Only

Memory, EEPROM, flash mem〇ry, magnetic RAM, MRAM, Spin_Transfer Torque MRAM, MRAM, conductive bridge random Access memory (c〇nductivebridging RAM 'CBRAM), ferroelectric random access memory (Ferr〇electric RAM, FeRAM), phase change random called bidirectional universal memory (OUM) Access memory (phase change 39 201238231 41432pif RAM ' PRAM ), resistive random access memory (Resistive RAM, RRAM or ReRAM), nanotube RRAM, polymer random storage Take memory (Polymer RAM, PoRAM), Nano Floating Gate Memory 'NFGM, holographic memory, Molecular Electronics Memory, or insulation resistance change memory Insulator Resistance Change Memory. The electronic device 5000 can be a personal computer (Pc), a portable computer, a portable mobile sfL device' or a consumer device (c〇nsumer equipment' CE). Portable mobile communication devices include personal digital assistants (PDAs) and portable multimedia players (PMPs). The electronic device 5000 can also be an e-book, a gaming device, a game controller, a navigator, or an electronic musical instrument. The inventive concept can be applied as a hard or soft body, or as a combination of a hard body and a soft body. The inventive concept can also be embodied as a computer readable code on a computer readable medium. A computer-readable record is a data storage device that can be read by the computer system after being stored in (4) (4). Examples of computer readable recording media include read only memory (ROM), random access memory (MM), optical, mechanical, magnetic, floppy, and optical data storage devices. The computer can also record the media can also be distracted _ _ _ system, making the computer readable = knife, way to store and execute. Furthermore, the present invention pertains to the field of the art, and understands the functional programs, codes, and code segments that fulfill the inventive concept. 201238231 41432pif As described above, according to some exemplary embodiments, the pulse width is based on the comparison of the charge signal of the charge=pu and the selected reference voltage, and the amount of the current input to the electric pump of 4 pumps is controlled by the lion. The wave width is controlled to prevent the _ effect from occurring in the power supply. Therefore, the power supply unit does not require an external Schottky diode' to thereby reduce the manufacturing price. On the other hand, the internal Schottky diode can be removed from the power supply, so that the wafer size: two =: the peak current during charge pump operation is reduced, so that the contact pressure is reduced and the power consumption is also reduced. Although the exemplary embodiments have been described in detail and disclosed above, the present invention is inconsistent with the fact that in the spirit and scope defined by the circumstance, such as the form and details. Illustrating. 1 is a block diagram of a power supply according to some exemplary embodiments. FIG. 2 is a detailed block diagram of a drawing according to an exemplary embodiment. T J electricity you should refer to Figure 3 in detail as shown in Figure 2 Figure 4 is a voltage versus time diagram, which shows the operation of Figure 2 ^ inrush current controller. Fig. 5 is a diagram showing the signal timing® according to an example. - (4) The operation of the power supply of the embodiment of the present invention. Fig. 1 is a block diagram of the power supply of the exemplary embodiment. 201238231 41432pif FIG. 7 is a block diagram of a power supply according to other exemplary embodiments. FIG. 8 is a flow diagram of a power supply method, in accordance with some demonstrative embodiments. Figure 9 is a block diagram of a power supply in accordance with other exemplary embodiments. Figure 10 is a detailed block diagram of the power supply shown in Figure 9 in accordance with an illustrative embodiment. Figure 11 is a block diagram of the pulse generator shown in Figure 10, according to an exemplary embodiment. Figure 12 is a schematic diagram showing the internal structure of a pulse wave generator shown in Figure η in accordance with some exemplary embodiments. FIG. 13 is a schematic diagram showing the internal structure of a pulse wave generator illustrated in the drawing according to other exemplary embodiments. 14A through 14C are signal timing diagrams illustrating the operation of a power supply in accordance with other exemplary embodiments. Figure 15 is a timing diagram showing the operation of a power supply in accordance with other exemplary embodiments. Figure 16 is a block diagram of a power supply in accordance with other exemplary embodiments. FIG. 17 is a flow chart of a power supply method according to other exemplary embodiments. 18A and 18B are schematic diagrams of waveforms in a power supply and a timing diagram of an input signal in the power supply 8 201238231 41432pif, in accordance with some exemplary embodiments. 19 is a diagram of an output signal of a power supply, in accordance with some demonstrative embodiments. Figure 20 is a block diagram of a display system including a power supply, in accordance with some demonstrative embodiments. 21 is a block diagram of a display system including a power supply, in accordance with other exemplary embodiments. Figure 22 is a block diagram of an electronic device including a power supply, in accordance with some demonstrative embodiments. [Main component symbol description] 1 : Panel 2, 2': Gate driver 3, 3': Source driver 4, 4': Controller 5: Display driver 100, 100': Internal power supply 101 First switch 102 inductor 103 load circuit 150 first voltage generator 200 charge pump 300, 300', 300": inrush current controller 310: first sampling block 311: second switch 43 201238231 41432pif 320: reference voltage generator 330: first generation block 340: selection block 350: first comparator 400: timing controller 500, 500', 500": pulse generator 501: inverter 502: second comparator 510: second generation block 520: first waveform generator 521: first circuit 522: bias selection circuit 523: stabilization circuit 524: pull-up circuit 525: memory 530: second waveform generator 531: comparator 532: latch circuit 533: pull-down circuit 540: second circuit 541: decoder 542: level shifter 550: sawtooth pulse generator 551: sawtooth pulse output terminal 8 201238231 41432pif 560: sawtooth pulse wave comparison signal generator 600: pulse wave module 650: Control signal generation 1000, 1100, 1200, 2000, 2000': power supply 4000, 4000': display system 5000: electronic device 5100 · central processing unit 5200: memory device 5300: input/output interface unit 5400: bus A, Soft_Pulse: soft pulse period B, Max_Pulse: maximum pulse period BIAS: bias signal COMP_REF: sawtooth pulse comparison signal COMP_OUT: comparison result COMP_OUT1: first comparison result COMPJ3UT2: second comparison result CP_CK, SMPS_CK: Clock signal CP_Sig Bu CP_Sig2: Enable signal FB_VM: Feedback signal f_SAW ··Drop signal GND: Ground terminal LSW: Switch pulse wave LSW1: First switching pulse 45 201238231 41432pif LSW2 : Second switching pulse MAX_PULSE_EN: Second Enable signal MUX: multiplexer Pull, Pul2: pulse wave

Pull_Sel: pulse width modulation control signal of the first logic level (low level)

Pul2_Sel: pulse width modulation control signal of the second logic level (high level)

Pul_CON: Pulse width modulation control signal

Pul_CONl: first pulse width modulation control signal

Pul_CON2: second pulse width modulation control signal PW1: first pulse width PW2: second pulse width PW_Max: maximum pulse width REF_EN: first enable signal REF_SEL: level selection signal SEL_Sig: control signal SAW_CMP_REF: Serrated pulse reset reference SAW_PULSE : sawtooth pulse SAW_PULSE@VREF : sawtooth pulse generated according to reference voltage SAW_PULSE@VREF1 : first sawtooth pulse SAW_PULSE@VREF2 : second sawtooth pulse SAW_REF : sawtooth pulse basic signal SAW_REF@ VREF1: Generated according to the secondary reference voltage VREF1 8 201238231 41432pif Sawtooth pulse basic signal SAW_REF@VREF2: Sawtooth pulse basic signal SEL generated according to the secondary reference voltage VREF2: Reference voltage selection signal SEL_SW1, SEL_SW2: Switch Sigl : soft bias signal Sig2: maximum bias signal S_VSP: comparison target signal VDD: supply voltage VGH: second voltage (second positive voltage) VGL: second voltage (second negative voltage) VREF1, VREF2: secondary reference voltage VREF_1 SELECTION: second reference voltage signal VREF-2 SELECTION: second reference voltage signal VREF_SEL: select reference voltage VREF_SEL1: first main To reference voltage VREF_SEL2: second main reference voltage VREF-SMPS: internal reference voltage Rstring: resistor string VSN: first voltage (first negative voltage) VSP: first voltage (first positive voltage) X: orthodontic pulse wave Output 47

Claims (1)

201238231 41432pif VII. Patent application scope: 1. A power supply device, comprising: an internal power supply, comprising a first voltage generator, wherein the first voltage generator is configured to generate a signal according to a pulse width modulation control signal An electric charge pump for receiving the first voltage and generating a second voltage; and an inrush current controller connected between the charge pump and the internal power supply and configured to be based on the target signal And selecting a reference voltage to generate the pulse width modulation control signal. 2. The power supply device of claim 1, wherein the inrush current controller comprises: a first sampling circuit for dividing the first voltage in response to the first enable signal and based on Deriving the target signal; the reference voltage generator is configured to output the selection reference voltage in response to the reference voltage selection signal; and the first comparator is configured to compare the target signal with the selection reference Voltage 'and outputs the pulse width modulation control signal. 3. The power supply device of claim 2, wherein the reference voltage generator comprises: a first generation circuit that divides the supply voltage by a plurality of resistors, and according to a voltage divider Supplying a voltage to generate a plurality of primary reference voltages; and selecting a circuit that responds to the reference voltage selection signal and turns the said (D 201238231 414 izizifif the wiper as the selected reference voltage. The power supply device according to Item 1, wherein a pulse wave having a different pulse width is respectively applied to the =:, the supplier, and the internal power supply responds to the wave generated by the inrush current. Width modulation control signal, and selecting one of the pulse waves, and generating the first voltage. 5. The power supply device of claim w, wherein the first voltage generator is used to generate a back The internal power supply includes a pulse wave generator, and the pulse wave generator generates a pulse wave according to the feedback signal. The pulse wave generator includes, For generating a graded pulse wave having a slope, the mineral tooth wave modulating the control signal and the second enable signal according to the pulse width; the sawtooth pulse comparison signal generator, in response to the a second enable signal to output the target signal or the feedback signal as a sawtooth pulse comparison signal; and a second comparator for comparing the sawtooth pulse to the sawtooth pulse to compare the signal 6. The power supply device of claim 5, wherein the miscellaneous pulse generator comprises: a second generating circuit that divides the internal reference voltage by a plurality of resistors, And generating a plurality of secondary reference voltages according to the voltage division; a first waveform generator connected between the second generation circuit and the sawtooth pulse output end, according to the second enable signal The majority of the times 49 201238231 41432pif selects the voltage 'and pulls the ground voltage to generate the first waveform by responding to the voltage selected from the plurality of minor: the towel; the tooth waveform, the shape generator Connected to the second generating circuit and between the station and the terminal, and pull down the voltage of the terminal by responding to the falling signal to generate a second waveform, the falling signal is a t-shaped thief Generating, the down signal is based on the sampling household, and the sampling voltage is according to the power supply device according to the internal power supply, and the power supply device described in item 6 of the patent application scope. The first waveform generator includes: a Π circuit that outputs a maximum bias signal as a soft signal, or a fr = a first enable signal, in response to the pulse width control signal a mineral tooth wave substantially sfl number; a pull-up circuit that pulls up the electrical output of the mineral tooth wave wave in response to the sawtooth pulse wave basic signal; and a memory 'connected to the weaving pulse wave (4) And storing the pull-up signal between the ground terminal and generating the first waveform. 8. The power supply device according to claim 6, wherein the first waveform generator comprises: ^ a first circuit that selects and outputs a number of responses in response to the pulse width modulation control signal. The secondary circuit (4) is the soft bias signal; 8 50 201238231 The second circuit selects and outputs one of the plurality of secondary reference voltages as the maximum bias in response to the level selection signal. a voltage signal; a bias circuit that outputs the soft bias signal* or the maximum bias signal as a sawtooth pulse basic signal in response to the second enable signal; and an it circuit that responds The sawtooth pulse wave fundamentally pulls up the ground voltage to generate the first waveform. [The power supply device of claim 6, wherein the second waveform generator comprises: a second sampling circuit that performs a reset operation according to the sawtooth pulse wave and the sawtooth pulse wave reset reference, and And outputting the falling signal; and a pull-down circuit that pulls down the voltage of the output end of the sawtooth pulse wheel in response to the pull-down signal. Ιυ. The power supply device of claim 5, wherein the mine 较 较 产生 产生 在 在 在 在 在 在 在 在 在 在 在 软 软 软 软 软 软 软 软 软 软 软 软 软 软 软The tooth pulse compares the signal, and outputs the feedback signal 'as the job pulse comparison signal when the maximum pulse wave responds to the second enable signal. 51