KR101852065B1 - Power supply apparatus for latch-up free charge pump and method there-of - Google Patents

Abstract

A power supply and a power supply method are disclosed. The present invention uses the pulse width modulation to compare the output signal of the internal power supply with the selection reference voltage and controls the pulse width according to the result. And a power supply apparatus and method for preventing latch-up by adjusting the amount of input current inputted to the charge pump in the power supply unit based on the pulse width.

Description

[0001] POWER SUPPLY APPARATUS FOR LATCH-UP FREE CHARGE PUMP AND METHOD THERE-OF [0002]

The present invention relates to a power supply, and more particularly, to a power supply including a charge pump.

Generally, electrical and electronic devices require a DC power supply that converts commercial AC power to DC voltage so that the device can operate. Switching mode power supply (SMPS), which is high efficiency and small and light in weight, is mainly used as the DC power supply.

The DC power supplied from the SMPS is applied to each system component located in the electronic device. However, since the power supplied from the SMPS is limited to 5V, 3.3V, and 12V, a DC voltage supplied from the SMPS is applied to the power supply of the electronic device in order to generate a voltage level required for components such as a chipset and a memory A charge pump for boosting the voltage to an appropriate DC voltage level is provided.

However, when the current distribution is not uniform due to environmental conditions such as a design error and an ambient temperature difference, for example, there is a possibility that a component is damaged when a latch up due to a peak current occurs.

Latch-up is a phenomenon in which a circuit breaks due to undesirable currents flowing in the circuit more than a few hundred [mA]. For example, a parasitic PNPN junction (also referred to as a thyristor structure) may be generated between NMOS and PMOS adjacent to each other in a device having a CMOS structure, and an inrush current may flow through the thyristor structure. Therefore, when the input and output voltage exceed the rated voltage and the inrush current (or leakage current) flows to the internal device or the voltage of the power supply terminal exceeds the rated voltage and the internal device is in the breakdown state, a large inrush current flows, It can be destroyed. In order to prevent such latch-up, external Schottky diodes are used in many cases. Internal Schottky diodes are used in the integrated circuits.

However, if an external Schottky diode is used, the cost of the module may increase and the price competitiveness may be deteriorated. If the internal Schottky diode is used, the chip size may not be competitive due to the area occupied by the chip. Therefore, there is a need for a power supply system capable of preventing latch-up without using external Schottky diodes or internal Schottky diodes.

SUMMARY OF THE INVENTION The present invention provides a power supply device capable of preventing a latch-up caused by a peak current at the moment when a charge pump operation is started, and a method thereof.

According to an aspect of the present invention, there is provided a power supply apparatus including a first differential voltage generator for generating a first differential voltage and a feedback signal by a switching operation from a supply voltage, An internal power supply unit including a pulse generating unit for generating and using the pulse for the switching operation; A charge pump for receiving the first differential voltage and generating a second differential voltage; And an inrush current controller connected between the charge pump and the internal power supply to compare the comparison target signal with a selected reference voltage and to control pulse width modulation with a pulse width modulation control signal reflecting the comparison result.

Wherein the input current controller comprises: a first sampling unit for dividing the input signal from a plurality of resistor connections connected between the first differential voltage and a ground terminal when the first enable signal is applied, A reference voltage generator for outputting the selection reference voltage in response to a reference voltage selection signal; And a first comparator for comparing the comparison target signal with the selection reference voltage to output the pulse width modulation control signal.

Wherein the pulse generator comprises: a square wave generator for generating a square wave in which a slope is adjusted in response to the pulse width modulation control signal and the second enable signal; A square wave comparison signal generator for outputting the comparison target signal or the feedback signal as a square wave comparison signal in response to the second enable signal; And a second comparator for comparing the square wave and the square wave comparison signal and outputting the comparison pulse as a switching pulse.

The square wave generating unit may include a second generating block for dividing a voltage from a plurality of resistors connected between an internal reference voltage and a ground terminal to generate a plurality of second reference voltages; And a second waveform generator coupled to the second generating block and the rectangular wave output terminal for pulling up from the ground voltage in response to any one of the plurality of second reference voltages selected by the second enable signal, A first waveform generator for generating a first waveform; And generating a second waveform by pulling down from the square wave output terminal voltage in response to a polling signal sampled according to a clock signal of the internal power supply, the second voltage being generated between the second generating block and the square wave output terminal And a second waveform generator.

Wherein the first waveform generator comprises: a bias circuit that outputs a soft bias signal or a predetermined maximum bias signal selected by the pulse width modulation control signal among the plurality of second reference voltages, as a bias signal in response to the second enable signal; A pull-up circuit for pulling up the square wave output terminal voltage in response to the bias signal; And a storage unit coupled to the square wave output terminal and the ground terminal to store the pull-up signal to generate a first waveform.

According to another aspect of the present invention, there is provided a method of supplying power to a power supply including an internal power supply and a charge pump according to another embodiment of the present invention. When a first enable signal is applied, Generating a first sampling signal from the first differential voltage generated in the first differential voltage; Generating a selected reference voltage divided in response to a reference voltage selection signal from a plurality of resistor connections connected between a supply voltage terminal and a ground terminal; Comparing the first sampling signal with the selection reference voltage and outputting the comparison result as a pulse width modulation control signal; Outputting, as a switching pulse, a pulse generated by the timing controller and selected in accordance with the pulse width modulation control signal among pulses having a plurality of predetermined pulse widths applied to the internal power supply unit; Adjusting the amount of the input current that is input to the charge pump by the switching operation of the internal power supply unit according to the switching pulse; And generating the secondary voltage by the charge pump.

The power supply apparatus and method according to the embodiment of the present invention controls the pulse width by reflecting the result of comparing the input signal of the charge pump with the selection reference voltage so as to prevent the latch-up by controlling the input current inputted to the charge pump . As a result, it is not necessary to use an external Schottky diode, thus ensuring the cost competitiveness of the module and eliminating the internal Schottky diode, thereby securing the chip size competitiveness. In addition, it can reduce instantaneous peak current at the time of charge pumping, reduce the stress applied to the contact, and at the same time, can achieve power saving effect.

BRIEF DESCRIPTION OF THE DRAWINGS A brief description of each drawing is provided in order to provide a thorough understanding of the drawings recited in the description of the present invention.
1 is a block diagram illustrating a power supply apparatus according to an embodiment of the present invention.
2 is a block diagram specifically showing the power supply device shown in FIG.
3 is a block diagram showing the inrush current controller shown in FIG. 2 in detail.
4 is a graph of voltage versus time illustrating the operation of the inrush current controller shown in FIG.
5 is a signal timing diagram illustrating operation of a power supply according to an embodiment of the present invention.
6 is a block diagram of a power supply according to another embodiment of the present invention.
7 is a block diagram of a power supply according to another embodiment of the present invention.
8 is a flowchart illustrating a power supply method according to another embodiment of the present invention.
9 is a block diagram illustrating a power supply according to another embodiment of the present invention.
10 is a block diagram specifically showing the power supply device shown in FIG.
11 is a block diagram showing the internal structure of the pulse generator shown in FIG.
12 is a block diagram illustrating an internal configuration of the pulse generator shown in FIG. 11 according to an embodiment of the present invention.
13 is a block diagram showing an internal configuration according to another embodiment of the pulse generator shown in FIG.
14 is a signal timing diagram illustrating operation of a power supply according to another embodiment of the present invention.
15 is a signal timing diagram illustrating the operation of a power supply according to another embodiment of the present invention.
16 is a block diagram of a power supply according to another embodiment of the present invention.
17 is a flowchart of a power supply method according to another embodiment of the present invention.
18 is a timing chart of waveforms and applied signals of the power supply device according to the embodiment of the present invention.
19 is a graph of output signals of a power supply device according to an embodiment of the present invention.
20 is a block diagram of a display device including a power supply device according to an embodiment of the present invention.
21 is a block diagram of a display device including a power supply device according to another embodiment of the present invention.
22 is a block diagram of an electronic device including a power supply device according to an embodiment of the present invention.

Specific structural and functional descriptions of embodiments according to the concepts of the present invention disclosed in this specification or application are merely illustrative for the purpose of illustrating embodiments in accordance with the concepts of the present invention, The examples may be embodied in various forms and should not be construed as limited to the embodiments set forth herein or in the application.

Embodiments in accordance with the concepts of the present invention can make various changes and have various forms, so that specific embodiments are illustrated in the drawings and described in detail in this specification or application. It is to be understood, however, that it is not intended to limit the embodiments according to the concepts of the present invention to the particular forms of disclosure, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first and / or second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are intended to distinguish one element from another, for example, without departing from the scope of the invention in accordance with the concepts of the present invention, the first element may be termed the second element, The second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, the terms "comprises ", or" having ", or the like, specify that there is a stated feature, number, step, operation, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as ideal or overly formal in the sense of the art unless explicitly defined herein Do not.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings.

1 is a block diagram illustrating a power supply apparatus according to an embodiment of the present invention.

Referring to FIG. 1, a power supply 1000 includes an internal power supply 100, a charge pump 200, an input current controller 300, and a timing controller 400.

The internal power supply unit 100 is a device that controls the flow of the incoming current according to the pulse width by performing a switching operation in response to a clock (SMPS_CK) and a pulse applied from the timing controller 400. The internal power supply unit 100 receives the supply voltage VDD and generates a primary voltage. The generated primary voltage includes a positive voltage and a negative voltage. For convenience of explanation, it is assumed that the first height voltage is VSP and the first sub voltage is VSN. The internal power supply unit 100 used in the present invention will be described by taking a switching mode power supply (SMPS) as an example, but it can be variously implemented by using a pulse width modulation method according to an embodiment.

The charge pump 200 repeatedly performs a charging step (or a charging operation) and a discharging step (or a discharging operation) in response to a clock signal CP_CK applied from the timing controller 400, And outputs the second voltage. The secondary voltage generated at this time includes a high voltage (Positive Voltage) and a negative voltage (Negative Voltage). For convenience of explanation, let us say that the generated second high voltage is VGH and the second negative voltage is VGL. The charge pump may be variously implemented according to the embodiment.

The inrush current controller 300 receives the first differential voltage VSP output from the internal power supply unit 100 and input to the charge pump 200 and compares the first differential voltage VSP with the selected reference voltage VREF_SEL to generate a pulse width modulation control signal Pul_CON).

The timing controller 400 applies a predetermined plurality of pulses having different pulse widths to the internal power supply unit 100. In response to the pulse width modulation control signal Pul_CON, any one of the plurality of pulses Pul1 and Pul2 One is used as the switching pulse LSW to the internal power supply unit to control the amount of the input current to be input to the charge pump 100.

2 is a block diagram specifically showing the power supply device shown in FIG.

Referring to FIG. 2, the power supply apparatus 1000 includes an internal power supply 100, a charge pump 200, an input current controller 300, and a timing controller 400. For convenience of description, differences from FIG. 1 will be mainly described.

The internal power supply unit 100 includes a first voltage generation unit 150 and a pulse generation unit 500. The first voltage generation unit 150 includes a first switching device 101, And a load circuit (103).

The internal power supply 100 operates as follows. The switching pulse LSW issued from the pulse generating unit 500 is applied to the control terminal of the first switching device 101. [ When the first switching device 101 is turned on, energy is accumulated from the supply voltage VDD to the inductor 102. [ When the first switching device 101 is turned off, the energy stored in the inductor 102 is discharged to the load 103. [ When this operation is repeated with a constant period, the primary voltages VSP and VSN are generated. The feedback signal FB_VM obtained by dividing the first differential voltage is applied to the pulse generator 500 to generate the switching pulse LSW.

The input current controller 300 includes a sampling unit 310, a reference voltage generation unit 320, and a comparison unit 350.

When the first enable signal REF_EN is not applied to the inrush current controller 300, the pulse generator 500 generates a predetermined arbitrary signal REF_EN based on the feedback signal FB_VM connected to the first differential voltage generator 150 And applies the switching pulse LSW to the primary voltage generator 150. [ However, when the first enable signal REF_EN is applied to the inrush current controller 300, the inrush current controller 300 generates the pulse width modulation control signal Pul_CON. The pulse width modulation control signal Pul_CON selects either one of the first pulse Pul1 and the second pulse Pul2 having different pulse widths and applies the selected pulse to the pulse generator 500. [ The pulse applied to the pulse generator 500 is generated by a switching pulse LSW for controlling the amount of the input current supplied to the charge pump 200 through the pulse width modulation.

A charge pump 200 boosts the first differential voltages VSP and VSN controlled by the controlled pulses in the internal power supply 100 to output second differential voltages VGH and VGL. At this time, the charge pump 200 is enabled by the switching pulse LSW to generate a secondary voltage before the primary voltage reaches a predetermined maximum output. The configuration and operation of the inrush current controller 300 will be described later in more detail with reference to FIG.

FIG. 3 is a block diagram showing the inrush current controller 300 shown in FIG. 2 in detail.

Referring to FIG. 3, the input current controller 300 includes a first sampling unit 310, a reference voltage generating unit 320, and a first comparing unit 350.

When the first enable signal REF_EN is applied, the first sampling unit 310 divides the voltage from a plurality of resistors connected between the first differential voltage and the ground terminal, and outputs the divided signal to the comparison target signal S_VSP. The first sampling unit 310 is connected between the first differential voltage output terminal VSP or VSN and the ground terminal GND and includes a second switching device 311 and a plurality of resistors. When the first enable signal REF_EN is applied to the control terminal of the second switching device 311, the sampling unit 310 outputs the first signal REF_EN, which is output from the internal power supply unit 100 and is input to the charge pump circuit 200, Divides the voltage to output the comparison object signal S_VSP.

However, the present invention is not limited to the above example. The first differential voltage VSP may be directly used as a comparison target signal according to an embodiment of the present invention, and may be divided and divided according to a comparison reference voltage VREF_SEL level It is possible.

The reference voltage generator 320 outputs the selection reference voltage VREF_SEL in response to the reference voltage selection signal SEL. The reference voltage generator 320 generates a plurality of first reference voltages VREF_SEL_n for detecting the first voltage and includes a first generating block 330 and a selecting block 340.

The first generating block 330 generates a plurality of first reference voltages VREF_SEL_n by dividing the voltage from a plurality of resistor connections connected between the supply voltage terminal VDD and the ground terminal GND. For example, assuming that the target reference value is set to two cases, the first generation block generates the reference voltage 1 (VREF_SEL1) having the first target reference value and the reference voltage 2 (VREF_SEL2) having the second target reference value. At this time, the target reference value may be set to two or more according to the embodiment.

The selection block 340 outputs one of the plurality of first reference voltages VREF_SEL_n to the selection reference voltage VREF_SEL in response to the reference voltage selection signal SEL and is connected to each of the reference voltage output terminals And includes a plurality of switching elements SEL_SW1 and SEL_SW2. The switching element SEL_SW outputs one selected reference voltage VREF_SEL corresponding to the reference voltage selection signal SEL when the first reference voltage generated in the generation block 330 is more than two. In this example, the reference voltage selection signal SEL selects the reference voltage 1 (VREF_SEL1) or the reference voltage 2 (VREF_SEL2) and outputs it as the selection reference voltage VREF_SEL. The switching element SEL_SW may be variously implemented according to the embodiment.

The first comparator 350 includes a comparator. The first comparator 350 receives and compares the sampled signal S_VSP with the selection reference voltage VREF_SEL. The first comparator 350 outputs a low pulse width modulation control signal Pul_CON when the comparison signal S_VSP is lower than the selection reference voltage VREF_SEL. However, if the comparison target signal S_VSP is higher than the selected reference voltage VREF_SEL, the first comparator 350 outputs High as the pulse width modulation control signal Pul_CON.

4 is a voltage time graph showing the operation of the inrush current controller 300 shown in FIG.

For example, in FIG. 4, the first comparator 350 outputs a low pulse width modulation control signal Pul_CON when the compared signal S_VSP is lower than the selected reference voltage VREF_SEL. On the other hand, when the comparison target signal S_VSP is higher than the selected reference voltage VREF_SEL, the first comparator 350 outputs a High signal as the pulse width modulation control signal Pul_CON.

For example, when the first reference voltage VREF_SEL1 is input to the first comparator 350 as the selection reference voltage VREF_SEL, the first comparator 350 outputs the first pulse width modulation control signal Pul_CON1 . Meanwhile, when the second reference voltage VREF_SEL2 is input to the first comparator 350 as the selection reference voltage VREF_SEL, the first comparator 350 outputs the second pulse width modulation control signal Pul_CON2. The pulse width modulation control signal Pul_CON1 or Pul_CON2 is applied to the pulse width modulation control unit 500 in the internal power supply unit 100. [ At this time, the pulse width modulation control signal Pul_CON is determined according to the reference voltage selection signal SEL.

The pulse width modulation controller 500 applies the first pulse Pul1 to the pulse generator 500 when the received pulse width modulation control signal Pul_CON is high. However, if the received pulse width modulation control signal Pul_CON is low, the second pulse Pul2 having a pulse width different from that of the first pulse Pul1 is applied to the pulse generator 500.

As a result, the first differential voltages VSP and VSN of the internal power supply unit 100 are gradually generated in the soft pulse interval of the first pulse Pul1 or the second pulse Pul2 to prevent the peak current The clock signal CP_Sig is applied to the charge pump at the front end of the soft-pulse period. When the clock signal CP_Sig is applied and operation is enabled, an input current (Inrush Current) is gradually input to the charge pump 200, latch-up is prevented, and the voltage is normally converted to generate the secondary voltages VGH and VGL . Here, the soft pulse refers to a case where the pulse has a pulse width smaller than the maximum pulse width (Max_width) within a preset range. That is, when the primary voltages VSP and VSN are generated in the internal power supply unit 100 and the secondary voltages VGH and VGL are generated in the charge pump 200, From when the second voltage is stabilized.

The operation of controlling the inrush current based on the above-described pulse width modulation control will be described in detail in Fig.

5 is a signal timing diagram illustrating operation of a power supply according to an embodiment of the present invention.

5, the internal power supply unit 100 and the charge pump 200 receive clocks SMPS_CK and CP_CK of different frequencies generated from the timing controller 400, respectively.

First, the inrush current controller 300 branches and samples the first differential voltage VSP output from the internal power supply unit 100 when the enable signal REF_EN is applied, and compares the first reference voltage VREF_SEL with the selected reference voltage VREF_SEL And compares the level of the target signal S_VSP. The timing controller 400 controls the timing controller 400 so that the first pulse Pul1 (for example, the soft pulse width PW1, the maximum pulse width PW_Max) and the second pulse Pul2 (for example, the soft pulse width PW2, Width PW_Max). When the timing controller 400 applies the first pulse Pul1 and the second pulse Pul2 to the internal power supply unit 100, the pulse generating unit 500 generates a pulse based on the pulse width modulation control signal Pul_CON The first pulse (Pul1) or the second pulse (Pul2) is selected and applied to the control terminal of the first switching device (101). As a result, the pulse width modulation control signal (Pul_CON) controls the switching operation in the internal power supply unit 100, so that the first differential voltage (VSP, VSN) of the internal power supply unit (100) 200 are enabled (Charge Pump Operation Period). That is, the charge pump 200 is operated before the pulse LSW having the maximum pulse width PW_Max in the internal power supply unit 100 is applied to the control terminal of the first switching device 101, Since the charge pump 200 gradually increases, a large amount of current does not flow instantaneously into the charge pump 200, thereby preventing latch-up.

At this time, when the reference voltages having the target reference values are two (VREF_SEL1, VREF_SEL2), the pulse width modulation control signals Pul_CON1 and Pul_CON2 may be generated corresponding to the respective reference voltages VREF. Accordingly, the enable signal CP_Sig for the charge pump operation also changes to CP Sig1 or CP Sig2, respectively. However, the pulse width, the number of reference voltages, and the level of the reference voltage are not limited to the above-described embodiments, but may be variously implemented according to the embodiments.

6 is a block diagram of a power supply according to another embodiment of the present invention.

Referring to FIG. 6, the power supply 1100 includes an internal power supply 100, a charge pump 200, an input current controller 300 ', and a timing controller 400. For convenience of description, differences from the embodiment of the present invention shown in Figs. 2 and 3 will be mainly described.

The inrush current controller 300 'may use a negative voltage (VSN) of the primary voltage as an input signal unlike in FIG. That is, when the enable signal REF_EN is applied to the inrush current controller 300 ', it samples (S_VSN) by using the negative voltage (VSN) of the first differential voltage generated in the internal power supply unit 100 as an input signal, And is compared with the selection reference voltage VREF_SEL. And the comparison result is applied to the pulse generating unit 500 of the internal power supply unit 100 to control the amount of the incoming current in the charge pump 200. At this time, the operation of the inrush current controller 300 'is the same as the principle shown in FIG.

7 is a block diagram of a power supply according to another embodiment of the present invention.

Referring to FIG. 7, the power supply 1200 includes an internal power supply 100, a charge pump circuit 200, an input current controller 500, and a timing controller 400 '. For convenience of description, differences from the embodiment of the present invention shown in Figs. 2 and 3 will be mainly described.

The inrush current controller 500 compares the comparison target signal S_VSP with the selection reference voltage VREF_SEL to generate the pulse width modulation control signal Pul_CON. The operation of the inrush current controller 500 is the same as that shown in Fig. However, the pulse width modulation control signal Pul_CON is applied to the timing controller 400 'instead of being applied to the pulse generator 500 as in the embodiment of FIGS.

That is, the timing controller 400 'stores information on two or more predetermined pulse widths, and when the pulse width modulation control signal Pul_CON is applied, a pulse Pul having a corresponding pulse width is supplied to the internal power supply (400).

As a result, the pulse (Pul) is applied to the internal power supply unit 100 through the switching pulse LSW through the pulse generator 500, so that the first differential voltages VSP and VSN are gradually formed, and the switching pulses LSW The charge pump enable signal CP_Sig is applied to the charge pump 200 at the preceding stage of the soft pulse interval. Thereafter, the input current is gradually input to the charge pump 200, latch-up is prevented, and the boost-up operation is normally performed to generate the secondary voltage.

8 is a flowchart illustrating a power supply method according to another embodiment of the present invention.

Referring to FIG. 8, when the supply voltage VDD is input, the internal power supply 100 using the pulse width modulation generates it as the boosted primary voltage VSP. The first differential voltage VSP is generated through the charge pump 200 to a higher voltage and a second differential voltage VGH. At this time, the negative voltage is generated by the above process (GND, VSN, or VGL). The internal power supply 100 using the pulse width modulation may be a switching mode power supply (SMPS), but may be variously implemented according to the embodiment. Also, the charge pump 200 may be variously implemented according to the embodiment.

At this time, when the first voltage is generated in the internal power supply 100 using the pulse width modulation and input to the charge pump 200, the first voltage is branched (S10). The branched first voltage is sampled when the first enable signal REF_EN is applied (S11). At this time, the sampling step may sample the inputted first primary voltage as it is or may be sampled by voltage conversion through a divide according to the selected reference voltage VREF_SEL, but it is not limited to this, . ≪ / RTI > Also, the first differential voltage may use a high voltage (VSP) or a negative voltage (VSN).

Generates at least one first reference voltage VREF_SEL_n at the supply voltage S12 and outputs any one of the first reference voltages VREF_SEL_n as the selection reference voltage VREF_SEL according to the reference voltage selection signal SEL (S13).

Compares the comparison target signal S_VSP or S_VSN with the level of the selection reference voltage VREF_SEL, and outputs the pulse width modulation control signal Pul_CON. If the sampled comparison signal S_VSP or S_VSN has a level lower than the selected reference voltage VREF_SEL, the comparator circuit 50 outputs the low level LOW as the pulse width modulation control signal Pul_CON and the comparison target signal S_VSP or S_VSN, (HIGH) is output as the pulse width modulation control signal Pul_CON (S14) when the voltage VREF_SEL is higher than the selection reference voltage VREF_SEL.

The internal power supply 100 controls the pulse width according to the pulse width modulation control signal Pul_CON (S15). In one embodiment, the pulse width control selects the first pulse Pul1 generated by the timing controller 400 when the pulse width modulation control signal Pul_CON is low and outputs the pulse width modulation control signal Pul_CON Is high, the second pulse Pul2 generated in the timing controller 400 can be selected.

In another embodiment, when the pulse width modulation control signal Pul_CON is low, the timing controller 400 'selects a predetermined first pulse Pul1 and applies it to the internal power supply 100, When the pulse width modulation control signal Pul_CON is high, the timing controller 400 'may select a predetermined second pulse Pul2 and apply it to the internal power supply unit 100. [

In each of the above-described embodiments, the amount of incoming current is controlled by the switching pulse LSW output to the charge pump 200 (S16). That is, the charge pump enable signal CP_Sig is applied to the charge pump 200 from the beginning of the soft pulse section, and the amount of the input current is gradually increased to generate the second voltages VGH and VGL without latch-up by the peak current (S17).

9 is a block diagram illustrating a power supply according to another embodiment of the present invention.

Referring to FIG. 9, the power supply 2000 includes an internal power supply 100, a charge pump 200, an input current controller 300, and a timing controller 400. For convenience of description, differences from the embodiments of the present invention shown in FIGS. 2 and 3 will be mainly described.

The internal power supply unit 100 is a device in which the flow of the incoming current is controlled according to the width of the pulse by performing a switching operation in response to a clock (SMPS_CK) applied from the timing controller 400. The internal power supply unit 100 includes a primary voltage generator 150 and a pulse generator 500.

The first voltage generator 150 receives the supply voltage VDD and generates the first and second differential voltages VSP and VSN and the feedback signal FB_VM. The generated primary voltage includes a positive voltage and a negative voltage. The pulse generating unit 500 receives the feedback signal FB_VM and the internal power supply unit clock signal SMPS_CK to generate a switching pulse LSW and applies the switching pulse LSW to the primary voltage generating unit 150 again.

 The input current controller 300 receives the first differential voltage VSP and the first enable signal RER_EN that are output from the internal power supply unit 100 and input to the charge pump 200 and receive the selected reference voltage VREF_SEL And outputs the pulse width modulation control signal Pul_CON and the comparison target signal S_VSP to the internal power supply unit 100. [ At this time, the pulse width modulation control signal Pul_CON is applied to the pulse generator 500 as a signal for selecting the soft bias signal Sig1 related to the slope of the rectangular wave to adjust the width of the pulse.

A charge pump 200 boosts the first differential voltages VSP and VSN controlled by the controlled pulses in the internal power supply 100 to output second differential voltages VGH and VGL. At this time, the charge pump 200 is enabled by the switching pulse LSW to generate a secondary voltage before the primary voltage reaches a predetermined maximum output.

10 is a block diagram specifically showing the power supply apparatus shown in FIG.

Referring to FIG. 10, the power supply 2000 includes an internal power supply 100, a charge pump 200, an input current controller 300, and a timing controller 400. For convenience of explanation, differences from FIG. 9 will be mainly described.

The internal power supply unit 100 includes a primary voltage generator 150 and a pulse generator 500. The first voltage generation unit 150 includes a first switching device 101, an inductor 102, and a load circuit 103. The internal power supply 100 operates as follows. The switching pulse LSW issued from the pulse generating unit 500 is applied to the control terminal of the first switching device 101. [ When the first switching device 101 is turned on, energy is accumulated from the supply voltage VDD to the inductor 102. [ When the first switching device 101 is turned off, the energy stored in the inductor 102 is discharged to the load 103. [ If this operation is repeated with a certain period (LSW), the primary voltages VSP and VSN are generated. The feedback signal FB_VM obtained by dividing the first differential voltage is applied to the pulse generator 500 to generate the switching pulse LSW.

The input current controller 300 includes a sampling unit 310, a reference voltage generation unit 320, and a first comparison unit 350.

When the first enable signal REF_EN is not applied to the inrush current controller 300, the pulse generator 500 of the internal power supply unit generates the feedback signal FB_VM based on the feedback signal FB_VM connected to the first voltage generator 150 And applies the preset arbitrary switching pulse LSW to the first voltage generator 150. [ However, when the first enable signal REF_EN is applied to the inrush current controller 300, the inrush current controller 300 generates the pulse width modulation control signal Pul_CON. The pulse width modulation control signal Pul_CON is applied to the pulse generator 500 as a signal for selecting the soft bias signal Sig1 related to the slope of the square wave to adjust the width of the pulse. The soft bias signal Sig1 is a signal based on the second reference voltage signal VREF_1_SELECTION or VREF_2_SELECTION.

 The pulse generating unit 500 generates a switching pulse LSW for controlling the amount of the input current supplied to the charge pump 200 through pulse width modulation. Hereinafter, the operation principle of the pulse generator 500 will be described in detail with reference to FIG.

11 is a block diagram showing the internal structure of the pulse generator shown in FIG.

Referring to FIG. 11, the pulse generator 500 includes a square wave generator 550, a square wave comparison signal generator (MUX) 560, and a second comparator 502.

The square wave generator 550 generates a square wave SAW_PULSE in response to the pulse width modulation control signal Pul_CON and the second enable signal MAX_PULSE_EN. At this time, the clock signal SMPS_CK of the internal power supply, the internal reference voltage VREF_SMPS, and the supply voltage VDD may be used for square wave generation.

The square wave comparison signal generator (MUX) 560 outputs the comparison signal S_VSP or the feedback signal FB_VM in response to the second enable signal MAX_PULSE_EN as the square wave comparison signal COMP_REF.

The second comparator 502 receives the square wave SAW_PULSE to the non-inverting terminal + and the rectangular wave comparing signal COMP_REF to the inverting terminal -, compares the result COMP_OUT with the switching pulse LSW, .

At this time, the second comparison unit 502 may further include an inverter 501 according to an embodiment. The inverter 501 inverts the result COMP_OUT of the second comparator 502 so as to be suitable for switching the first differential voltage generator 150 and outputs it as a switching pulse LSW.

Hereinafter, the configuration and operation principle of the pulse generator 500 will be described in detail with reference to FIG. 12 to FIG.

12 is a block diagram illustrating an internal configuration of the pulse generator shown in FIG. 11 according to an embodiment of the present invention.

Referring to FIG. 12, the pulse generator 500 includes a square wave generator 550, a square wave comparison signal generator 560, and a second comparator 502.

The SAW generator 550 includes a second generating block 510, a first waveform generator 520, and a second waveform generator 530.

The second generating block 510 divides a plurality of resistors connected between the internal reference voltage VREF_SMPS and the ground terminal GND to generate a plurality of second reference voltages. At this time, the second reference voltage may be the base signal VREF1 or VREF2 of the soft bias signal Sig1, the maximum bias signal Sig2, or the square wave reset reference SAW_CMP_CMP.

The first waveform generator 520 includes a bias selection circuit 522, a pull-up circuit 524, and a storage unit 525. The first waveform generator 520 is connected between the second generating block 510 and the square wave output terminal 551 and generates a first waveform having a voltage level selected by one of the plurality of second reference voltages MAX_PULSE_EN And generates a first waveform Rising by pulling up from the ground voltage in response to a bias signal BIAS in accordance with the square wave base signal SAW_REF as a square wave base signal SAW_REF.

The bias selection circuit 522 outputs the soft bias signal Sig1 or the predetermined maximum bias signal Sig2 selected by the pulse width modulation control signal Pul_CON among the plurality of second reference voltages to the second enable signal MAX_PUSEL_EN And outputs it as a square wave base signal SAW_REF.

For example, when the second enable signal MAX_PUSEL_EN is low (when the maximum pulse width is not enabled), the soft bias signal Sig1 is outputted as the square wave base signal SAW_REF, ) (When the maximum pulse width is enabled), the maximum bias signal Sig2 is outputted as the square-wave-based signal SAW_REF. At this time, the soft bias signal Sig1 is a signal selected by the pulse width modulation control signal Pul_CON among the plurality of second reference voltages VREF1 and VREF2 generated in the second generation block 510. The maximum bias signal Sig2 may be any one of a plurality of second reference voltages VREF1 and VREF2 generated in the second generation block 510. [

The bias selection circuit 522 may further include a stabilization circuit 523 for stable output of the bias signal BIAS. The stabilization circuit 523 may be a buffer that outputs the square wave base signal SAW_REF as the bias signal BIAS, but may be variously implemented according to the embodiment.

The pull-up circuit 524 is connected between the supply voltage VDD terminal and the rectangular-wave output terminal x and pull-ups the square-wave output terminal x in response to the bias signal BIAS. up. The pull-up circuit 524 may be a PMOS as a switching element, but may be implemented variously according to an embodiment.

The storage unit 525 is connected between the square wave output terminal x and the ground terminal GND to store the pull-up signal to generate a first waveform. The generated first waveform may be a rising waveform of a square wave.

The second waveform generation unit 530 includes a second sampling unit and a pull-down circuit 533. [

The second sampling unit includes a comparator 531 and a latch circuit 532. The second sampling unit is connected between the supply voltage terminal VDD and the square wave output terminal x to reset the supply voltage to the internal power supply unit in response to the clock signal SMPS_CK after resetting the latch circuit 532. [ And outputs the sampled polling signal f_SAW. At this time, the latch circuit 532 further includes a comparator 531 to generate a reset signal by comparing a SAW pulse fed back from the square wave output terminal x with a predetermined square wave reset reference SAW_CMP_REF.

The pull-down circuit 533 is connected between the square wave output terminal x and the ground terminal GND and pulls up the square wave output terminal x voltage in response to the polling signal f_SAW. . The pull-up circuit 524 may be an NMOS as a switching element, but may be variously implemented according to an embodiment.

The square wave comparison signal generating unit 560 generates a comparison signal in response to the second enable signal MAX_PULSE_EN in a soft pulse period (when the second enable signal is not enabled and MAX_PULSE_EN is low) (S_VSP) as the square wave comparison signal, and outputs the feedback signal FB_VM to the square wave comparison signal (MAX_PULSE_EN) when the maximum pulse interval (the interval during which the second enable signal is enabled, MAX_PULSE_EN is high) (COMP_REF).

The second comparator 502 receives the square wave SAW_PULSE to the non-inverting terminal + and the rectangular wave comparing signal COMP_REF to the inverting terminal -, compares the result COMP_OUT with the switching pulse LSW, .

At this time, the second comparison unit 502 may further include an inverter 501 according to an embodiment. The inverter 501 inverts the result COMP_OUT of the second comparator 502 so as to be suitable for switching the first differential voltage generator 150 and outputs it as a switching pulse LSW.

As a result, when the soft bias signal Sig1 is selected in response to the pulse width modulation control signal Pul_CON, the bias signal BIAS for determining the slope of the rectangular wave is output correspondingly.

For example, the higher the bias signal (BIAS) signal, the larger the slope of the first waveform. When the slope of the first waveform becomes large, the comparison result signal COMP_OUT outputted after the square wave SAW_PULSE is compared with the square wave comparison signal COMP_REF has a larger pulse width. As a result, the switching pulse LSW inverts the comparison result signal COMP_OUT, resulting in a smaller pulse width. Conversely, the lower the level of the bias signal BIAS, the smaller the slope of the first waveform. When the slope of the first waveform becomes smaller, the comparison result signal COMP_OUT outputted after the square wave SAW_PULSE is compared with the square wave comparison signal COMP_REF has a smaller pulse width. As a result, the switching pulse LSW inverts the comparison result signal, resulting in a larger pulse width.

The pulse generator 500 controls the pulse width modulation according to the above-described principle to generate a switching pulse LSW applied to the first switching device 101 of the internal power supply. The amount of the incoming current flowing from the internal power supply 100 to the charge pump 200 is controlled by the switching pulse LSW and as a result the instantaneous peak current is reduced to prevent latch-up.

13 is a block diagram showing an internal configuration according to another embodiment of the pulse generator shown in FIG.

Referring to FIG. 13, the pulse generator 500 includes a square wave generator 550, a square wave comparison signal generator (MUX) 560, and a second comparator 502. For convenience of explanation, differences from FIG. 12 will be mainly described.

The first waveform generator 520 includes a bias selection circuit 522, a pull-up circuit 524, and a storage unit 525. The first waveform generator 520 is connected between the second generating block 510 and the square wave output terminal 551 and generates a first waveform having a voltage level selected by one of the plurality of second reference voltages MAX_PULSE_EN Up from the ground voltage to generate a first waveform Rising.

The bias selection circuit 522 outputs the soft bias signal Sig1 or the maximum bias signal Sig2 in response to the second enable signal MAX_PUSEL_EN as a bias signal BIAS. At this time, the soft bias signal Sig1 is a signal selected by the pulse width modulation control signal Pul_CON in the first circuit 521 of the plurality of second reference voltages VREF1 and VREF2 generated in the second generation block 510 .

The first waveform generator 520 shown in FIG. 13 further includes a second circuit 540 that generates a maximum bias signal Sig2, unlike the one shown in FIG.

The second circuit 540 outputs the maximum bias signal Sig2 selected by the level selection signal REF_SEL among the plurality of second reference voltages generated in the second generation block 510. [ At this time, the level selection signal REF_SEL is a signal made up of N (N is a natural number of 2 or more) bits and is generated by dividing the total voltage of the second generation block into N voltages, Can be selected. The second circuit 540 may include a decoder 541 and a level shifter 542, but may be implemented variously according to an embodiment.

The bias selection circuit 522 may further include a stabilization circuit 523 for stable output of the bias signal BIAS. The stabilization circuit 523 includes a buffer.

As a result, the maximum bias signal Sig2 can be set more variously according to the characteristics of the primary voltage VSP or the power supply 2000. That is, the second circuit 540 and the pulse generating unit 500 including the second circuit 540 adjust the slope of the square wave according to the physical environment conditions such as heat and temperature which can be changed variously according to the operation, so that the maximum pulse width MAX_PULSE Width ) Can be reset.

FIG. 14 is a signal timing diagram illustrating the operation of a power supply according to another embodiment of the present invention. For convenience of description, it is assumed that VREF1 has a voltage higher than VREF2.

First, referring to Fig. 14 (a), each of the operation signal timings when the pulse width modulation control signal Pul_CON is selected as the square wave base signal SAW_REF is VREF1.

If the second enable signal MAX_PULSE_EN is low and the soft pulse duration is present, the first circuit 521 selects VREF1 when the pulse width modulation control signal Pul_CON low (LOW) is applied. VREF1 is generated as a bias signal BIAS via the stabilization circuit 523 as a square wave base signal SAW_REF. The supply voltage VDD is sampled in the latch circuit 532 according to the clock signal SMPS_CK of the internal power supply 100 to generate the polling signal f_SAW. In response to the bias signal BIAS, the pull-up circuit 524 and the storage 525 generate a first waveform and the pull-down circuit 533 responds to the polling signal f_SAW A second waveform (falling) is generated to generate a first square wave (SAW_PULSE) based on VREF1. The first square wave SAW_PULSE @ VREF1 is applied to the non-inverting terminal (+) and the first square wave comparing signal COMP_REF is applied to the inverting terminal (-). The second comparator 502 compares the square wave comparing signal COM_REF And outputs a first comparison result signal COMP_OUT1. That is, if the first square wave SAW_PULSE is higher than the square wave comparison signal COM_REF and the first rectangular wave SAW_PULSE is smaller than the rectangular wave comparison signal COM_REF, And the first comparison result signal COMP_OUT1 is inverted through the inverter 501 to become the first switching pulse LSW1.

Referring to Fig. 14B, each of the operation signal timings when the pulse width modulation control signal Pul_CON is selected as the square wave base signal SAW_REF is VREF2.

In the case of FIG. 14 (b), a square wave (SAW_PULSE @ VREF2) is generated on the basis of FIG. 14 (a). However, since the voltage is lower than VREF1, the slope of the second square wave (SAW_PULSE @ VREF2) is gentler than that of the first square wave (SAW_PULSE @ VREF1). The second comparison result signal COMP_OUT2 and the second switching pulse LSW2 are generated based on the second square wave SAW_PULSE @ VREF2.

Referring to Fig. 14C, signal waveforms obtained by comparing respective operation signals when the square wave base signal SAW_REF is selected as VREF1 and VREF2.

First, when the square wave base signal SAW_REF is compared, VREF1 is larger than VREF2, so that the slope of the first square wave is larger than the slope of the second square wave. And compares the first square wave or the second square wave with the square wave comparison signal COM_REF to output a comparison result signal COMP_OUT. That is, when the square wave signal COM_REF is higher than the square wave comparing signal COM_REF and the square wave SAW_PULSE is smaller than the square wave comparing signal COM_REF, the low level signal is outputted. Since the slope of the first square wave is larger than the slope of the second square wave The pulse width of the comparison result signal COMP_OUT is larger in the case of the first square wave than in the case of the second square wave. The comparison result signal COMP_OUT is inverted through the inverter 501 and becomes a switching pulse LSW, so that a switching pulse LSW having a smaller pulse width is generated as the slope is increased.

As described above, the pulse width modulation control signal Pul_CON adjusts the width of the switching pulse LSW by adjusting the slope of the rectangular wave in the soft pulse section (when the second enable signal is LOW).

15 is a signal timing diagram illustrating the operation of a power supply according to another embodiment of the present invention.

4 and 15, clocks SMPS_CK and CP_CK of different frequencies generated from the timing controller 400 are applied to the internal power supply unit 100 and the charge pump 200, respectively.

The comparator 350 in the input current controller 300 outputs a low pulse width modulation control signal Pul_CON when the first sampling signal S_VSP is lower than the selected reference voltage VREF_SEL. Meanwhile, when the first sampling signal S_VSP is higher than the selected reference voltage VREF_SEL, the comparator 350 outputs a high pulse width modulation control signal Pul_CON.

4, when the first reference voltage VREF_SEL1 is input to the first comparator 350 as the selection reference voltage VREF_SEL, the first comparator 350 compares the first reference voltage VREF_SEL1 with the first reference voltage VREF_SEL, And outputs the control signal Pul_CON1. (However, when the second reference voltage VREF_SEL2 is input to the first comparator 350 as the selection reference voltage VREF_SEL, the first comparator 350 outputs the second pulse width modulation control signal Pul_CON2) The first pulse width modulation control signal Pul_CON1 (or the second pulse width modulation control signal Pul_CON2) is applied to the pulse generator 500 in the internal power supply unit 100.

When the second enable signal MAX_PULSE_EN is input to the second circuit 522 at a low level and the first pulse width modulation control signal Pul_CON1 is input to the first circuit 521 And when the first pulse width modulation control signal Pul_CON1 is low, VREF1 of the second reference voltages is selected and output to the soft bias signal Sig1, and on the basis of this, And outputs a switching pulse LSW1. On the other hand, when the first pulse width modulation control signal Pul_CON1 is high, VREF2 of the second reference voltages is selected and output to the soft bias signal Sig1, and on the basis of this, And outputs a switching pulse LSW2.

When the second enable signal MAX_PULSE_EN is inputted to the second circuit 522 at a high level, the pulse generating unit 500 generates the maximum bias signal selected by the level selection signal REF_SEL among the second reference voltages Sig2) and outputs a switching pulse LSW1 or LSW2 having the maximum pulse width PW_MAX based on the output.

The internal power supply unit 100 generates first and second primary voltages VSP and VSN and an input current to be input to the charge pump 100 according to the switching pulse. When the inrush current is gradually applied to the charge pump 200, the charge pump 200 is activated (Charge Pump Enable Signal) before the switching pulse LSW having the maximum pulse width PW_MAX is applied, So that latch-up can be prevented. In the above embodiment, two soft bias signals Sig1 are described according to the state of the pulse width modulation control signal Pul_CON. However, the present invention is not limited thereto. The number, and the level of the base voltage can be implemented more variously.

16 is a block diagram of a power supply according to another embodiment of the present invention.

Referring to FIG. 16, the power supply 2000 includes an internal power supply 100, a charge pump 200, and a timing controller 400. For convenience of description, differences from the power supply apparatus 2000 of FIG. 9 will be mainly described.

The power supply 2000 shown in FIG. 16 does not include the inrush current controller 300 as shown in FIG. The internal power supply unit 100 includes a first voltage generation unit 150 and a pulse module 600. The pulse module 600 includes a pulse generation unit 500 and a control signal generation unit SEL_Con, do.

The internal power supply unit 100 applies the first differential voltage VSP to the charge pump 200 as well as the pulse module 600. The pulse module 600 generates a control signal SEL_Sig for controlling the pulse width modulation in the control signal generator 650 based on the first differential voltage VSP. The pulse generating unit 500 generates a soft bias signal Sig1 in response to the control signal SEL_Sig and generates a switching pulse LSW having a pulse width PW corresponding thereto. At this time, the control signal SEL_Sig is a signal of 2 or more bits and can be variously implemented according to the embodiment.

That is, the power supply apparatus 2000 that controls the amount of the incoming current flowing into the charge pump 200 by controlling the pulse width modulation of the internal power supply unit 100 on the basis of the primary voltage without the input current controller 300 is provided do.

17 is a flowchart of a power supply method according to another embodiment of the present invention.

Referring to FIG. 17, a method of supplying power to the power supply unit including the internal power supply unit 100 and the charge pump 200 by the switching operation is as follows.

First, when the first enable signal REF_EN is applied to the inrush current controller 300, the first sampling signal S-VSP is generated (S100). The inrush current controller 300 generates a selection reference voltage VREF_SEL from the supply voltage VDD in step S110 and compares the first sampling signal S-VSP with the selection reference voltage VREF_SEL, (Pul_CON) (S120).

The pulse width modulation control signal Pul_CON is applied to the internal power supply unit 100 and the pulse generator 500 in the internal power supply unit 100 applies the second enable signal MAX_PULSE_EN and the pulse width modulation control signal Pul_CON And generates a first waveform that is pulled up in response to the first rising (S130). At this time, the slope of the first waveform is changed according to the soft bias signal Sig1 selected by the pulse width modulation control signal Pul_CON. The pulse generating unit 500 generates a second waveform falling down from the first waveform in accordance with the clock signal SMPS_CK of the internal power supply unit S140 so that the first waveform and the second waveform, (SAW_PULSE) (S150).

Meanwhile, the pulse generator 500 generates either the comparison target signal S_VSP or the feedback signal FB_VM in response to the second enable signal MAX_PULSE_EN to the rectangular wave comparison signal COMP_REF for fine adjustment of the incoming current amount control (S160). The pulse generating unit 500 generates the switching pulse LSW by comparing the square wave SAW_PULSE with the rectangular wave comparing signal COMP_REF at step S170. At this time, the width of the switching pulse LSW is adjusted according to the slope of the SAW_PULSE.

The internal power supply unit 100 generates the first differential voltages VSP and VSN and the input current in response to the switching pulse LSW at step S180 and the charge pump 200 generates the first differential voltages VSP and VSN according to the first differential voltage and the input current And generates a secondary voltage (S190). As a result, the charge pump 200 is prevented from latching up because the operation of the charge pump 200 is enabled before the switching pulse having the maximum pulse width PW_MAX is applied according to the adjusted amount of the input current.

18 is a waveform and an applied signal timing diagram of the power supply apparatus 1000 according to an embodiment of the present invention.

18, in the operation of the internal power supply unit 100 using the pulse width modulation to control the input current to the charge pump 200, The pulse width can be adjusted according to the voltage (VSP) level.

18 (a), when the comparison target signal S_VSP obtained by sampling the first differential voltage VSP outputted from the internal power supply unit 100 becomes equal to or greater than the selected reference voltage VREF_SEL, the charge pump 200 Are enabled to generate the secondary voltages VGH and VGL. At this time, by limiting the energy stored in the inductor 102 through the pulse width modulation control, the peak current that can be generated when the power supply 1000 is powered on is prevented.

Referring to FIG. 18B, in the case of the pulse PULSE, the supply voltage VDD is controlled by the energy of the inductor 102 in the internal power supply 100 as a soft pulse width to output the primary voltage VSP Increase slightly (section A). The internal power supply 100 supplies the charge pump 200 to the internal power supply 100 through the input current controller 300 or the pulse generator 500 when the output of the first voltage VSP exceeds a predetermined level. Able to operate and input the inrush current. The internal power supply unit 100 further increases the input current to a predetermined maximum pulse width PW_Max to increase the inductance of the charge pump 200 To prevent latch-up. At this time, the pulse width can be variously set according to the embodiment in design.

19 is a graph of output signals of a power supply device according to an embodiment of the present invention.

19, when the first and second differential voltages VSP and VSN and the second differential voltages VGH and VGL are generated from the supply voltage using the power supply apparatus according to the embodiment of the present invention, I can see not doing.

That is, when the enable signal REF_EN is applied to the inrush current controller 300, a pulse signal LSW, which reflects the result of comparing the signal S_VSP obtained by sampling the first voltage and the selection reference voltage VREF_SEL, Is applied to the control terminal of the first switching device 101 of the supply unit 100 to gradually form the first differential voltage VSP (Soft Pulse Start Point). When the first voltage VSP becomes equal to or higher than a certain level, the internal power supply unit 100 enables the charge pump 200 at the front end of the soft pulse interval to slowly input the input current, The secondary voltage VGH is generated normally without boosting. The negative voltages VSN and VGL are generated on the same principle.

20 is a block diagram of a display device including a power supply device according to embodiments of the present invention.

20, a display device 4000 includes a panel 1, a source driver 3, a gate driver 2, a controller 4, and a power supply device 1000. [

The panel 1 includes a plurality of data lines, a plurality of gate lines, and a plurality of pixels connected between the plurality of data lines and the plurality of gate lines.

The source driver 3 drives the plurality of data lines (or source lines) implemented in the panel 110 in response to the control signals output from the controller 4 and the voltage output from the power supply apparatus 1000 To output the analog voltages.

The gate driver 2 can supply the analog voltages output from the source driver 3 to the plurality of pixels in response to the control signals output from the controller 4 and the voltage output from the power supply apparatus 1000 A plurality of gate lines (or scan lines) implemented in the panel 1 are sequentially driven.

The power supply apparatus 1000 described with reference to Figs. 1 to 17 supplies a voltage (i.e., a secondary voltage) boosted to the source driver 3 or the gate driver 2 in response to a signal output from the controller 4 Can supply.

The controller 4 generates timing control signals for controlling the operation timings of the plurality of data lines of the source driver 2 and the plurality of gate lines of the gate driver 2. [

21 is a block diagram of a display device including a power supply device according to another embodiment of the present invention.

Referring to FIG. 21, a display device 4000 'includes a panel 1 and a display driver 5.

The display driver 5 includes a source driver 3 ', a gate driver 2', a controller 4 'and a power supply 1000, and can be implemented in one chip or package as shown However, the present invention is not limited thereto, and can be variously implemented according to the embodiments.

22 is a block diagram of an electronic device including a power supply device according to an embodiment of the present invention.

22, the electronic device 5000 includes a power supply unit 1000, a CPU 5100, a memory device 5200, an input / output interface unit 5300, and a bus 5400.

The CPU 5100 can control the exchange of data between the power supply apparatus 1000, the memory device 5200 and the input / output interface section 5300 via the bus 5400. [

The memory device 5300 may be implemented as a non-volatile memory device. The non-volatile memory device may include a plurality of non-volatile memory cells.

Each of the non-volatile memory cells may be electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic RAM, spin transfer torque MRAM, conductive bridging RAM (CBRAM), ferroelectric RAM ), A phase change RAM (PRAM), also called an Ovonic Unified Memory (OUM), a resistive RAM (RRAM or ReRAM), a nanotube RRAM, a polymer RAM (PoRAM), a nano floating gate memory Nano Floating Gate Memory (NFGM), a holographic memory, a Molecular Electronics Memory Device, or an Insulator Resistance Change Memory.

The electronic device 5000 may be a PC, a portable computer, a portable mobile communication device, or a CE (consumer equipment). The portable mobile communication device includes a mobile phone, a PDA, or a PMP. The consumer equipment (CE) may be a digital TV, a home automation device, or a digital camera. The electronic device may also be an e-book, a game machine, a game controller, a navigator, or an electronic musical instrument.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

100: Internal power supply
200: charge pump
300,300 ': Inrush current controller
310: first sampling unit 320: reference voltage generating unit 330: first generating block
350: Selection block
400,400 ': Timing controller
500: Pulse generator
501: second comparator
510: second generation block 520: first waveform generation block 530: second waveform generation block
521: first circuit 524: pull-up circuit
533: a pull-down circuit 540: a second circuit
550: Square wave generation unit
560: Square wave comparison signal generator
1000, 1100, 1200, 2000, 2000 ': Power supply
4000: Display device
5000: electronic device

Claims (10)

A first differential voltage generator for generating a first differential voltage and a feedback signal by a switching operation from a supply voltage; And a pulse generator for generating a pulse from the feedback signal and using the pulse for the switching operation;
A charge pump for receiving the first differential voltage and generating a second differential voltage; And
And an inrush current controller coupled between the charge pump and the internal power supply to compare a comparison object signal with a selected reference voltage and to control pulse width modulation with a pulse width modulation control signal reflecting the comparison result,
The inrush current controller includes a reference voltage generator for outputting the selected reference voltage in response to a reference voltage selection signal,
The reference voltage generator
A first generating block for dividing a plurality of resistor connections connected between a supply voltage terminal and a ground terminal to generate a plurality of first reference voltages; And
And a selection block which outputs one of the plurality of first reference voltages as the selection reference voltage in response to the reference voltage selection signal. 2. The apparatus of claim 1, wherein the inrush current controller
A first sampling unit which divides the first and second differential signals from a plurality of resistance connections connected between the first differential voltage and a ground terminal when the first enable signal is applied, And
And a first comparator for comparing the comparison target signal with the selection reference voltage to output the pulse width modulation control signal. delete The method according to claim 1,
Wherein, when pulses having a plurality of predetermined pulse widths are applied to the internal power supply from the timing controller, one of the pulses is selected in response to the pulse width modulation control signal. A first differential voltage generator for generating a first differential voltage and a feedback signal by a switching operation from a supply voltage; And a pulse generator for generating a pulse from the feedback signal and using the pulse for the switching operation;
A charge pump for receiving the first differential voltage and generating a second differential voltage; And
And an inrush current controller coupled between the charge pump and the internal power supply to compare a comparison object signal with a selected reference voltage and to control pulse width modulation with a pulse width modulation control signal reflecting the comparison result,
The pulse generator
A square wave generator for generating a square wave in which a slope is adjusted in response to the pulse width modulation control signal and the second enable signal;
A square wave comparison signal generator for outputting the comparison target signal or the feedback signal as a square wave comparison signal in response to the second enable signal; And
And a second comparator for comparing the square wave and the square wave comparison signal and outputting the comparison pulse as a switching pulse. 6. The apparatus of claim 5, wherein the square wave generator
A second generating block for dividing the voltage from a plurality of resistors connected between the internal reference voltage and the ground terminal to generate a plurality of second reference voltages;
Connected between the second generating block and the square wave output terminal and pulled up from the ground voltage in response to any one of the plurality of second reference voltages selected by the second enable signal A first waveform generator for generating a first waveform; And
And a pull-down resistor connected between the second generating block and the rectangular-wave output terminal for pulling down the supply voltage from the rectangular-wave output terminal voltage in response to a polling signal sampled according to a clock signal of the internal power- 2 < / RTI > waveform. 7. The apparatus of claim 6, wherein the first waveform generator
A first circuit for outputting a soft bias signal selected by the pulse width modulation control signal among the plurality of second reference voltages;
A second circuit for outputting a maximum bias signal selected by the level selection signal among the plurality of second reference voltages;
A bias circuit for outputting the soft bias signal or the maximum bias signal as the bias signal in response to the second enable signal; And
And a pull-up circuit for pulling up the ground voltage in response to the bias signal to generate the first waveform. 7. The apparatus of claim 6, wherein the second waveform generator
A second sampling unit for comparing and resetting the square wave with a predetermined square wave reset reference and outputting a polling signal obtained by sampling the supply voltage according to a clock signal of the internal power supply unit; And
And a pull-down circuit for pulling up the square wave output terminal voltage in response to the polling signal. A power supply method for a power supply including an internal power supply unit and a charge pump by a switching operation,
Generating a first sampling signal from a first differential voltage generated by the internal power supply when the first enable signal is applied;
Generating a selected reference voltage divided in response to a reference voltage selection signal from a plurality of resistor connections connected between a supply voltage terminal and a ground terminal;
Comparing the first sampling signal with the selection reference voltage and outputting the comparison result as a pulse width modulation control signal;
Outputting, as a switching pulse, a pulse generated by the timing controller and selected in accordance with the pulse width modulation control signal among pulses having a plurality of predetermined pulse widths applied to the internal power supply unit;
Adjusting the amount of the input current that is input to the charge pump by the switching operation of the internal power supply unit according to the switching pulse; And
And the charge pump generating a secondary voltage. 10. The method of claim 9, wherein outputting with the switching pulse comprises:
Dividing the internal reference voltage to generate a plurality of reference voltages;
Generating a soft bias signal selected by the pulse width modulation control signal among the plurality of reference voltages;
Generating a maximum bias signal selected by a level selection signal among the plurality of reference voltages;
Outputting the soft bias signal or the maximum bias signal as a bias signal in response to a second enable signal; And
Generating a first waveform by pulling up a ground voltage in response to the bias signal;
Outputting a square wave by generating a second waveform by pulling down the first waveform in response to a polling signal obtained by sampling the supply voltage according to a clock signal of the internal power supply;
Outputting a comparison target signal or a feedback signal as a square wave comparison signal in response to the second enable signal; And
And comparing the square wave and the square wave comparison signal to generate the switching pulse.

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