CN114613316A - Driving circuit of display panel and display device - Google Patents
Driving circuit of display panel and display device Download PDFInfo
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- CN114613316A CN114613316A CN202210141764.7A CN202210141764A CN114613316A CN 114613316 A CN114613316 A CN 114613316A CN 202210141764 A CN202210141764 A CN 202210141764A CN 114613316 A CN114613316 A CN 114613316A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Abstract
The application discloses display panel's drive circuit and display device, this drive circuit includes power module and the boost module of being connected with power module, power module is used for exporting first logic voltage, first negative reference voltage and first positive reference voltage, drive circuit includes power sequential control circuit, power sequential control circuit connects between power module and boost module, power sequential control circuit is used for receiving first logic voltage, first negative reference voltage and first positive reference voltage, and export the second logic voltage to boost module in proper order, second negative reference voltage and the positive reference voltage of second. According to the mode, the reliability of the driving circuit can be improved.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a driving circuit of a display panel and a display device.
Background
In the prior art, a power module and a boost module that are connected to each other are usually disposed in a driving circuit of a display panel, and the power module is configured to output a logic voltage, a negative reference voltage, and a positive reference voltage to the boost module, so that the boost module performs corresponding boost processing based on a received voltage.
The conventional technology has the defects that when a power chip generates a logic voltage, a negative reference voltage and a positive reference voltage, the logic voltage and the positive reference voltage are generally generated and output to a boost module synchronously after receiving the power voltage, and then the negative reference voltage can be generated and output to the boost module.
Disclosure of Invention
The technical problem that this application mainly solved is how to improve drive circuit's reliability.
In order to solve the above technical problem, the first technical solution adopted by the present application is: the utility model provides a display panel's drive circuit, include power module and the boost module of being connected with power module, power module is used for exporting first logic voltage, first negative reference voltage and first positive reference voltage, drive circuit includes power sequential control circuit, power sequential control circuit connects between power module and boost module, power sequential control circuit is used for receiving first logic voltage, first negative reference voltage and first positive reference voltage to export the second logic voltage in proper order, second negative reference voltage and the positive reference voltage of second to the boost module.
The power supply time sequence control circuit comprises a first time sequence circuit, a second time sequence circuit and a third time sequence circuit; the first timing circuit is used for outputting a second logic voltage to the boosting module when the first logic voltage reaches a preset logic voltage difference threshold value; the second sequential circuit is used for outputting a second negative reference voltage to the boosting module after the boosting module receives the first logic voltage; the third sequential circuit is used for outputting a second positive reference voltage to the boosting module after the boosting module receives the first negative reference voltage.
The input end of the first timing circuit is connected with the power supply module, and the output end of the first timing circuit is connected with the boosting module; the input end of the second sequential circuit is connected with the power supply module, the output end of the second sequential circuit is connected with the boosting module, and the drive end of the second sequential circuit is connected with the output end of the first sequential circuit; the input end of the third sequential circuit is connected with the power supply module, the output end of the third sequential circuit is connected with the boosting module, and the driving end of the third sequential circuit is connected with the output end of the second sequential circuit.
Wherein, first sequence circuit includes: one end of the first switch tube is connected with the logic voltage output end of the power supply module, and the other end of the first switch tube is connected with the logic voltage input end of the boosting module; one end of the first resistor is connected with one end of the first switch tube, and the other end of the first resistor is connected with the driving end of the first switch tube; and one end of the second resistor is connected with the driving end of the first switching tube, and the other end of the second resistor is grounded.
Wherein, the second sequential circuit includes: one end of the second switch tube is connected with the negative reference voltage output end of the power supply module, and the other end of the second switch tube is connected with the negative reference voltage input end of the boosting module; one end of the third resistor is connected with one end of the second switch tube, and the other end of the third resistor is connected with the driving end of the second switch tube; one end of the fourth resistor is connected with the driving end of the second switch tube, and the other end of the fourth resistor is connected with the logic voltage input end of the boosting module.
Wherein, the third sequential circuit includes: one end of the third switching tube is connected with the positive reference voltage output end of the power supply module, and the other end of the third switching tube is connected with the positive reference voltage input end of the boosting module; one end of the fifth resistor is connected with one end of the third switching tube, and the other end of the fifth resistor is connected with the driving end of the third switching tube; one end of the sixth resistor is connected with the driving end of the third switching tube, and the other end of the sixth resistor is connected with the negative reference voltage input end of the boosting module.
The first switch tube is a PMOS tube, one end of the first switch tube is a source electrode, and the driving end of the first switch tube is a grid electrode; the second switch tube is an NMOS tube, one end of the second switch tube is a source electrode, and the driving end of the second switch tube is a grid electrode; the third switching tube is a PMOS tube, one end of the third switching tube is a source electrode, and the driving end of the third switching tube is a grid electrode; when the grid-source voltage difference of the first switching tube reaches a first voltage difference threshold value, one end of the first switching tube is conducted with the other end of the first switching tube, wherein the grid-source voltage difference of the first switching tube is a product obtained by multiplying a first logic voltage by a first resistance ratio, and the first resistance ratio is a quotient obtained by dividing the resistance value of the first resistor by the sum of the resistance value of the first resistor and the resistance value of the second resistor; when the gate-source voltage difference of the second switching tube reaches a second voltage difference threshold value, one end of the second switching tube is conducted with the other end of the second switching tube, wherein the gate-source voltage difference of the second switching tube is a product obtained by multiplying a first voltage difference by a second resistance ratio, the first voltage difference is a difference value between a second logic voltage and a first negative reference voltage, and the second resistance ratio is a quotient obtained by dividing the resistance value of the third resistor by the sum of the resistance value of the third resistor and the resistance value of the fourth resistor; and when the gate-source voltage difference of the third switching tube reaches a third voltage difference threshold value, one end of the third switching tube is conducted with the other end of the third switching tube, wherein the gate-source voltage difference of the third switching tube is a product obtained by multiplying a second voltage difference by a third resistance ratio, the second voltage difference is a difference value between the first positive reference voltage and the second negative reference voltage, and the third resistance ratio is a quotient obtained by dividing the resistance value of the fifth resistor by the sum of the resistance value of the fifth resistor and the resistance value of the sixth resistor.
The power supply module comprises a voltage reduction circuit, a negative voltage circuit and a pressurization circuit; the voltage reduction circuit receives a power supply voltage and outputs a first logic voltage based on the power supply voltage, the negative voltage circuit receives the power supply voltage and outputs a first negative reference voltage based on the power supply voltage, and the voltage boost circuit receives the power supply voltage and outputs a first positive reference voltage based on the power supply voltage.
The boost module comprises a logic circuit and a voltage boosting circuit, wherein the logic circuit is connected with the voltage boosting circuit; the logic circuit receives a second logic voltage, and the voltage boosting circuit receives a second negative reference voltage and a second positive reference voltage, respectively.
In order to solve the above technical problem, the second technical solution adopted by the present application is: a display device includes a display panel, a processor, and a driving circuit of the display panel.
The beneficial effect of this application lies in: different from the prior art, this application is through setting up a power sequential control circuit between power module and boost module, receive first logic voltage, first negative reference voltage and first positive reference voltage through power sequential control circuit, and output second logic voltage, second negative reference voltage and second positive reference voltage to boost module in proper order based on received voltage, make boost module can receive logic voltage, negative reference voltage and positive reference voltage in proper order, avoid the mistake to trigger boost module's overcurrent protection mechanism and make whole drive circuit unable normal operation, drive circuit's reliability has been improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a first embodiment of a driving circuit of a display panel according to the present application;
FIG. 2 is a schematic diagram of a second embodiment of a driving circuit of a display panel according to the present application;
FIG. 3 is a schematic structural diagram of a third embodiment of a driving circuit of a display panel according to the present application;
FIG. 4 is a schematic voltage waveform in one application scenario of the present application;
FIG. 5 is a schematic diagram of a fourth embodiment of a driving circuit of a display panel according to the present application;
fig. 6 is a schematic structural diagram of an embodiment of a display device of the present application.
The reference signs are: a power supply module 11; a voltage-decreasing circuit 111; a negative voltage circuit 112; a voltage application circuit 113; a boost module 12; a logic circuit 121; a voltage boost circuit 122; a power supply timing control circuit 13; a first timing circuit 131; a first switch tube 1311; a first resistor 1312; a second resistor 1313; a second timing circuit 132; a second switching tube 1321; a third resistor 1322; a fourth resistor 1323; a third sequential circuit 133; a third switching tube 1331; a fifth resistor 1332; a sixth resistor 1333; a display device 60; a drive circuit 61; a processor 62; a display panel 63.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first", "second" and "first" in this application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless explicitly specified otherwise. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
The present application firstly proposes a driving circuit of a display panel, as shown in fig. 1, fig. 1 is a schematic structural diagram of a first embodiment of the driving circuit of the display panel of the present application, and the driving circuit includes: the power supply module comprises a power supply module 11, a boosting module 12 connected with the power supply module 11 and a power supply time sequence control circuit 13 connected between the power supply module 11 and the boosting module 12, wherein the power supply module 11 is connected with the boosting module 12 through the power supply time sequence control circuit 13.
The power module 11 is configured to output a first logic voltage, a first negative reference voltage, and a first positive reference voltage, and the power timing control circuit 13 is configured to receive the first logic voltage, the first negative reference voltage, and the first positive reference voltage output by the power module 11, and output a second logic voltage, a second negative reference voltage, and a second positive reference voltage to the voltage boost module 12 in sequence.
It should be noted that, under the condition that the boost module 12 can sequentially receive the corresponding voltages according to the sequence of the second logic voltage, the second negative reference voltage and the second positive reference voltage, the boost module 12 will not erroneously trigger its own over-current protection mechanism due to receiving the second positive reference voltage in advance, so as to avoid the occurrence of a phenomenon that the boost module 12 causes the turn-off of the driving circuit of the entire display panel due to erroneously triggering the over-current protection mechanism in the normal driving operation process.
Specifically, as shown in fig. 1, the power timing control circuit 13 may receive a first logic voltage (e.g., VDD1 shown in fig. 1), a first negative reference voltage (e.g., VGL1 shown in fig. 1) and a first positive reference voltage (e.g., VGH1 shown in fig. 1) output by the power module 11, and sequentially output a second logic voltage (e.g., VDD2 shown in fig. 1), a second negative reference voltage (e.g., VGL2 shown in fig. 1) and a second positive reference voltage (e.g., VGH2 shown in fig. 1) to the boost module 12.
Be different from prior art, this application is through setting up a power sequential control circuit between power module and boost module, receive first logic voltage, first negative reference voltage and first positive reference voltage through power sequential control circuit, and output second logic voltage, second negative reference voltage and second positive reference voltage to boost module in proper order based on received voltage, make boost module can receive logic voltage, negative reference voltage and positive reference voltage in proper order, avoid the overcurrent protection mechanism of spurious triggering boost module and make whole drive circuit unable normal operating, drive circuit's reliability has been improved.
The present application further provides a driving circuit of a display panel, as shown in fig. 2, fig. 2 is a schematic structural diagram of a second embodiment of the driving circuit of the display panel of the present application, and the driving circuit includes: the power supply module comprises a power supply module 11, a boosting module 12 connected with the power supply module 11 and a power supply time sequence control circuit 13 connected between the power supply module 11 and the boosting module 12, wherein the power supply module 11 is connected with the boosting module 12 through the power supply time sequence control circuit 13.
The power module 11 is configured to output a first logic voltage, a first negative reference voltage, and a first positive reference voltage, and the power timing control circuit 13 is configured to receive the first logic voltage, the first negative reference voltage, and the first positive reference voltage output by the power module 11, and output a second logic voltage, a second negative reference voltage, and a second positive reference voltage to the voltage boost module 12 in sequence.
The power supply timing control circuit 13 includes a first timing circuit 131, a second timing circuit 132, and a third timing circuit 133.
The first timing circuit 131 is configured to output a second logic voltage to the boost module when the first logic voltage reaches a preset logic voltage difference threshold. The second timing circuit 132 is configured to output the first negative reference voltage to the voltage boosting module 12 after the voltage boosting module receives the second logic voltage. The third timing circuit 133 is configured to output the first positive reference voltage to the boost module after the boost module 12 receives the second negative reference voltage.
Specifically, as shown in fig. 2, a logic voltage output end a of the power module 11 is configured to output a first logic voltage, a negative reference voltage output end B of the power module 11 is configured to output a first negative reference voltage, a positive reference voltage output end C of the power module 11 is configured to output a first positive reference voltage, a logic voltage input end D of the voltage boosting module 12 is configured to receive a second logic voltage, a negative reference voltage input end E of the voltage boosting module 12 is configured to receive a second negative reference voltage, and a positive reference voltage input end F of the voltage boosting module 12 is configured to receive a second positive reference voltage.
Optionally, as shown in fig. 2, an input end of the first timing circuit 131 is connected to the power module 11, and an output end of the first timing circuit 131 is connected to the voltage boosting module 12.
The input end of the second timing circuit 132 is connected to the power module 11, the output end of the second timing circuit is connected to the boost module 12, and the driving end of the second timing circuit 132 is connected to the output end of the first timing circuit 131.
The input end of the third sequential circuit 133 is connected to the power module 11, the output end of the third sequential circuit 133 is connected to the boost module 12, and the driving end of the third sequential circuit 133 is connected to the output end of the second sequential circuit 132.
Specifically, as shown in fig. 2, an input end of the first timing circuit 131 is connected to the logic voltage output end a of the power module 11, and an output end of the first timing circuit 131 is connected to the logic voltage input end D of the voltage boost module 12.
The input end of the second sequential circuit 132 is connected to the negative reference voltage output end B of the power module 11, the output end of the second sequential circuit 132 is connected to the negative reference voltage input end E of the boost module 12, and the driving end G of the second sequential circuit 132 is connected to the output end of the first sequential circuit 131 or the logic voltage input end D of the boost module 12.
The input end of the third sequential circuit 133 is connected to the positive reference voltage output end C of the power module 11, the output end of the third sequential circuit 133 is connected to the positive reference voltage input end F of the voltage boost module 12, and the driving end H of the third sequential circuit 133 is connected to the output end of the second sequential circuit 132 or the negative reference input end E of the voltage boost module 12.
Different from the prior art, this application is through setting up a power sequential control circuit between power module and boost module, receive first logic voltage, first negative reference voltage and first positive reference voltage through power sequential control circuit, and output second logic voltage, second negative reference voltage and second positive reference voltage to boost module in proper order based on received voltage, make boost module can receive logic voltage, negative reference voltage and positive reference voltage in proper order, avoid the mistake to trigger boost module's overcurrent protection mechanism and make whole drive circuit unable normal operation, drive circuit's reliability has been improved.
The present application further provides a driving circuit of a display panel, as shown in fig. 3, fig. 3 is a schematic structural diagram of a third embodiment of the driving circuit of the display panel of the present application, and the driving circuit includes: the power supply module comprises a power supply module 11, a boosting module 12 connected with the power supply module 11 and a power supply time sequence control circuit 13 connected between the power supply module 11 and the boosting module 12, wherein the power supply module 11 is connected with the boosting module 12 through the power supply time sequence control circuit 13.
The power module 11 is configured to output a first logic voltage, a first negative reference voltage, and a first positive reference voltage, and the power timing control circuit 13 is configured to receive the first logic voltage, the first negative reference voltage, and the first positive reference voltage output by the power module 11, and output a second logic voltage, a second negative reference voltage, and a second positive reference voltage to the voltage boost module 12 in sequence.
The power supply timing control circuit 13 includes a first timing circuit 131, a second timing circuit 132, and a third timing circuit 133.
The first timing circuit 131 is configured to output a second logic voltage to the boost module when the first logic voltage reaches a preset logic voltage difference threshold. The second timing circuit 132 is configured to output the first negative reference voltage to the voltage boosting module 12 after the voltage boosting module receives the second logic voltage. The third timing circuit 133 is configured to output the first positive reference voltage to the boost module after the boost module 12 receives the second negative reference voltage.
The first timing circuit 131 includes: a first switch 1311, a first resistor 1312 and a second resistor 1313.
One end of the first switch tube 1311 is connected to the logic voltage output end a of the power module 11, the other end of the first switch tube 1311 is connected to the logic voltage input end D of the voltage boost module 12, one end of the first resistor 1312 is connected to one end of the first switch tube 1311, the other end of the first resistor 1312 is connected to the driving end of the first switch tube 1311, one end of the second resistor 1313 is connected to the driving end of the first switch tube 1311, and the other end of the second resistor 1313 is grounded.
Specifically, as shown in fig. 3, the first switch 1311 is a PMOS transistor, one end of the first switch 1311 (the end connected to the logic voltage output end a of the power module 11) is a source, and the driving end of the first switch 1311 is a gate.
The gate-source voltage difference of the first switch tube 1311 is a product obtained by multiplying the first logic voltage by a first resistance ratio, and the first resistance 1312 ratio is a quotient obtained by dividing the resistance value of the first resistance 1312 by the sum of the resistance value of the first resistance 1312 and the resistance value of the second resistance 1313. When the gate-source voltage difference of the first switch tube 1311 reaches the first voltage difference threshold, the first switch tube 1311 is turned on, that is, one end of the first switch tube 1311 is turned on with the other end, so that the logic voltage input end D of the voltage boost module 12 receives the second logic voltage corresponding to the first logic voltage output by the logic voltage output end a of the power supply module 11.
Optionally, as shown in fig. 3, the second timing circuit 132 includes: a second switch 1321, a third resistor 1322 and a fourth resistor 1323.
One end of the second switch tube 1321 is connected to the negative reference voltage output end B of the power module 11, the other end of the second switch tube 1321 is connected to the negative reference voltage input end E of the voltage boost module 12, one end of the third resistor 1322 is connected to one end of the second switch tube 1321, the other end of the third resistor 1322 is connected to the driving end of the second switch tube 1321, one end of the fourth resistor 1323 is connected to the driving end of the second switch tube 1321, and the other end of the fourth resistor 1323 is connected to the logic voltage input end D of the voltage boost module 12.
Specifically, as shown in fig. 3, the second switch tube 1321 is an NMOS tube, one end of the second switch tube 1321 (the end connected to the negative reference voltage output end B of the power module 11) is a source, and the driving end of the second switch tube 1321 is a gate.
The gate-source voltage difference of the second switch tube 1321 is a product obtained by multiplying a first voltage difference, which is a difference between the second logic voltage and the first negative reference voltage, by a second resistance ratio, which is a quotient obtained by dividing the resistance value of the third resistor 1322 by the sum of the resistance value of the third resistor 1322 and the resistance value of the fourth resistor 1323. When the gate-source voltage difference of the second switching tube 1321 reaches the second voltage difference threshold, the second switching tube 1321 is turned on, that is, one end of the second switching tube 1321 is turned on with the other end, so that the negative reference voltage input end E of the voltage boost module 12 receives the second negative reference voltage corresponding to the first negative reference voltage output by the negative reference voltage output end B of the power supply module 11.
Further, the third timing circuit 133 includes: a third switch tube 1331, a fifth resistor 1332 and a sixth resistor 1333.
One end of the third switching tube 1331 is connected to the positive reference voltage output end C of the power module, the other end of the third switching tube 1331 is connected to the positive reference voltage input end F of the boost module, one end of the fifth resistor 1332 is connected to one end of the third switching tube 1331, the other end of the fifth resistor 1332 is connected to the driving end of the third switching tube 1331, one end of the sixth resistor 1333 is connected to the driving end of the third switching tube 1331, and the other end of the sixth resistor 1333 is connected to the negative reference voltage input end E of the boost module.
Specifically, as shown in fig. 3, the third switch 1331 is a PMOS transistor, one end of the third switch 1331 is a source, and the driving end of the third switch 1331 is a gate.
The gate-source voltage difference of the third switching tube 1331 is a product obtained by multiplying a second voltage difference, which is a difference between the first positive reference voltage and the second negative reference voltage, by a third resistance ratio, which is a quotient obtained by dividing the resistance value of the fifth resistor 1332 by the sum of the resistance value of the fifth resistor 1332 and the resistance value of the sixth resistor 1333. When the gate-source voltage difference of the third switching tube 1331 reaches the third voltage difference threshold, one end of the third switching tube 1331 is conducted with the other end, that is, one end of the third switching tube 1331 is conducted with the other end, so that the positive reference voltage input end F of the boost module 12 receives the second positive reference voltage corresponding to the first positive reference voltage output by the positive reference voltage output end C of the power module 11.
Based on the above manner, the time difference between the second logic voltage received by the boosting module 12 and the power voltage received by the power module 11 can be adjusted by adjusting the magnitude of the first resistance ratio, the time difference between the second negative reference voltage received by the boosting module 12 and the second logic voltage received by the boosting module 12 can be adjusted by adjusting the magnitude of the second resistance ratio, and the time difference between the second positive reference voltage received by the boosting module 12 and the second negative reference voltage received by the boosting module 12 can be adjusted by adjusting the magnitude of the third resistance ratio.
For example, as shown in fig. 4, fig. 4 is a schematic voltage waveform diagram in an application scenario of the present application, the power supply voltage shown in fig. 4 is a supply voltage of the power module 11, and the second logic voltage, the second negative reference voltage, and the second positive reference voltage shown in fig. 4 are waveforms of voltages received by the voltage boost module 12.
As shown in fig. 4, based on the above manner, the boosting module 12 may sequentially receive the second logic voltage, the second negative reference voltage, and the second positive reference voltage, wherein the time difference T1 between the second logic voltage and the power voltage received by the power module 11 may be adjusted by adjusting the magnitude of the first resistance ratio, the time difference T2 between the second negative reference voltage and the second logic voltage received by the boosting module 12 may be adjusted by adjusting the magnitude of the second resistance ratio, and the time difference T3 between the second positive reference voltage and the second negative reference voltage received by the boosting module 12 may be adjusted by adjusting the magnitude of the third resistance ratio, so as to implement more precise control.
Be different from prior art, this application is through setting up a power sequential control circuit between power module and boost module, receive first logic voltage, first negative reference voltage and first positive reference voltage through power sequential control circuit, and output second logic voltage, second negative reference voltage and second positive reference voltage to boost module in proper order based on received voltage, make boost module can receive logic voltage, negative reference voltage and positive reference voltage in proper order, avoid the overcurrent protection mechanism of spurious triggering boost module and make whole drive circuit unable normal operating, drive circuit's reliability has been improved.
The present application further provides a driving circuit of a display panel, as shown in fig. 5, fig. 5 is a schematic structural diagram of a fourth embodiment of the driving circuit of the display panel of the present application, and the driving circuit includes: the power supply module comprises a power supply module 11, a boosting module 12 connected with the power supply module 11 and a power supply time sequence control circuit 13 connected between the power supply module 11 and the boosting module 12, wherein the power supply module 11 is connected with the boosting module 12 through the power supply time sequence control circuit 13.
The power module 11 is configured to output a first logic voltage, a first negative reference voltage, and a first positive reference voltage, and the power timing control circuit 13 is configured to receive the first logic voltage, the first negative reference voltage, and the first positive reference voltage output by the power module 11, and output a second logic voltage, a second negative reference voltage, and a second positive reference voltage to the voltage boost module 12 in sequence.
The power module 11 includes a voltage-decreasing circuit 111, a negative voltage circuit 112, and a voltage-increasing circuit 113.
The voltage dropping circuit 111 receives a power voltage (e.g., VIN in fig. 5) and outputs a first logic voltage (e.g., VDD1 in fig. 5) based on the power voltage, the negative voltage circuit 112 receives the power voltage and outputs a first negative reference voltage (e.g., VGL1 in fig. 5) based on the power voltage, and the voltage boosting circuit 113 receives the power voltage and outputs a first positive reference voltage (e.g., VGH1 in fig. 5) based on the power voltage.
Specifically, the power supply voltage may be stepped down by using the step-down circuit 111 to obtain a first logic voltage, the power supply voltage may be stepped down by using the negative voltage circuit 112 to obtain a first negative reference voltage, and the power supply voltage may be stepped up by using the step-up circuit 113 to obtain a first positive reference voltage.
Optionally, the boost module 12 includes a logic circuit 121 and a voltage boost circuit 122, and the logic circuit 121 is connected to the voltage boost circuit 122.
The logic circuit 121 receives a second logic voltage (e.g., VDD2 in FIG. 5), and the voltage boost circuit receives a second negative reference voltage (e.g., VGL2 in FIG. 5) and a second positive reference voltage (e.g., VGH2 in FIG. 5), respectively.
Specifically, the second logic voltage may be an operating voltage of the logic circuit 121, after receiving the second logic voltage, the logic circuit 121 may output a signal to be boosted to the voltage boosting circuit, and the voltage boosting circuit 122 may perform voltage reduction or voltage boosting processing on the signal to be boosted based on the received second negative reference voltage and the second positive reference voltage to obtain a driving signal (e.g., VOUT in fig. 5) to be output by the driving circuit.
Be different from prior art, this application is through setting up a power sequential control circuit between power module and boost module, receive first logic voltage, first negative reference voltage and first positive reference voltage through power sequential control circuit, and output second logic voltage, second negative reference voltage and second positive reference voltage to boost module in proper order based on received voltage, make boost module can receive logic voltage, negative reference voltage and positive reference voltage in proper order, avoid the overcurrent protection mechanism of spurious triggering boost module and make whole drive circuit unable normal operating, drive circuit's reliability has been improved.
The present application further provides a display device, as shown in fig. 6, fig. 6 is a schematic structural diagram of an embodiment of the display device of the present application, and the display device 60 includes a display panel 63, a processor 62, and a driving circuit 61 of any one of the display panels described in the previous embodiments.
Specifically, the display device 60 may further include: a data driving chip (not shown).
The data driving chip is connected to the driving circuit 61, and is used for driving the display operation of the display panel 63 based on the driving signal sent by the driving circuit 61.
The power module 11 in the driving circuit 61 may include a PWM (Pulse width modulation) chip for outputting a logic signal (VDD), a high voltage signal (VGH) and a low voltage signal (VGL), and may be other types of power chips, which is not limited herein.
The processor 62 may be any type of device having computing or data processing capabilities and is not limited thereto.
The display panel 63 may include a plurality of pixel units arranged in an array, each pixel unit including at least one light emitting device, such as a light-emitting diode (LED).
The display panel 63 may be any one of a TN (Twisted Nematic) panel, an IPS (In-Plane Switching) panel, a VA (Vertical Alignment) panel, and other types of display panels, and is not limited herein.
Be different from prior art, this application is through setting up a power sequential control circuit between power module and boost module, receive first logic voltage, first negative reference voltage and first positive reference voltage through power sequential control circuit, and output second logic voltage, second negative reference voltage and second positive reference voltage to boost module in proper order based on received voltage, make boost module can receive logic voltage, negative reference voltage and positive reference voltage in proper order, avoid the overcurrent protection mechanism of spurious triggering boost module and make whole drive circuit unable normal operating, drive circuit's reliability has been improved.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A driving circuit of a display panel includes a power module and a boosting module connected to the power module, the power module for outputting a first logic voltage, a first negative reference voltage and a first positive reference voltage,
the driving circuit comprises a power supply time sequence control circuit, the power supply time sequence control circuit is connected between the power supply module and the boosting module, and the power supply time sequence control circuit is used for receiving the first logic voltage, the first negative reference voltage and the first positive reference voltage and outputting a second logic voltage, a second negative reference voltage and a second positive reference voltage to the boosting module in sequence.
2. The drive circuit according to claim 1, wherein the power supply timing control circuit includes a first timing circuit, a second timing circuit, and a third timing circuit;
the first timing circuit is used for outputting the second logic voltage to the boosting module when the first logic voltage reaches a preset logic voltage difference threshold value;
the second sequential circuit is used for outputting the second negative reference voltage to the boosting module after the boosting module receives the first logic voltage;
the third sequential circuit is configured to output the second positive reference voltage to the boost module after the boost module receives the first negative reference voltage.
3. The drive circuit according to claim 2,
the input end of the first timing circuit is connected with the power supply module, and the output end of the first timing circuit is connected with the boosting module;
the input end of the second sequential circuit is connected with the power supply module, the output end of the second sequential circuit is connected with the boosting module, and the driving end of the second sequential circuit is connected with the output end of the first sequential circuit;
the input end of the third sequential circuit is connected with the power supply module, the output end of the third sequential circuit is connected with the boosting module, and the driving end of the third sequential circuit is connected with the output end of the second sequential circuit.
4. The drive circuit according to claim 2 or 3, wherein the first timing circuit comprises:
one end of the first switch tube is connected with the logic voltage output end of the power supply module, and the other end of the first switch tube is connected with the logic voltage input end of the boosting module;
one end of the first resistor is connected with one end of the first switch tube, and the other end of the first resistor is connected with the driving end of the first switch tube;
one end of the second resistor is connected with the driving end of the first switch tube, and the other end of the second resistor is grounded.
5. The driving circuit according to claim 4, wherein the second timing circuit comprises:
one end of the second switch tube is connected with the negative reference voltage output end of the power supply module, and the other end of the second switch tube is connected with the negative reference voltage input end of the boosting module;
one end of the third resistor is connected with one end of the second switch tube, and the other end of the third resistor is connected with the driving end of the second switch tube;
one end of the fourth resistor is connected with the driving end of the second switch tube, and the other end of the fourth resistor is connected with the logic voltage input end of the boosting module.
6. The driving circuit according to claim 5, wherein the third timing circuit comprises:
one end of the third switching tube is connected with the positive reference voltage output end of the power supply module, and the other end of the third switching tube is connected with the positive reference voltage input end of the boosting module;
one end of the fifth resistor is connected with one end of the third switching tube, and the other end of the fifth resistor is connected with the driving end of the third switching tube;
one end of the sixth resistor is connected with the driving end of the third switching tube, and the other end of the sixth resistor is connected with the negative reference voltage input end of the boosting module.
7. The driving circuit according to claim 6, wherein the first switch transistor is a PMOS transistor, one end of the first switch transistor is a source, and a driving end of the first switch transistor is a gate; the second switch tube is an NMOS tube, one end of the second switch tube is a source electrode, and the driving end of the second switch tube is a grid electrode; the third switching tube is a PMOS tube, one end of the third switching tube is a source electrode, and the driving end of the third switching tube is a grid electrode;
when the gate-source voltage difference of the first switching tube reaches a first voltage difference threshold value, conducting one end of the first switching tube with the other end of the first switching tube, wherein the gate-source voltage difference of the first switching tube is a product obtained by multiplying the first logic voltage by a first resistance ratio, and the first resistance ratio is a quotient obtained by dividing the resistance value of the first resistor by the sum of the resistance value of the first resistor and the resistance value of the second resistor;
when the gate-source voltage difference of the second switching tube reaches a second voltage difference threshold value, conducting one end of the second switching tube with the other end of the second switching tube, wherein the gate-source voltage difference of the second switching tube is a product obtained by multiplying a first voltage difference by a second resistance ratio, the first voltage difference is a difference value between the second logic voltage and the first negative reference voltage, and the second resistance ratio is a quotient obtained by dividing a resistance value of the third resistor by a sum of a resistance value of the third resistor and a resistance value of the fourth resistor;
and when the gate-source voltage difference of the third switching tube reaches a third voltage difference threshold value, conducting one end and the other end of the third switching tube, wherein the gate-source voltage difference of the third switching tube is a product obtained by multiplying a second voltage difference by a third resistance ratio, the second voltage difference is a difference value between the first positive reference voltage and the second negative reference voltage, and the third resistance ratio is a quotient obtained by dividing the resistance value of the fifth resistor by the sum of the resistance value of the fifth resistor and the resistance value of the sixth resistor.
8. The drive circuit according to any one of claims 1 to 3, wherein the power supply module includes a voltage step-down circuit, a negative voltage circuit, and a voltage step-up circuit;
the voltage reduction circuit receives a power supply voltage and outputs the first logic voltage based on the power supply voltage, the negative voltage circuit receives the power supply voltage and outputs the first negative reference voltage based on the power supply voltage, and the voltage boost circuit receives the power supply voltage and outputs the first positive reference voltage based on the power supply voltage.
9. The driving circuit of claim 8, wherein the boost module comprises a logic circuit and a voltage boost circuit, the logic circuit being connected to the voltage boost circuit;
the logic circuit receives the second logic voltage, and the voltage boost circuit receives the second negative reference voltage and the second positive reference voltage, respectively.
10. A display device comprising a display panel, a processor, and a driving circuit of the display panel according to any one of claims 1 to 9.
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| CN202210141764.7A CN114613316A (en) | 2022-02-16 | 2022-02-16 | Driving circuit of display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210141764.7A CN114613316A (en) | 2022-02-16 | 2022-02-16 | Driving circuit of display panel and display device |
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