201233069 六、發明說明： 【發明所屬之技術領域】 接一種逐次近似暫存器類比數位轉換器，尤其是可以維 ，並藉由優化響糾_提高狱性的一種 概触雜11，収糊該秋近姆存麵比數位轉 換盗的類比數位轉換方法。 【先前技術】 ㈣i員i匕紐轉換器(anaIog_to_digital converter，縦)係為用於將類比 轉換為數位魏置，mc對_邮餘樣，並簡取樣的類比 信號轉換為對應於戶綱装類比信號之大小的數位碼或數位錢。在 中，逐次近似暫存器類比數位轉換器(繼esslve卿r()ximatl()n re麵r 搬1〇Η〇-ώ_ converter，SAR娜）包含：逐次近似暫存器(臟㈤ve approbation register . SAR)，, 減小’並將所結合的數位碼與類比信號作比較，以接近於鞠比信號。 典型的SARADC包括N位元(其中N係為大於或等於！的整數)數位類 比轉換器（digitai-t〇-anai〇gCOnverter，DAC)以及比較器。該 N 位元 dac 將N位元數位碼轉換為相對應的類比電壓。該比較器將該N位產生 的該類比賴錢人類比信餅比較。如果職人類比信號大於該類比電 壓’該比健產生高鱗信號，即具有邏輯值〗的信號。如果鋪比電壓 大於或等於該輸入類比信號，該比較器產生低位準信號，即具 的信號。 ' 當設定輸入至該N位元DAC的該數位碼的最高有效位元（m〇st significant bit，MSB)為邏輯值卜並將該n位元DAC產生的該類比電壓 與該輸入類比信號作比較時，可以決定N位元數位碼的MSB。然後，重複 上述比較處理，同時依序改變輸入至該N位元DAC的該數位碼的後續位 元’以決定對應該類比信號的該N位元數位碼。 然而，這樣的習知SAR ADC包含啟動級以及反相閘，用於重定產生 MSB的數位信號的SR正反器。將啟動信號START輸入至該啟動級，接著 201233069 透過該啟動級在該反相閘中，對該啟動信號START的相位進行反向，並因 此反相閉產生重設信號RESET。在該重設信號reSEt輸入至該SR正反_ 時，該SR正反器產生MSB的該數位信號。此時，如第丨圖及第2圖所示器 由於MSB的該數位信號與該啟動信號START具有兩個相位差，增加了7^ 算時間。因此’在對於騎度的最辦_難轉行該逐次近似暫存器邏 輯電路SAR，以及為了獲得適於解析度的相同的運行時間，該逐次近似暫 存器邏輯電路SAR所遭遇到了諸如快速提供輸入至該逐次近似暫存器邏 電路SAR的一時鐘週期的問題。 進一步地’該典型的DAC包含如第2圖所示的二進位加權電容。含有 二進位加權電容的該DAC具有比電阻更高的線性，且有利於低功率消耗的 設計。然而，如升高解析度，具有最大尺寸的電容與具有最小尺寸的電容 的比率急劇升高。例如，在8位SDAC的情況中，與該MSB對應的電容 的尺寸疋最小電容尺寸的128倍。當一單元電容用於匹配特徵，需要256 個電容。因此，當考慮到匹配所確定的電容尺寸非常大時，該DAC的總面 積升高’由此，破壞整體整合性且使電路複雜化。 【發明内容】 因此’本發明係有關於一種逐次近似暫存器類比數位轉換器(saradc) 及利用該逐次近似暫存器類比數位轉換器的類比數位轉換方法，其實質上 是排除由於習知技術的限制與缺點造成的一或多個的問題。 、 本發明的一目的在於，提供一種SARADC及其類比數位轉換方法，其 可維持對贿析度的最錢行賴，並藉由提轉斜間而提升穩定性。 本發明的其他優點及特徵，將在下面的說明書中部分地闡述，以及部 分的對於熟悉該項技藝者在研習下文後是顯而易見的，或可通過實踐本發 明習知。本發明的目的及其他優點，可藉由本說明書、申請專利範圍及圖 式所指出的結構而實現與獲得。 為了達到這些及其他優點，以及依照本發明的目的，在此，整體而概 括地描述，一種逐次近似暫存器類比數位轉換器（SARA〇c)包括〔一取 樣及保持放大器(sample-and-hold amplifier，SHA)，其用於取樣並保持一外 部輸入類比電壓；-比較器，其用於比較所取樣並保持的外部輸入類比電 201233069 制位準與對應於MU元的類比信賴位準，其中n絲不小於i的整數， 以及依據比較結果產生-比較紐；-逐次近㈣存器邏輯電路，其用於 從最高有效位元（MSB)至最低有效位元（LSB)依序產生__數位^號， 以響應該比較信化-齡_賴_从），翻於雜序產生的=信 號轉換為類比信號，並提供該類比信號至該比較器；以及一輸出暫存器， 其用於保持㈣MSB至LSB所依序產生的數位信號，以產生—η位缝 位信號’其巾當從外部無-啟動餓時，該逐次近似暫存^邏輯電路產 生相對於啟動錢具有-位元相錢遲之最高有效位元賴位信號。 該逐次近似暫存器邏輯電路可包含：一啟動級，其用於接㈣比較信 號，並使該比較信號與該時鐘信號同步；一位移暫存器，包含(η+ι)個串聯 級’並根據該啟動信號與時鐘信號而依序產生第—位移脈衝至第叫位移 脈衝；η個邏觸極，餘依序產生n個邏輯信號，以響應通過該啟動級斑 该第二位移脈衝至該第n+1位移脈衝而依序產生的該比較信號；以及一逐 次近似暫存H，其驗依序接收該第_位移脈衝至^ n轉脈衝、該η個 邏輯信號，並賴最高有舰元至最低有錄元辦產找η㈣數位信 該DAC可具有-c_2c梯形結構以及具有至少一開關元件以及第一電容 串聯連接的配置’纽該至少—_元件錢該第 接的複數個第二電容之間的—連接節點，以平行於該等第二電妾容在串聯連 以響數個細H魏序產生複數麵傾果信號， 以響應通猶啟舰位移_祕序產生的槪較信號。 包含於該位移暫存器的該n+1個争聯級的第一級可係為一 D正反器， 2=2:設定電壓的一輸人終端，該第—級將對應於該設定電塵的 ^存器正二=第—位移脈衝，施加於該逐次近似暫存器的第一位移 暫存器正反Is ’轉應該啟動信號，而該第—位移暫存器正反器與一 步產生她於紐動錢具有—位元她 疋的該數位信號。 取πτπ双伹 比提供—翻隠近罐隱舰轉換器的類 ' 匕.取樣並保持一外部輸入類比電壓；比較所取樣祐 …的外部輸入類比電魔的位準與對應於η位元的類比信號的位準，其中η 201233069 係f科於一1的整數’以及依據比較結果產生一比較信號；依序產生來自 最尚有效位το (MSB)至最低有效位元（LSB)的一數位信號，以響應該 比較信號；將依序產生的數位信號轉換為類比信號，並產生該類比信號； 以及保持從該MSB至該LSB所依序產生的數位信號，以產生一 n位元數 位信號》 »亥依序產生一數位彳§號可包含：當外部接收一啟動信號時，產生相對 於該啟動信號具有-位元相位延遲之最高有效位元的數位信號。 序產生-數健號可包含：触該比較信號，並使該比較信號與 時鐘城辭；輯接收自外部的該啟動信驗該雜信驗序產生第一 位f脈衝至第n+1位移脈衝；依序產生n個邏輯信號，以響應該同步的比 較信號與該第二位移脈衝至第n+1位移脈衝；以及依序接收該第—位移脈 衝至第η娜_與n位元賴職’並從該最高有效位元至最低有效位 元依序產生該η位元數位信號。 可使用梯雜構的DAC:騎依序產生的數位錢轉換為該類比 信號並產线類比信號，在該DAC中至少一開關元件以及第一電容串聯連 接’並連接至在_聯連接的複數㈣二電容之_—連 該等第二電容。 丁 η產生相對於該啟動信號具有一位元相位延遲之最高有效位元的數位俨 號包含：施加-設定電塵至包含在該位移暫存器中的該等串聯級的第一級 : 施加對應於該設定電壓的該第一位移脈衝至該第一級，以響應該啟動信號· ^及產生相對於該啟動信號具有一位元相位延遲之最高有效位元的數位俨 號，以響應該第一位移脈衝與該第一邏輯結果信號。 β須知，前述的總說明以及下文的詳細說明，都是示例性與轉性的， 是為了進一步闡明本發明的申請專利範圍。 【實施方式】 現將引用所關式辑細說明本發_频實施例。盡可能地 圖式中涉及的相同或類似的元件將採用相同的附圖標記。 、 第3圖係為說明依據本發明實施例之逐次近似暫存器類比數 的方塊圖。第3圖的逐次近似暫存器類比數位轉換器包含：、取 201233069 樣保持放大器(SHA) 2，其用於取樣並保持一外部輸入類比電壓vjn ;比較 器4 ’其用於比較所取樣並保持的類比輸入電壓的位準與對應n位元的類比 輸出信號的位準，以及依據比較結果產生一比較信號c_〇ut;逐次近似暫存 器邏輯電路6，其用於依序產生從最高有效位元(MSB)至最低有效位元(LSB) 的一數位信號，以響應該比較信號C—out;數位類比轉換器(dac) 1〇，其用 於將依序產生的數位k號轉換為類比輸出信號，並提供該類比輸出信^至 比較器4 ;以及輸出暫存器8，其用於保持從MSB至LSB所依序產生的數 位信號’以產生一 η位元數位信號〇utn。 如上述構成的該SAR ADC可進一步包含：供電器，用於產生驅動諸 如取樣保持放大器2、比較器4、輸出暫存器8等之組成元件所需的驅動電 壓，例如，設定電壓VDD、接地電壓VSS、以及施加於數位類比轉換器1〇 的參考電壓Vref;以及時鐘產生器，其提供至少一時鐘信號咖至逐次近 似暫存器邏輯電路6。或者’該供電器與該時鐘產生器可如第3圖所示單獨 構成，使得施加該等驅動電壓，例如設定電壓VDD、接地電壓vss與參考 電壓Vref以及至少一時鐘信號CLK至該SAR。 該SARADC的取樣保持放大器2對外部輸入類比電壓Vin取樣，保 持並放大所取樣的電壓’以免使所取樣的電壓失真，以及產生所取樣並保 持的類比輸人電壓Vh。取樣保持放大器2主要用於取樣並保持—高解析度 類比圖形信號，並包括至少一電容、一放大電路與一切換元件。 比較器4比較所取樣並保持的類比輸入電壓Vh的位準與對應n位元之 依次輸入的類比信號的位準，並依據比較結果產生高或低位準的比較信號 C_〇u=由於第-輸人紙信號的轉相#於職參考錢μ的位準:它° 可能高於聽持醜比龍vh。比㈣4產生高或低位準的比較信號 C_〇ut ’以使依序輸入至少一位元為單位的類比輸出信號D—v的位準等於 保持類比電壓Vh的位準。 逐次近似暫存轉輯電路6财產倾MSB至LSB的n預設位元的 數位信號0她’以響應高或低位準的比較信號C_〇ut。特別地，當啟動信 號由外部輸人’逐次独暫存器麵電路6產生她於啟練號I有一位 兀相位延遲的MSB的數位域，轉餘時鐘產生器纽的時號CM ，、從比lx器4產生的比較信號c—⑽。將所產生的MSB的數位信號施加於 201233069 =類比轉齡1G。Μ，逐麵似暫存騎輯電路6產生她於 具有-位相位延遲的位元數位信肋響麟鐘信號咖較 c_〇m，它們都隨著下一相位延遲輸入。在此樹，二= =6依序產生從_至LSB之預設n位元的數位信號，以響應子從= 產生器產生的時鐘«CLK與從比較器4產生的至少—位元為單位的高或 低位準_較《 C』Ut。暖將麻料逐:域崎存^賴電路“ 數位類比轉換H 1G將從逐次近似暫存n邏輯· 6依序輸入之至 -位元為單㈣數位舰賴騎應n低_比細錢β v。數位類 比轉換器H)可為具有簡化的電路配置的小規模•梯形數位類比轉換 盗。在數位類比轉換器1G中，相互串聯連接之至少—切換元件以及第一電 容付連接至在複數個串聯連接的第二電容之間的連接節點。數位類比轉 換器10依據從逐次近似暫存器邏輯電路6依序輸人之至少_位福單位的 數位信號’藉由施加接地電壓VSS或參考電壓Vref至在該等第二電容之間 的連接節點，產生對應於n位元的類比輸出信號D v。 曰 如上所述，對應於η位元_比輸出信號D_v的位準依據從逐次近似 暫存器邏Μ路6依序輸人喊位錄㈣彳卜因此，峻^4依據比較 對應於η侃之依序輸人類比輸出信號D_v的位準與所保持之類比輸入電 壓vh的位準的結果，產生比較紐c_〇ut，由此使逐二欠近似暫存器邏輯電 路6依序產生數位信號的後續位元。然後，重複數位類比轉換器ι〇再次 依據依序產生的後續位元產生對應於n位元_比輸出錢D—v以及比較 器4比較輸入信號位準的處理。結果，確定對應於所保持的類比輸入電壓 Vh的η位元數位信號。 輸出暫存器8依序保持通過逐次近似暫存器邏輯電路6從MSB至lSB 所產生的數位信號，以產生η位元數位信號〇utn。 第4圖係為說明第3圖所示之SAR邏輯電路ό的方塊圖。 逐次近似暫存器邏輯電路6包含：啟動級SD，其用於接收來自該較器 4的比較仏號C—out ’並使比較信號C_〇ut與外部輸入時鐘信號CLK同步； 位移暫存器SR，其包含複數個級D0至Dn，並根據啟動信號St與時鐘信 號CLK依序產生位移脈衝s〇至Sn ;複數個邏輯閘AGi至AGn，其用於 依序產生邏輯信號，以響應通過啟動級SD與位移脈衝s〇至Sn而依序產 9 201233069 ^的比較信號c_GUt;以及逐錢轉如SAR，帛贿序触該等位移 脈衝S0至Sn與該等邏輯信號，並依序產生從娜至LSB的n位元數位 信號Outn。 該啟動級SD可包含至少-D正反器。啟動級SD將至少一位元為單 =而依序輸入的比較錢c_out同步於外部輸入的時鐘信號clk，並依序 產生至少一位元週期為單位的比較信號。 ^移暫存器SR包含：複數個串聯級D〇至〇η，並根據外部輸入的啟 動城St與依序輸入的時鐘信號CLK依序產生該等位移脈衝s〇至如。各 :聯級〇0至〇„可包含D正反器。該等D正反器相互串聯。如果輸入啟 動減St，鱗D正反ϋ根據依次提供㈣鐘信號clk依序位移啟動信號 St，並產生位移脈衝so至Sn。 各個該等邏輯閘鳩至AGn可為娜閘極。反相閘極ng可連接至 啟動級SD的比較信號C_out的輸出終端，以反相比較信號c⑽的相 ，。含有AND閉極的邏輯閘AG1至AGn依序產生邏輯結果信號，以響應 j過啟動級SD與位移脈衝s〇至如依次所產生之依序輸入的反相比較信 逐次近似暫存H SAR包含第-至第n位移暫存器正反器如至娜， 、同時接收時鐘信號CLK。第-至第n位移暫存器正反器测至SRn連 妾至對應於各自的位移暫存器SR的串聯級D〇至Dn的輸出終端，並通過 各自，第一輸入終端S而接收對應的位移脈衝s〇至Sn。第一至第n位移 =存器正反器SR1至SRn也連接至對應於各自的邏輯閘AG1至AGn的輸 ’並通過各自的第二輸人終端R接收對應的邏輯信號。第—至第n位 β暫存器正反器SR1至SRn根據依序輸入的位移脈衝s〇至㈤與邏輯信201233069 VI. Description of the invention: [Technical field to which the invention pertains] A successive approximation register analog-to-digital converter, in particular, can be dimensioned, and by optimizing the ringing correction _ to improve the prisoner's characteristics, The analog digital conversion method of the autumn near the face is more than the digital conversion. [Prior Art] (4) The iA_____ converter is used to convert the analog to digital, mc to _ postal samples, and the analog sampled signal is converted to the corresponding class. A digital code or digit of the size of the signal. In, the successive approximation register analog-to-digital converter (following esslveqing r() ximatl() n reface r moving 1〇Η〇-ώ_ converter, SAR na) contains: successive approximation register (dirty (five) ve approbation register SAR),, reduce 'and compare the combined digital code to the analog signal to approximate the analog signal. A typical SARADC includes a N-bit (where N is an integer greater than or equal to !) a digital analog converter (digitai-t〇-anai〇gCOnverter, DAC) and a comparator. The N-bit dac converts the N-bit digit code into a corresponding analog voltage. The comparator compares the analogy produced by the N-bit to the leaner human than the letter cake. If the occupational human ratio signal is greater than the analog voltage, the ratio produces a high-scale signal, i.e., a signal having a logical value. If the plot voltage is greater than or equal to the input analog signal, the comparator produces a low level signal, i.e., a signal. When setting the most significant bit (MSB) of the digital code input to the N-bit DAC to a logical value and making the analog voltage generated by the n-bit DAC and the input analog signal When comparing, the MSB of the N-bit digit code can be determined. Then, the above comparison processing is repeated while sequentially changing the subsequent bit ' of the digital code input to the N-bit DAC to determine the N-bit digital code corresponding to the analog signal. However, such conventional SAR ADCs include a start stage and an inverting gate for resizing an SR flip-flop that produces a digital signal of the MSB. The start signal START is input to the start-up stage, and then 201233069 through the start-up stage, the phase of the start signal START is reversed in the inverter, and thus the reset signal RESET is generated. When the reset signal reSEt is input to the SR positive and negative _, the SR flip-flop generates the digital signal of the MSB. At this time, as shown in the first diagram and the second diagram, since the digital signal of the MSB has two phase differences from the start signal START, the calculation time is increased by 7^. Therefore, the successive approximation register logic circuit SAR is successively approximated in the most difficult state of riding, and in order to obtain the same running time suitable for resolution, the successive approximation register logic circuit SAR is encountered such as fast provisioning. A problem of one clock cycle input to the successive approximation register logic circuit SAR. Further, the typical DAC includes a binary weighted capacitance as shown in Fig. 2. The DAC with binary weighted capacitance has a higher linearity than the resistance and is advantageous for low power consumption designs. However, if the resolution is increased, the ratio of the capacitor having the largest size to the capacitor having the smallest size is sharply increased. For example, in the case of an 8-bit SDAC, the size of the capacitor corresponding to the MSB is 128 times the minimum capacitance size. When a cell capacitor is used to match features, 256 capacitors are required. Therefore, when the capacitance determined in consideration of the matching is very large, the total area of the DAC rises', thereby damaging the overall integration and complicating the circuit. SUMMARY OF THE INVENTION Accordingly, the present invention relates to a successive approximation register analog-to-digital converter (saradc) and an analog-to-digital conversion method using the successive approximation register analog-to-digital converter, which substantially excludes conventional knowledge. One or more problems caused by technical limitations and shortcomings. SUMMARY OF THE INVENTION It is an object of the present invention to provide a SARADC and analogous digital conversion method which maintains the most costly reliance on bribery and improves stability by improving the slanting interval. Other advantages and features of the present invention will be set forth in part in the description which follows. The objectives and other advantages of the invention may be realized and obtained by the structure of the invention. To achieve these and other advantages, and in accordance with the purpose of the present invention, as a whole, generally described, a successive approximation register analog-to-digital converter (SARA〇c) includes [a sample-and-hold amplifier (sample-and- Hold amplifier, SHA), which is used to sample and maintain an external input analog voltage; a comparator for comparing the sampled and held external input analog to the 201233069 level and the analog trust level corresponding to the MU element, Wherein n is not less than an integer of i, and generates a comparison-comparison according to the comparison result; - successively near (four) register logic circuit for sequentially generating from the most significant bit (MSB) to the least significant bit (LSB) a _digit ^ in response to the comparison of the letter-age _ _ _ _), the = signal generated by the mutated sequence is converted to an analog signal, and the analog signal is provided to the comparator; and an output register, For maintaining (4) the digital signal generated by the MSB to the LSB in order to generate the -n position slot signal 'when the towel is not activated from the outside, the successive approximation temporary logic circuit generates a bit relative to the start money Metaphase Lai Chi of the most significant bit signal. The successive approximation register logic circuit can include: a start stage for connecting (4) the comparison signal and synchronizing the comparison signal with the clock signal; a displacement register comprising (n+ι) series stages And sequentially generating a first displacement pulse to a first displacement pulse according to the start signal and the clock signal; n logic poles, and sequentially generating n logic signals in response to the second displacement pulse passing through the startup stage spot The comparison signal generated sequentially by the n+1th shift pulse; and a successive approximation temporary storage H, the program sequentially receiving the _th shift pulse to the n-th pulse, the n logic signals, and the highest The DAC can have a η (four) digital letter. The DAC can have a -c_2c ladder structure and a configuration having at least one switching element and a first capacitor connected in series. The connection node between the two capacitors generates a complex surface declination signal in parallel with the second electrical capacitance in series and several times in order to respond to the 产生 秘 位移 _ _ _ _ More signal. The first stage of the n+1 contention stage included in the displacement register may be a D flip-flop, 2=2: an input terminal of a set voltage, and the first stage will correspond to the setting. The electric dust is stored as the first displacement pulse, and the first displacement register applied to the successive approximation register is forward and reverse Is' the start signal, and the first displacement register is the forward and reverse Producing her digital signal with the money in her hand. Take the πτπ double 伹 ratio to provide - turn the near-tank hidden converter class ' 匕. Sampling and maintain an external input analog voltage; compare the external input analog of the analog ... to the level of the electric magic and corresponding to the η bit The level of the analog signal, where η 201233069 is an integer of '1' and generates a comparison signal according to the comparison result; sequentially generates a digit from the most significant bit το (MSB) to the least significant bit (LSB) And responsive to the comparison signal; converting the sequentially generated digital signal into an analog signal and generating the analog signal; and maintaining the digital signal sequentially generated from the MSB to the LSB to generate an n-bit digital signal The generation of a digit 彳 § can include: when externally receiving a start signal, generating a digital signal having the most significant bit of the -bit phase delay relative to the enable signal. The sequence generation-number key may include: touching the comparison signal, and causing the comparison signal to be synchronized with the clock city; and receiving the start signal from the outside to detect the noise sequence to generate the first bit f pulse to the n+1th shift Pulses; sequentially generating n logic signals in response to the synchronized comparison signal and the second displacement pulse to the n+1th shift pulse; and sequentially receiving the first displacement pulse to the ηna_ and n-bit ray The job' generates the n-bit digital signal sequentially from the most significant bit to the least significant bit. A ladder DAC can be used: the digitally generated digital data is converted into the analog signal and the line analog signal, in which at least one switching element and the first capacitor are connected in series 'and connected to the complex number in the _ connection (4) Two capacitors _ - connected to the second capacitor. The digits of the most significant bit having a one-dimensional phase delay relative to the enable signal include: applying-setting the dust to the first stage of the series stages included in the shift register: Corresponding to the first displacement pulse of the set voltage to the first stage, in response to the enable signal and generating a digital apostrophe having a most significant bit of a one-dimensional phase delay with respect to the enable signal, in response to the The first displacement pulse is coupled to the first logic result signal. The above general description and the following detailed description are exemplary and versatile, and are intended to further clarify the scope of the invention. [Embodiment] The present embodiment will now be described in detail with reference to the related embodiments. The same or similar elements referred to in the drawings will be given the same reference numerals as possible. Figure 3 is a block diagram showing the number of successive approximation register analogies in accordance with an embodiment of the present invention. The successive approximation register analog-to-digital converter of Figure 3 contains: a 201233069 sample-hold amplifier (SHA) 2 for sampling and holding an external input analog voltage vjn; a comparator 4' for comparing the samples and Maintaining the level of the analog input voltage and the level of the analog output signal corresponding to the n-bit, and generating a comparison signal c_〇ut according to the comparison result; sequentially approximating the register logic circuit 6, which is used to sequentially generate the slave a digital signal from the most significant bit (MSB) to the least significant bit (LSB) in response to the comparison signal C_out; a digital analog converter (dac) 1〇, which is used to sequentially generate the digit k number Converting to an analog output signal and providing the analog output signal to comparator 4; and output register 8 for maintaining the digital signal generated sequentially from MSB to LSB to generate an n-bit digital signal. Utn. The SAR ADC constructed as described above may further include: a power supply for generating a driving voltage required to drive constituent elements such as the sample-and-hold amplifier 2, the comparator 4, the output register 8, and the like, for example, setting voltage VDD, grounding a voltage VSS, and a reference voltage Vref applied to the digital analog converter 1〇; and a clock generator that provides at least one clock signal to the successive approximation register logic circuit 6. Alternatively, the power supply and the clock generator may be separately constructed as shown in Fig. 3 such that the driving voltages such as the set voltage VDD, the ground voltage vss and the reference voltage Vref, and at least one clock signal CLK are applied to the SAR. The sample-and-hold amplifier 2 of the SARADC samples the external input analog voltage Vin to maintain and amplify the sampled voltage 'to avoid distorting the sampled voltage and to generate the sampled and held analog input voltage Vh. The sample and hold amplifier 2 is mainly used for sampling and maintaining a high resolution analog pattern signal and includes at least one capacitor, an amplifying circuit and a switching element. The comparator 4 compares the level of the analog input voltage Vh sampled and held with the level of the analog signal sequentially input corresponding to the n-bit, and generates a comparison signal of the high or low level according to the comparison result C_〇u= - Inverted paper signal phase inversion # 职 reference money μ level: it ° may be higher than listening to the ugly than the dragon vh. The comparison signal C_〇ut' is generated at a higher or lower level than (4) 4 such that the level of the analog output signal D_v in which at least one bit is sequentially input is equal to the level of the analog voltage Vh. The digital signal 0 of the n preset bit of the temporary dump circuit 6 to the LSB is successively approximated to respond to the high or low level comparison signal C_〇ut. In particular, when the enable signal is generated by the external input, the successive single-storage surface circuit 6 generates a digital field of the MSB having a phase delay of the start number I, and the time code CM of the remaining clock generator The comparison signal c_(10) generated by the lx device 4. The generated digital signal of the MSB is applied to 201233069 = analogy to age 1G. Μ, the face-to-face temporary storage circuit 6 produces her bit-level symmetry signal c_〇m with a phase delay, which are both delayed with the next phase input. In this tree, two ==6 sequentially generates a digital signal of the preset n-bit from _ to LSB in response to the clock «CLK generated by the slave from the generator and at least the bit-generated from the comparator 4. The high or low level is better than the "C" Ut. Warm will be hemp material: domain resilience ^ Lai circuit "digital analog conversion H 1G will be sequentially approximated n logic · 6 sequentially input to - bit is single (four) number of ships Lai riding should be low _ than fine money β v. The digital analog converter H) can be a small-scale • trapezoidal digital analog conversion with a simplified circuit configuration. In the digital analog converter 1G, at least the switching elements and the first capacitor are connected to each other in series a plurality of connection nodes between the second capacitors connected in series. The digital analog converter 10 is based on a digital signal of at least _bits of a unit of input from the successive approximation register logic circuit 6 by applying a ground voltage VSS or The reference voltage Vref to the connection node between the second capacitors generates an analog output signal Dv corresponding to n bits. As described above, the level corresponding to the n-bit_output signal D_v is successively Approximate register logic channel 6 sequentially instructs the caller to record the position (4). Therefore, Jun^4 compares the level of the human output signal D_v and the analog input voltage vh according to the order corresponding to the η侃. The result of the level, resulting in a comparison of new c_ 〇ut, thereby causing the two-bit owing approximation register logic circuit 6 to sequentially generate subsequent bits of the digital signal. Then, the repeated digital analog converter ι 〇 again generates the n-bit corresponding to the subsequent bit generated sequentially. The processing of comparing the input signal level with the output money D_v and the comparator 4. As a result, the n-bit digital signal corresponding to the held analog input voltage Vh is determined. The output register 8 is sequentially maintained by successive approximation. The logic circuit 6 generates a digital signal generated from the MSB to the lSB to generate an n-bit digital signal 〇utn. Fig. 4 is a block diagram showing the SAR logic circuit shown in Fig. 3. Successive approximation register The logic circuit 6 includes a startup stage SD for receiving the comparison symbol C_out ' from the comparator 4 and synchronizing the comparison signal C_〇ut with the external input clock signal CLK; a shift register SR, which includes a plurality of stages D0 to Dn, and sequentially generate displacement pulses s〇 to Sn according to the start signal St and the clock signal CLK; a plurality of logic gates AGi to AGn, which are used to sequentially generate logic signals in response to the start stage SD and Displacement pulse s 〇 to Sn The comparison signal c_GUt of the pre-production 9 201233069 ^; and the transfer of money as SAR, the bribes touch the displacement pulses S0 to Sn and the logic signals, and sequentially generate the n-bit digital signal Outn from Na to LSB. The startup stage SD may include at least a -D flip-flop. The startup stage SD synchronizes at least one bit to a single = and the sequentially input comparison money c_out is synchronized with the externally input clock signal clk, and sequentially generates at least one bit period. The unit comparison signal. The shift register SR includes: a plurality of series stages D〇 to 〇η, and sequentially generates the displacement pulses s according to the externally input starter city St and the sequentially input clock signal CLK. Such as. Each: the joint 〇0 to 〇 „ can include D flip-flops. The D flip-flops are connected in series with each other. If the input starts to decrease St, the scale D is positively and negatively ϋ according to the sequential (four) clock signal clk sequentially shifting the start signal St, And generating displacement pulses so to Sn. Each of the logic gates to AGn may be a gate. The inverting gate ng may be connected to the output terminal of the comparison signal C_out of the startup stage SD to invert the phase of the comparison signal c(10). The logic gates AG1 to AGn with AND closed electrodes sequentially generate logical result signals in response to the j-over-start stage SD and the displacement pulse s〇 to the inverted comparison signals sequentially generated in sequence, sequentially approximating the temporary H SAR The first to the nth shift register flip-flops, such as 至娜, receive the clock signal CLK at the same time. The first to the nth shift register flip-flops measure the SRn connection to correspond to the respective shift register The series stages D of SR are connected to the output terminals of Dn, and receive corresponding displacement pulses s 〇 to Sn through respective first input terminals S. First to nth displacements = register flip-flops SR1 to SRn are also connected to Corresponding to the respective logic gates AG1 to AGn's inputs' and through their respective second input terminals R Receiving a first logic signal corresponding - to n-th bit flip-flop β register SR1 to SRn are sequentially inputted from the displacement pulse s〇 to (v) and logical channels
Du依序產生來自MSB至LSB的η位元數位信號outn，以響應依次提供 的時鐘信號CLK。 ’ 、 第5圖係為說明第3圖所示之數位類比轉換器的電路圖。 第5圖的數位類比轉換器1〇具有c_2c獅結構。在數位類比轉換器川 ’相互串聯連接之至少__切換元件以及第__t容c平行連接至在相互串 聯連接的複數個第二電容2(：之_連接節點。 由於最大電容的容量相對小於由二進位加權電容組成的習知數位類比 201233069 轉換器，本發明的數位類比轉換器可減少其總面積。 數位類比轉換器10產生對應於η位元的類比輸出信號D_v，其電壓位 準根據從逐次近似暫存器邏輯電路6以至少一位元為單位依序輸入的位元 信號out—1至out—n而變化。也就是，根據從逐次近似暫存器邏輯電路6 以至少一位元為單位依序輸入的位元信號〇ut—l至〇ut—n，c_2c梯形的數位 類比轉換器10導致接地電壓VSS或參考電壓Vref被施加於在第二電容2C 之間的連接節點，由此產生對應於n位元的類比輸出信號D_v，並施加對 應於η位元的類比輸出信號D_v於比較器4。 第6圖係為說明第4圖所示之逐次近似暫存器邏輯電路的操作方法的 驅動波形圖。S 7 ®係為說明第4 @1所示之逐次近似暫存器邏輯電路的操 作方法的示意圖。在第6圖與第7圖卜將描述作為一實施例❾12位元逐 次近似暫存器數位類比轉換器，以及在第7圖中，將描述開始於第Η位元 之三MSB的轉換處理。 參閱第4圖、第6圖與第7圖，當輸入啟動信號St至包含於逐次近似 暫存器邏輯電路6中的位移暫存器SR的第一串聯級D〇時，藉由施加於 第一串聯級D0的D輸入終端的設定電壓VDD而設置第一串聯級D〇。所 設置的第-φ魏DG提賴應於位逐次独暫存器⑽㈣—位移暫存 器正反器SIU的設;t電壓的高邏輯的第—位移脈衝S()。然後逐次近似暫存 益SAR的第-位移暫存器正反器如與第一位移脈衝s〇同步地產生‘ρ 的MSB的數位舰，以及其他的位移暫存器正反器肥、奶施 二=位L號。ut—2、〇ut_3…。ut_n。也就是，該逐次近似暫存器s 始化為___，的數位信號。此時，如第6圖所示，蠢的數 與啟動信號St具有一相位差。因此，由於廳的數位信號_ 與=動信號St具有-她差，與在聰的_請_丨與啟動信號-汾 之間具有2相位差的習知技術相比，本發明可減少運算時間。 :後’將從逐次近似暫存器SAR產生的數位信號，_〇_〇〇,施加 電比轉，10，且數位類比轉換器10將數位信號轉換為類比輸出 較4賴比輸㈣壓D—績在脱2惊細轉的^ 作為比較結果，當類比輸入信號Vh大於或等於類比輸出信號比 201233069 較器4產“辦的比較信^—⑽。高轉紙雛號C_〇ut_位藉由 欠動級反相閘極船中反相，且比較信號c—〇ut被轉換為低位準的 比較信號。當輸入低位$的比較信號至·間極AG時，娜問極ag 產生-低位準’並因此第—位移暫存器正反器SR1保持‘丨，的位元數位信 °虎換σ之逐-人近似暫存器SAR藉由一回馈處理產生數位作於 ‘100000000000,。 同時，作為一比較結果’當類比輸入信號vh小於類比輸出信號D—v 時^比較器4產生低位準的比較信號c—⑽。低位準的比較域c—〇ut的相 位藉由啟動級SD在反相閘極NG中反相，且比較信號c—⑽被轉換為高 位準的比較信號。高位準的比較信號藉由娜閑極AG而被轉換為高位 準’ f施加於第-位移暫存器正反器SR1的S終端。重定第-位移暫存器 正反器SR卜以產生具有值‘〇,的MSB。換言之，逐次近似暫存器藉 由一回饋處理產生數位信號‘00000000000〇,。 然後，第一串聯級D0的位移脈衝與時鐘信號CLK同步地被位移至第 二串聯級D1⑧輸人終端。然·次近靖存器驗㈣二位移暫存器 正反器SR2與第二位移脈衝S1同步地產生具有—位以，的數位信號 _2且其他位移暫存II正反器產生具有—位以，的數位信號〇也」、 =t_4...out_n。換言之，逐次近似暫存器產生初始化為[聰嶋刪 [ο ιοοοοοοοοοο]的數位信號。 數位類比轉㈣1G即麵⑽麵⑻陶⑽麵麵⑻]的數位信號轉 換為類比輸出電壓D_v。比較器4將類比輸出電壓D ;持 大器2中娜樣顧持的_輸人舰Vh佩較。—狀保持放 作為比較料，當酿輸人信號Vh A於鱗_ 較器4產生高辦的崎職d鱗的比較紐 較l喊。將低位準的比較信號輸入至娜閘極AG2。娜閘極迎產 =二低位準’翻此第二位移暫存器正反器SR2保持ί，的位讀位信號。 崎純SAR|1自—喃處理纽數絲船___〇, 或 010000000000,。 同時’作為一比較結果，當類比輸入信號yh小於類比輸出信號Ο) 12 201233069 時，比較器4產生低位準的比較信號C_out。低位準的比較信號C_out的相 位藉由啟動級SD在反相閘極NG中反相，且比較信號C_out被轉換為高 位準的一比較信號。高位準的比較信號藉由AND閘極AG2而被轉換為高 位準，並重定第二位移暫存器正反器SR2，以產生一位元‘〇,的數位信號。 換言之’逐次近似暫存器SAR產生數位信號‘looooooooooo,或 ‘000000000000,〇 依此方法，逐次近似暫存器邏輯電路6從MSB至LSB依序產生預設η 位元的數位信號’以響應從時鐘產生器依序輸入的時鐘信號以及從比較器4 以至少一位元為單位輸入的高或低位率的比較信號c—〇ut。數位類比轉換 器10將從逐次近似暫存器邏輯電路6以至少一位元為單位依序輸入的數位 信號轉換為對應於η位元的類比輸出信號d_v。 第8圖係為說明第3圖之逐次近似暫存器類比數位轉換器的n位元數 位信號判斷方法的圖表。 參閱第6圖與第8圖，通過數位類比轉換器1〇以至少一位元為單位產 生之對應於η位元類比輸出信號D_v的位準根據逐次近似暫存器SAR之依 序輸入的數位信號〇utn而變彳卜比較n 4比較對應於n位元之依序輸入的 類比輸itMs號D_v的位軸所絲賴比輸人輕vh的辦，並依序產 生比較信號C_〇ut。逐次近似雜騎輯祕6依隸生触信號的後續 位疋，以響應所依序產生的比較信號C—out。數位類比轉換器1〇產生對應 於η位元的類比輸出信號D_v，以響應所依序產生的後續位元，且比較器 4比較輸人信號位準，由此判斷對應於所保持_比輸人輕％的位準的 Μ^數位信號outn。輸出暫存器8依序保持從議至娜通過逐次近 電路6祕序產生的數位錢，以產生續讀健號0咖。 依據本發明所規範的實關，具有上騎_ SAR wc及使用· =AC的數位類比轉換方法，可藉由在處理n位所需的運算時間期間，僅產 最並不需要額外的運算時間，而保持對於解析度的 ，j算時間。進-步地，藉由一絲微分結構形成sar奶匚，具有使 二❿梯形類比數位轉換器關化電路結構，由此降低雜訊干擾。 孰决太^離本發_精神絲®⑽相本發·各讎《變更對於 謝領_增_咖。，她旨磁她 13 201233069 範圍和相等量的範圍内提供的本發明的修飾和變更。 本申凊案主張2010年12月1〇日提交之韓國專利申 10-2010-0126553 號及 2011 主 11 日 17 〇 坦-_ ^ ^ 贶汉年11月17日提交之韓國專利申 10-2011-G11991G號的權利’透過㈣將其全部結合到本巾請案中。 【圖式簡單說明】 所附圖式其中提供關於本發明實施例的進一步理解並且結合與構成本 説明書的-部份’說明本發_實施例並且描述—同提供對發 例之原則的轉。 货乃頁拖 圖式中： 第1圖係為說明依據習知技術之逐次近似暫存器邏輯電路的操作方 的藤動波形圖； ' / 第2圖係為說明依據習知技術之數位類比轉換器的電路圖； 、方=·_為說據本發明實施例之逐次近似暫存器類比數位轉換器 第4圖係為說明第3圖所示之逐次近似暫存器邏輯電路的方塊圖. 第5圖係為說明第3圖所示之數位類比轉換器的電路圖； ， 第6圖係為說明第4圖所示之逐次近似暫存器邏輯電路的操 、、 驅動波形圖； 、方法的 第7圖係為說明第4圖所示之逐次近似暫存器邏輯電路的操 系意圖；以及 、F乃法的 第8圖係為說明第3圖之逐次近似暫存器類比數 位信號判斷方法_表。 職㈣Μ立元數 【主要元件符號說明】 取樣及保持放大器 ^ 比較器 i 逐次近似暫存器邏輯電路 | 輸出暫存器 0 數位類比轉換器 201233069 AG1 〜AGn 1邏輯閘 C—out 比較信號 CLK 時鐘信號 DO 〜Dn 級 D_v 類比輸出信號 LSB 最低有效位元 MSB 最高有效位元 NG 反相閘極 out_l 〜out· _n第1〜第η位元信號 Outn η位元數位信號 RESET 重設信號 SAR 逐次近似暫存器 SD 啟動級 SR 位移暫存器 SRI〜SRn第一〜第n位移暫存器正反器 St 啟動信號 SO 〜Sn 位移脈衝 START 啟動信號 VDD 設定電壓 Vin 外部輸入類比電壓 Vh 類比電壓 Vref 參考電壓 VSS 接地電壓 15Du sequentially generates an n-bit digital signal outn from the MSB to the LSB in response to the sequentially supplied clock signal CLK. Fig. 5 is a circuit diagram showing the digital analog converter shown in Fig. 3. The digital analog converter 1 of Fig. 5 has a c_2c lion structure. At least the __ switching element and the __t capacitance c connected in series with each other in the digital analog converter are connected in parallel to a plurality of second capacitors 2 connected in series with each other (the _ connection node. Since the capacity of the maximum capacitance is relatively smaller) A conventional digital analog analog converter composed of binary weighted capacitors, the digital analog converter of the present invention can reduce its total area. The digital analog converter 10 generates an analog output signal D_v corresponding to n bits, the voltage level of which is based on Changing from the successive approximation register logic circuit 6 by the bit signals out-1 to out-n sequentially input in at least one bit unit, that is, at least one bit according to the slave approximation register logic circuit 6 The bit signal 〇ut-1 to 〇ut_n, the c_2c trapezoidal digital analog converter 10, which is sequentially input by the unit, causes the ground voltage VSS or the reference voltage Vref to be applied to the connection node between the second capacitors 2C. Thus, an analog output signal D_v corresponding to n bits is generated, and an analog output signal D_v corresponding to n bits is applied to the comparator 4. Fig. 6 is a schematic diagram showing the successive approximation shown in Fig. 4. Driving waveform diagram of the operation method of the logic circuit. S 7 ® is a schematic diagram illustrating the operation method of the successive approximation register logic circuit shown in the fourth @1. It will be described as a figure in FIG. 6 and FIG. Embodiment ❾ 12-bit successive approximation of the register digital analog converter, and in Fig. 7, conversion processing starting from the third MSB of the third bit will be described. Referring to Fig. 4, Fig. 6, and Fig. 7, When the start signal St is input to the first series stage D〇 of the shift register SR included in the successive approximation register logic circuit 6, by the set voltage VDD applied to the D input terminal of the first series stage D0 The first series stage D〇 is set. The set first-φ Wei DG is applied to the bit-by-single register (10) (four)-displacement register flip-flop SIU setting; the high-logic first-displacement pulse S of the t voltage (). Then successively approximating the first-shift register flip-flop of the temporary SAR, such as the digital ship of the MSB of 'ρ in synchronization with the first displacement pulse s〇, and other displacement register positive and negative fertilizers , milk Shi 2 = L number. ut-2, 〇ut_3.... ut_n. That is, the successive approximation The s is initialized to a digital signal of ___. At this time, as shown in Fig. 6, the stupid number has a phase difference from the start signal St. Therefore, since the hall digital signal _ and = the dynamic signal St have - she Poor, the present invention can reduce the computation time compared to the conventional technique of having 2 phase differences between Cong's ___ and the start signal - 。: After 'the digital signal generated from the successive approximation register SAR , _ 〇 _ 〇〇, apply the electrical ratio to turn, 10, and the digital analog converter 10 converts the digital signal to an analog output. 4 is more than the output (four) pressure D - performance in the off 2 shocked ^ as a comparison result, when The analog input signal Vh is greater than or equal to the analog output signal than the 201233069 comparator 4 "comparison letter ^ (10). The high-turning paper number C_〇ut_ bit is inverted by the inverting stage reverse gate ship, and the comparison signal c_〇ut is converted to a low level comparison signal. When the comparison signal of the lower bit $ is input to the inter-pole AG, Nao asks the ag to generate the low-level and thus the first-displacement register flip-flop SR1 maintains '丨, the bit number of the letter - The human approximation register SAR generates a digit by '100000000000' by a feedback process. At the same time, as a comparison result 'when the analog input signal vh is smaller than the analog output signal D_v, the comparator 4 produces a lower level comparison signal c - (10). The phase of the lower-level comparison domain c_〇ut is inverted by the startup stage SD in the inverting gate NG, and the comparison signal c-(10) is converted to a high-level comparison signal. The high-level comparison signal is converted to a high level by the idler AG, and is applied to the S terminal of the first-shift register flip-flop SR1. Re-determining the first-shift register The flip-flop SR generates an MSB with the value '〇. In other words, the successive approximation register generates a digital signal '00000000000〇 by a feedback process. Then, the displacement pulse of the first series stage D0 is shifted to the second series stage D18 input terminal in synchronization with the clock signal CLK. However, the second nearest register device (4) two shift register flip-flop SR2 and the second shift pulse S1 synchronously generate a digital signal _2 having a bit position, and other displacement temporary storage II flip-flops have a - bit The digit signal is also "," = t_4...out_n. In other words, the successive approximation register generates a digital signal that is initialized to [c 嶋 嶋 [ο ιοοοοοοοοοοοο The digital analog to (4) 1G instant (10) face (8) pottery (10) face (8)] digital signal is converted to analog output voltage D_v. The comparator 4 compares the analog output voltage D with the _ input ship Vh of the holding device 2 . - Keeping the shape as a comparison, when the input signal Vh A is in the scale _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The low level comparison signal is input to the nano gate AG2. Na gate is very popular = two low level 'turned this second displacement register flip-flop SR2 to maintain ί, the bit read signal. Saki Pure SAR|1 self-halo processing New Zealand silk ship ___〇, or 010000000000,. At the same time, as a result of comparison, when the analog input signal yh is smaller than the analog output signal Ο) 12 201233069, the comparator 4 generates a low level comparison signal C_out. The phase of the low-level comparison signal C_out is inverted by the enable stage SD in the inverting gate NG, and the comparison signal C_out is converted to a high-level comparison signal. The high level comparison signal is converted to a high level by the AND gate AG2, and the second shift register flip-flop SR2 is reset to generate a one-bit '〇' digital signal. In other words, 'the successive approximation register SAR generates the digital signal 'looooooooooo', or '000000000000, according to this method, successively approximating the register logic circuit 6 sequentially generates the digital signal of the preset n-bit from the MSB to the LSB' in response to the The clock signal sequentially input by the clock generator and the comparison signal c_〇ut of the high or low bit rate input from the comparator 4 in units of at least one bit. The digital analog converter 10 converts the digital signal sequentially input from the successive approximation register logic circuit 6 in units of at least one bit into an analog output signal d_v corresponding to n bits. Fig. 8 is a graph for explaining the n-bit digital signal judging method of the successive approximation register analog-to-digital converter of Fig. 3. Referring to FIG. 6 and FIG. 8, the digits corresponding to the n-bit analog output signal D_v generated by the digital analog converter 1〇 in at least one bit unit are sequentially input according to the successive approximation register SAR. The signal 〇utn changes 彳b compares n 4 compares the bitwise axis corresponding to the n-bit sequential input, the bit axis of the itMs number D_v is lower than the input light vh, and sequentially produces a comparison signal C_〇ut . Subsequent approximations of the chic 6 are followed by the subsequent signal of the signal, in response to the sequentially generated comparison signal C_out. The digital analog converter 1 〇 generates an analog output signal D_v corresponding to the n bit in response to the successive bits generated in sequence, and the comparator 4 compares the input signal level, thereby determining that the corresponding _ ratio is The human digital signal is out of the digital signal outn. The output register 8 sequentially maintains the digital money generated from the discussion to the Na through the successive circuit 6 secrets to generate a continuous reading number 0 coffee. According to the specification of the present invention, the digital analog conversion method with the upper riding _ SAR wc and the using · AC can be used only during the processing time required for processing n bits, and no additional processing time is required. While maintaining the resolution, j counts the time. Further, the sar milk mash is formed by a filament differential structure, which has a two-turn ladder analog-digital converter shutdown circuit structure, thereby reducing noise interference.孰 太 ^ ^ ^ ^ ^ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ She is interested in the modifications and variations of the present invention provided by her range of 13 201233069. This application claims to be filed on December 1st, 2010, Korean Patent Application No. 10-2010-0126553 and 2011 Main 11th 17 〇坦-_ ^ ^ Korean Patent Application 10-2011 submitted on November 17, 2005 -G11991G's right 'through (4) to combine all of them into the case request. BRIEF DESCRIPTION OF THE DRAWINGS [0009] The accompanying drawings, which provide a further understanding of the embodiments of the invention, . The cargo is in the form of a page drag: FIG. 1 is a diagram showing the operation waveform of the operator of the register logic circuit according to the conventional technique; ' / Fig. 2 is a digital analogy according to the prior art. Circuit diagram of the converter; square =·_ is a sequential approximation register analog-to-digital converter according to an embodiment of the present invention. FIG. 4 is a block diagram illustrating the successive approximation register logic circuit shown in FIG. 5 is a circuit diagram for explaining a digital analog converter shown in FIG. 3; and FIG. 6 is a diagram showing the operation and driving waveforms of the successive approximation register logic circuit shown in FIG. 4; Figure 7 is a schematic diagram illustrating the operation of the successive approximation register logic circuit shown in Figure 4; and Figure 8 of the F-method is a method for judging the approximation register analog digital signal of the successive approximation of Figure 3 _table. Jobs (4) 元立元数 [Main component symbol description] Sample and hold amplifier ^ Comparator i successive approximation register logic circuit | Output register 0 Digital analog converter 201233069 AG1 ~ AGn 1 Logic gate C_out Compare signal CLK clock Signal DO~Dn Stage D_v Analog Output Signal LSB Least Significant Bit MSB Most Significant Bit NG Inverted Gate Out_l~out· _n 1st to nth Bit Signal Outn η Bit Digit Signal RESET Reset Signal SAR Successive Approximation Register SD Startup Stage SR Displacement Register SRI~SRn First to nth Displacement Register Reverser St Start Signal SO~Sn Displacement Pulse START Start Signal VDD Set Voltage Vin External Input Analog Voltage Vh Analog Voltage Vref Reference Voltage VSS Ground Voltage 15