KR101691976B1 - Offset cancellation apparatus using delay locked loop - Google Patents

Abstract

An offset correcting apparatus using the delay locked loop according to the present invention comprises: a DAC for converting an input digital signal into an analog signal and supplying the analog signal to a comparator; and a comparator for comparing the level of the sampled and held input signal provided from the DAC with the level of the analog output signal A digital DLL unit for detecting an offset of the comparator by using a comparison signal output from the comparator and adjusting the switching of the comparator based on a result of the detection; A decision logic section for determining which of the outputs of the comparison signal is temporally faster and delivering a high or low level output to the SAR logic section; and a decision logic section for determining, based on the high or low level output from the decision logic section, The number of bits of n bits that are set in sequence from bit to least significant bit It may include the SAR logic unit configured to output a signal.

Description

TECHNICAL FIELD [0001] The present invention relates to an offset correction apparatus using a delay locked loop (hereinafter referred to as " OFFSET CANCELATION APPARATUS USING DELAY LOCKED LOOP &

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for correcting the offset of a comparator for an analog-to-digital converter (ADC), and more particularly to a method of detecting an offset in a comparator using a delay locked loop (DLL) To an offset correction device using a delay locked loop suitable for compensating an offset by adjusting a capacitor of the comparator.

As is well known, in actual implementation of a chip, if there is a mismatch between the capacitor size of the time-domain comparator and the input transistor size, Depending on the result of the comparator, which determines the digital bit, a completely different bit is obtained which is called the comparator offset, which is the dominant noise in the performance of the ADC ) Component.

It is very difficult to implement 12 bits due to the offset of the capacitive DAC and the comparator without any correction technique in the existing SAR (success approximation register) ADC. In order to accurately implement 10 bits or more, Is required.

Korean Patent Laid-Open Publication No. 2013-0048690 (Publication date: May 10, 2013)

The present invention provides a new offset correction technique that can detect an offset in a comparator itself using a delay locked loop (DLL) and adjust a capacitor switch of a comparator using the detection result to correct a delay caused by an offset I would like to propose.

The problems to be solved by the present invention are not limited to those mentioned above, and another problem to be solved by the present invention can be clearly understood by those skilled in the art from the following description will be.

According to one aspect of the present invention, there is provided a DAC which converts an input digital signal into an analog signal and supplies the analog signal to a comparator, and a comparator that compares the level of the sampled and held input signal provided from the DAC with the level of the analog output signal, A comparator for comparing the output signal of the comparator with the output signal of the comparator and outputting a comparison signal of a level of the comparison signal; a digital DLL part for detecting an offset of the comparator using the comparison signal output from the comparator, A decision logic section for determining which of the outputs of the decision logic section is temporally fast and for delivering a high or low level output to the SAR logic section; and a decision logic section for determining, from the most significant bit to the least significant bit And outputs the digital signals as many as n bits, And an offset correction device using a delay locked loop including a rectilinear portion.

The comparator of the present invention may be configured as a differential time domain comparator.

The digital DLL unit of the present invention may include two delay cells.

Each of the delay cells of the present invention may include a signal delay line and an offset calculation unit.

The offset calculator of the present invention may include a plurality of D flip-flops (DFF) and a plurality of exclusive NOR gates (XNOR).

Each offset output in the offset calculator of the present invention can be mapped 1: 1 with the capacitor array of the comparator.

The signal delay line of the present invention may be composed of a plurality of inverters.

The present invention adjusts the capacitor switch of the comparator using the offset in the comparator detected using a delay locked loop (DLL) to compensate for the delay due to the offset, thereby reducing the ADC performance due to the offset of the comparator It is possible to realize a SAR ADC of more than 10 bits.

1 is a block diagram of an offset correction apparatus using a delay locked loop according to the present invention.
2 is an operation timing chart for various waveforms applied to the offset correction apparatus of the present invention.
3 is an exemplary circuit diagram for the comparator shown in FIG.
4 is a pulse diagram for explaining that the offset is corrected according to the present invention.
5A and 5B are block diagrams of two delay cells included in the digital DLL unit.
6 is a detailed configuration diagram of a delay cell included in the digital DLL unit according to the present invention.

First, the advantages and features of the present invention, and how to accomplish them, will be clarified with reference to the embodiments to be described in detail with reference to the accompanying drawings. While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

In the following description of the present invention, detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. It is to be understood that the following terms are defined in consideration of the functions of the present invention, and may be changed according to intentions or customs of a user, an operator, and the like. Therefore, the definition should be based on the technical idea described throughout this specification.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[Example]

FIG. 1 is a block diagram of an offset correcting apparatus using a delay locked loop according to the present invention. The apparatus includes a capacitive DAC (digital to analog converter) 102, a comparator 104, a digital DLL a delay locked loop portion 106, a decision logic portion 108 and a success approximation register (SAR) logic portion 110,

2 is an operation timing diagram of various waveforms applied to the offset correction apparatus of the present invention. The clock signal CLK, the RESET signal, the sampling and holding (S / H) signal, the digital DLL signal, .

Referring to FIG. 2, it can be known from the clock signal that N cycles are required to convert n bits on the SAR ADC structure. Before the start of each conversion, a reset and a sampling process are performed. In this process, Since there is no processing (that is, a time during which the signals of Vdacp and Vdacn are kept constant), correction using the digital DLL can be performed in real time without any additional cycle.

In general, because there is a cycle for correction, the speed of operation is inevitably slowed down. With this structure and timing, more accurate conversion can be performed while maintaining the existing speed.

Referring to FIG. 1, the DAC 102 lowers or raises the sampled analog signal according to logic switching information (bit information) provided from the SAR logic unit 110 to determine digital bits, that is, And may provide functions such as converting a digital signal of two inputs (Vinp, Vinm) (differential input) to an analog signal, and the analog signal output therefrom is provided as an input to the comparator 104. [

For this purpose, the DAC 102 may include a sampling / holding amplifier (SHA), which is composed of a plurality of capacitors, amplification circuits, switching elements, etc., for sampling and holding an analog voltage input from the outside, In this way, sampling mode or hold mode can be executed.

Next, the comparator 104 compares the level of the sampled and held input voltage delivered from the DAC 102 with the level of the analog output signal per cycle, and outputs a high or low level comparison signal on the basis of the comparison result And the comparator 104 may have a configuration as shown in FIG. 3 (for example, a differential time domain comparator). For example, when the clock signal is low, the drain portion of the transistor (e.g., PMOS) is charged to VDD. When the clock signal is high, discharge is started according to the input signal, The output of the comparison signal is output.

That is, referring to FIG. 3, the transistors M1 and M2 receive a differential input, and the amount of current varies depending on the voltage, which affects the discharge time and the output waveform thereafter.

The differential time domain comparator has DP0 to DP3 and DN0 to DN3 outputs for offset correction. The comparator operates in a dynamic manner in synchronization with the clock signal. When the clock signal is low, the transistor M5 , M6 is turned on and nodes A and B are charged to VDD. This process is called reset and is executed for each cycle during conversion. The transistors M5 and M6 are turned off and the transistors M3 and M4 are turned on so that a discharge path is formed when the clocks are high (non-overlapping but the state is the same signal) do.

At this time, the voltages of the nodes A and B are lowered. When the input signal is higher, a larger current flows to turn on the transistor M7 or M8, and the output of the threshold voltage Voutp and Voutn is output first.

If the same input signal is input, there should be no difference in output, but in practice, it will have a certain time difference (Td) as Voutp and Voutn shown in FIG. 4 and this can be defined as an offset. By adjusting these offsets by adjusting the switches DP3 to DP0 and DN3 to DN0 in the nodes A and B via the digital DLL unit 106, the time difference Td can be reduced to an error tolerance range.

Next, the digital DLL section 106 detects the offset in the comparator 104 using the comparison signal outputs Voutp and Voutn from the comparator 104, and adjusts the switching of the comparator 104 based on the detection result (Delay correction). For this purpose, the digital DLL unit 106 may include, for example, two delay cells as shown in FIGS. 5A and 5B, One delay cell may include a signal delay line 502a and an offset calculator 504a and the other delay cell may include a signal delay line 502b and an offset calculator 504b.

Here, each of the signal delay lines may be composed of a plurality of inverters in series in a time series, for example, as shown in FIG. 6, and each offset calculator may include a plurality of D flip flops DFF and a plurality of exclusive The digital DLL section 106 detects the offset of the comparator itself by using the output of the comparison signal of the comparator 104 and outputs the detected The information is used to adjust the switching of the comparator to provide a function to compensate for the delay due to the offset. That is, the digital DLL unit 106 can provide a function of adjusting a capacitor switch of a comparator to correct an offset by determining a bit using two delay cells.

Referring to FIG. 6, Voutp and Voutn are outputs of the comparator 104, one of which is a clock signal of the D-flip-flop and the other of which is delayed through a delay cell.

6, Voutn is faster than Voutp. At this time, the output of the first D-flip-flop becomes 1, and when Voutn is delayed, the data comes later than the clock signal and the D- There is a case in which the output is outputted. At this time, the output of one of DN0 to DN3 becomes high when the output of the D-flip-flop is changed by the stage tied to each other's exclusive Noah gate.

This is the amount of delay. By matching (mapping) 1: 1 with the switch shown in FIG. 3, it becomes possible to correct Td to within 0.5 LSB as shown in FIG. 4 as an example. When the DN is switched, there is an offset to the current Vdacn, but because of the increase in total capacitance at the node B, the RC delay increases to match the difference. Here, the reason why the delay cells are used as a pair is that two delay cells are used because they can not know which one is fast, thereby correcting the value according to the result.

For this purpose, the offset can be corrected by mapping each offset output (DN0 - DN3, DP0 - DP3) in the offset calculation unit in the digital DLL unit 106 to the capacitor array of the comparator 104 in a 1: 1 manner.

Then, the decision logic unit 108 determines which of the two outputs Voutp and Voutn of the comparison signal is temporally faster, and transfers the output of the high or low level to the SAR logic unit 110 of the next stage .

Next, the SAR logic unit 110 sequentially holds the most significant bit to the least significant bit based on the output of the high or low level provided from the decision logic unit 108, and outputs the digital signal by the predetermined number of n bits Where the most significant bit digital signal generated herein may be provided to the DAC 102 as logic switching information.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims. It is easy to see that this is possible. That is, the embodiments disclosed in the present invention are not intended to limit the scope of the present invention but to limit the scope of the present invention.

Therefore, the scope of protection of the present invention should be construed in accordance with the following claims, and all technical ideas within the scope of equivalents should be interpreted as being included in the scope of the present invention.

102: DAC
104: comparator
106: Digital DLL section
108: decision logic section
110: SAR logic unit
502a, 502b: signal delay lines
504a and 504b:

Claims (7)

A DAC that converts an input digital signal into an analog signal and supplies the analog signal to a comparator,
A comparator for comparing a level of the sampled and held input signal provided from the DAC with a level of an analog output signal to output a high or low level comparison signal;
A digital DLL unit for detecting an offset of the comparator by using a comparison signal output from the comparator and adjusting the switching of the comparator based on the detection result,
A decision logic unit for determining which of the output signals of the comparison signal is temporally fast and delivering a high or low level output to the SAR logic unit,
And outputting a digital signal corresponding to a predetermined number of n bits sequentially from a most significant bit to a least significant bit based on an output of a high logic level or a low logic level,
Lt; / RTI >
The digital DLL unit,
And includes two delay cells each having a signal delay line and an offset calculator
An offset correction apparatus using a delay locked loop.
The method according to claim 1,
The comparator comprising:
Which is composed of a differential time domain comparator
Is an offset correction device using a delay locked loop.
delete delete The method according to claim 1,
Wherein the offset calculator comprises:
A plurality of D flip-flops (DFF) and a plurality of exclusive NOR gates (XNOR)
An offset correction apparatus using a delay locked loop.
6. The method of claim 5,
Wherein each of the offset outputs in the offset calculator comprises:
Lt; RTI ID = 0.0 > 1: 1 < / RTI > with the capacitor array of the comparator
An offset correction apparatus using a delay locked loop.
The method according to claim 1,
Wherein the signal delay line comprises:
Consisting of a plurality of inverters
An offset correction apparatus using a delay locked loop.

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