TW201318352A - Successive approximation analog to digital converter with a direct switching technique for capacitor array through comparator output and method thereof - Google Patents

Abstract

A method for a successive approximation register ADC which includes at least one capacitor array and a plurality of switches is provided, wherein the capacitors of the capacitor array are one-to-one corresponding to the switches. The method comprises the following steps: firstly, at least one multiplexer is configured. Then, a first comparison voltage is outputted based on the terminal voltages on the terminals of the capacitor array, and a comparison result is outputted according to the first comparison voltage and a second comparison voltage. Afterwards, a sequence of comparisons is controlled based on the comparison result to enter into a sequence of comparison phases. Finally, the switches are orderly selected, by the multiplexer based on the comparison phases, to switch directly according to the comparison result.

Description

Gradual approximation analog to digital converter and method for directly switching capacitor array through comparator output

The present invention relates to a gradual approximation analog to digital converter, and more particularly to a gradual approximation analog to digital converter and method thereof for directly switching a capacitor array through a comparator output to increase the slew rate.

Please refer to the first figure, which is a schematic diagram of a conventional octade approximation register ADC (SAR ADC). As shown in FIG. First, the SAR analog-to-digital converter 1 comprises two symmetrical digital to analog converter (digital to analog converter, DAC) 11,13, respectively, by the capacitor array (C ₉ -C ₀₎ of the Composition. In operation, first, the comparator 15 samples and compares the differential input signals V _ip , V _in , and the gradual approximation control logic (SAR) 17 switches the switches S _P9 , S _N9 according to the comparison result of the comparator 15 to control junction potentials of the capacitor C _9. Due to the change of the contact potential, the two sets of digital to analog converters 11, 13 will generate a new potential, and the comparator 15 will sequentially compare the digits to the output of the analog converters 11, 13, by the progressive approximation control logic 17 Corresponding digits B ₁ -B ₁₀ are parsed based on the comparison result of the comparator 15.

Specifically, the gradual approximation control logic (SAR) 17 generally includes a logic circuit 171 for receiving the comparison results outp, outn of the comparator 15 and calculating the switches S _Pi and S _Ni at each comparison stage. The voltage level below. Please refer to the second figure, which is a schematic diagram of a logic circuit used to control a switch. As shown in the second figure, the comparison results outp, outn generated in each comparison phase must pass at least one NAND gate 1711, two D-FFs 1712, 1713, and an AND gate 1714. In order to obtain the signals of the control switches S _Pi , S _Ni . The self-delay of the digital logic gate takes a lot of time, and after each digit is parsed, it is necessary to go through the logic circuit 171 to determine how to switch the next switch S _Pi , S _Ni . As the number of bits in the ADC increases, the resulting delay is greater, which greatly increases the conversion time of the entire SAR ADC system.

Therefore, for the integrated circuit design, it is urgent to propose a circuit that can shorten the conversion time of the digital bit, thereby improving the conversion rate and performance of the design circuit.

In view of the above, one of the objects of embodiments of the present invention is to provide a gradual approximation analog to digital converter that uses a multiplexer to control the switch to improve the slew rate and performance of the design circuit.

The present invention discloses a progressive approximation analog to digital converter (SAR ADC) that increases the slew rate, including a first digital to analog converter (DAC), a progressive approximation control logic (SAR), a comparator, and a The first multiplexer. The first digit to analog converter comprises a first capacitor array and a plurality of first switches, wherein the capacitance of the first capacitor array is in one-to-one correspondence with the first switch. Gradual approximation control logic is used to control the sequential entry into a series of comparison phases. The comparator is coupled to the first digit to the analog converter for outputting a first comparison result according to a second comparison voltage and a first comparison voltage of the first digit to the analog converter. The first multiplexer is coupled between the comparator and the gradual approximation control logic circuit, and is configured to select one of the switches of the first switch according to the comparison phase that the gradual approximation control logic circuit currently enters, directly according to the first comparison result. Switch.

The invention further discloses a method for gradually approximating an analog to digital converter, the gradual approximation analog to digital converter comprising at least one capacitor array and a plurality of switches, wherein the capacitance of the capacitor array is in one-to-one correspondence with the switches. The method includes the following steps: first, configuring at least one multiplexer; then, outputting a first comparison voltage according to a junction potential of the capacitor array, and outputting a comparison result according to the first comparison voltage and a second comparison voltage After that, according to the comparison result, a series of comparisons are controlled, and a series of comparison stages are entered; finally, the multiplexer sequentially selects the switches according to the comparison stage to directly switch according to the comparison result.

First, please refer to the third figure, which is a circuit diagram of a gradual approximation analog-to-digital converter (SAR ADC) 3 for increasing the slew rate according to an embodiment of the present invention. As shown in the third figure, the SAR ADC 3 includes a first digit to analog converter (DAC) 31, a second digit to analog converter 33, a comparator 35, a first multiplexer 36 _P , and a first The second multiplexer 36 _N and a progressive approximation control logic (SAR) 37. The first digit to analog converter 31 includes a first capacitor array C ₉ -C ₀ and a plurality of first switches S _P9 -S _P1 , wherein the capacitor C ₉ -C ₁ of the first capacitor array is coupled to the first switch S _P9 -S _P1 one-to-one correspondence; likewise, the second digit to analog converter 33 comprises a second capacitor array C ₉ -C ₀ and a plurality of second switches S _N9 -S _N1 , wherein the capacitance C _{9 of the} second capacitor array The -C ₁ system is in one-to-one correspondence with the second switches S _N9 -S _N1 . Ideally, the capacitance values of the first capacitor array C ₉ -C ₀ and the second capacitor array C ₉ -C ₀ are binary weights.

The comparator 35 has a non-inverting (positive) input and an inverting input for receiving and comparing the output of the first digit to the analog converter 31 and the second digit to the analog converter 33, respectively. The gradual approximation control logic circuit 37 is used to generate a series of clock signals (Ф _{1 -} Ф ₉ ) to control the sequential entry into a series of comparison stages. During each comparison phase, the comparator 35 outputs a first comparison result outp and a second comparison according to the first comparison voltage outputted by the first digit to the analog converter 31 and the second comparison voltage outputted by the second digit to the analog converter 33. The result is outn.

The first multiplexer 36 _P and the second multiplexer 36 _N are coupled between the comparator 35 and the gradual approximation control logic circuit 37 for selecting according to the comparison phase that the gradual approximation control logic circuit 37 is currently entering. A switch is directly switched according to the comparison result to control the capacitance of the capacitor array to be coupled to the first reference voltage V _refp or the second reference voltage V _refn .

Please refer to the fourth figure. For convenience of explanation, the first multiplexer 36 _{P is taken} as an example. As shown in the fourth figure, the first multiplexer 36 _P includes a plurality of latch circuits 361 that are in one-to-one correspondence with the first switches S _Pi . Each latch comprises a latch circuit 361 switches to a reverse SФ _i and two inverters 3611,3613 coupled through latch switch SФ _i, wherein the latch switch SФ _i lines coupled to the first output of the comparator 35 A comparison result is output between the outp and the inverters 3611, 3613.

At each comparison stage, the first multiplexer 36 _P controls the selected first switch S _{Pi to} be directly switched to the first comparison result outp output by the comparator 35. Specifically, the first multiplexer 36 _P sequentially turns on the latch circuit 361 according to a series of comparison stages to sequentially output the first comparison result generated in all comparison stages to switch the corresponding first switch S _Pi . For example, when the gradual approximation control logic circuit 37 generates the clock signal Ф ₁ and enters the first comparison phase, the first multiplexer 36 _P turns on the latch switch S Ф ₁ to output the output generated in the first comparison phase. The first comparison result outp switches the corresponding first switch S _P9 to the first reference voltage V _refp or the second reference voltage V _refn . Capacitance C of the first capacitor array ₉ in accordance with a first junction potentials will switch the switch S _P9 is controlled to generate a first comparison voltage according to the comparison of the next stage.

Similarly, when the gradual approximation control logic circuit 37 generates the clock signal Ф ₂ and enters the second comparison phase, the first multiplexer 36 _P turns on the latch switch S Ф ₂ to output the output in the second comparison phase. The first comparison result outp is to switch the corresponding first switch S _P8 . By analogy, the first multiplexer 36 _P sequentially turns on the latch switches S Ф ₁ -S Ф ₉ according to the currently entering comparison phase, and sequentially outputs the generated first comparison result outp to switch the corresponding first Switch S _P9 -S _P1 . Wherein, in each comparison phase, the first multiplexer 36 _P only selects to switch one of the first switches S _Pi . Since the first switch S _Pi is directly controlled according to the first comparison result outp, when the gradual approximation control logic circuit 37 outputs a series of corresponding digits B ₁ according to the first comparison result outp generated in a series of comparison stages - At B ₁₀ , the conversion rate can be increased and the conversion time can be reduced. Compared with the conventional control of the switch via digital logic, the present invention utilizes multiplexer selection to switch the switch to reduce the conversion time by 20%, as shown in the fifth figure.

In one embodiment, a plurality of sampling switches S Ф _{s are} disposed in the first digit to the analog converter 31 and the first multiplexer 36 _P. Each sampling switch S _{s s} in the first multiplexer 36 _P is coupled between a voltage terminal VDD and a corresponding latch circuit 361 (as shown in the fourth figure) for use in a sampling phase. (sample phase), the terminal of the first capacitor array C ₉ -C ₁ is switched to the first reference voltage V _refp or the second reference voltage V _refn . Subsequently (during the sampling phase), the first digit to analog converter 31 samples the differential input signal V _ip via an internal sampling switch S Ф _s (as shown in the third figure). It should be noted that the gradual approximation control logic circuit 37 can generate a clock signal Ф _s to switch the sampling switch S Ф _s to enter the sampling phase. In the sampling phase and the successive comparison phase, the second digit to analog converter 33 operates symmetrically with the first digit to analog converter 31.

Finally, please refer to the sixth figure, which is a flowchart of a method for increasing the conversion rate according to an embodiment of the present invention. It should be noted that, in order to simplify the description, the sixth figure only shows the operation flow of the first digit to analog converter 31, and the second digit to analog converter 33 is symmetric with the first digit to analog converter 31 as described above. Operation. The method is a gradual approximation analog to digital converter 3 for the third diagram, which is configured with a first multiplexer 36 _P and a second multiplexer 36 _N .

First, in step S601, the gradual approximation control logic circuit 37 controls to enter the sampling phase to sample the differential input signals V _ip , V _in . Next, in step S603, the gradual approximation control logic circuit 37 controls to enter a series of comparison phases, and in step S605, outputs a comparison voltage based on the determined contact potential. Thereafter, in step S607, the comparator 35 compares the two digits to the first comparison voltage generated by the analog converters 31, 33 and the second comparison voltage to output the comparison result outp.

In step S609, when the first multiplexer 36 _P receives the comparison result outp, it selects the corresponding first switch S _{Pi to} directly switch according to the comparison result according to the comparison phase currently entered. Wherein, in each comparison phase, the first multiplexer 36 _P only selects to switch one of the first switches S _Pi . For example, in the first comparison phase, the first multiplexer 36 _P turns on the latch switch SФ ₁ to output the comparison result outp generated in the first comparison phase to switch the corresponding first switch S _P9 . Thereby, the contact potential of the capacitor C ₉ can be determined according to the switched first switch S _P9 .

Finally, in step S611, it is judged whether or not all comparison phases have been completed. If no, the process returns to step S605 to continue the comparison. If a series of comparison phases have been completed, the progressive approximation control logic circuit 37 outputs the corresponding digits B ₁ -B ₁₀ based on each comparison result (step S613).

According to the above embodiment, the gradual approximation analog-to-digital converter and the method thereof for improving the slew rate are selected by the multiplexer to select a switch corresponding to the current comparison phase, and output a comparison result to directly control the selected one. The switch can shorten the conversion time of the digital bit, thereby improving the conversion rate and performance of the design circuit.

The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application.

Conventional knowledge

1. . . Gradual approximation analog to digital converter

C ₉ -C ₀ . . . Capacitor array

V _ip , V _in . . . Differential input signal

S _P9 -S _P1 . . . switch

S _N9 -S _N1 . . . switch

11,13. . . Digital to analog converter

17. . . Gradual approximation control logic

171. . . Logic circuit

1711. . . Reverse gate

1712, 1713. . . D-FF

1714. . . Gate

Outp, outn. . . Comparing results

B ₁ -B ₁₀ . . . Digit

this invention

3. . . Gradually approximating analog to digital converters

31. . . First digit to analog converter

33. . . Second digit to analog converter

C ₉ -C ₀ . . . Capacitor array

V _refp . . . First reference voltage

V _refn . . . Second reference voltage

35. . . Comparators

36 _P . . . First multiplexer

36 _N . . . Second multiplexer

361. . . Latch circuit

3611, 3613. . . inverter

S s. . . Sampling switch

S ₁ -S ₉ . . . Latch switch

37. . . Gradual approximation control logic

B ₁ -B ₁₀ . . . Digit

Outp. . . First comparison result

Outn. . . Second comparison result

S _P9 -S _P1 . . . First switch

S _N9 -S _N1 . . . Second switch

S601-S613. . . step

The first diagram is a schematic diagram of a conventional tensor gradual approximation analog to digital converter (SAR ADC).
The second figure is a schematic diagram of a conventional logic circuit for controlling a switch.
The third figure is a circuit diagram of a gradual approximation analog to digital converter that increases the slew rate in accordance with an embodiment of the present invention.
The fourth figure is a circuit diagram of a first multiplexer according to an embodiment of the present invention.
The fifth figure is a simulation result of the conversion time according to an embodiment of the present invention.
The sixth figure shows a flow chart of a method for increasing the slew rate according to an embodiment of the present invention.

3. . . Gradually approximating analog to digital converters

31. . . First digit to analog converter

33. . . Second digit to analog converter

C ₉ -C ₀ . . . Capacitor array

V _refp . . . First reference voltage

V _refn . . . Second reference voltage

35. . . Comparators

36 _P . . . First multiplexer

36 _N . . . Second multiplexer

37. . . Gradual approximation control logic

B ₁ -B ₁₀ . . . Digit

Outp. . . First comparison result

Outn. . . Second comparison result

S _P9 -S _P1 . . . First switch

S _N9 -S _N1 . . . Second switch

Claims (13)

A gradual approximation analog to digital converter (SAR ADC) that includes:
a first digital to analog converter (DAC), comprising a first capacitor array and a plurality of first switches, wherein a capacitance of the first capacitor array is in one-to-one correspondence with the first switches;
A gradual approximation control logic (SAR) for controlling sequential entry into a series of comparison phases;
a comparator coupled to the first digit to the analog converter, the comparator outputting a first comparison result according to a second comparison voltage and a first comparison voltage of the first digit to the analog converter; a multiplexer coupled between the comparator and the gradual approximation control logic circuit for selecting one of the first switches according to the comparison phase currently entered by the gradual approximation control logic circuit The first comparison result is used for switching.

The gradual approximation analog to digital converter according to claim 1, wherein the contact potential of the first capacitor array is controlled according to the switched first switches to generate the first digit to The first comparison voltage of the analog converter.

The gradual approximation analog to digital converter as described in claim 2, wherein, in each of the comparison stages, the first multiplexer controls the selected first switch to directly switch to the output of the comparator The first comparison result.

The gradual approximation analog to digital converter as described in claim 3, wherein the first multiplexer includes a plurality of latch circuits that are in one-to-one correspondence with the first switches.

The gradual approximation analog to digital converter according to claim 4, wherein the first multiplexer sequentially turns on the latch circuits according to the series of comparison stages to sequentially output the comparison stages. The first comparison results are generated to switch the corresponding first switches.

The gradual approximation analog to digital converter according to claim 5, wherein each of the latch circuits includes two reverse coupled inverters and a latch switch, the latch open relationship coupling And the output of the first comparison result is outputted between the comparator and the inverters.

According to the gradual approximation analog to digital converter described in claim 6, the first multiplexer sequentially turns on the latch switches according to the series of comparison stages, so that the sequential output is generated in the comparison stages. The first comparison results are used to switch the corresponding first switches.

The gradual approximation analog to digital converter as described in claim 7 of the patent application, wherein the first multiplexer further comprises:
A sampling switch is coupled between a voltage terminal and the latch circuits for controlling the first capacitor array for sampling during a sample phase.

As mentioned in the third paragraph of the patent application, the gradual approximation to the analog converter also includes:
a second digit to analog converter (DAC), comprising a second capacitor array and a plurality of second switches, wherein a capacitance of the second capacitor array is in one-to-one correspondence with the second switches; and a second multiplexing The device is coupled between the comparator and the gradual approximation control logic circuit, and is configured to directly select one of the switches of the second switch to switch according to the comparison phase that the gradual approximation control logic circuit currently enters;
The junction potential of the second capacitor array is controlled according to the switched second switches to generate the second comparison voltage of the second digit to the analog converter, and during the series of comparison phases The second digit to analog converter operates symmetrically with the first digit to analog converter.

A method for gradually approximating an analog to digital converter, the gradual approximation analog to digital converter comprising at least one capacitor array and a plurality of switches, wherein a capacitance of the capacitor array is in one-to-one correspondence with the switches, the method comprising :
Configuring at least one multiplexer;
Outputting a first comparison voltage according to a junction potential of the capacitor array;
Outputting a comparison result according to the first comparison voltage and a second comparison voltage;
A series of comparisons are controlled according to the comparison result, and enter a series of comparison stages; and the multiplexer sequentially selects the switches according to the comparison stages to directly switch according to the comparison result.

The method of claim 10, wherein the step of outputting the first comparison voltage comprises:
Controlling a junction potential of the capacitor array according to the switched switches to generate the first comparison voltage;
Wherein, the corresponding first comparison voltage is generated in each of the comparison stages.

The method of claim 11, wherein the step of selecting the switches to directly switch according to the comparison result comprises:
Controlling the switch selected by the multiplexer to directly switch to the comparison result;
Wherein, in each of the comparison stages, the multiplexer only selects to switch one of the switches.

The method of claim 12, wherein the multiplexer comprises a plurality of latch circuits corresponding to the switches, and the multiplexer according to the series of comparison stages The latch circuits are sequentially turned on to sequentially output the comparison results generated in the comparison stages to switch the corresponding switches.