JP3576073B2 - Solid-state imaging device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a solid-state imaging device that converts an incident light image into a digital video signal and outputs the digital image signal. More particularly, it is intended to reduce the size of a CMOS image sensor equipped with a column-parallel AD converter.
[0002]
[Prior art]
FIG. 7 is a block diagram illustrating a CMOS image sensor equipped with a conventional column-parallel AD converter. The A / D converters 111, 112 to 11m for one row simultaneously perform A / D conversion on outputs of one row of the pixels 121, 122 to 12m, and output the selection switches 151, 152 to 152 based on the output of the shift register 14. The output of the AD converter 111 is output as a digital video signal from output amplifiers 191, 192 to 19n connected to the output signal lines 181, 182 to 18n via 15n. Next, the output of the AD converter 112 is output as digital video signals from the output amplifiers 191, 192 to 19 n connected to the output signal lines 181, 182 to 18 n via the selection switches 161, 162 to 16 n. The output of 11 m from converter 113 is output as a digital video signal.
[0003]
The pixels 131, 132 to 13m of the next row are also converted by the AD converters 111, 112 to 11n, and output as digital video signals from the output amplifiers 191, 192 to 19n.
[0004]
Hereinafter, similarly, each row is sequentially AD-converted and output as digital video signals from the output amplifiers 191, 192 to 19n. The result of the A / D conversion needs to be held during the period of outputting the digital video signal for one row, but by providing a latch at the output of the A / D converter, the A / D conversion time can be reduced to the signal output period for one row. Can be stretched.
[0005]
However, (column number × bit number) latches were required as a memory for holding the digital value during the video signal output period. Compared to the analog output image sensor, the image sensor equipped with the column-parallel AD converter has a memory for holding the AD conversion result for the number of bits corresponding to the required resolution of the output signal line, and a memory for storing the AD signal. A signal line for outputting the result is required, and there is a problem that the chip size becomes large.
[0006]
[Problems to be solved by the invention]
As described above, the conventional solid-state imaging device has a problem that the chip size becomes large because memory elements and output signal lines are required for the number of bits corresponding to the required resolution.
[0007]
An object of the present invention is to provide a solid-state imaging device in which a chip size is reduced by reducing the number of memory elements and the number of output signal lines after AD conversion of a CMOS image sensor equipped with a column parallel type AD converter. .
[0008]
[Means for Solving the Problems]
In order to solve the above-described problem, the present invention includes a plurality of pixel elements arranged in a matrix and converting an incident light amount into an electric signal and outputting the electric signal. The plurality of pixel elements are sequentially selected and output in row units. In a solid-state imaging device that further sequentially selects output signals of pixel element columns to be output in units of columns and outputs signals in pixel units, an output signal of a pixel element column selected in units of rows is converted to a digital output signal in units of pixel elements. , A first switch for selecting the digital output signal converted by the first converter in bit units, and holding the voltage of the selected digital output signal in bit units. A first capacitor, a second capacitor connected in parallel with the first capacitor, and a second capacitor for averaging a voltage held in each of the first capacitor and the second capacitor. switch And stage, the voltage held in the second capacitance and a sample hold circuit for sampling and holding, a second conversion and outputting the sampled and held voltage as an analog output signal corresponding to the digital output signal Means, selecting means for sequentially selecting the analog output signals output from the second converting means in units of columns , and third means for converting the analog output signals sequentially selected in units of columns into digital signals to obtain output signals. Conversion means.
Further, according to the present invention, there is provided a plurality of pixel elements which are arranged in a matrix and convert the amount of incident light into an electric signal and output the same, and the plurality of pixel elements are sequentially selected in row units and the output of a pixel element column is output. In a solid-state imaging device that further sequentially selects signals in column units and outputs signals in pixel units, a first reference voltage that changes linearly and a first reference voltage that changes stepwise in synchronization with the first reference voltage are provided. Reference voltage generating means for generating a second reference voltage, and comparing means for comparing an output signal of a pixel element column selected for each row with the first reference voltage and outputting a trigger signal when the two match. Sample and hold means for sampling and holding the second reference voltage based on a trigger signal from the comparing means, selection means for sequentially selecting the sampled and held second reference voltage in column units, and sequential selection in column units Was done The second reference voltage is converted into a digital signal that comprises a converting means for the output signal.
[0009]
According to this means, since a large amount of information can be transmitted with a small number of signal lines, the wiring area of the chip can be significantly reduced. Further, the number of memories for holding the video signal output period values only needs to be the number of memories for holding the values that have been DA-converted by the D / A converters, and the chip can be downsized.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0011]
FIG. 1 is a block diagram for explaining a first embodiment of the present invention. The same components as those in FIG. 7 are denoted by the same reference numerals, and different portions will be mainly described here.
[0012]
That is, the output signals of the pixels 121, 122 to 12m are converted into digital signals by the AD converters 111, 112 to 11m. The 10-bit outputs of the AD converters 111, 112 to 11m are input to the three sets of DA converters 211 to 213 in a row of 3 bits, 3 bits, and 4 bits from the high order, respectively, and are multivalued containing information of a plurality of bits. Outputs analog signal voltage of level. Hereinafter, the AD converters 112 to 11m similarly output multi-level analog signals.
[0013]
The selection switches 151 to 153 are controlled by the outputs of the shift register 14 to output the outputs of the multi-level D / A converters 211 to 213 and output the signals to three output signal lines. The AD converters 231 to 233 reproduce and output 3- or 4-bit data from the multilevel analog signal.
[0014]
In the same manner, the analog signals converted to multi-value levels by the AD converters 112 to 11m are converted from the multi-level analog signals into 3 or 4 bits through the corresponding AD converters based on the output of the shift register 14. Reproduce and output the data.
[0015]
FIG. 2 shows a configuration example of the DA converter used in FIG. This DA converter is shown as one that can obtain 4-bit resolution. The three-bit resolution can be realized only by removing the buffer amplifier BA1 and the switch S1 connected to the least significant bit D0.
[0016]
FIG. 3 is a timing chart for explaining the operation of FIG. The capacitors C1 and C2 have the same capacitance. First, prior to the DA conversion, the switch Sr is closed to discharge the capacitors C1 and C2. The input digital values are output from the buffer amplifiers BA1 to BA4 to output a stable high-level voltage VHH or low-level voltage VLL to remove noise from the digital circuit. After the switch Sdac is opened and the switch S1 is closed to store the least significant bit information voltage in the capacitor C1, the switch S1 is opened and the switch Sdac is closed to average the charges stored in the capacitors C1 and C2 (D0 / 2). Next, when the switch Sdac is opened, the switch S2 is closed, and then the switch C2 is opened and the information of one bit is stored in the capacitor C1, then the switch Sdac is closed and the electric charges of the capacitors C1 and C2 are averaged. An analog voltage {(2D1 + D0) / 4} is obtained.
[0017]
Similarly, by repeating the desired opening and closing operations in the order of the switches S3, Sdac, S4, and Sdac, a voltage obtained by DA-converting a 4-bit digital value can be generated. This voltage is buffered by the buffer amplifier 202 having a gain of 1, and is output as (Vmix + Vof) to the signal output line Vo via the selection switch SELn.
[0018]
Here, Vof is an offset voltage between input and output of the buffer amplifier 202. When the switch Sr is closed and the charge of the capacitors C1 and C2 is discharged while the selection switch SELn is selected, the offset voltage Vof is output to the signal output line Vo. The offset voltage 202 can be canceled, and information of a plurality of pixels can be reproduced without error from the multi-value level. This is because the coupling capacitor 203 and the clamp switch 204 clamp the signal line voltage at the timing of the CP pulse, the sample-and-hold circuit 205 samples and holds the voltage change at the time of discharge, and the influence of the offset voltage of the buffer amplifier 202 is obtained. A non-existent signal is input to an AD converter, and a multi-bit multiplex signal can be reproduced without error.
[0019]
In this DA converter, since the capacitors C1 and C2 have both the weighting function of the DA converter and the function of holding a multi-valued level, and can hold data with only two capacitors having fewer input bits, the chip size is reduced. Has the effect of reducing.
[0020]
In this embodiment, since 10-bit information can be transmitted only by three signal lines, the wiring area of the chip is greatly reduced. Further, the number of memories for holding the video signal output period values may be the same as the number of memories for holding the values that have been D / A converted by the D / A converters 211 to 213, and the chip can be downsized.
[0021]
FIG. 4 is a block diagram for explaining a second embodiment of the present invention, and FIG. 5 is a timing chart thereof.
[0022]
The signal voltages output from the pixels 121, 122 to 12m are input to ratio inverting inputs of the voltage comparators 411, 412 to 41m, respectively. The inverted inputs of the voltage comparators 411, 412 to 41m are all connected to the output of a DA converter 43 that converts the output of the counter circuit 42 into an analog signal. The voltage comparators 411, 412 to 41m output a high-level output when the output signal from the pixel is larger than the output of the DA converter 43, and output a low-level output when the output signal is smaller than the output of the DA converter 43. The sample hold circuits 441 to 443 sample the input signal when the control input to which the output of the voltage comparator 411 is connected is at a high level, and hold when the control input is at a low level. The output of the counter circuit 42 is divided into three bits, three bits, and four bits, which are input to the D / A converters 461 to 463, respectively.
[0023]
These DA converters 461 to 463 output staircase waves having different periods as shown by Va, Vb, and Vc in FIG. 5, and the combinations of the voltages correspond one-to-one with the timing. Therefore, by holding Va, Vb, and Vc when the output of the DA converter 43 becomes equal to the signal level, an analog value corresponding to the AD conversion value of the pixel signal can be obtained. The analog values are sequentially selected, digital values are obtained by the AD converters 471 to 473, and the digital values are combined to obtain a 10-bit digital value.
[0024]
In this embodiment, a 10-bit digital value can be held by only three sample / hold circuits per column, the number of required memory elements can be significantly reduced, and the chip size can be reduced. .
[0025]
FIG. 6 is a block diagram for explaining a third embodiment of the present invention. Here, only components necessary for simultaneously performing AD conversion and video signal output are shown. The same components will be described with the same reference numerals.
[0026]
That is, two sample hold circuits 441 are prepared and combined as sample hold circuits 441a and 441b, and AD conversion and video signal output are alternately performed by the line selection signal from the timing generation circuit 62 using the AND gate circuits 61a and 61b. By doing so, it is possible to alternately repeat outputting the signals converted into a plurality of multi-level signals by the AD conversion operation for one horizontal time over the next one horizontal time, thereby obtaining a continuous output.
[0027]
In this embodiment, the power can be extended by one horizontal scanning period during the AD conversion period, so that the power consumption can be further reduced.
[0028]
【The invention's effect】
As described above, according to the solid-state imaging device of the present invention, it is possible to reduce the number of memory elements for holding AD conversion results and output signal lines, and to reduce the chip area.
[Brief description of the drawings]
FIG. 1 is a block diagram for explaining a first embodiment of the present invention.
FIG. 2 is a block diagram for explaining a configuration example of a DA converter in FIG. 1;
FIG. 3 is a timing chart for explaining the operation of FIG. 2;
FIG. 4 is a block diagram for explaining a second embodiment of the present invention.
FIG. 5 is a timing chart for explaining the operation of FIG. 4;
FIG. 6 is a block diagram for explaining a third embodiment of the present invention.
FIG. 7 is a block diagram for explaining a conventional speed-up technique.
[Explanation of symbols]
111, 112 to 11m AD converters 121, 122 to 12m, 131, 132 to 13m Pixel 14 Shift registers 151, 152 to 15n, 161, 162 to 16n Selection switches 181, 182 to 18n Output signal line 211 213, 221 to 223 DA converters 231 to 233 AD converters 411, 412 to 41m Voltage comparator 42 Counter circuit 43 DA converters 441 to 443, 451 to 453, 441a, 441b Sample hold circuit 461 to 463 DA converters 471 to 473 AD converters 61a, 61b, 63a, 63b AND gate circuit 62 Timing generator circuit

Claims (3)

A plurality of pixel elements that are arranged in a matrix and convert the amount of incident light into electric signals and output the electric signals, and output the pixel element columns that are sequentially selected and output in units of rows, and further output in column units In the solid-state imaging device that sequentially selects and outputs a pixel unit signal,
First conversion means for converting an output signal of a pixel element column selected in units of rows into a digital output signal in units of pixel elements;
A first switch for selecting a digital output signal converted by the first conversion unit on a bit-by-bit basis, a first capacitor for holding a voltage of the selected digital output signal on a bit-by-bit basis, A second capacitor connected in parallel with the first capacitor; a second switch for averaging voltages held in the first capacitor and the second capacitor; A sample-and-hold circuit that samples and holds the voltage held by the capacitance of the second conversion means, and outputs the sampled and held voltage as an analog output signal corresponding to the digital output signal ;
Selecting means for sequentially selecting the analog output signal output from the second converting means in the column unit;
A solid-state imaging device comprising: a third conversion unit that converts an analog output signal sequentially selected in a column unit into a digital signal and outputs the digital signal. The first conversion means converts the output signal of the pixel element row into a bit string of a digital output signal for each pixel element,
The second conversion means converts the bit sequence of the digital signal converted by the first conversion means into the analog output signal for each predetermined number of bits,
2. The solid-state imaging device according to claim 1, wherein the third converter converts the analog output signal converted by the second converter into a bit string of the digital signal having the predetermined number of bits. 3. A plurality of pixel elements that are arranged in a matrix and convert the amount of incident light into electric signals and output the electric signals, and output the pixel element columns that are sequentially selected and output in units of rows, and further output in column units In the solid-state imaging device that sequentially selects and outputs a pixel unit signal,
Reference voltage generating means for generating a first reference voltage that changes linearly and a second reference voltage that changes stepwise in synchronization with the first reference voltage;
A comparing unit that compares an output signal of the pixel element column selected in the row unit with the first reference voltage and outputs a trigger signal when both match.
Sample and hold means for sampling and holding the second reference voltage based on a trigger signal from the comparison means;
Selecting means for sequentially selecting the sampled and held second reference voltage in column units;
A solid-state imaging device comprising: a conversion unit that converts the second reference voltage sequentially selected in the column unit into a digital signal and outputs the digital signal as an output signal.

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