201233047 六 [0001] [0002] Ο ο 100102979 發明說明： 【發明所屬之技術領域】 本發明係有關於一種直流馬達驅動電路，特別是有關 於一種以互補式金氧半場效電晶體MOSFET為基礎，利用 閘極偏壓技術來控制Ν型金氧半場效電晶體（nm〇S)的導通 /截止，以免除需要死區時間的產生之Η電橋直流馬達驅 動電路。 【先前技術】 直流馬達為進行整流，而存在著電刷與整流子，因此 有產生火化之虞，不宜在高温、易燃等環境下工作’但 其具有較大的啟動轉矩、速度調整容，及使用直流電 源可以用電池供電等優點因此低功♦直流馬達被應用 在諸如電動簡77、錄音機、錄雜、CD唱盤、模型汽 車及玩具等使用環境較安全的消費或可擴式電子產品 上。而大功率的直流馬達則使用在電動車 、快速電梯、 機械人、工作母捲 可錢、及工廠自動化等地方α馬達控制的 本、匕括馬達的啟動與停止、馬達的轉向與轉速 其中直桃馬達之逮度控制，可簡單的經由控制其端電 壓來達成’最典型的方式是利用脈波寬度調變法（剛）來 進行、里由功率電晶體之導通及截止狀態之切換，調整 #導通週期比(Duty CycU Rati〇)，來改 變輸出電壓 之大小，進而控制直流馬達之轉速。 為了控制直>4馬達之轉速與轉向 ’ Η電橋乃為直流馬 達之最主要且重要的驅動器架構。目前被用來作為開關 的功率電晶體有雙接面電晶體（BJT)、金氧半場效電晶體 (M〇SFET)及問極絶緣雙接面電晶體（IGBT)等幾種半導體 表單編號A0101 丁 ▼肢 第 3 頁/共 23 頁 1002005261-0 201233047 兀件；其中BJT之切換速度較慢，導通時的集_射極間飽 和電壓較高，所以切換損失及導通損失均較大，但其具 有較高的耐壓及耐流能力，適於中功率之應用。而 M0SFET則因其切換速度快，切換損失較小，且其導通電 阻與耐壓強度為正相關，在低功率的轉換器中，因電源 電壓及導通時之電流均較小，所以導通損失亦較小，因 此很適合應用在低功率的直流電動機控制。I Gbt則是結 合了 M0SFET的閘極輸入特性及bjt的集-射極輸出特性， 其切換速度較BJT快，而耐壓及耐流能力則較高 ，而且仍持續發展提升中，適於中功率之應用。為獲取 較高的驅動高效率，本發明將採用以互補式M〇SFET為基 礎的驅動器設計架構，並提出一種閘極偏壓技術，除能 增加驅動效率外，隶重要的貢獻便是免除需有死區時間 (Dead Time)的產生；如此也將降低所提H電橋軀動器 之電路成本。 Η電橋一般可分為半橋（Half bridge)與全橋^^丄 Bridge)兩種裝置’經常廣泛被應用^Dc/Dc轉換器中。 而全橋裝置更是一種典型直流馬達驅動架構，用以控制 馬達的轉向與轉速。以下將就全橋式Η電橋基本結構、與 其死區時間效應作一闡述。 基本之全橋式Η電橋示意電路如第丨圖所示，其中s ~ 呂4是作為功率電晶體開關，而D〗，為保護二極體， 疋用來防止馬達線圈通電時所產生反電動勢電壓的破壞 。其切換控制是當Si、S4導通時，則s2、\必須要截止 ，反之亦然；且每一控制週期此四顆功率電晶體均須執 行一次導通/截止的切換動作。相較於單—功率電晶體的 1002005261-0 100102979 表單編號A0101 第4頁/共23頁 201233047 電路架構，其切換損失增加3倍且效率降低。然而為了可 改變直流馬達M’的轉動方向，此一全橋結構是必需的； 而且以MOSFET功率電晶體作為電子開關將具有較低的導 通電阻，進而獲得較高的效率。在此M〇SFET電橋電路中 ’四顆電晶體可以全部採則刪，但為保持上臂的開極 與汲極間之vGS電壓能達到導通之條件，需迫使上臂的間 極電壓高於汲極電壓，所以需利用電荷幫浦（Charge Pump)電路來產生比較高的電位，方可保證上臂的nm〇s 動作，因此其電路較為複雜。另一電橋型態則是採用兩 》 組互補式M0S電晶體來加以組構，此一型態其控制電路就 相對較為簡單。 不論採用何種型態的M0SFET電橋r電掎同側之上臂 與下臂功率電晶體不可同時導通，而且需考慮功率電晶 體在導通及截止過程中之延遲現象。在上下臂開關切換 狀態時，須先執行開關之截止，經過一小段時間，確保 完成截止動作後，再令另一個開關導通，嵗避免電源短 路之情形發生。而這個等待截止動作完成之時間，被稱 為死區時間，此時間之設定需視使用的功率電晶體之種 類及特性而定，若採用切換速度較快的M〇SFET，則其值 約為數百ns。因此’為避免電源短路產生過大電流打穿 (Shoot Through)電晶體的現象，死區時間的存在是有 其必要。然而此一時間會形成導通週期比之下限，而限 制低速運轉時之最低轉速，尤其在高頻切換時更形嚴重 ;並會使得命令電壓和實際輸出電壓的誤差過大，以及 產生電流波形扭曲所造成力矩輸出不足的問題，使得控 制電壓對轉速的轉換特性，產生如第2圖所示的非線性的 100102979 表單編號 A0101 第 5 頁/共 23 頁 1002005261-0 201233047 情形，為此需加強控制器的設計，以補償此一現象。傳 統的Η電橋驅動器均需有—死區時間產生電路以設定死區 時間’除增加電路複雜度外，也對其㈣效率有所影響 【發明内容】 [0003] 直流馬達驅動器之效率，除取決於Η電橋中電晶體的 導通電阻外，當使用ρ醫作為直流馬達轉迷控制時，驅動 器可控制的轉速範圍，亦可視作評估11電橋驅動器效率的 一項參數。本發明提出—種直流馬達驅動電路，係以互 補式MOSFET為麵之Η·驅觸，並_ _偏壓設計 方法’以免除傳統所需死區時間的限制，因而可 高的驅動效率。 本發月之無需死區時間的直流馬達驅動電路可包括第 -金氧半場效電晶體、第二金氧半場效電晶體、第三金 氧半場效電晶體、第四金氧半場效電晶體以及偏壓產生 電路其巾帛—金氧半場效電_的_電性連接於一 第-電壓且其祕電性連接於—馬達之—端受一第一 信號控制而導通或關閉。第二金氧半場效電晶體的源極 電除連接於第-電麗且其汲極電性連接於馬達之另一端 ，受一第二信號控制而導通或關。第三金氧半場效電 晶體的源極電性連接於—第二電壓且其汲極電性連接於 馬達之-端。第四金氧半場效電晶體的源極電性連接於 第-電壓且其祕電性連接於馬達之另—端。當第一信 號為脈衝寬度調變（PWM) k唬而第二信號為低位準 偏壓產生電路提供第三金龛 杯~金氧+ W電晶體隨PWM信號之責 任週期增加在略大於臨界 100102979 表單編號_ 下變化之一閑極偏 1002 201233047 麗給第三金氧半場效電晶體的閘極，且提供該第四金氧 半場效電晶體隨PWM信號之責任週期增加在略大於臨界電 壓（Vth)以上變化之一閘極偏壓給第四金氧半場效電晶體 的閉極’藉以使第一金氧半場效電晶體及第四金氧半場 效電晶體為導通’而第二金氧半場效電晶體為關閉，第 二金氧半場效電晶體之工作區域係從臨界截止之夾止區 朝截止區變化’且第一金氧半場效電晶體以及第三金氧 半場效電晶體不會同時導通，當第一信號為低位準而第 -½號為脈衝寬度調變信號時，偏壓產生電路提供第三 Ο 金氧半場效電晶體隨PWM信號之責任週期增加在略大於臨 界電壓（Vth)以上變化的一閘極偏壓給第三金氧半場效電 晶體的閘極，且提供第四金氡半場效電晶體隨PWM信號之 責任週期增加在略大於臨界電壓（th)以下變化之一閘極 偏壓給第四金氧半場效電晶體的閘極，藉以使第二金氧 半場效電晶體及第三金氧半場效電晶體為導通，第一金 氧半場效電晶體為關閉，第四金氧半場效電晶體之工作 區域係從臨界截止之夹止區朝截止區變化，且第二金氧 〇 半場效電晶體以及第四金氧半場效電晶體不會同時導通 其中，第一金氧半場效電晶體及第二金氧半場效電晶 體可為p型金氧半場效電晶體。 其中，第二金氧半場效電晶體及第四金氧半場效電晶 體可為N型金氧半場效電晶體。 其中，偏壓產生電路可包括一第一反相器、一第二反 相器、一第三反相器、一第四反相器、—第—電阻器' 100102979 一第二電阻器、一第三電阻器 表單編號A0101 第7頁/共23頁 一第四電阻器、一第五 1002005261-0 201233047 電阻器、一第六電阻器、一第一電容器以及一第二電容 器。其中第一反相器輸入第一信號並輸出至第一金氧半 場效電晶體的閘極。第二反相蒸輸入第二信號並輸出至 第二金氧半場效電晶體的閘極。第三反相器輸入第一信 號並輸出至第三金氧半場效電晶體的閘極。第四反相器 輸入第二信號並輸出至第四金氧半場效電晶體的閘極。 第一電阻器的一端電性連接於第一反相器的輸出端及第 一金氧半場效電晶體的閘極之間且另一端電性連接至第 一電壓。第一電容器的一端電性連接於第一反相器的輸 出端及第一金氧半場效電晶體的閘極之間且另一端接地 。第二電阻器的一端電性連接於第二反相器的輸出端及 第二金氧半場效電晶體的閘極之間且另一端電性連接至 第一電壓。第二電容器的一端電性連接於第二反相器的 輸出端及第二金氧半場效電晶體的閘極之間且另一端接 地。第三電阻器的一端電性連接於第三反相器的輸出端 及第三金氧半場效電晶體的閘極之間且另一端電性連接 至一電壓源。第四電阻器的一端電性連接於第四反相器 的輸出端及第四金氧半場效電晶體的閘極之間且另一端 電性連接至一電壓源。第五電阻器的一端電性連接於第 三反相器的輸出端及第三金氧半場效電晶體的閘極之間 且另一端電性連接至第二信號。第六電阻器的一端電性 連接於第四反相器的輸出端及第四金氧半場效電晶體的 閘極之間且另一端電性連接至第一信號。 [0004] 其中，第一電壓可為一電壓源。 其中，第二電壓可接地。 100102979 表單編號A0101 第8頁/共23頁 1002005261-0 201233047 、_上述無需死區時間的直流馬達驅動電路可更包括第— —、四保護二極體。第一保護二極體的陽極電 於第金氧半場效電晶體的汲極且其陰極電性連接 極電性連=半~效電晶體的源極。第二保護二極體的陽 ❹ [0005] Ο 100102979 性連接於2第—錢半職電晶體的③極且其陰極電 、一金氣半場效電晶體的源極。第三保護二極 、陽極電性連接於第三金氧半場效電晶體的源極且其 陰極電性連接於第三金氧半場效電晶體收極。第四保 護二極體㈣極電性連接於第四金氧半場效電晶體的源 極且其陰極電性連接於第四金氧半場效電晶體的沒極。 【實施方式】 第3圓係依據本發明以互補式MOSFET為架構之η電橋 驅動器電路的電路圖，其中由兩個觸⑽丨和建構其 上臂，而由兩個NM〇S (Qs和形成其下臂，Dr、則 為保護二極體。在此電路設計中，無需複雜的控制電路 ;僅需4個具開集極的反相器（w，以^為控制邏輯 仏號（A和B)之緣衝器，及配合一些被動元件：電阻器 (R^Rp與電容器（c )即可。201233047 [0001] [0001] [0002] ο ο 100102979 Description of the Invention: [Technical Field] The present invention relates to a DC motor drive circuit, and more particularly to a complementary MOS field-effect transistor MOSFET, The gate bias technology is used to control the on/off of the 金-type MOS field-effect transistor (nm〇S) to avoid the need for a bridge DC motor drive circuit that requires dead time. [Prior Art] The DC motor is rectified, but there are brushes and commutators, so there is a cremation, it is not suitable to work in high temperature, flammable environment, but it has a large starting torque and speed adjustment capacity. And the use of DC power can be powered by batteries, so low-power ♦ DC motors are used in consumer or expandable electronic products such as electric Jane 77, recorders, recordings, CD players, model cars and toys. on. The high-power DC motor is used in electric vehicles, fast elevators, robots, working mother rolls, and factory automation. The motor is controlled by α motor, including the start and stop of the motor, the steering and speed of the motor. The control of the peach motor can be achieved simply by controlling the voltage at its terminal. The most typical way is to use the pulse width modulation method (just) to switch on and off the power transistor. The turn-on period ratio (Duty CycU Rati〇) is used to change the output voltage to control the speed of the DC motor. In order to control the speed and steering of the '4' motor, the ’ bridge is the most important and important drive architecture for DC motors. The power transistors currently used as switches have several semiconductor form numbers A0101, such as double junction transistor (BJT), gold oxide half field effect transistor (M〇SFET), and gate insulated double junction transistor (IGBT).丁 ▼ 第 第 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; It has high pressure and flow resistance and is suitable for medium power applications. The M0SFET has a fast switching speed and a small switching loss, and its on-resistance is positively correlated with the withstand voltage. In a low-power converter, since the power supply voltage and the current during the conduction are small, the conduction loss is also Smaller, so it is well suited for low power DC motor control. I Gbt combines the gate input characteristics of M0SFET and the collector-emitter output characteristics of bjt. Its switching speed is faster than BJT, and its withstand voltage and current resistance are higher, and it is still developing and improving. Power application. In order to obtain higher drive efficiency, the present invention will adopt a driver design structure based on a complementary M〇SFET, and propose a gate bias technology. In addition to increasing drive efficiency, an important contribution is to eliminate the need. There is a dead time (this) will also reduce the circuit cost of the proposed H-bridge body. ΗBridges can be generally divided into half bridges (Half bridges and full bridges), which are often widely used in ^Dc/Dc converters. The full bridge unit is a typical DC motor drive architecture that controls the steering and speed of the motor. The basic structure of the full-bridge Η bridge and its dead time effect will be explained below. The basic full-bridge Η bridge schematic circuit is shown in the figure, where s ~ Lu 4 is used as a power transistor switch, and D is used to protect the diode, 疋 used to prevent the motor coil from being energized The destruction of the electromotive voltage. The switching control is that when Si and S4 are turned on, s2 and \ must be turned off, and vice versa; and the four power transistors are required to perform an on/off switching operation every control period. Compared to single-power transistor 1002005261-0 100102979 Form No. A0101 Page 4 of 23 201233047 Circuit architecture, its switching loss is increased by 3 times and efficiency is reduced. However, in order to change the direction of rotation of the direct current motor M', this full bridge structure is necessary; and the use of a MOSFET power transistor as an electronic switch will have a lower on-resistance, thereby achieving higher efficiency. In this M〇SFET bridge circuit, 'four transistors can be all removed, but to maintain the condition that the vGS voltage between the open and the drain of the upper arm can be turned on, the voltage of the upper arm must be forced higher than 汲. Extreme voltage, so the charge pump circuit is needed to generate a relatively high potential to ensure the upper arm's nm〇s action, so the circuit is more complicated. The other bridge type is constructed by using two complementary MOS transistors. The control circuit of this type is relatively simple. Regardless of the type of MOSFET bridge, the upper arm and the lower arm power transistor cannot be turned on at the same time, and the delay of the power transistor during conduction and turn-off should be considered. When the upper and lower arm switches are switched, the switch must be turned off. After a short period of time, ensure that the other switch is turned on after the cut-off action is completed, and the power supply short circuit is avoided. The time to wait for the completion of the cut-off action is called the dead time. The setting of this time depends on the type and characteristics of the power transistor used. If a M〇SFET with a fast switching speed is used, the value is approximately Hundreds of ns. Therefore, in order to avoid the phenomenon of excessive current through the transistor caused by the short circuit of the power supply, it is necessary to have the dead time. However, this time will form the lower limit of the conduction period, and limit the minimum speed during low speed operation, especially when the high frequency is switched; and the error of the command voltage and the actual output voltage will be too large, and the current waveform distortion will be generated. The problem of insufficient torque output causes the switching characteristic of the control voltage to the rotational speed to produce a nonlinear 100102979, as shown in Fig. 2, Form No. A0101, Page 5 of 23, 1002005261-0 201233047, for which the controller needs to be strengthened. The design is to compensate for this phenomenon. The traditional Η bridge driver needs to have a dead time generation circuit to set the dead time. In addition to increasing the circuit complexity, it also affects the efficiency of the (4) [invention] [0003] The efficiency of the DC motor driver, except Depending on the on-resistance of the transistor in the bridge, the range of speeds that the driver can control can also be considered as a parameter for evaluating the efficiency of the 11-bridge driver when using ρ as the DC motor sniffer control. The present invention proposes a DC motor drive circuit that uses a complementary MOSFET as a surface drive and a _ bias design method to eliminate the conventional dead time limitation and thus high drive efficiency. The DC motor driving circuit of the present month without dead time may include a first-gold oxygen half field effect transistor, a second gold oxygen half field effect transistor, a third gold oxygen half field effect transistor, and a fourth gold oxygen half field effect transistor. And the bias generating circuit is electrically connected to a first voltage and electrically connected to the motor to be turned on or off by a first signal. The source of the second gold-oxygen half-effect transistor is connected to the first-electrode and its drain is electrically connected to the other end of the motor, and is turned on or off controlled by a second signal. The source of the third gold-oxygen half-field effect transistor is electrically connected to the second voltage and its drain is electrically connected to the end of the motor. The source of the fourth gold-oxygen half-field effect transistor is electrically connected to the first voltage and is electrically connected to the other end of the motor. When the first signal is pulse width modulation (PWM) k唬 and the second signal is low level quasi-bias generating circuit, the third gold cup to gold oxide + W transistor increases with the duty cycle of the PWM signal at a slightly greater than the critical 100102979 Form No. _ One of the changes is idle 1002 201233047 Li gives the third gold oxide half field effect transistor gate, and provides the fourth gold oxide half field effect transistor with the duty cycle of the PWM signal increases slightly above the threshold voltage ( Vth) one of the above changes of the gate bias to the fourth gold oxide half field effect transistor's closed pole 'to make the first gold oxygen half field effect transistor and the fourth gold oxygen half field effect transistor to conduct' and the second gold oxygen The half field effect transistor is turned off, and the working area of the second gold oxide half field effect transistor changes from the critical cutoff region to the cutoff region' and the first gold oxide half field effect transistor and the third gold oxide half field effect transistor are not It will be turned on at the same time. When the first signal is low and the -1⁄2 is the pulse width modulation signal, the bias generating circuit provides the third Ο gold oxide half field effect transistor with the duty cycle of the PWM signal increasing slightly above the threshold voltage. (Vth) The above-mentioned change of one gate bias is applied to the gate of the third gold-oxygen half-field effect transistor, and the fourth gold-half half-field effect transistor is provided with the duty cycle of the PWM signal increasing at a value slightly less than the threshold voltage (th) The gate bias is applied to the gate of the fourth gold oxide half field effect transistor, so that the second gold oxide half field effect transistor and the third gold oxide half field effect transistor are turned on, and the first gold oxide half field effect transistor is turned off. The working region of the fourth gold-oxygen half-field effect transistor changes from the clamping region of the critical cutoff to the cut-off region, and the second gold oxide half field effect transistor and the fourth gold oxide half field effect transistor are not simultaneously turned on, A gold-oxygen half field effect transistor and a second gold oxide half field effect transistor may be p-type gold oxide half field effect transistors. The second gold oxide half field effect transistor and the fourth gold oxide half field effect transistor may be N type gold oxide half field effect transistors. The bias generating circuit can include a first inverter, a second inverter, a third inverter, a fourth inverter, a first resistor, a 100102979, a second resistor, and a second resistor. The third resistor form number A0101, page 7 / page 23, a fourth resistor, a fifth 1002005261-0 201233047 resistor, a sixth resistor, a first capacitor and a second capacitor. The first inverter inputs the first signal and outputs it to the gate of the first metal oxide half field effect transistor. The second reverse phase steam is input to the second signal and output to the gate of the second gold oxide half field effect transistor. The third inverter inputs the first signal and outputs it to the gate of the third metal oxide half field effect transistor. The fourth inverter inputs the second signal and outputs it to the gate of the fourth gold-oxide half field effect transistor. One end of the first resistor is electrically connected between the output end of the first inverter and the gate of the first gold-oxygen half-effect transistor, and the other end is electrically connected to the first voltage. One end of the first capacitor is electrically connected between the output end of the first inverter and the gate of the first metal oxide half field effect transistor, and the other end is grounded. One end of the second resistor is electrically connected between the output end of the second inverter and the gate of the second metal oxide half field effect transistor, and the other end is electrically connected to the first voltage. One end of the second capacitor is electrically connected between the output end of the second inverter and the gate of the second metal oxide half field effect transistor, and the other end is grounded. One end of the third resistor is electrically connected between the output end of the third inverter and the gate of the third metal oxide half field effect transistor, and the other end is electrically connected to a voltage source. One end of the fourth resistor is electrically connected between the output end of the fourth inverter and the gate of the fourth gold-oxygen half-effect transistor, and the other end is electrically connected to a voltage source. One end of the fifth resistor is electrically connected between the output end of the third inverter and the gate of the third gold-oxygen half-effect transistor, and the other end is electrically connected to the second signal. One end of the sixth resistor is electrically connected between the output end of the fourth inverter and the gate of the fourth gold-oxygen half-effect transistor, and the other end is electrically connected to the first signal. [0004] wherein the first voltage can be a voltage source. Wherein, the second voltage can be grounded. 100102979 Form No. A0101 Page 8 of 23 1002005261-0 201233047 _ The above DC motor drive circuit without dead time may further include the first and fourth protection diodes. The anode of the first protective diode is electrically connected to the drain of the gold oxide half field effect transistor and its cathode is electrically connected to the source of the semi-electrical transistor. The second protective diode of the anode [0005] Ο 100102979 is connected to the 3 pole of the 2nd money-dollar transistor and its cathode electric, the source of a gold gas half field effect transistor. The third protective diode and the anode are electrically connected to the source of the third gold oxide half field effect transistor and the cathode is electrically connected to the third gold oxide half field effect transistor. The fourth protection diode (4) is electrically connected to the source of the fourth gold oxide half field effect transistor and the cathode thereof is electrically connected to the electrode of the fourth gold oxide half field effect transistor. [Embodiment] The third circle is a circuit diagram of an n-bridge driver circuit constructed by a complementary MOSFET according to the present invention, wherein two uppers are constructed by two touches (10) and two NM〇S (Qs and formed thereof) The lower arm, Dr, is the protection diode. In this circuit design, no complicated control circuit is needed; only four inverters with open collectors are needed (w, with ^ as the control logic apostrophe (A and B) The edge of the punch, and with some passive components: resistors (R ^ Rp and capacitor (c) can be.
1 U 不同於傳統Η電橋電路需要有死區時間產生之設計方 法，本發明將閘極偏壓技術應用於所提驅動器之電路設 計。考慮在^和!^輸出為高電位狀況下，依據重疊原理 ，兩個_S (Q#Q4)❼閘極電壓（、和乂㈣）將分別 如式（1)與式（2)所示：1 U is different from the traditional tantalum bridge circuit which requires a dead time generation design method. The present invention applies the gate bias technique to the circuit design of the proposed driver. Considering that the output of ^ and !^ is high, according to the overlap principle, the two _S (Q#Q4) ❼ gate voltages (, and 乂 (4)) will be as shown in equations (1) and (2), respectively. :
VGN3=(R5/^R3 + R5))xVH+(R3/^3 + R5))xVB (D VGN4=(R6/(R4 + R6))xVH+(R4/^4 + R6))xVa (2) 其中vHa邏輯工作電壓（例如5伏特），v和v分 表單編號麵 第9頁/共㈣ A B ^002005261_0 201233047 輸入端A和B的邏輯電壓。當控制信號Α*β皆為低電位時 ，兩個PMOS (Q^nQ2)將立即被關閉。若選擇適當的%、 %與%、，則將針對〇3和\建立起兩個略大於臨界電 壓（Vth)的閘極偏壓，也因此\和、於此時進入導通狀態 ;而\^和、1^4也就相當於下列二式： VGN3=(R5/(R3 + R5))XVH-1 2 3 4 5th (3) VGN4 = (V(W)6 7 8 9¥Vth (4)VGN3=(R5/^R3 + R5))xVH+(R3/^3 + R5))xVB (D VGN4=(R6/(R4 + R6))xVH+(R4/^4 + R6))xVa (2) vHa logic operating voltage (eg 5 volts), v and v sub-form number face page 9 / total (four) AB ^002005261_0 201233047 Input terminal A and B logic voltage. When the control signal Α*β is low, the two PMOSs (Q^nQ2) will be turned off immediately. If the appropriate %, %, and % are selected, two gate biases slightly larger than the threshold voltage (Vth) will be established for 〇3 and \, and thus \ and will enter the conduction state at this time; And 1^4 is equivalent to the following two formulas: VGN3=(R5/(R3 + R5))XVH-1 2 3 4 5th (3) VGN4 = (V(W)6 7 8 9¥Vth (4)
再從式（3)與式（4)中，便可分別找出R /R與R /R 3 5 ’、4 6 之比例關係，如式（5)所示： R3/R5=R4/R6〜(VH/Vth)-1 (5) 現考慮一PWM信號輸入A端，而B端仍保持於低電位， 且此PWM信號週期小於^時間常數，因此致使、將一直 處於導通狀態，而vGN4則被修改為： VGN4 = Vth+('R4/('R4 + R6^XVHXl) (6) 此處D為PWM信號之責任週期（Duty (^^幻率，且 PWM信號高準位電壓為、（例如5 v)。由於有閘極偏壓的存 在’因此’以較小責任週期的pWM信號粳容易啟動\導通 。此時雖然PWM信號也同時出現在u的輸入端，然而v 〇 GN3 如式（Ό所示： 100102979 表單編號A0101 第10頁/共23頁 1002005261-0 1 GN3=(R5/(R3 + R5))xVhx〇-I>) (7) 2 將隨PWM信號之責任週期在略大於臨界電壓（v )以下 3 th 4 變化’因此q3之工作區域僅能從臨界截止之夾止區至截 5 止區間變化，而確保\與%同側不會同時導通，故無需 6 死區時間的存在必要。同理，當pWM信號輸入8端，且A端 7 保持於低電位，則q截止、Q導通，而Q同上述僅 8 1 2 3 4 9 會於臨界截止之夾止區至截止區間動作。 201233047 本發明之Η電橋驅動器有著一般直流馬達控制的4種基 本動作功能，包括：停止、正轉、反轉、與剎停。表1所 示即為此Η電橋驅動器之動作功能表，其詳細動作說明如 下所述： [0006] 入 馬達動作 A B 低電位Lo 低電位Lo 停止 PWM 低電位Lo 正轉(由PWM控制轉速） 低電位Lo PWM 反轉(由PWM控制轉速） 高電位Hi 雨電位Hi 剎停 表1 [0007] (1 )當A = B= “Lo”時，Qi和〇2關閉，而由所建立務大於From equations (3) and (4), the ratio of R / R to R / R 3 5 ', 4 6 can be found separately, as shown in equation (5): R3/R5 = R4/R6 ~(VH/Vth)-1 (5) Now consider a PWM signal input A terminal, and the B terminal remains at a low potential, and the PWM signal period is less than the ^ time constant, so that it will always be in the on state, and vGN4 It is modified to: VGN4 = Vth+('R4/('R4 + R6^XVHXl) (6) where D is the duty cycle of the PWM signal (Duty (^^ illusion, and the PWM signal high-level voltage is , ( For example, 5 v). Because of the presence of the gate bias, 'pure' the pWM signal with a small duty cycle is easy to start and turn on. At this time, although the PWM signal also appears at the input of u, v 〇 GN3 (Ό: 100102979 Form No. A0101 Page 10/Total 23 Page 1002005261-0 1 GN3=(R5/(R3 + R5))xVhx〇-I>) (7) 2 The duty cycle with the PWM signal is abbreviated It is greater than the 3 th 4 change below the threshold voltage (v). Therefore, the working area of q3 can only change from the pinch-off zone to the cut-off zone of the critical cutoff, and it is ensured that the same side of % is not turned on at the same time, so there is no need for 6 dead zones. The existence of time Similarly, when the pWM signal is input to the 8 terminal and the A terminal 7 is kept at a low potential, q is turned off and Q is turned on, and Q is the same as the above 8 1 2 3 4 9 will be in the critical cutoff region to the cutoff interval. 201233047 The Η bridge driver of the present invention has four basic motion functions of general DC motor control, including: stop, forward rotation, reverse rotation, and brake stop. Table 1 shows the action function of the Η bridge driver. The detailed operation description of the table is as follows: [0006] Into motor action AB Low potential Lo Low potential Lo Stop PWM Low potential Lo Forward (by PWM control speed) Low potential Lo PWM inversion (rotation by PWM) High potential Hi Rain potential Hi brake stop table 1 [0007] (1) When A = B = "Lo", Qi and 〇2 are closed, and the established task is greater than
Vth的偏壓V 與V 致使Q和Q導通。由於此時並無任 ΟΝ 〇 bN 4 d 4 - 何電流流經電晶體，因此馬達處於停止狀態。 (2) 當A=B= “Hi”時，Q^〇Q2導通，而〇3和〇4截止；如 此將產生一瞬間剎停的效果。 (3) 當A=PWM，B= “Lo”時，卩丨導通，Q2截止，而\則 受控於PWM信號；可隨PWM信號責任週期，從截止（D=0) 到完全導通（D = l)。因此，馬達有正轉效果，且轉速與責 任週期成正比。此時Q3亦是隨PWM信號責任週期變化，從 臨界截止之夾止區朝截止區（D=l)動作。 (4) 反之，當A= “Lo” ，B= PWM時，❾丨截止，Q2導通， 而1則受控於PWM信號；同（3)所述，只是Q。與Q,動作互 〇 3 4 換，且此時馬達反轉運行。 在操作上此驅動器有一限制：就是當一輸入端受控於 100102979 表單編號A0101 第11頁/共23頁 1002005261-0 201233047 PWM信號時’而另一輸入端為高電位是不被允許的，否則 在PWM信號輸入侧之pm〇S與NM0S會有電流打穿現象，故 應保持於低電位。 [0008] 藉由提供偏壓於兩個NOMS閘極的技術，本發明之η電 橋驅動器之最主要特色：便是無需有死區時間產生電路 的存在；且在PWM控制下，可從較小的責任週期便能驅動 直流馬達，因此可以增加馬達轉速的控制範圍，進而提 升了驅動效率。此外，也由於控制電路的精簡，更有助 於降低硬體的設計成本。當PWM控制時’雖然在PWM信號 輸入侧之PM0S與NMOS不會造成兩者同時導通。但當PWM 信號責任週期較小時，此NM0S工作於臨界截止之夾止區 中，仍會有少量的電流通過，遣是Λ—驅動器電路設計 所需付出的額外代價；而此電流則會隨責任週期增加至 10 0%而趨近於〇。因此，妥善地設計NOMS閘極偏壓，便 能在降低損耗電流與增加缚動效率兩者間取得平衡。 ：'：：·" :+: . : r . . th 底下以一實驗來驗證本潑:萌之效果，莫中使用2個 PMOS功率電晶體C IRF9540)及2個NMOS功率電晶體 (IRF540)來建構Η電橋。這些功率MOSFET其臨界電壓v 約為3V，且根據前述原理，選擇RQ= 1^ = 1ΚΩ及R = r 1· 8ΚΩ，以分別建立兩個NOMS的閘極偏壓= v = GN3 GN4 3. 2V。此外，此驅動器設定可驅動直流馬達電壓範圍為 5 V〜2 4 V，而最大承受電流則為1 0 A。相關量測條件如下 :所提供的PWM信號頻率為1 5. 625KHz，直流馬達供給電 壓則為12V。將PWM信號輸入至此驅動器的某一控制輸入 端，而另一控制輸入端則保持邏輯低電位。當調整改變 100102979 表單編號A0101 第12頁/共23頁 1002005261-0 201233047 PWM彳5號責任週期（從0~100%)時，以數位儲存示波器分 另J觀測電路中各端點之電壓變化情形；以下將逐一說明 各量測波形。 第4圖所示為：當B端（CH2)輸入一責任週期為50%之 號，而A端（CH1)保持低電位時，分別於\與\閘 、所測得之Vgn3(CH3)和電壓波形。從圖中 明^5臺中tr , 韦m VGN3的大小，在PWM信號ON期間，其平均電壓 從所建立偏壓3. 2丫往上提升至約4. 09V而驅動Q3導通（此 》 =處於截止狀態）。在此\雖然保持導通，然而的 ”句電壓部從由所建立偏壓& 2V往下降低至約1.61乂而 ，q4截止。因此’電橋同侧之Q外)與W並不會 同時導通’自然就不需要存在洗:區咖。同時，第5圖中 扪頋㈣丨的閘級電壓拉升至12V以關閉\，而即便有 L號輸入’ 的閘級電壓則被箝制於低電位以導通\ 右考慮加至馬達兩端點的電壓，亦即相當於分別量測 0咖4沒極端點電麗。在第&圖，’㈤顯―的平均淡 ) ㈣壓隨責任週期増加而變小，而此時因Q2是完全導通 ，目此Q4的沒極電壓（CH2)就-直保持在12V。相同地， «責任週期改為3〇%Bf，所有電晶體動作皆同5()%責任週 期之PWM信號輸入，尸县v ^ ^ ^ ^The bias voltages V and V of Vth cause Q and Q to conduct. Since there is no ΟΝ 〇 bN 4 d 4 - current flows through the transistor, the motor is at a standstill. (2) When A=B= “Hi”, Q^〇Q2 is turned on, and 〇3 and 〇4 are turned off; thus, an instantaneous brake effect is generated. (3) When A=PWM, B=“Lo”, 卩丨 is turned on, Q2 is turned off, and \ is controlled by PWM signal; can follow the duty cycle of PWM signal, from cutoff (D=0) to full turn-on (D) = l). Therefore, the motor has a forward rotation effect and the rotation speed is proportional to the duty cycle. At this time, Q3 also changes with the duty cycle of the PWM signal, and moves from the pinch-off region of the critical cutoff to the cut-off region (D=l). (4) Conversely, when A = "Lo", B = PWM, ❾丨 is turned off, Q2 is turned on, and 1 is controlled by the PWM signal; as described in (3), it is only Q. With Q, the action is 〇 3 4 and the motor is reversed. In operation, this driver has a limitation: when an input is controlled by 100102979 Form No. A0101 Page 11 / 23 Page 1002005261-0 201233047 PWM signal 'When the other input is high, it is not allowed, otherwise pm〇S and NM0S on the PWM signal input side have current breakdown, so they should be kept at a low potential. [0008] By providing a bias voltage to two NOMS gates, the main feature of the η bridge driver of the present invention is that there is no need to have a dead time generating circuit; and under PWM control, A small duty cycle can drive the DC motor, which increases the control range of the motor speed, which in turn increases drive efficiency. In addition, due to the streamlining of the control circuit, it is also helpful to reduce the hardware design cost. When PWM is controlled, the PMOS and NMOS on the PWM signal input side do not cause both to turn on at the same time. However, when the duty cycle of the PWM signal is small, the NM0S operates in the clamping region of the critical cutoff, and a small amount of current still passes, which is an additional cost to the driver circuit design; this current will follow The duty cycle has increased to 100% and is approaching 〇. Therefore, proper design of the NOMS gate bias can balance the reduction of the loss current with the increase of the binding efficiency. :'::·" :+: . : r . . th Under an experiment to verify the effect of this splash: Meng, using 2 PMOS power transistors C IRF9540) and 2 NMOS power transistors (IRF540) ) To build a bridge. These power MOSFETs have a threshold voltage v of about 3V, and according to the foregoing principle, RQ = 1^ = 1ΚΩ and R = r 1· 8ΚΩ are selected to establish the gate bias of two NOMSs respectively = v = GN3 GN4 3. 2V . In addition, this drive is designed to drive DC motor voltages from 5 V to 2 4 V and a maximum withstand current of 10 A. The relevant measurement conditions are as follows: The supplied PWM signal frequency is 15.2 625 KHz, and the DC motor supply voltage is 12 V. The PWM signal is input to one of the control inputs of this driver while the other control input remains at a logic low. When the adjustment changes 100102979 Form No. A0101 Page 12 / Total 23 Page 1002005261-0 201233047 PWM 彳 No. 5 responsibility cycle (from 0 to 100%), the digital oscilloscope is stored in the J observation circuit The following measurement waveforms will be explained one by one. Figure 4 shows: When the B-terminal (CH2) input has a duty cycle of 50%, and the A terminal (CH1) remains low, respectively, the \ and \ gates, the measured Vgn3 (CH3) and Voltage waveform. From the figure, the size of tr, Wei m VGN3, during the PWM signal ON, the average voltage is raised from the established bias voltage of 3.2 丫 to about 4. 09V and the drive Q3 is turned on (this) = at Cutoff status). Here, although it remains on, the "sentence voltage" is reduced from the established bias & 2V down to about 1.61 乂, and q4 is cut off. Therefore, 'the Q on the same side of the bridge is not the same as W. Turning on 'naturally does not need to have a wash: the district cafe. At the same time, the voltage of the gate of the 扪頋(4) 第 in Figure 5 is pulled up to 12V to turn off\, and even if there is the input voltage of the L number, the voltage of the gate is clamped to low. The potential is turned on/right to consider the voltage applied to the two ends of the motor, which is equivalent to measuring 0 coffee 4 without extreme points. In the & graph, '(5) display - average light) (4) pressure with responsibility cycle It is smaller and smaller, and at this time, because Q2 is fully turned on, the Q4's immersed voltage (CH2) is kept at 12V. Similarly, «the duty cycle is changed to 3〇%Bf 5 ()% duty cycle PWM signal input, corpse v ^ ^ ^ ^
^VGN3之平均電壓上升至約3. 74V ’而VGN4之平均電壓下降至約2.25V (如第7圖所示）；當 然馬達轉動速度就變緩。 上述實驗中，除量測本發明之驅動器各端點波形外， 另外也選用一顆同為互補式_FET型態之市售Η電橋晶片 (TC4424)做測試比較。在採用相同直流馬達的驅動條 1002005261-0 件下，若使用本發明Η電橋驅動器以簡信號操控，當其 100102979 表單編號A0101 第13頁/共23頁 、 201233047 責任週期從〇開始調升，大約調升至12· 5%時，& 、建便能 從完全停止到開始啟動。而若於全速轉動後開始滅$ 則責任週期大約調降至8%以下，才迫使馬達停止。 °然而 ，若改用現有晶片TC4424，當PWM信號責任週期大約， 升至21%時，方可使馬達從靜止中啟動；而在全速轉動後 開始減速，責任週期則大約調降至16%以下，馬達便停止 轉動。 综上所述，傳統Η電橋受限於死區時間，而需有死區 時間產生電路’或甚而亦需要補償電路，自然增加硬體 設計成本。本發明提出一種建構於亙補式MOSFET為基礎 之Η電橋驅動器，並且採用NMOS閘極偏壓技術，以免除死 區時間效應的影響。從實際實驗結果中，本發明之Η電橋 驅動器確實有效改善了傳統Η電橋之驅動效率；其pwm信 號可調整轉速範圍也較傳統Η電橋來得大》由於無需有死 區時間產生電路，此驅動器電路之設計將更為精簡，且 有助於未來實現於積體電路晶片中α 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明’任何其所屬技術領域中具有通常知識者， 在不脫離本發明之精神和範圍内，當可作任意之更動與 潤飾，因此本發明之保護範圍當視後附之申請專利範圍 所界定者為準。 【圖式簡單說明】 [0009] 100102979 第1圖係一習知Η電橋之電路圖。 第2圖顯示習知直流馬達之控制電壓對轉速的關係。 第3圖係依據本發明之η電橋驅動電路之電路圖。 第4圖顯示測試本發明之η電橋驅動電路於輸入責任週 表單編號Α0101 第14頁/共23頁 1002005261-0 201233047 期為50%之NMOS閘極電壓。 第5圖顯示測試本發明之Η電橋驅動電路於輸入責任週 期為50%之PM0S閘極電壓。 第6圖顯示測試本發明之Η電橋驅動電路於輸入責任週 期為50°/。之NM0S汲極電壓。 第7圖顯示測試本發明之Η電橋驅動電路於輸入責任週 期為30%之NM0S閘極電壓。 【主要元件符號說明】 [0010] ο [0011] 習知技術 Μ， 直流馬達 保護二極體 SrS4 功率電晶體開關 本發明 Μ 直流馬達 D1~D4 保護二極體 q「q2 P型金乳半場效電晶體 VQ4 N型金氧半場效電晶體 ϋΓϋ4 反相器 C1~C2 電容器 RrR6 電阻器 A, B 控制信號輸入端 ❹ 100102979 表單編號Α0101 第15頁/共23頁 1002005261-0The average voltage of ^VGN3 rises to about 3.74V' and the average voltage of VGN4 drops to about 2.25V (as shown in Figure 7); of course, the motor rotates at a slower speed. In the above experiment, in addition to measuring the waveforms of the respective end points of the driver of the present invention, a commercially available tantalum bridge chip (TC4424) of the same complementary FET type was also used for test comparison. Under the driving strip 1002005261-0 with the same DC motor, if the Η bridge driver of the present invention is used to operate with a simple signal, when its 100102979 form number A0101 page 13 / 23, 201233047 responsibility cycle starts from 〇, When it is raised to about 12.5%, & construction can start from the complete stop to the start. If the duty cycle starts to extinguish after full speed rotation, the duty cycle is reduced to less than 8%, forcing the motor to stop. ° However, if the existing chip TC4424 is used, the motor signal can be started from a standstill when the duty cycle of the PWM signal rises to about 21%; and the deceleration starts after the full speed rotation, and the duty cycle is reduced to about 16%. The motor stops rotating. In summary, the traditional Η bridge is limited by the dead time, but requires a dead time generating circuit ‘or even a compensation circuit, which naturally increases the hardware design cost. The present invention proposes a Η bridge driver based on a 亘-compensated MOSFET and employs an NMOS gate bias technique to avoid the effects of dead time effects. From the actual experimental results, the Η bridge driver of the present invention effectively improves the driving efficiency of the conventional Η bridge; the pwm signal can adjust the speed range to be larger than that of the conventional Η bridge, since there is no need to have a dead time generating circuit. The design of the driver circuit will be more streamlined and will be implemented in the integrated circuit wafer in the future. Although the present invention has been disclosed in the preferred embodiments as above, it is not intended to limit the present invention to any of the technical fields of the present invention. It is intended that the scope of the present invention be defined by the scope of the appended claims. [Simple description of the diagram] [0009] 100102979 The first diagram is a circuit diagram of a conventional bridge. Figure 2 shows the relationship between the control voltage of a conventional DC motor and the rotational speed. Figure 3 is a circuit diagram of an n-bridge drive circuit in accordance with the present invention. Figure 4 shows the NMOS gate voltage for testing the η bridge drive circuit of the present invention in the input responsibility week Form No. Α0101 Page 14 of 23 1002005261-0 201233047. Figure 5 shows the PMOS gate voltage for testing the Η bridge drive circuit of the present invention with an input duty cycle of 50%. Figure 6 shows the test of the Η bridge drive circuit of the present invention with an input duty cycle of 50°/. NM0S drain voltage. Figure 7 shows the NM0S gate voltage for testing the Η bridge drive circuit of the present invention with an input duty cycle of 30%. [Main component symbol description] [0010] </ RTI> [0011] The prior art Μ, DC motor protection diode SrS4 power transistor switch 本 DC motor D1 ~ D4 protection diode q "q2 P type gold milk half field effect Transistor VQ4 N-type gold-oxygen half-field effect transistor ϋΓϋ4 Inverter C1~C2 Capacitor RrR6 Resistor A, B Control signal input terminal 102 100102979 Form No. 1010101 Page 15 of 23 1002005261-0