CN201601657U - Power amplifier output circuit without dead time - Google Patents

Abstract

A power amplifier output circuit without dead time relates to electronic technique and comprises a first power tube (1) and a second power tube (2) which are connected in series, and a first driving circuit (10) and a second driving circuit (20) which are respectively connected to control terminals of the two power tubes. A Q-point is an output end, the first driving circuit (10) includes a first driving tube (11) and a second driving tube (12) which are connected in series, and the second driving circuit (20) includes a third driving tube (21) and a fourth driving tube (22) which are connected in series. The power amplifier output circuit can eliminate distortion and reduce system total harmonic distortion.

Description

The power amplifier output-stage circuit of no Dead Time

Technical field

The utility model relates to electronic technology, particularly a kind of output-stage circuit of power amplifier.

Background technology

Traditionally two power tubes are connected to constitute output stage in power amplifier, each power tube all has one to terminate to output.Drive circuit provides suitable drive signal for the control end of power tube.In the D class A amplifier A, its power tube must work on off state, so power tube adopts FET (field effect transistor) more.Because the power tube series connection so should avoid working simultaneously, causes damage in order to avoid cause the output stage overcurrent to power tube.Therefore, when the design driven circuit, will introduce so-called Dead Time, power controlling Guan Buhui conducting simultaneously.But this Dead Time will cause the distortion of output signal.

The D class A amplifier A comprises integrator, pulse width modulator, gate driving, level translator, MOSFETs and low pass filter.Circuit needs a Dead Time, provides the time-delay of symmetry can reduce distortion for two power tubes.But Dead Time still can cause a lot of noises.

The utility model content

Technical problem to be solved in the utility model is to provide a kind of power amplifier output-stage circuit with no Dead Time characteristic, with the noise of solution prior art and the problem of distortion.

The technical scheme that the utility model solve the technical problem employing is, the power amplifier output-stage circuit of no Dead Time, first power tube and second power tube that comprise series connection, and first drive circuit and second drive circuit that are connected respectively to two power tube control ends, the Q point is an output, first drive circuit comprises first driving tube and second driving tube of series connection, voltage is that first accessory power supply of Vboost connects the Q point by first driving tube and second driving tube, the tie point of first driving tube and second driving tube connects the grid of first power tube, the input termination high level of first power tube, output termination Q point;

Second drive circuit comprises the 3rd driving tube and the 4th driving tube of series connection, voltage is that second accessory power supply of Vdd passes through the 3rd driving tube and the 4th driving tube ground connection, the tie point of the 3rd driving tube and the 4th driving tube connects the grid of second power tube, the output head grounding of second power tube, input termination Q point;

Wherein, first power tube is identical with the parasitic capacitance of second power tube; Threshold voltage is also identical, is V _Th, the conducting resistance of first driving tube is R _On11, the conducting resistance of second driving tube is R _On12, the conducting resistance of the 3rd driving tube is R _On21, the conducting resistance of the 4th driving tube is R _On22, parameters satisfies following two formulas:

$\frac{R_{\mathrm{on}12}}{R_{\mathrm{on}12}+R_{\mathrm{on}21}}=\frac{V_{\mathrm{th}}}{\mathrm{Vboost}}$

$\frac{R_{\mathrm{on}22}}{R_{\mathrm{on}11}+R_{\mathrm{on}22}}=\frac{V_{\mathrm{th}}}{\mathrm{Vdd}}.$

The utility model has been overturned the prejudice of recommending the essential Dead Time of output.In existing technology,, all Dead Time must be arranged usually in the application even shortcomings such as introducing distorted signals is arranged.Output of the present utility model no longer needs Dead Time, and prior art increases the distortion of output because Dead Time is arranged.The utility model can be removed this distortion, reduces the total harmonic distortion (THD) of system.Prior art must have a special circuit to produce Dead Time.After using new technology, can remove this circuit, reduce the complexity of circuit, reduce cost.Non-stack clock circuit is subjected to technogenic influence big, and the Dead Time size is wayward, reduces the consistency of systematic function.The utility model does not relate to the absolute value of device parameters, so be subjected to the influence of technological fluctuation little, can improve stability, consistency and the rate of finished products of system.

Below in conjunction with the drawings and specific embodiments the utility model is further described.

Description of drawings

Fig. 1 is a circuit diagram of the present utility model.

Fig. 2 is the oscillogram of prior art output rising edge.

Fig. 3 is the oscillogram of prior art output trailing edge.

Fig. 4 is the oscillogram of the utility model output rising edge.

Fig. 5 is the oscillogram of the utility model output trailing edge.

Embodiment

Referring to Fig. 1.

The utility model impels the threshold voltage of power tube to intersect the no Dead Time of realization the other way around simultaneously when importing opposite input signal at the same time by drive circuit, therefore no longer require to increase for special consideration power tube the time delay circuit of Dead Time.

Realize the push-pull power amplifier output-stage circuit of this purpose, comprise:

First power tube 1 and second power tube 2 of series connection, and first drive circuit 11 and second drive circuit 12 that are connected respectively to two power tube control ends;

Power tube has threshold voltage, and when control end voltage was higher than threshold voltage vt h, the power tube conducting was lower than threshold voltage, not conducting of power tube.

Two drive circuit receiving inputted signals, and control power tube is separately made the response to input signal.When receiving suitable input signal, drive circuit impels the crossing simultaneously the other way around threshold voltage that reaches of the control voltage of power tube.When a power tube was opened, another power tube was turned off, and had avoided power tube conducting simultaneously, had also avoided Dead Time.The utility model is based on such fact: when control voltage through threshold voltage, power tube open and shutoff is not to take place moment, but through change-over time of a weak point.Because avoided power tube conducting simultaneously, this has just allowed power tube can be in this transition status simultaneously.All very big and especially true when pressing rightabout and changing when control signal.

Desirable situation is, drive circuit is received synchronous reverse input signal, and the time difference between the signal is within several nanoseconds.So just simplified the design of drive circuit.Certainly, also can set up suitable time-delay for the asynchronous input signal of drive circuit.Herein, reverse input signal is interpreted as reverse step or the input signal of certain slope is arranged, and a signal is low by hypermutation, and another signal is then by the low height that becomes.

The utility model has been overturned the prejudice of recommending the essential Dead Time of output.In existing technology,, all Dead Time must be arranged usually in the application even shortcomings such as introducing distorted signals is arranged.

In the first-selected embodiment of the utility model such as Fig. 1,

First drive circuit 10 comprises first driving tube 11 and second driving tube 12 of series connection, voltage is that first accessory power supply of Vboost connects the Q point by first driving tube 11 and second driving tube 12, the tie point of first driving tube 11 and second driving tube 12 connects the grid of first power tube 1, the input termination high level of first power tube 1, output termination Q point;

Second drive circuit 20 comprises the 3rd driving tube 21 and the 4th driving tube 22 of series connection, voltage is that second accessory power supply of Vdd passes through the 3rd driving tube 21 and the 4th driving tube 22 ground connection, the tie point of the 3rd driving tube 21 and the 4th driving tube 22 connects the grid of second power tube 2, the output head grounding of second power tube 2, input termination Q point;

The conducting resistance R of parameter request second driving tube 12 of the present utility model _On12Equal the ratio of the threshold voltage vt h and the first accessory power supply voltage Vboost substantially with the ratio of second driving tube 12, the 3rd driving tube 21 resistance sums, promptly

$\frac{R_{\mathrm{on}12}}{R_{\mathrm{on}12}+R_{\mathrm{on}21}}=\frac{V_{\mathrm{th}}}{\mathrm{Vboost}}$

Drain-source resistance when resistance herein is the driving tube conducting, first accessory power supply are the accessory power supply of first drive circuit.First and second accessory power supplys need not be equal to the supply voltage of power tube.

Equally, the ratio of the resistance of the 4th driving tube 22 and first driving tube 11, the 4th driving tube 22 resistance sums equals the ratio of the threshold voltage and the second accessory power supply voltage Vdd substantially.That is:

$\frac{R_{\mathrm{on}22}}{R_{\mathrm{on}11}+R_{\mathrm{on}22}}=\frac{V_{\mathrm{th}}}{\mathrm{Vdd}}$

This ratio has provided the suitable sequential of drive circuit to the control signal of power tube.

Under power tube 1 situation identical with 2, parasitic capacitance is also equal, that is: Cgdh=Cgdl, Cgsh=Cgsl.Export Vout from high to low when power output stage, then require the VinHigh input low, VinLow imports high.Be in conducting state simultaneously for fear of power tube 1 and 2, the output voltage that requires drive circuit 10 and 20 is the threshold voltage vt h of power tube 1 and 2 simultaneously.So just have:

$\frac{\mathrm{Vboost}-V_{\mathrm{th}}}{1/R_{\mathrm{on}12}}=\frac{V_{\mathrm{th}}}{1/R_{\mathrm{on}21}}$

Be equivalent to

$\frac{R_{\mathrm{on}12}}{R_{\mathrm{on}12}+R_{\mathrm{on}21}}=\frac{V_{\mathrm{th}}}{\mathrm{Vboost}}$

Equally

$\frac{R_{\mathrm{on}22}}{R_{\mathrm{on}11}+R_{\mathrm{on}22}}=\frac{V_{\mathrm{th}}}{\mathrm{Vdd}}$

Because the ratio of driving tube satisfies above-mentioned relation, then has the power tube grid voltage and is charged to V from 0 _ThTime and discharge into V from Vdd/Vboost _ThTime equate.Like this, in the process of switching power tube, the grid voltage of two power tubes always reaches V simultaneously at the same time _ThThis just means two power tubes while switch always, and opposite states, so there is not the state of conducting simultaneously, does not also have Dead Time.

The utility model is when implementing, and the conducting resistance that suitably increases driving tube 11 and 21 can increase the robustness of circuit.

Referring to Fig. 2---5.

Among four figure, putting in order of waveform is the same, is respectively the voltage waveform of node VinLow, VinHigh, Vgl, Vgh and Vout from top to bottom.

VinLow and VinHigh must make both earlier simultaneously for high when changing in the prior art, and one is descended.VinLow and VinHigh are Dead Time for the high time simultaneously.At Dead Time, Vout can not export a definite voltage.Technology of the present utility model, VinLow and VinHigh can change simultaneously, do not have Dead Time.

Claims (1)

1. the power amplifier output-stage circuit that does not have Dead Time, first power tube (1) and second power tube (2) that comprise series connection, and first drive circuit (10) and second drive circuit (20) that are connected respectively to two power tube control ends, the Q point is an output, it is characterized in that:

First drive circuit (10) comprises first driving tube (11) and second driving tube (12) of series connection, voltage is that first accessory power supply of Vboost connects the Q point by first driving tube (11) and second driving tube (12), the tie point of first driving tube (11) and second driving tube 12 connects the grid of first power tube (1), the input termination high level of first power tube (1), output termination Q point;

Second drive circuit (20) comprises the 3rd driving tube (21) and the 4th driving tube (22) of series connection, voltage is that second accessory power supply of Vdd passes through the 3rd driving tube (21) and the 4th driving tube (22) ground connection, the tie point of the 3rd driving tube (21) and the 4th driving tube (22) connects the grid of second power tube (2), the output head grounding of second power tube (2), input termination Q point;

Wherein, first power tube (1) is identical with the parasitic capacitance of second power tube (2); Threshold voltage is also identical, is V _Th, the conducting resistance of first driving tube 11 is R _On11, the conducting resistance of second driving tube (12) is R _On12, the conducting resistance of the 3rd driving tube 21 is R _On21, the conducting resistance of the 4th driving tube (22) is R _On22, parameters satisfies following two formulas:

$\frac{R_{\mathrm{on}12}}{R_{\mathrm{on}12}+R_{\mathrm{on}21}}=\frac{V_{\mathrm{th}}}{\mathrm{Vboost}}$

$\frac{R_{\mathrm{on}22}}{R_{\mathrm{on}11}+R_{\mathrm{on}22}}=\frac{V_{\mathrm{th}}}{\mathrm{Vdd}}.$

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