JP2009201256A - Transistor drive device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transistor drive device suitable for driving a transistor at the low side of a bridge circuit for driving a load. <P>SOLUTION: A transistor drive device 100 comprises a drive control part 10, a drive power supplying part 11, and a current level detecting part 12. The drive power supplying part 11 drives Q2 or Q4 which is a DMOSFET on the low side of an H bridge circuit only by PTr2, first; and when the Q2 or Q4 is discriminated as being in half-on state, based on the comparison signal from the current level detecting part 12 that compares the voltage level of a current detection resistor of the H bridge circuit with a voltage level in half-on state, a PTr3, as well as the PTr2, is turned on, a drive current is supplied to the gate terminal of Q2 or Q4 via these two transistors. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a transistor driving apparatus suitable for driving a low-side transistor of a bridge circuit that drives a load such as a motor from an off state to an on state.

  Conventionally, as a circuit for driving a load such as a motor, there are a half-bridge circuit, a full-bridge circuit, and the like including a transistor on a high potential side (high side) and a transistor on a low potential side (low side). . In such a bridge circuit, the high-side transistor and the low-side transistor are independently driven to be turned on or off, and the load is turned on or off.

For loads that require relatively high power and require high-speed switching operation, a MOSFET (metal-oxide-semiconductor field-effect transistor) designed for high power as a transistor that constitutes a bridge circuit Is used. An example of a high power MOSFET is DMOS (Double-Diffused MOSFET).
Further, as a circuit for driving the transistor on the low side of the bridge circuit, for example, there is a low side gate drive circuit described in Non-Patent Document 1. As shown in FIG. 14, the gate drive circuit includes an NPNTr that is an NPN bipolar transistor, a PNPTr that is a PNP bipolar transistor, a gate series resistance _RG, and a Schottky barrier diode SD. Is done. The emitter terminal of the NPNTr and the emitter terminal of the PNPTr are connected, the collector terminal of the NPNTr is connected to the power source, and the collector terminal of the PNPTr is grounded to constitute an emitter-follower circuit. The connection between NPNTr and PNPTr is electrically connected to the gate terminal of the FET Q2 on the low side of the bridge circuit via a gate series resistor R _G. Further, SD is connected in parallel with _{RG in} a direction that turns off when Q2 is turned on.

Therefore, when a high level (hereinafter referred to as H level) signal is input from a pulse generator (hereinafter referred to as PG) to the common input terminal of NPNTr and PNPTr, NPNTr is turned on and PNPTr and SD are turned off. become. As a result, a current flows between the collector and emitter of the NPNTr, and this current flows into the gate of Q2 via R _G. This flowing current charges the input capacitance C _iss (interelectrode capacitance + α) of Q2, raises the gate voltage of Q2 to the drive potential, and drives Q2 to the on state.

On the other hand, when a low level (hereinafter referred to as L level) signal is input from the PG to the input terminal, the PNPTr and SD are turned on and the NPNTr is turned off. As a result, the gate current of Q2 (the accumulated charge of _Ciss ) flows through SD through R _G, and is discharged to the ground (low potential side) through the emitter and collector of PNPTr. When the accumulated charge of _Ciss is released, Q2 is turned off.
Fundamentals and actual use of power MOSFET, Yasu Inaba, CQ Publisher, 2004, first edition, P.053-054

However, in the above prior art, during the transition of Q2 from the OFF state to the ON state, as shown in FIG. 15, the gate potential of Q2 is affected by the mirror effect due to the gate-drain capacitance C _gd of the Q2 transistor. A state (half-on state) in which the (input waveform) and the drain potential (output waveform) are constant at an intermediate potential occurs. In FIG. 15, the horizontal axis represents time [μs] and the vertical axis represents voltage [V]. In particular, as the C _{gd of} Q2 increases, the half-on state period becomes longer, which may cause problems in the operation of the bridge circuit. In addition, this half-on state causes a large through current between the high-side transistor and the low-side transistor, particularly during the on / off operation of the H-bridge circuit transistor, thereby increasing current consumption. There was a risk of causing it.

  Therefore, the present invention has been made paying attention to such an unsolved problem of the conventional technology, and is suitable for driving a transistor on the low side of a bridge circuit for driving a load. The purpose is to provide.

  [Mode 1] In order to achieve the above object, a transistor driving apparatus according to mode 1 includes a high-side first transistor and a low-side second transistor that are electrically connected to a load to be driven. A transistor driver for driving the second transistor of the bridge circuit in which the load is energized or de-energized by turning on or off the first and second transistors, the first power supply A first power supply node supplied with a potential, a second power supply node supplied with a second power supply potential lower than the first power supply potential, and between the first power supply node and the second power supply node A third transistor that is turned on / off at a first input and a fourth transistor that is turned on / off at a second input, connected in parallel, and the electric power of the third and fourth transistors. When the supply terminal is electrically connected to the drive terminal of the second transistor and one or both of the third and fourth transistors are turned on, the drive power is supplied to the drive terminal of the second transistor. Drive power supply means for supplying, and drive state detection means for detecting a half-on state in which the output voltage of the second transistor becomes substantially constant at an intermediate potential during the transition from the OFF state to the ON state of the second transistor When the second transistor is turned on from off, the first and second inputs are controlled to turn on the third transistor before the fourth transistor, and the driving state is detected. Drive control for controlling the first and second inputs to turn on the fourth transistor in addition to the third transistor when the means detects the half-on state Means.

  With this configuration, when the drive control unit controls the first and second inputs to turn on the third transistor, the drive potential is supplied to the second transistor and the supply of the drive current is started. Is done. When the drive current is supplied, the input capacitance of the second transistor is charged, and the second transistor shifts from off to on as the charge amount increases. During the transition from OFF to ON, when the drive state detection means detects that the second transistor is in the half-ON state, the drive control means controls the first and second inputs. Thus, the fourth transistor is turned on in addition to the third transistor. When the fourth transistor is turned on, the drive current from the fourth transistor is supplied to the second transistor in addition to the drive current from the third transistor.

As a result, the drive current from the two transistors flows into the second transistor in the half-on state, the charge speed of the input capacitance is increased, and compared with the conventional drive of one transistor, The effect that the period which becomes a half-on state can be shortened is acquired.
Furthermore, until the half-on state is detected, only the third transistor is turned on to supply current, and after the half-on state is detected, the fourth transistor is also turned on. There is an effect that the period of the half-on state can be shortened while reducing the occurrence of a rapid potential fluctuation until the half-on state is reached.

Here, sudden potential fluctuations that occur before the transistor is in a half-on state make it easy to generate a surge voltage due to inductor components such as wiring connected to the load. Destruction).
In particular, in the H-bridge circuit, the first transistor on the high side and the second transistor on the low side connected in the vertical direction may be turned on at the same time. Flows. Therefore, for example, when the second transistor is driven by turning on the third and fourth transistors at the same time or using a transistor having a larger current supply capacity than the third transistor from the beginning, the gate of the transistor The potential becomes higher than when driven by only the third transistor (it becomes flat once at a potential higher than V _TH ), and there is a possibility that the through current flowing through both of them will be increased.

In other words, the input capacitance is charged relatively slowly until the half-on state is reached, and charging is performed at a stroke after the half-on state is reached, making it difficult to generate surge voltage or increase the through current. However, the charge rate can be increased.
Here, the half-on state is a state that occurs because the input capacitance increases due to the effect of the Miller effect during charging of the input capacitance of the transistor, and the output voltage of the transistor is substantially constant at an intermediate potential. It is a state. As a specific example, for example, when the transistor is a MOSFET, a period in which the gate voltage of the MOSFET becomes substantially constant at an intermediate potential occurs due to the effect of the Miller effect during charging of the input capacitance by gate driving. During this period, the output voltage (drain voltage) of the FET is also substantially constant.
The current supply terminal is, for example, an emitter terminal when the third and fourth transistors are bipolar transistors, and is a drain terminal, for example, when the FET is an FET.

  [Mode 2] Further, the transistor drive device according to mode 2 is the transistor drive device according to mode 1, wherein the fourth transistor has a transistor size having a larger current supply capability than the third transistor.

  In such a configuration, until the half-on state is reached, the third transistor having a relatively small size (small current supply capability) is charged with the input capacitance of the second transistor, and the half-on state is obtained. In this state, in addition to the third transistor, the fourth transistor having a relatively large size (large current supply capability) can charge the input capacitance of the second transistor. Thereby, it is possible to charge with a relatively small amount of current until the half-on state is reached, and to charge the input capacitance at a stretch with a relatively large amount of current when the half-on state is established.

[Mode 3] Further, the transistor drive device according to mode 3 is the transistor drive device according to mode 2, wherein the drive control means replaces the third transistor when the half-on state is detected. The first and second inputs are controlled to turn on four transistors.
In such a configuration, until the half-on state is reached, the third transistor having a relatively small size (small current supply capability) is charged with the input capacitance of the second transistor, and the half-on state is obtained. In this state, the input capacitance of the second transistor can be charged by a fourth transistor having a relatively large size (a large current supply capability) instead of the third transistor. In other words, when the sizes of the third and fourth transistors are different (when the current supply capability is different), when the half-on state is entered, not both of them are turned on, but only the fourth transistor is turned on. Turn on.

[Mode 4] Furthermore, the transistor drive device according to mode 4 is the transistor drive device according to any one of modes 1 to 3, wherein the first and second transistors are field effect transistors, and the second The drive terminal of the transistor is a gate terminal.
With such a configuration, the turn-on time (charge time of the input capacitor) of the second transistor, which is a field effect transistor, can be shortened, and the period during which the half-on state is achieved as compared with the conventional case. Can be shortened.

  Here, when the field effect transistor (FET) is designed for high power, for example, the input capacity of the second transistor becomes relatively large, and the half-on state period is increased accordingly. Become. This input capacitance is a trade-off between the amount of current and the magnitude of resistance in the on state. That is, when it is desired to make the FET have a large current and a low resistance, it is necessary to increase the transistor size and the input capacitance also increases.

  [Mode 5] Further, the transistor drive device according to mode 5 is the transistor drive device according to any one of modes 1 to 4, wherein the drive state detection means passes through the load to the second transistor. A current detection unit that detects a current level of a flowing current; and a current level comparison unit that compares a current level detected by the current detection unit and a predetermined current level when the second transistor is in the half-on state. The half-on state is detected when the current level detected by the current detection unit reaches the predetermined current level.

  With such a configuration, when the third transistor is turned on and a driving current is supplied to the second transistor, the driving state detecting means passes the load through the second transistor in the current detecting unit. The current level of the current flowing in When the current level is detected, the current level comparison unit compares the detected current level with a prepared current level in the half-on state (hereinafter referred to as an incomplete current level). If the detected current level is smaller than the incomplete current level based on the comparison result, the drive control means turns on only the third transistor. On the other hand, when the detected current level is equal to or higher than the incomplete current level, the fourth transistor is turned on in addition to or instead of the third transistor.

As a result, the incomplete current level according to the characteristics of the load, the characteristics of the second transistor, and the like is obtained in advance by experiments or the like, so that the half-on state can be reliably detected. .
Here, the comparison of the current level may be performed by converting the current level into a voltage level.

  [Mode 6] Further, the transistor drive device according to Mode 6 is the transistor drive device according to any one of Modes 1 to 4, wherein the drive state detection means is configured to connect the load of the second transistor to the load. A voltage detection unit that detects a voltage level; and a voltage level comparison unit that compares the voltage level detected by the voltage detection unit with a predetermined voltage level when the second transistor is in the half-on state; And the half-on state is detected when the voltage level detected by the voltage detector becomes the predetermined voltage level.

  With such a configuration, when the third transistor is turned on and a driving current is supplied to the second transistor, the driving state detecting means detects the second transistor and the load in the voltage detecting unit. Detect the voltage level of electrical connections. When the voltage level is detected, the voltage level comparison unit compares the detected voltage level with a previously prepared voltage level in the half-on state (hereinafter referred to as an incomplete voltage level). If the detected voltage level is smaller than the incomplete voltage level based on the comparison result, the drive control means turns on only the third transistor. On the other hand, when the detected voltage level becomes equal to or higher than the incomplete voltage level, the fourth transistor is turned on in addition to or instead of the third transistor.

  As a result, it is possible to obtain the effect that the half-on state can be reliably detected by obtaining an incomplete voltage level according to the characteristics of the load, the characteristics of the second transistor, and the like in advance through experiments or the like. .

  [Mode 7] Furthermore, the transistor drive device according to mode 7 is the transistor drive device according to mode 6, wherein a time measuring means for measuring an elapsed time since a drive current is supplied to the second transistor, and the voltage A time recording unit that records information of a measurement time of the time measurement unit when the voltage level detected by the detection unit becomes the predetermined voltage level, and the drive control unit is measured by the time recording unit When the time is recorded, thereafter, the first and second inputs are controlled so as to turn on the fourth transistor at the timing when the measurement time of the time measuring means becomes the recorded measurement time. .

  With such a configuration, when the third transistor is turned on and the driving current is supplied to the second transistor, the time from when the supply of the driving current is started is measured by the time measuring means. On the other hand, the voltage detection unit detects the voltage level of the connection unit, and the voltage level comparison unit compares the detected voltage level with the incomplete voltage level. When the detected voltage level becomes an incomplete voltage level, the time recording means records the measurement time of the time measurement means at that time. After the measurement time is recorded, the drive control means thereafter changes the first transistor until the measurement time of the time measurement means reaches the recorded measurement time when turning the second transistor from the off state to the on state. Only the third transistor is turned on to supply the drive current, and the fourth transistor is turned on in addition to or instead of the third transistor at the timing when the measured time of the time measuring means becomes the recorded measurement time. .

Thereby, the effect that the said half-on state can be detected more reliably is acquired.
Furthermore, for example, when driving a load with little fluctuation after startup (for example, a fan motor of a PC), the operation of the voltage level comparison unit can be completely stopped after recording the measurement time. The effect that it can be made is also obtained.

  Here, the time measuring unit measures the elapsed time since the supply of the drive current to the second transistor is started, for example, by counting a clock supplied from the outside or inside by a counter circuit. Then, the time recording unit records the count value when the incomplete on-state occurs, and from the next time, the incomplete on-state occurs when the count value of the time measuring unit reaches the recorded count value. Judge.

  [Mode 8] Further, the transistor drive device according to mode 8 is the transistor drive device according to any one of modes 1 to 7, wherein the bridge circuit includes a pair of the first transistor on the high side and the low side side. A pair of the second transistors, and an H-bridge type circuit in which the first transistor and the second transistor located diagonally are turned on or off according to the direction of energization to the load. .

  With such a configuration, the second transistor on the low side of the H-bridge circuit that can arbitrarily change the direction of energization of the load can be changed to the half-on state as compared with the conventional case. The effect that the period during which the half-on state is achieved can be shortened while suppressing the occurrence of sudden potential fluctuations during the transition can be obtained.

  [Mode 9] Furthermore, the transistor drive device according to Mode 9 is the transistor drive device according to any one of Modes 1 to 8, wherein the drive power supply means includes the third transistor and the second power supply node. A fifth transistor that is connected in series between the fourth transistor and the fourth power source node, and that is connected in series between the fourth transistor and the second power supply node. A sixth transistor that is turned off, and the connection portion of the third and fifth transistors and the connection portion of the fourth and sixth transistors are electrically connected to the drive terminal of the second transistor. Connected to the second power supply node side from the second transistor when the third and fourth transistors are turned off and one or both of the fifth and sixth transistors are turned on The drive controller is configured to turn off both the third and fourth transistors when turning the second transistor from an on state to an off state. The first to fourth inputs are controlled so that both of the sixth transistors are turned on.

  With such a configuration, when the second transistor is turned from the on state to the off state, the charge accumulated as the input capacitance can be drawn to the second power supply node side via the two transistors. The turn-off time of the second transistor can be shortened as compared with the conventional case where the single transistor is used. Thereby, the effect that the period of the incomplete ON state generated during the transition to the OFF state can be shortened as compared with the conventional case is obtained.

[First Embodiment]
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. 1 to 9 are diagrams showing a first embodiment of a transistor driving device according to the present invention.
In the present embodiment, the transistor driving device according to the present invention is applied to an H-bridge circuit that drives a motor, and the low-side transistor of the H-bridge circuit is driven.

First, the structure of the motor drive device 1 according to the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of a motor drive device 1 according to the present invention.
As shown in FIG. 1, the motor driving device 1 includes a transistor driving device 100 and an H bridge circuit 200.
The transistor driving device 100 drives each transistor constituting the H bridge circuit 200 based on a control signal from a microcomputer (not shown).

  When the high-side transistor and the low-side transistor that constitute the H-bridge circuit 200 are independently driven and controlled by the transistor driving device 100, the DC motor that is a driving target is controlled according to the control contents. 2 is forward rotation drive, reverse rotation drive, brake drive, and the like.

Next, a detailed configuration of the H bridge circuit 200 will be described with reference to FIG.
Here, FIG. 2 is a diagram showing a detailed configuration of the H-bridge circuit 200.
As shown in FIG. 2, the H-bridge circuit 200 includes four N-channel type DMOSFETs Q1 to Q4 that function as switching elements, with Q1 and Q3 on the high side and Q2 and Q4 on the low side. Connected to an H-bridge type.
Specifically, the source terminal of Q1 and the drain terminal of Q2 are electrically connected, the source terminal of Q3 and the drain terminal of Q4 are electrically connected, and an output terminal that takes out an output from the connection part of Q1 and Q2 OUTA and an output terminal OUTB for taking out an output from a connection portion between Q3 and Q4 are formed. A DC motor 2 is connected to OUTA and OUTB. D1 to D4 are body diodes formed parasitically inside Q1 to Q4.

A driving voltage V _BB is supplied from the driving power source of the motor to the high side (the drain terminals of Q1 and Q3) of the H bridge circuit 200. On the other hand, the low side (the source terminal side of Q2 and Q4) is connected to the ground via a resistor Rs for current detection.
The drive lines from the transistor drive device 100 are electrically connected to the gate terminals of Q1 to Q4 of the H bridge circuit 200, respectively, and Q1 to Q4 are based on the drive potential and drive current supplied via the drive lines. Q4 is independently driven and controlled.

Next, the input capacitance of the DMOSFETs (Q1 to Q4) will be described with reference to FIG.
Here, FIG. 3 is a diagram showing an equivalent circuit of the DMOSFET.
As shown in FIG. 3, the DMOSFET has an interelectrode capacitance C _gd between the gate and the drain electrode and an interelectrode capacitance C _gs between the gate and the source electrode. The sum of C _gd and C _gs when the gate voltage is 0 [V] is called the input capacitance C _iss . In order to drive such a DMOSFET to an ON state, C _iss needs to be charged. However, in the process of transition to on-the DMOSFET is turned off, the gate - by a change in the source voltage V _GS, greatly changes capacity C _iss for capacity C _gd changes significantly (mirror effect). This apparent C _iss can be calculated by the following equation (1).

C _iss = C _gs + (1−A _V ) · C _gd (1)

In the above formula (1), _AV is a current amplification factor.

Due to the influence of the mirror effect, a state occurs in which V _GS at the time of transition from OFF to ON becomes substantially constant at an intermediate potential. During this period, the drain-source voltage V _DS is also substantially constant at the intermediate potential. This state is called a half-on state. The period of the half-on state becomes longer in proportion to the capacity of C _iss . For example, when the capacity becomes 300 to 500 [pF] in terms of layout, the half-on state period becomes longer, the charging time and the discharge time increase, and the turn-on time and turn-off time also increase. become longer.

  If the half-on period is long, the period during which current flows between the drain and the source in the high resistance state becomes long, which may cause problems such as destruction of the gate film due to heat generation of the DMOSFET. Therefore, the shorter the half-on state period is, the better. The present invention aims to shorten the half-on period of the low-side transistors (Q2, Q4) of the H-bridge circuit 200.

Next, the configuration of the transistor driving device 100 will be described with reference to FIG.
Here, FIG. 4 is a block diagram showing a schematic configuration of the transistor driving device 100.
As shown in FIG. 4, the transistor drive device 100 includes a drive control unit 10, a drive power supply unit 11, and a current level detection unit 12.
The drive control unit 10 controls the operation of the drive power supply unit 11 based on a control signal from a microcomputer (not shown) and a signal from the current level detection unit 12.

The drive power supply unit 11 includes a high-side drive circuit that independently controls the high-side Q1 and Q3, and a low-side drive circuit that independently controls the low-side Q2 and Q4. On / off operation of Q1 to Q4 of the H bridge circuit 200 is independently controlled based on the control signal from the control signal and the control signal from the drive control unit 10.
The current level detection unit 12 detects the level of the current flowing through the current detection resistor Rs of the H bridge circuit 200. Further, the detected current level is converted into a voltage level, the voltage level is compared with a reference voltage level, and a signal indicating the comparison result (hereinafter referred to as a comparison signal signal_a) is output to the drive control unit 10.

Next, the internal configuration of the drive control unit 10 and the drive power supply unit 11 will be described with reference to FIG.
Here, FIG. 5 is a block diagram showing an internal configuration of the drive control unit 10 and the drive power supply unit 11.
As shown in FIG. 5, the drive control unit 10 includes a first TG (timing generation) circuit 10a that controls a first LST (low-side transistor) drive circuit 11c of the drive power supply unit 11, and a second LST drive circuit 11d. And a second TG circuit 10b for controlling.

The first TG circuit 10a controls the operation of the first LST drive circuit 11c based on the control signal ctrl3 from the microcomputer, the clock signal CK from the oscillator (not shown), and the comparison signal signal_a from the current level detection unit 12. cnt_PTr3 (details will be described later) is generated and supplied to the first LST drive circuit 11c.
The second TG circuit 10b generates a control signal cnt_PTr3 for controlling the operation of the second LST drive circuit 11d based on the control signal ctrl4 from the microcomputer, the clock signal CK, and the comparison signal signal_a from the current level detection unit 12. Is supplied to the second LST drive circuit 11d.

Next, as shown in FIG. 5, the drive power supply unit 11 includes a first HST drive circuit 11a that controls the on / off operation of Q1 of the H bridge circuit 200 based on a control signal ctrl1 from the microcomputer, And a second HST driving circuit 11b for controlling the on / off operation of Q3 based on the control signal ctrl2.
The drive power supply unit 11 further includes a first LST drive circuit 11c that controls the on / off operation of the Q2 of the H bridge circuit 200 based on a control signal ctrl3 from the microcomputer and a control signal cnt_PTr2 (details will be described later); Based on the control signal ctrl4 from the microcomputer and the control signal cnt_PTr3 from the first TG circuit 10a, a second LST drive circuit 11d for controlling the on / off operation of Q4 is configured.

  Here, the control signals ctrl1 to ctrl4 from the microcomputer are signals (for example, PWM signals) for controlling on / off of Q1 to Q4 according to the driving contents of the motor, and Q1 to Q4 are in the transistor driving device 100. The control signal corresponding to each DMOSFET is controlled to be turned on at the L level and turned off at the H level.

Next, a detailed circuit configuration of the first HST drive circuit 11a will be described with reference to FIG.
Here, FIG. 6 is a diagram showing a detailed circuit configuration of the first HST drive circuit 11a.
As shown in FIG. 6, the first HST drive circuit 11 a includes P-channel field effect transistors PTr1 and PTr10, N-channel field effect transistors NTr1 and NTr10, a level shifter 30, and a voltage clamp circuit 32. Composed.
PTr1 and NTr1 are connected in series between a V _GH node supplied with a power supply potential V _BB + V _GL (V _GH ) and a V _BB node supplied with a power supply potential V _BB . Here, V _BB is the motor drive potential, V _GH is the gate drive potential of the high-side DMOSFETs (Q1, Q3), and V _GL is the gate drive potential of the low-side DMOSFETs (Q2, Q4).

More specifically, the source terminal of PTr1 is electrically connected to the V _GH node, the drain terminal is electrically connected to the drain terminal of NTr1, and the source terminal of NTr1 is electrically connected to the V _BB node. . The source terminal of PTr10 is electrically connected to the V _GH node, the drain terminal is electrically connected to the drain terminal of NTr10, the gate terminals of PTr10 and NTr10 are electrically connected to the voltage clamp circuit 32, and the source of NTr10 The terminal is electrically connected to the voltage clamp circuit 32 and the connection part (OUTA) of Q1 and Q2.

The gate terminals of PTr1 and NTr1 are electrically connected to the output terminal of the level shifter 30 through a common line. The drain connection part of PTr1 and NTr1 is electrically connected to the gate connection part of PTr10 and NTr10, and the drain connection part of PTr10 and NTr10 is electrically connected to the gate terminal of Q1.
The level shifter 30 includes a V _GL, and V _BB, on the basis of the three power supply potentials of the V _GH, the voltage level of the input signal 0 _{[V] ~V GL [V]} , V BB [V] ~V GH [ V] is a circuit that shifts the level to V and outputs the signal.

Specifically, when the signal voltage V ₁ of the control signal ctrl1 from the microcomputer is at L level (e.g. 0 [V]), the voltage level of the signal is shifted to _{V BB [V], V BB} [V] The signal is output. In this case, PTr1 is turned on and NTr1 is turned off, and a drive current is supplied to the gate terminal of Q1 via PTr1 to drive Q1 from off to on.
On the other hand, when the signal voltage V ₁ of the control signal from the microcomputer is at the H level (e.g., 5 [V]), the signal of the voltage level of the signal is level-shifted to _{V GH [V], V GH} [V] Is output. In this case, NTr1 is on, PTr1 is turned off, via the NTr1, draw the charge accumulated in the input capacitance C _iss of Q1 to V _BB node side.

The voltage clamp circuit 32 is configured by a Zener diode or the like, and is a circuit that protects a voltage higher than the rated voltage from being applied between the gate and source of the NTr10.
The second HST drive circuit 11b has the same configuration as that of the first HST drive circuit 11a, except that the target to be driven is Q3.

Next, a detailed circuit configuration of the first LST driving circuit 11c will be described with reference to FIG.
Here, FIG. 7 is a diagram showing a detailed circuit configuration of the first LST driving circuit 11c.
As shown in FIG. 7, the first LST driving circuit 11c includes a P-channel field effect transistor PTr2, N-channel field effect transistors NTr2, NTr3, and a P-channel field effect having a larger current supply capability than PTr2. A transistor PTr3 and a level shifter 31 are included.

PTr2 and NTr2 includes a V _GL node supplied the power supply potential V _GL (first power supply node) are connected in series between the ground node supplied a ground potential (second power supply node), PTr3 and NTr3 includes a V _GL nodes are connected in series between the ground node. These PTr2 and NTr2 connected in series and PTr3 and NTr3 are connected in parallel.

More specifically, the source terminal of PTr2 is electrically connected to the V _GL node, the drain terminal is electrically connected to the drain terminal of NTr2, the source terminal of NTr2 is electrically connected to the ground node . The source terminal of PTr3 is electrically connected to the V _GL node, the drain terminal is electrically connected to the drain terminal of NTr3, the source terminal of NTr3 is electrically connected to the ground node.

The gate terminals of PTr2 and NTr2 are electrically connected to the output terminal of the level shifter 31 through a common line. The drain connection part of PTr2 and NTr2 is electrically connected to the gate terminal of Q2.
The gate terminal of PTr3 is electrically connected to a terminal (not shown) that inputs a control signal from the microcomputer. The gate terminal of NTr3 is electrically connected to the output terminal of the level shifter 31. The connection between PTr3 and NTr3 is electrically connected to the gate terminal of Q2.

The level shifter 31 shifts the voltage level V ₂ [V] of the input signal to V _GL [V] based on three types of power supply potentials, V _GL , the control signal potential V ₂ from the microcomputer, and the ground potential. This circuit outputs a signal. When V ₂ is 0 [V], a signal of 0 [V] (ground potential) is output.
Specifically, when the signal voltage V ₂ of the control signal from the microcomputer is at L level (e.g. 0 [V]), the control signal of L level signal (signal of 0 [V]) cnt_PTr2 (first input) Output as. In this case, PTr2 is turned on and NTr2 is turned off, and the drive current is supplied to the gate terminal of Q2 via PTr2.

On the other hand, when the control signal from the microcomputer is at the H level (e.g., 5 [V]), the voltage level of the signal is level-shifted to V _GL [V], the signal of V _GL [V] as a control signal cnt_PTr2 Output. In this case, NTr2 is on, NTr3 is on, PTr2 is turned off, NTr2, NTr3 via draw the charge accumulated in the Q2 of the input capacitance C _iss to the ground node side.

That is, since the charge charged into the input capacitance C _iss is drawn through the two transistors, the half-on state at the time of transition from the on state to the off state is compared with the case where the single transistor is drawn. The period can be shortened and the turn-off time of Q2 can be shortened.
Furthermore, when a control signal cnt_PTr3 (second input) of L level (for example, 0 [V]) from the first TG circuit 10a is input to the gate terminal of PTr3, PTr3 is turned on and driven via PTr3. Current is supplied to the gate terminal of Q2. When this PTr3 is turned on simultaneously with PTr2, a driving current is supplied to Q2 through two transistors PTr2 and PTr3. In addition, since PTr3 having a larger current supply capability than PTr2 is added, the charge rate of the input capacitance is rapidly increased, and the period of the half-on state can be shortened.

Accordingly, the first TG circuit 10a in the drive control unit 10 uses both PTr2 and PTr3 to generate the control signal cnt_PTr3 at the timing for driving Q2 from the off state to the on state, and supplies the control signal cnt_PTr3 to the first LST drive circuit 11c. It is like that. The same applies to the second TG circuit 10b except that the target is the second LST drive circuit 11d.
The present invention is mainly characterized in that the PTr3 is provided and the PTr3 is turned on in addition to the PTr2 when the Q2 (Q4) is turned on, and the timing when the PTr3 is turned on. The timing for turning on PTr3 will be described later.

The second LST drive circuit 11d has the same configuration as that of the first LST drive circuit 11c, except that the target to be driven is Q4.
The transistor sizes of PTr2 and PTr3 are “PTr2 <PTr3”, but the transistor size of PTr2 is determined based on the device characteristics of Q2 and Q4. The transistor size of PTr3 is determined based on the turn-on time, turn-off time, turn-on, and propagation delay time at turn-off of Q2 and Q4.

  For example, the device characteristics of Q2 and Q4 are as follows: threshold voltage VTH is “1.4 ± 0.2 [V]”, resistance RON in ON state is “0.30Ω · mm2 or less”, breakdown voltage BVDS “60 V or more”, current Assuming that the capacitance is “1.0 [A] to 1.5 [A]”, the transistor size of PTr2 is determined based on these characteristics so that the gates of Q2 and Q4 can be driven.

  Further, the propagation delay time of Q2 and Q4 is “output current IO = ± 1.3 [A], 50% to 90% ENABLE ON to sink output ON 1.0 [μs]”, “output current IO = ± 1.3 [A], 50% If it is assumed that the output from to90% ENABLE is OFF to sink output OFF 0.8 [μs], the transistor size of PTr3 is determined based on these delay times.

Next, the configuration of the current level detection unit 12 will be described with reference to FIG.
Here, FIG. 8 is a diagram illustrating a configuration of the current level detection unit 12.
As shown in FIG. 8, the current level detector 12 includes an I / V conversion circuit 12a and a comparator 12b.
The input terminal of the I / V conversion circuit 12a is electrically connected to both ends of the current detection resistor Rs of the H bridge circuit 200, and the output terminal thereof is electrically connected to the input terminal of the comparator 12b. . When a current flowing through Rs of the H bridge circuit is input, the current is converted into a voltage and input to the comparator 12b.

The output terminal of the comparator 12b is electrically connected to the input terminals of the first TG circuit 10a and the second TG circuit 10b of the drive control unit 10. Then, the voltage V _s input from the I / V conversion circuit 12a is compared with the reference voltage V _ref, and if the voltage level of V _s is equal to or higher than the level of V _ref, an H level comparison signal signal_a is output. When the voltage level of V _s is lower than the level of V _ref , the L level comparison signal signal_a is output.

Here, the current Is flowing through Rs is, for example, as shown in FIG. 8, when Q3 of the H-bridge circuit 200 is in the on state, and Q2 shifts from the off state to the on state, and the drain-source of Q2 This is the current that flows through the coil ML of the motor 2 when a current flows between them (dotted line arrow in the figure).
In the present embodiment, the level of the detection voltage V _s is obtained from an experiment in advance to obtain the level (intermediate potential) at which the above-described half-on state is obtained, or from the characteristics of each element constituting the load (motor) and the circuit. It is obtained by calculation or the like, and the voltage at that level is input to the comparator 12b as the reference voltage _Vref .

That is, the current level detector 12 compares the V _ref by converting the level of Is flowing Rs to the voltage level V _s, and outputs the comparison result to the drive control unit 10.
Therefore, the signal signal_a indicating the comparison result is an H level signal when the detection voltage V _s is in an intermediate potential state, and an L level signal otherwise.

Next, the drive timing of PTr2 and PTr3 of the first or second LST drive circuit 11c or 11d will be described with reference to FIG.
Here, FIG. 9 is a timing chart showing drive timings of PTr2 and PTr3 of the first or second LST drive circuit 11c or 11d.
In the present invention, in order to shorten the period of the half-on state when Q2 and Q4 shift from the off-state to the on-state, the timing of turning on / off PTr2 and PTr3 of the first and second LST drive circuits 11c and 11d To control. The timing control of PTr2 and PTr3 has the same control contents in both the first and second LST drive circuits 11c and 11d, and therefore the timing control of PTr2 and PTr3 of the first LST drive circuit 11c will be described below.

In the present embodiment, the control signal ctrl3 from the microcomputer is directly input to the first LST drive circuit 11c. Then, the 1LST driving circuit 11c may, CTRL 3 is level-shifted to drive potential V _GL of the gate in the level shifter 31 in the case of H-level signal, supplies the signal to the gate terminal of PTr2. On the other hand, when ctrl3 is at L level, it is supplied to the gate terminal of PTr2 as it is.

Therefore, if ctrl3 is an L level signal, the control signal cnt_PTr2 for controlling PTr2 becomes an L level signal, and PTr2 is turned on. This will drive current supplied to the gate terminal of Q2 via PTr2, charge of the input capacitance C _iss is started.
On the other hand, the first TG circuit 10a generates a control signal cnt_PTr3 for controlling on / off of PTr3 based on ctrl3 which is a control signal from the microcomputer and signal_a input from the comparator 12b of the current level detection unit 12. To do.

Specifically, when ctrl3 from the microcomputer is an L level signal and signal_a from the comparator 12b is an L level signal as shown in FIG. 9, it can be determined that Q2 is not in a half-on state. Therefore, an H level signal is generated as cnt_PTr3, and this signal is supplied to the gate terminal of PTr3. In this case, PTr3 is turned off.
On the other hand, when ctrl3 is an L level signal and signal_a is an H level signal as shown in FIG. 9, it can be determined that Q2 is in a half-on state, so an L level signal as cnt_PTr3. And this signal is supplied to the gate terminal of PTr3. In this case, PTr3 is turned on. At this time, cnt_PTr2 is maintained at the L level, and the on state of PTr2 is maintained. Accordingly, the drive current is supplied to the gate terminal of Q2 via the two transistors PTr2 and PTr3.

When ctrl3 changes from L level to H level, cnt_PTr2 also changes to H level as shown in FIG. 9, and PTr2 is turned off. Since cnt_PTr2 is also supplied to the gate terminals of NTr2 and NTr3, both NTr2 and NTr3 are turned on. Through these two transistors, the charge charged in _Ciss of Q2 is drawn to the ground node side and released.

On the other hand, as shown in FIG. 9, when ctrl3 (cnt_PTr2) becomes an H level signal, the first TG circuit 10a generates an H level (V _GL ) signal as cnt_PTr3, and this signal is used as the gate terminal of PTr3. To supply. As a result, PTr3 is turned off.
In this embodiment, since PTr3 is formed with a transistor size having a larger current supply capability than PTr2, PTr2 may be turned off when PTr3 is turned on.

  As described above, the transistor driving apparatus 100 according to the present embodiment is a transistor that drives Q2 and Q4 on when the transistors Q2 and Q4 on the low side of the H bridge circuit 200 that drives the motor 2 are driven from off to on. In a certain PTr2 and PTr3, PTr2 is turned on first, the drive current is supplied to the gate of Q2 or Q4 only by PTr2, and the half-on state of Q2 or Q4 is detected from the comparison result of the current level detection unit 12 In this case, PTr3 was turned on in addition to PTr2, and the drive current was supplied to the gate of Q2 via the two transistors PTr2 and PTr3.

Accordingly, it is possible to reduce the period of the half-on state at the time of transition from the off state to the on state while reducing the occurrence of a rapid potential fluctuation until the transistor is in the half-on state.
Furthermore, when driving off the Q2, Q4 from ON, turns on the two transistors of NTr2 and NTr3, Q2, the input capacitance C _iss charged charges into the Q4 is in said drawn into the ground node side.

Thereby, the period of the half-on state at the time of transition from on to off can be shortened.
In the first embodiment, the drive power supply unit 11 corresponds to the drive power supply means described in the form 1 or 9, and the control processing of the drive power supply unit 11 by the drive control unit 10 and the microcomputer is the form 1 The current level detection unit 12 corresponds to the drive state detection unit according to the first or fifth aspect, corresponding to the drive control unit according to any one of 3 and 9.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to the drawings. 10 to 13 are diagrams showing a second embodiment of the transistor driving device according to the present invention.

This embodiment, to determine the half-on state of the Q2, Q4 of H-bridge circuit 200 of the first embodiment, Q2, Q4 drain - reference voltage V _DS between the source voltage V _ref and When driving Q2 and Q4 from the OFF state to the ON state for the first time, the first time, when only PTr2 is driven, the drive current is supplied to Q2 and Q4 and then half-on The time until the state (count value) is measured and recorded, and after the second time, when the count value reaches the recorded value, PTr3 is driven to turn on in addition to PTr2. This is different from the embodiment.

Hereinafter, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted as appropriate, and different portions will be described in detail.
First, based on FIG. 10, the structure of transistor drive device 100 'concerning this Embodiment is demonstrated.
Here, FIG. 10 is a block diagram showing a configuration of the transistor driving device 100 ′.

As shown in FIG. 10, the transistor drive device 100 ′ includes a drive control unit 13, a drive power supply unit 11, and a voltage level detection unit 14.
Based on the output signal out_PTr2 (signal supplied to the gate of Q2) of PTr2 from the first and second LST drive circuits 11c and 11d and the signal from the voltage level detection unit 14, the drive control unit 13 11 operations are controlled.

The voltage level detection unit 14 detects the V _DS of Q2, Q4 of H-bridge circuit 200 compares the voltage level with the reference voltage level, the signal indicating the comparison result (hereinafter, referred to as the comparison signal OutComp) a Output to the drive control unit 13.

Next, the internal configuration of the drive control unit 13 will be described with reference to FIG.
Here, FIG. 11 is a block diagram showing the internal configuration of the drive control unit 13 and the drive power supply unit 11.
As shown in FIG. 11, the drive control unit 13 includes a first control circuit 13a that controls the first LST drive circuit 11c and a second control circuit 13b that controls the second LST drive circuit 11d.

  The first control circuit 13a turns on PTr3 of the first LST drive circuit 11c based on the output signal out_PTr2 from the first LST drive circuit 11c, the clock signal CK from the oscillator (not shown), and the comparison signal outComp1 from the voltage level detection unit 14. A control signal cnt_PTr3 for controlling the off operation is generated and supplied to the first LST drive circuit 11c.

The second control circuit 13b controls the on / off operation of the PTr3 of the second LST drive circuit 11d based on the output signal out_PTr2 from the second LST drive circuit 11d, the clock signal CK, and the comparison signal outComp2 from the voltage level detection unit 14. A control signal cnt_PTr3 is generated and supplied to the second LST drive circuit 11d.
Although not shown, in order to obtain the output signal out_PTr2 from the first LST drive circuit 11c, the input terminal of out_PTr2 of the first control circuit 13a and the output terminal of PTr2 of the first LST drive circuit 11c are electrically connected. Yes.
Similarly, the input terminal of out_PTr2 of the second control circuit 13b and the output terminal of PTr2 of the second LST drive circuit 11d are electrically connected.

Next, based on FIG. 12, the structure of the voltage level detection part 14 is demonstrated.
Here, FIG. 12 is a diagram illustrating a configuration of the voltage level detection unit 14.
As shown in FIG. 12, the voltage level detector 14 includes a first comparator 14a and a second comparator 14b.

In the first comparator 14a, the connection portion N1 between Q1 and Q2 of the H bridge circuit 200 is electrically connected to the input terminal, and the output terminal is electrically connected to the input terminal of the first control circuit 13a of the drive control unit 10. Connected. Then, the potential of the connection portion N1 (V _{DS of} Q2) input to the input terminal is compared with the reference voltage V _ref, and if the voltage level of V _DS is equal to or higher than the level of V _ref , the first of H level. The comparison signal outComp1 is output, and if the voltage level of V _DS is less than the level of V _ref , the L-level first comparison signal outComp1 is output.

In the second comparator 14b, the connection portion N2 between Q3 and Q4 of the H bridge circuit 200 is electrically connected to the input terminal, and the output terminal is electrically connected to the input terminal of the second control circuit 13b of the drive control portion 10. Connected. Then, the potential of the connection portion N2 (V _{DS of} Q4) input to the input terminal is compared with the reference voltage V _ref, and if the voltage level of V _DS is equal to or higher than the level of V _ref , the second of H level. The comparison signal outComp2 is output, and if the voltage level of V _DS is less than the level of V _ref , the L-level second comparison signal outComp2 is output.

Here, the level of V _DS is proportional to the charge amount of the input capacitance of Q2 or Q4. Therefore, in the present embodiment, it is detected whether or not the level of V _{DS is} a level at which the half-on state is achieved.
In the present embodiment, the V _DS levels of Q2 and Q4 are obtained in advance by experiment to obtain the level (intermediate potential) at which the above-described half-on state is achieved, or each element constituting a load (motor) or a circuit. The voltage at that level is obtained as a reference voltage _Vref and is input to the comparator 12b.

That is, the voltage level detection unit 14 compares the voltage levels V _DS and V _ref of the connection units N 1 and N 2 and outputs the comparison result to the drive control unit 13.
Therefore, the signals outComp1 and outComp2 indicating the comparison results are H level signals when V _{DS of} Q2 and Q4 are in an intermediate potential state, and are L level signals otherwise.

Next, a detailed circuit configuration of the first control circuit 13a will be described with reference to FIG.
Here, FIG. 13 is a diagram showing a detailed circuit configuration of the first control circuit 13a.
As shown in FIG. 13, the first control circuit 13a includes a first TG (timing generator) 40, a counter 41, an FF (flip flop) circuit 42, a comparator 43, and a second TG 44. .

  The first TG 40 is electrically connected to the counter 41 and the FF circuit 42, respectively. The signal cnt_PTr2 from the first LST drive circuit 11c, the comparison signal outComp1 from the voltage level detection unit 14, and the clock signal CK from the oscillator Based on the above, a reset signal for the counter and a latch timing signal for the FF circuit 42 are generated and output to each. The reset signal of the counter 41 is output to the counter 41 when the level of cnt_PTr2 changes from H level to L level. As the latch timing signal, when outComp1 changes from L level to H level only once, a signal that changes from L level to H level, for example, is output to the FF circuit 42.

The counter 41 is electrically connected to the FF circuit 42 and the comparator 43, counts CK input from the oscillator, and outputs a count signal indicating the count value to the FF circuit 42 and the comparator 43. When a reset signal is input from the first TG 40, the counter is reset to the initial value.
The FF circuit 42 latches the count signal (the signal of each bit) input from the counter 41 based on the latch timing signal input from the first TG 40, and outputs the latched count value signal to the comparator 43. The latch timing signal is controlled so as to continue to hold the latched count value (for example, fixed at the L level). That is, the time (count value) in which the drive current is supplied to Q2 and the half-on state is reached is recorded (held) in the FF circuit 42.

  The comparator 43 is electrically connected to the second TG 44, compares the count signal input from the counter 41 with the latched count signal input from the FF circuit 42, and the count value of the count signal is When it is less than the count value of the latched count signal, an L level signal is output to the second TG 44. On the other hand, when the count value of the count signal is equal to or greater than the count value of the latched count signal, an H level signal is output to the second TG 44. That is, when Q2 is in a half-on state, an H level signal is output to the second TG 44.

  The second TG 44 is electrically connected to the gate terminal of PTr3 of the first LST driving circuit 11c, and when the H level signal is input from the comparator 43, the L level control signal cnt_PTr3 is supplied to the gate terminal of PTr3. When an L level signal is input, an H level control signal cnt_PTr3 is output to the gate terminal of PTr3.

  That is, the first control circuit 13a first drives Q2 from the off state to the on state after the power is turned on, and after the signal out_PTr2 supplied to the gate terminal of Q2 becomes H level, Q2 Is measured in the half-on state (CK count number), and this is held in the FF circuit 42. In the second and subsequent times, outComp1 is ignored, the held count value is compared with the count value of the counter 41, and when the count value of the counter 41 becomes equal to or larger than the count value held in the FF 42, PTr3 is set. The L level cnt_PTr3 to be turned on is output. As a result, when ctrl3 from the microcomputer is input to the first LST drive circuit 11c, Q2 is initially supplied with drive current only by PTr2, and eventually when Q2 is in a half-on state, PTr3 is turned on in addition to PTr2. Thus, the drive current is supplied by the two transistors PTr2 and PTr3.

The operation of the first LST drive circuit 11c is the same as that in the first embodiment.
Further, the second control circuit 13b has the same configuration and operation as the first control circuit 13a, except that the target to be driven is the PTr3 of the second LST drive circuit 11d.
On the other hand, in the present embodiment, in the second and subsequent operations, power supply to the first comparator 14a and the second comparator 14b of the voltage level detector 14 can be switched on / off (not shown). The switch is switched to stop the current supply to the first comparator 14a of the voltage level detector 14. Note that the current supply to the second comparator 14b is stopped for the second and subsequent operations of Q4.

  For example, if the motor 2 is a load with little fluctuation, the current supply stop (off) timing is set to the stop state throughout the second and subsequent operations. Depending on the nature of the load, such as when the motor 2 is a load that does not fluctuate until the operating state (normal rotation, reverse rotation, brake, etc.) changes, the motor 2 is stopped until the operating state changes. Timing can be controlled.

As described above, in the transistor drive device 100 ′ according to the present embodiment, when the half-on state is detected, the voltage level detection unit 14 detects the V _{DS of} Q2 and Q4. By comparing with the voltage level V _{ref in the} on state, it is possible to output a signal indicating that the half on state is obtained when V _DS becomes V _ref or more.
This makes it possible to make a determination based on the voltage applied to the gate having a close relationship with the input capacitances of Q2 and Q4, so that the half-on state can be detected more accurately.

  Furthermore, at the time of driving from the first off state to the on state for the first time, the elapsed time (count value) from when the drive current is supplied to Q2 or Q4 until the half on state is measured is measured. In the second and subsequent times, this retained elapsed time is compared with the measured time, and when the measured time is equal to or greater than the retained elapsed time, it is determined that Q2 or Q4 is in a half-on state. Then, it is possible to generate and output a signal for driving PTr3 on. Furthermore, in the second and subsequent operations of Q2 and Q4, power supply to the first comparator 14a and the second comparator 14b can be stopped.

Thereby, when the elapsed time until the half-on state is recorded, the operation of the comparator can be stopped and the control based on the count value of the counter 41 can be performed, so that the current consumption can be reduced.
In the second embodiment, the drive power supply unit 11 corresponds to the drive power supply unit described in the form 1 or 9, and the control processing of the drive power supply unit 11 by the drive control unit 13 and the microcomputer is in the form 7. Alternatively, the voltage level detection unit 14 corresponds to the drive state detection unit described in the sixth aspect.

  In the first and second embodiments, when Q2 and Q4 are turned from the on state to the off state, both NTr2 and NTr3 are turned on from the beginning. However, the present invention is not limited to this. Similarly to PTr2 and PTr3, only NTr2 may be turned on first, and when a half-on state is detected, NTr3 may be turned on in addition to NTr2. In this case, the transistor sizes of NTr2 and NTr3 may be “NTr2 <NTr3”. Further, when “NTr2 <NTr3” is set, NTr3 may be turned on instead of NTr2 when a half-on state is detected.

In the first and second embodiments, the first and second HST drive circuits 11a and 11b and the first and second LST drive circuits 11c and 11d are connected to field effect transistors (NTr1 to 3, 10 and PTr1). However, the present invention is not limited to this, and a bipolar transistor capable of driving Q1 to Q4 may be used.
In the first and second embodiments, Q1 to Q4 are all N-channel type DMOSFETs. However, the present invention is not limited to this, and the high-side Q1 and Q3 are configured as P-channel types. Not only the DMOSFET but also other power transistors or IGBTs (Insulated Gate Bipolar Transistors) may be used.

  In the first and second embodiments, the present invention is applied to an H bridge circuit that drives a DC motor. However, the present invention is not limited to this, and the present invention is applied to a bridge circuit that drives a load such as an electromagnetic valve. You may apply. In particular, since the solenoid valve only needs to energize in one direction to the valve opening side or the valve closing side, the bridge circuit can have a half-bridge configuration.

It is a block diagram which shows the structure of the motor drive device 1 which concerns on this invention. 2 is a diagram illustrating a detailed configuration of an H-bridge circuit 200. FIG. It is a figure which shows the equivalent circuit of DMOSFET. 1 is a block diagram showing a schematic configuration of a transistor drive device 100. FIG. 3 is a block diagram showing the internal configuration of a drive control unit 13 and a drive power supply unit 11. FIG. It is a figure which shows the detailed circuit structure of the 1st HST drive circuit 11a. It is a figure which shows the detailed circuit structure of the 1st LST drive circuit 11c. FIG. 3 is a diagram illustrating a configuration of a current level detection unit 12. It is a timing chart which shows the drive timing of PTr2 and PTr3 of the 1st or 2nd LST drive circuit 11c or 11d. It is a block diagram which shows the structure of transistor drive device 100 '. 3 is a block diagram showing the internal configuration of a drive control unit 13 and a drive power supply unit 11. FIG. 3 is a diagram illustrating a configuration of a voltage level detection unit 14. FIG. It is a figure which shows the detailed circuit structure of the 1st control circuit 13a. It is a figure which shows an example of the gate drive circuit of the conventional low side transistor. It is a wave form diagram which shows the example of a half-on state.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Motor drive device, 2 ... DC motor, 100 ... Transistor drive device, 200 ... H bridge circuit, Q1-Q4 ... N channel type DMOSFET, 10, 13 ... Drive control circuit, 10a, 10b ... 1st, 2nd TG Circuit 11, drive power supply unit 11 a, 11 b, first and second HST drive circuit 11 c, 11 d, first and second LST drive circuit 12, current level detection unit 12 a, I / V conversion circuit 12 b,. Comparator, 13a, 13b ... first and second control circuits, 14 ... voltage level detector, 14a, 14b ... first and second comparators, PTr1-PTr3, PTr10 ... P-channel field effect transistors, NTr1- NTr3, NTr10 ... N channel type field effect transistor, 41 ... counter, 42 ... FF circuit, 43 ... comparator

Claims (9)

A high-side first transistor and a low-side second transistor that are electrically connected to a load to be driven, and turning the first and second transistors on or off to load the load Is a transistor driving device for driving the second transistor of the bridge circuit that is energized or de-energized,
A first power supply node to which a first power supply potential is supplied; a second power supply node to which a second power supply potential lower than the first power supply potential is supplied; the first power supply node and the second power supply node; A third transistor that is turned on / off at a first input and a fourth transistor that is turned on / off at a second input, connected in parallel between the first and second transistors, and currents of the third and fourth transistors When the supply terminal is electrically connected to the drive terminal of the second transistor and one or both of the third and fourth transistors are turned on, the drive power is supplied to the drive terminal of the second transistor. Drive power supply means for supplying,
Driving state detecting means for detecting a half-on state in which the output voltage of the second transistor is substantially constant at an intermediate potential in the middle of the transition of the second transistor from off to on;
When turning on the second transistor from off to on, the first and second inputs are controlled to turn on the third transistor before the fourth transistor, and the driving state detecting means Drive control means for controlling the first and second inputs to turn on the fourth transistor in addition to the third transistor when the half-on state is detected, Transistor driving device.   2. The transistor driving apparatus according to claim 1, wherein the fourth transistor has a transistor size having a larger current supply capability than the third transistor.   The drive control means controls the first and second inputs to turn on the fourth transistor in place of the third transistor when the half-on state is detected. The transistor driving device according to claim 2.   4. The transistor according to claim 1, wherein the first and second transistors are field effect transistors, and a drive terminal of the second transistor is a gate terminal. 5. Drive device.   The driving state detection means includes a current detection unit for detecting a current level of a current flowing through the load to the second transistor, a current level detected by the current detection unit, and the second transistor including the half- A current level comparison unit that compares a predetermined current level when the on state is entered, and when the current level detected by the current detection unit becomes the predetermined current level, the half-on state The transistor driving device according to claim 1, wherein the transistor driving device is detected.   The driving state detecting means includes a voltage detecting unit that detects a voltage level of an electrical connection portion of the second transistor with the load, the voltage level detected by the voltage detecting unit, and the second transistor. A voltage level comparison unit that compares a predetermined voltage level when the half-on state is reached, and when the voltage level detected by the voltage detection unit becomes the predetermined voltage level, The transistor driving device according to claim 1, wherein a half-on state is detected. Time measuring means for measuring an elapsed time since the driving current is supplied to the second transistor;
A time recording unit for recording information of a measurement time of the time measurement unit when the voltage level detected by the voltage detection unit becomes the predetermined voltage level;
After the measurement time is recorded by the time recording means, the drive control means turns on the fourth transistor at a timing when the measurement time of the time measurement means becomes the recorded measurement time. 7. The transistor driving device according to claim 6, wherein the first and second inputs are controlled.   The bridge circuit includes a pair of the first transistors on the high side and a pair of the second transistors on the low side, and the first is located diagonally according to the energization direction to the load. The transistor driving device according to claim 1, wherein the transistor driving circuit is an H-bridge circuit in which the transistor and the second transistor are turned on or off. The drive power supply means includes a fifth transistor connected in series between the third transistor and the second power supply node and turned on / off at a third input; the fourth transistor; A sixth transistor that is connected in series with the second power supply node and that is turned on / off at a fourth input; and a connection portion between the third and fifth transistors, and the fourth and second transistors. 6 is electrically connected to the drive terminal of the second transistor, the third and fourth transistors are turned off, and one or both of the fifth and sixth transistors are turned on. In this configuration, current is drawn from the second transistor to the second power supply node.
The drive control means turns off both the third and fourth transistors and turns on both the fifth and sixth transistors when turning the second transistor from an on state to an off state. The transistor driving device according to claim 1, wherein the first to fourth inputs are controlled so as to satisfy the following conditions.

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